1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * Device driver for the Sundance Tech. TC9021 10/100/1000
34 * Ethernet controller.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #ifdef HAVE_KERNEL_OPTION_HEADERS
41 #include "opt_device_polling.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/endian.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/taskqueue.h>
57 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_vlan_var.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/mii_bitbang.h>
71 #include <dev/mii/miivar.h>
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
76 #include <dev/stge/if_stgereg.h>
78 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 MODULE_DEPEND(stge, pci, 1, 1, 1);
81 MODULE_DEPEND(stge, ether, 1, 1, 1);
82 MODULE_DEPEND(stge, miibus, 1, 1, 1);
84 /* "device miibus" required. See GENERIC if you get errors here. */
85 #include "miibus_if.h"
88 * Devices supported by this driver.
90 static const struct stge_product {
91 uint16_t stge_vendorid;
92 uint16_t stge_deviceid;
93 const char *stge_name;
95 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
96 "Sundance ST-1023 Gigabit Ethernet" },
98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
99 "Sundance ST-2021 Gigabit Ethernet" },
101 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
102 "Tamarack TC9021 Gigabit Ethernet" },
104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
105 "Tamarack TC9021 Gigabit Ethernet" },
108 * The Sundance sample boards use the Sundance vendor ID,
109 * but the Tamarack product ID.
111 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
112 "Sundance TC9021 Gigabit Ethernet" },
114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
115 "Sundance TC9021 Gigabit Ethernet" },
117 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
118 "D-Link DL-4000 Gigabit Ethernet" },
120 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
121 "Antares Gigabit Ethernet" }
124 static int stge_probe(device_t);
125 static int stge_attach(device_t);
126 static int stge_detach(device_t);
127 static int stge_shutdown(device_t);
128 static int stge_suspend(device_t);
129 static int stge_resume(device_t);
131 static int stge_encap(struct stge_softc *, struct mbuf **);
132 static void stge_start(struct ifnet *);
133 static void stge_start_locked(struct ifnet *);
134 static void stge_watchdog(struct stge_softc *);
135 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
136 static void stge_init(void *);
137 static void stge_init_locked(struct stge_softc *);
138 static void stge_vlan_setup(struct stge_softc *);
139 static void stge_stop(struct stge_softc *);
140 static void stge_start_tx(struct stge_softc *);
141 static void stge_start_rx(struct stge_softc *);
142 static void stge_stop_tx(struct stge_softc *);
143 static void stge_stop_rx(struct stge_softc *);
145 static void stge_reset(struct stge_softc *, uint32_t);
146 static int stge_eeprom_wait(struct stge_softc *);
147 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
148 static void stge_tick(void *);
149 static void stge_stats_update(struct stge_softc *);
150 static void stge_set_filter(struct stge_softc *);
151 static void stge_set_multi(struct stge_softc *);
153 static void stge_link_task(void *, int);
154 static void stge_intr(void *);
155 static __inline int stge_tx_error(struct stge_softc *);
156 static void stge_txeof(struct stge_softc *);
157 static int stge_rxeof(struct stge_softc *);
158 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
159 static int stge_newbuf(struct stge_softc *, int);
160 #ifndef __NO_STRICT_ALIGNMENT
161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
164 static int stge_miibus_readreg(device_t, int, int);
165 static int stge_miibus_writereg(device_t, int, int, int);
166 static void stge_miibus_statchg(device_t);
167 static int stge_mediachange(struct ifnet *);
168 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
170 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
171 static int stge_dma_alloc(struct stge_softc *);
172 static void stge_dma_free(struct stge_softc *);
173 static void stge_dma_wait(struct stge_softc *);
174 static void stge_init_tx_ring(struct stge_softc *);
175 static int stge_init_rx_ring(struct stge_softc *);
176 #ifdef DEVICE_POLLING
177 static int stge_poll(struct ifnet *, enum poll_cmd, int);
180 static void stge_setwol(struct stge_softc *);
181 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
182 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
183 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
188 static uint32_t stge_mii_bitbang_read(device_t);
189 static void stge_mii_bitbang_write(device_t, uint32_t);
191 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
192 stge_mii_bitbang_read,
193 stge_mii_bitbang_write,
195 PC_MgmtData, /* MII_BIT_MDO */
196 PC_MgmtData, /* MII_BIT_MDI */
197 PC_MgmtClk, /* MII_BIT_MDC */
198 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
199 0, /* MII_BIT_DIR_PHY_HOST */
203 static device_method_t stge_methods[] = {
204 /* Device interface */
205 DEVMETHOD(device_probe, stge_probe),
206 DEVMETHOD(device_attach, stge_attach),
207 DEVMETHOD(device_detach, stge_detach),
208 DEVMETHOD(device_shutdown, stge_shutdown),
209 DEVMETHOD(device_suspend, stge_suspend),
210 DEVMETHOD(device_resume, stge_resume),
213 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
214 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
215 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
220 static driver_t stge_driver = {
223 sizeof(struct stge_softc)
226 static devclass_t stge_devclass;
228 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
229 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
231 static struct resource_spec stge_res_spec_io[] = {
232 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
233 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
237 static struct resource_spec stge_res_spec_mem[] = {
238 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
239 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
244 * stge_mii_bitbang_read: [mii bit-bang interface function]
246 * Read the MII serial port for the MII bit-bang module.
249 stge_mii_bitbang_read(device_t dev)
251 struct stge_softc *sc;
254 sc = device_get_softc(dev);
256 val = CSR_READ_1(sc, STGE_PhyCtrl);
257 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
258 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
263 * stge_mii_bitbang_write: [mii big-bang interface function]
265 * Write the MII serial port for the MII bit-bang module.
268 stge_mii_bitbang_write(device_t dev, uint32_t val)
270 struct stge_softc *sc;
272 sc = device_get_softc(dev);
274 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
275 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
276 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
280 * sc_miibus_readreg: [mii interface function]
282 * Read a PHY register on the MII of the TC9021.
285 stge_miibus_readreg(device_t dev, int phy, int reg)
287 struct stge_softc *sc;
290 sc = device_get_softc(dev);
292 if (reg == STGE_PhyCtrl) {
293 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
295 error = CSR_READ_1(sc, STGE_PhyCtrl);
301 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
307 * stge_miibus_writereg: [mii interface function]
309 * Write a PHY register on the MII of the TC9021.
312 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
314 struct stge_softc *sc;
316 sc = device_get_softc(dev);
319 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
325 * stge_miibus_statchg: [mii interface function]
327 * Callback from MII layer when media changes.
330 stge_miibus_statchg(device_t dev)
332 struct stge_softc *sc;
334 sc = device_get_softc(dev);
335 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
339 * stge_mediastatus: [ifmedia interface function]
341 * Get the current interface media status.
344 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
346 struct stge_softc *sc;
347 struct mii_data *mii;
350 mii = device_get_softc(sc->sc_miibus);
353 ifmr->ifm_status = mii->mii_media_status;
354 ifmr->ifm_active = mii->mii_media_active;
358 * stge_mediachange: [ifmedia interface function]
360 * Set hardware to newly-selected media.
363 stge_mediachange(struct ifnet *ifp)
365 struct stge_softc *sc;
366 struct mii_data *mii;
369 mii = device_get_softc(sc->sc_miibus);
376 stge_eeprom_wait(struct stge_softc *sc)
380 for (i = 0; i < STGE_TIMEOUT; i++) {
382 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
391 * Read data from the serial EEPROM.
394 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
397 if (stge_eeprom_wait(sc))
398 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
400 CSR_WRITE_2(sc, STGE_EepromCtrl,
401 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
402 if (stge_eeprom_wait(sc))
403 device_printf(sc->sc_dev, "EEPROM read timed out\n");
404 *data = CSR_READ_2(sc, STGE_EepromData);
409 stge_probe(device_t dev)
411 const struct stge_product *sp;
413 uint16_t vendor, devid;
415 vendor = pci_get_vendor(dev);
416 devid = pci_get_device(dev);
418 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
420 if (vendor == sp->stge_vendorid &&
421 devid == sp->stge_deviceid) {
422 device_set_desc(dev, sp->stge_name);
423 return (BUS_PROBE_DEFAULT);
431 stge_attach(device_t dev)
433 struct stge_softc *sc;
435 uint8_t enaddr[ETHER_ADDR_LEN];
441 sc = device_get_softc(dev);
444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
446 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
447 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
448 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
453 pci_enable_busmaster(dev);
454 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
455 val = pci_read_config(dev, PCIR_BAR(1), 4);
457 sc->sc_spec = stge_res_spec_mem;
459 val = pci_read_config(dev, PCIR_BAR(0), 4);
460 if (!PCI_BAR_IO(val)) {
461 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
465 sc->sc_spec = stge_res_spec_io;
467 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
469 device_printf(dev, "couldn't allocate %s resources\n",
470 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
473 sc->sc_rev = pci_get_revid(dev);
475 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
476 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
477 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
478 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
480 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
481 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
482 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
483 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
485 /* Pull in device tunables. */
486 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
487 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
488 "rxint_nframe", &sc->sc_rxint_nframe);
490 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
491 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
492 device_printf(dev, "rxint_nframe value out of range; "
493 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
494 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
498 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
499 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
500 "rxint_dmawait", &sc->sc_rxint_dmawait);
502 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
503 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
504 device_printf(dev, "rxint_dmawait value out of range; "
505 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
506 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
510 if ((error = stge_dma_alloc(sc) != 0))
514 * Determine if we're copper or fiber. It affects how we
517 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
522 /* Load LED configuration from EEPROM. */
523 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
526 * Reset the chip to a known state.
529 stge_reset(sc, STGE_RESET_FULL);
533 * Reading the station address from the EEPROM doesn't seem
534 * to work, at least on my sample boards. Instead, since
535 * the reset sequence does AutoInit, read it from the station
536 * address registers. For Sundance 1023 you can only read it
539 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
542 v = CSR_READ_2(sc, STGE_StationAddress0);
543 enaddr[0] = v & 0xff;
545 v = CSR_READ_2(sc, STGE_StationAddress1);
546 enaddr[2] = v & 0xff;
548 v = CSR_READ_2(sc, STGE_StationAddress2);
549 enaddr[4] = v & 0xff;
553 uint16_t myaddr[ETHER_ADDR_LEN / 2];
554 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
555 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
557 myaddr[i] = le16toh(myaddr[i]);
559 bcopy(myaddr, enaddr, sizeof(enaddr));
563 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
565 device_printf(sc->sc_dev, "failed to if_alloc()\n");
571 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
572 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
573 ifp->if_ioctl = stge_ioctl;
574 ifp->if_start = stge_start;
575 ifp->if_init = stge_init;
576 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
577 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
578 IFQ_SET_READY(&ifp->if_snd);
579 /* Revision B3 and earlier chips have checksum bug. */
580 if (sc->sc_rev >= 0x0c) {
581 ifp->if_hwassist = STGE_CSUM_FEATURES;
582 ifp->if_capabilities = IFCAP_HWCSUM;
584 ifp->if_hwassist = 0;
585 ifp->if_capabilities = 0;
587 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
588 ifp->if_capenable = ifp->if_capabilities;
591 * Read some important bits from the PhyCtrl register.
593 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
594 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
596 /* Set up MII bus. */
597 flags = MIIF_DOPAUSE;
598 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
599 flags |= MIIF_MACPRIV0;
600 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
601 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
604 device_printf(sc->sc_dev, "attaching PHYs failed\n");
608 ether_ifattach(ifp, enaddr);
610 /* VLAN capability setup */
611 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
612 if (sc->sc_rev >= 0x0c)
613 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
614 ifp->if_capenable = ifp->if_capabilities;
615 #ifdef DEVICE_POLLING
616 ifp->if_capabilities |= IFCAP_POLLING;
619 * Tell the upper layer(s) we support long frames.
620 * Must appear after the call to ether_ifattach() because
621 * ether_ifattach() sets ifi_hdrlen to the default value.
623 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
626 * The manual recommends disabling early transmit, so we
627 * do. It's disabled anyway, if using IP checksumming,
628 * since the entire packet must be in the FIFO in order
629 * for the chip to perform the checksum.
631 sc->sc_txthresh = 0x0fff;
634 * Disable MWI if the PCI layer tells us to.
637 if ((cmd & PCIM_CMD_MWRICEN) == 0)
638 sc->sc_DMACtrl |= DMAC_MWIDisable;
643 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
644 NULL, stge_intr, sc, &sc->sc_ih);
647 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
660 stge_detach(device_t dev)
662 struct stge_softc *sc;
665 sc = device_get_softc(dev);
668 #ifdef DEVICE_POLLING
669 if (ifp && ifp->if_capenable & IFCAP_POLLING)
670 ether_poll_deregister(ifp);
672 if (device_is_attached(dev)) {
678 callout_drain(&sc->sc_tick_ch);
679 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
683 if (sc->sc_miibus != NULL) {
684 device_delete_child(dev, sc->sc_miibus);
685 sc->sc_miibus = NULL;
687 bus_generic_detach(dev);
696 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
699 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
701 mtx_destroy(&sc->sc_mii_mtx);
702 mtx_destroy(&sc->sc_mtx);
707 struct stge_dmamap_arg {
708 bus_addr_t stge_busaddr;
712 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
714 struct stge_dmamap_arg *ctx;
719 ctx = (struct stge_dmamap_arg *)arg;
720 ctx->stge_busaddr = segs[0].ds_addr;
724 stge_dma_alloc(struct stge_softc *sc)
726 struct stge_dmamap_arg ctx;
727 struct stge_txdesc *txd;
728 struct stge_rxdesc *rxd;
731 /* create parent tag. */
732 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
733 1, 0, /* algnmnt, boundary */
734 STGE_DMA_MAXADDR, /* lowaddr */
735 BUS_SPACE_MAXADDR, /* highaddr */
736 NULL, NULL, /* filter, filterarg */
737 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
739 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
741 NULL, NULL, /* lockfunc, lockarg */
742 &sc->sc_cdata.stge_parent_tag);
744 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
747 /* create tag for Tx ring. */
748 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
749 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
750 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
751 BUS_SPACE_MAXADDR, /* highaddr */
752 NULL, NULL, /* filter, filterarg */
753 STGE_TX_RING_SZ, /* maxsize */
755 STGE_TX_RING_SZ, /* maxsegsize */
757 NULL, NULL, /* lockfunc, lockarg */
758 &sc->sc_cdata.stge_tx_ring_tag);
760 device_printf(sc->sc_dev,
761 "failed to allocate Tx ring DMA tag\n");
765 /* create tag for Rx ring. */
766 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
767 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
768 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
769 BUS_SPACE_MAXADDR, /* highaddr */
770 NULL, NULL, /* filter, filterarg */
771 STGE_RX_RING_SZ, /* maxsize */
773 STGE_RX_RING_SZ, /* maxsegsize */
775 NULL, NULL, /* lockfunc, lockarg */
776 &sc->sc_cdata.stge_rx_ring_tag);
778 device_printf(sc->sc_dev,
779 "failed to allocate Rx ring DMA tag\n");
783 /* create tag for Tx buffers. */
784 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
785 1, 0, /* algnmnt, boundary */
786 BUS_SPACE_MAXADDR, /* lowaddr */
787 BUS_SPACE_MAXADDR, /* highaddr */
788 NULL, NULL, /* filter, filterarg */
789 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
790 STGE_MAXTXSEGS, /* nsegments */
791 MCLBYTES, /* maxsegsize */
793 NULL, NULL, /* lockfunc, lockarg */
794 &sc->sc_cdata.stge_tx_tag);
796 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
800 /* create tag for Rx buffers. */
801 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
802 1, 0, /* algnmnt, boundary */
803 BUS_SPACE_MAXADDR, /* lowaddr */
804 BUS_SPACE_MAXADDR, /* highaddr */
805 NULL, NULL, /* filter, filterarg */
806 MCLBYTES, /* maxsize */
808 MCLBYTES, /* maxsegsize */
810 NULL, NULL, /* lockfunc, lockarg */
811 &sc->sc_cdata.stge_rx_tag);
813 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
817 /* allocate DMA'able memory and load the DMA map for Tx ring. */
818 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
819 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
820 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
822 device_printf(sc->sc_dev,
823 "failed to allocate DMA'able memory for Tx ring\n");
827 ctx.stge_busaddr = 0;
828 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
829 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
830 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
831 if (error != 0 || ctx.stge_busaddr == 0) {
832 device_printf(sc->sc_dev,
833 "failed to load DMA'able memory for Tx ring\n");
836 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
838 /* allocate DMA'able memory and load the DMA map for Rx ring. */
839 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
840 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
841 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
843 device_printf(sc->sc_dev,
844 "failed to allocate DMA'able memory for Rx ring\n");
848 ctx.stge_busaddr = 0;
849 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
850 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
851 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
852 if (error != 0 || ctx.stge_busaddr == 0) {
853 device_printf(sc->sc_dev,
854 "failed to load DMA'able memory for Rx ring\n");
857 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
859 /* create DMA maps for Tx buffers. */
860 for (i = 0; i < STGE_TX_RING_CNT; i++) {
861 txd = &sc->sc_cdata.stge_txdesc[i];
864 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
867 device_printf(sc->sc_dev,
868 "failed to create Tx dmamap\n");
872 /* create DMA maps for Rx buffers. */
873 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
874 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
875 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
878 for (i = 0; i < STGE_RX_RING_CNT; i++) {
879 rxd = &sc->sc_cdata.stge_rxdesc[i];
882 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
885 device_printf(sc->sc_dev,
886 "failed to create Rx dmamap\n");
896 stge_dma_free(struct stge_softc *sc)
898 struct stge_txdesc *txd;
899 struct stge_rxdesc *rxd;
903 if (sc->sc_cdata.stge_tx_ring_tag) {
904 if (sc->sc_cdata.stge_tx_ring_map)
905 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
906 sc->sc_cdata.stge_tx_ring_map);
907 if (sc->sc_cdata.stge_tx_ring_map &&
908 sc->sc_rdata.stge_tx_ring)
909 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
910 sc->sc_rdata.stge_tx_ring,
911 sc->sc_cdata.stge_tx_ring_map);
912 sc->sc_rdata.stge_tx_ring = NULL;
913 sc->sc_cdata.stge_tx_ring_map = 0;
914 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
915 sc->sc_cdata.stge_tx_ring_tag = NULL;
918 if (sc->sc_cdata.stge_rx_ring_tag) {
919 if (sc->sc_cdata.stge_rx_ring_map)
920 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
921 sc->sc_cdata.stge_rx_ring_map);
922 if (sc->sc_cdata.stge_rx_ring_map &&
923 sc->sc_rdata.stge_rx_ring)
924 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
925 sc->sc_rdata.stge_rx_ring,
926 sc->sc_cdata.stge_rx_ring_map);
927 sc->sc_rdata.stge_rx_ring = NULL;
928 sc->sc_cdata.stge_rx_ring_map = 0;
929 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
930 sc->sc_cdata.stge_rx_ring_tag = NULL;
933 if (sc->sc_cdata.stge_tx_tag) {
934 for (i = 0; i < STGE_TX_RING_CNT; i++) {
935 txd = &sc->sc_cdata.stge_txdesc[i];
936 if (txd->tx_dmamap) {
937 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
942 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
943 sc->sc_cdata.stge_tx_tag = NULL;
946 if (sc->sc_cdata.stge_rx_tag) {
947 for (i = 0; i < STGE_RX_RING_CNT; i++) {
948 rxd = &sc->sc_cdata.stge_rxdesc[i];
949 if (rxd->rx_dmamap) {
950 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
955 if (sc->sc_cdata.stge_rx_sparemap) {
956 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
957 sc->sc_cdata.stge_rx_sparemap);
958 sc->sc_cdata.stge_rx_sparemap = 0;
960 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
961 sc->sc_cdata.stge_rx_tag = NULL;
964 if (sc->sc_cdata.stge_parent_tag) {
965 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
966 sc->sc_cdata.stge_parent_tag = NULL;
973 * Make sure the interface is stopped at reboot time.
976 stge_shutdown(device_t dev)
979 return (stge_suspend(dev));
983 stge_setwol(struct stge_softc *sc)
988 STGE_LOCK_ASSERT(sc);
991 v = CSR_READ_1(sc, STGE_WakeEvent);
992 /* Disable all WOL bits. */
993 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
995 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
996 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
997 CSR_WRITE_1(sc, STGE_WakeEvent, v);
998 /* Reset Tx and prevent transmission. */
999 CSR_WRITE_4(sc, STGE_AsicCtrl,
1000 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1002 * TC9021 automatically reset link speed to 100Mbps when it's put
1003 * into sleep so there is no need to try to resetting link speed.
1008 stge_suspend(device_t dev)
1010 struct stge_softc *sc;
1012 sc = device_get_softc(dev);
1016 sc->sc_suspended = 1;
1024 stge_resume(device_t dev)
1026 struct stge_softc *sc;
1030 sc = device_get_softc(dev);
1034 * Clear WOL bits, so special frames wouldn't interfere
1035 * normal Rx operation anymore.
1037 v = CSR_READ_1(sc, STGE_WakeEvent);
1038 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1039 WE_WakeOnLanEnable);
1040 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1042 if (ifp->if_flags & IFF_UP)
1043 stge_init_locked(sc);
1045 sc->sc_suspended = 0;
1052 stge_dma_wait(struct stge_softc *sc)
1056 for (i = 0; i < STGE_TIMEOUT; i++) {
1058 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1062 if (i == STGE_TIMEOUT)
1063 device_printf(sc->sc_dev, "DMA wait timed out\n");
1067 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1069 struct stge_txdesc *txd;
1070 struct stge_tfd *tfd;
1072 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1073 int error, i, nsegs, si;
1074 uint64_t csum_flags, tfc;
1076 STGE_LOCK_ASSERT(sc);
1078 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1081 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1082 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1083 if (error == EFBIG) {
1084 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS);
1091 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1092 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1098 } else if (error != 0)
1108 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1109 if (m->m_pkthdr.csum_flags & CSUM_IP)
1110 csum_flags |= TFD_IPChecksumEnable;
1111 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1112 csum_flags |= TFD_TCPChecksumEnable;
1113 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1114 csum_flags |= TFD_UDPChecksumEnable;
1117 si = sc->sc_cdata.stge_tx_prod;
1118 tfd = &sc->sc_rdata.stge_tx_ring[si];
1119 for (i = 0; i < nsegs; i++)
1120 tfd->tfd_frags[i].frag_word0 =
1121 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1122 FRAG_LEN(txsegs[i].ds_len));
1123 sc->sc_cdata.stge_tx_cnt++;
1125 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1126 TFD_FragCount(nsegs) | csum_flags;
1127 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1128 tfc |= TFD_TxDMAIndicate;
1130 /* Update producer index. */
1131 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1133 /* Check if we have a VLAN tag to insert. */
1134 if (m->m_flags & M_VLANTAG)
1135 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1136 tfd->tfd_control = htole64(tfc);
1138 /* Update Tx Queue. */
1139 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1140 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1143 /* Sync descriptors. */
1144 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1145 BUS_DMASYNC_PREWRITE);
1146 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1147 sc->sc_cdata.stge_tx_ring_map,
1148 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1154 * stge_start: [ifnet interface function]
1156 * Start packet transmission on the interface.
1159 stge_start(struct ifnet *ifp)
1161 struct stge_softc *sc;
1165 stge_start_locked(ifp);
1170 stge_start_locked(struct ifnet *ifp)
1172 struct stge_softc *sc;
1173 struct mbuf *m_head;
1178 STGE_LOCK_ASSERT(sc);
1180 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1181 IFF_DRV_RUNNING || sc->sc_link == 0)
1184 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1185 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1186 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1190 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1194 * Pack the data into the transmit ring. If we
1195 * don't have room, set the OACTIVE flag and wait
1196 * for the NIC to drain the ring.
1198 if (stge_encap(sc, &m_head)) {
1201 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1202 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1208 * If there's a BPF listener, bounce a copy of this frame
1211 ETHER_BPF_MTAP(ifp, m_head);
1216 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1218 /* Set a timeout in case the chip goes out to lunch. */
1219 sc->sc_watchdog_timer = 5;
1226 * Watchdog timer handler.
1229 stge_watchdog(struct stge_softc *sc)
1233 STGE_LOCK_ASSERT(sc);
1235 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1239 if_printf(sc->sc_ifp, "device timeout\n");
1241 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1242 stge_init_locked(sc);
1243 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1244 stge_start_locked(ifp);
1248 * stge_ioctl: [ifnet interface function]
1250 * Handle control requests from the operator.
1253 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1255 struct stge_softc *sc;
1257 struct mii_data *mii;
1261 ifr = (struct ifreq *)data;
1265 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1267 else if (ifp->if_mtu != ifr->ifr_mtu) {
1268 ifp->if_mtu = ifr->ifr_mtu;
1270 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1271 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1272 stge_init_locked(sc);
1279 if ((ifp->if_flags & IFF_UP) != 0) {
1280 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1281 if (((ifp->if_flags ^ sc->sc_if_flags)
1282 & IFF_PROMISC) != 0)
1283 stge_set_filter(sc);
1285 if (sc->sc_detach == 0)
1286 stge_init_locked(sc);
1289 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1292 sc->sc_if_flags = ifp->if_flags;
1298 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1304 mii = device_get_softc(sc->sc_miibus);
1305 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1308 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1309 #ifdef DEVICE_POLLING
1310 if ((mask & IFCAP_POLLING) != 0) {
1311 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1312 error = ether_poll_register(stge_poll, ifp);
1316 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1317 ifp->if_capenable |= IFCAP_POLLING;
1320 error = ether_poll_deregister(ifp);
1324 CSR_WRITE_2(sc, STGE_IntEnable,
1326 ifp->if_capenable &= ~IFCAP_POLLING;
1331 if ((mask & IFCAP_HWCSUM) != 0) {
1332 ifp->if_capenable ^= IFCAP_HWCSUM;
1333 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1334 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1335 ifp->if_hwassist = STGE_CSUM_FEATURES;
1337 ifp->if_hwassist = 0;
1339 if ((mask & IFCAP_WOL) != 0 &&
1340 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1341 if ((mask & IFCAP_WOL_MAGIC) != 0)
1342 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1344 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1345 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1346 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1348 stge_vlan_setup(sc);
1352 VLAN_CAPABILITIES(ifp);
1355 error = ether_ioctl(ifp, cmd, data);
1363 stge_link_task(void *arg, int pending)
1365 struct stge_softc *sc;
1366 struct mii_data *mii;
1370 sc = (struct stge_softc *)arg;
1373 mii = device_get_softc(sc->sc_miibus);
1374 if (mii->mii_media_status & IFM_ACTIVE) {
1375 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1381 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1382 sc->sc_MACCtrl |= MC_DuplexSelect;
1383 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1384 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1385 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1386 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1388 * Update STGE_MACCtrl register depending on link status.
1389 * (duplex, flow control etc)
1391 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1392 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1393 v |= sc->sc_MACCtrl;
1394 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1395 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1396 /* Duplex setting changed, reset Tx/Rx functions. */
1397 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1398 ac |= AC_TxReset | AC_RxReset;
1399 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1400 for (i = 0; i < STGE_TIMEOUT; i++) {
1402 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1405 if (i == STGE_TIMEOUT)
1406 device_printf(sc->sc_dev, "reset failed to complete\n");
1412 stge_tx_error(struct stge_softc *sc)
1418 txstat = CSR_READ_4(sc, STGE_TxStatus);
1419 if ((txstat & TS_TxComplete) == 0)
1422 if ((txstat & TS_TxUnderrun) != 0) {
1425 * There should be a more better way to recover
1426 * from Tx underrun instead of a full reset.
1428 if (sc->sc_nerr++ < STGE_MAXERR)
1429 device_printf(sc->sc_dev, "Tx underrun, "
1431 if (sc->sc_nerr == STGE_MAXERR)
1432 device_printf(sc->sc_dev, "too many errors; "
1433 "not reporting any more\n");
1437 /* Maximum/Late collisions, Re-enable Tx MAC. */
1438 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1439 CSR_WRITE_4(sc, STGE_MACCtrl,
1440 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1450 * Interrupt service routine.
1453 stge_intr(void *arg)
1455 struct stge_softc *sc;
1460 sc = (struct stge_softc *)arg;
1465 #ifdef DEVICE_POLLING
1466 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1469 status = CSR_READ_2(sc, STGE_IntStatus);
1470 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1473 /* Disable interrupts. */
1474 for (reinit = 0;;) {
1475 status = CSR_READ_2(sc, STGE_IntStatusAck);
1476 status &= sc->sc_IntEnable;
1479 /* Host interface errors. */
1480 if ((status & IS_HostError) != 0) {
1481 device_printf(sc->sc_dev,
1482 "Host interface error, resetting...\n");
1487 /* Receive interrupts. */
1488 if ((status & IS_RxDMAComplete) != 0) {
1490 if ((status & IS_RFDListEnd) != 0)
1491 CSR_WRITE_4(sc, STGE_DMACtrl,
1495 /* Transmit interrupts. */
1496 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1499 /* Transmission errors.*/
1500 if ((status & IS_TxComplete) != 0) {
1501 if ((reinit = stge_tx_error(sc)) != 0)
1508 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1509 stge_init_locked(sc);
1512 /* Re-enable interrupts. */
1513 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1515 /* Try to get more packets going. */
1516 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1517 stge_start_locked(ifp);
1526 * Helper; handle transmit interrupts.
1529 stge_txeof(struct stge_softc *sc)
1532 struct stge_txdesc *txd;
1536 STGE_LOCK_ASSERT(sc);
1540 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1543 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1544 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1547 * Go through our Tx list and free mbufs for those
1548 * frames which have been transmitted.
1550 for (cons = sc->sc_cdata.stge_tx_cons;;
1551 cons = (cons + 1) % STGE_TX_RING_CNT) {
1552 if (sc->sc_cdata.stge_tx_cnt <= 0)
1554 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1555 if ((control & TFD_TFDDone) == 0)
1557 sc->sc_cdata.stge_tx_cnt--;
1558 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1560 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1561 BUS_DMASYNC_POSTWRITE);
1562 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1564 /* Output counter is updated with statistics register */
1567 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1568 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1569 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1571 sc->sc_cdata.stge_tx_cons = cons;
1572 if (sc->sc_cdata.stge_tx_cnt == 0)
1573 sc->sc_watchdog_timer = 0;
1575 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1576 sc->sc_cdata.stge_tx_ring_map,
1577 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1580 static __inline void
1581 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1583 struct stge_rfd *rfd;
1585 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1586 rfd->rfd_status = 0;
1589 #ifndef __NO_STRICT_ALIGNMENT
1591 * It seems that TC9021's DMA engine has alignment restrictions in
1592 * DMA scatter operations. The first DMA segment has no address
1593 * alignment restrictins but the rest should be aligned on 4(?) bytes
1594 * boundary. Otherwise it would corrupt random memory. Since we don't
1595 * know which one is used for the first segment in advance we simply
1596 * don't align at all.
1597 * To avoid copying over an entire frame to align, we allocate a new
1598 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1599 * prepended into the existing mbuf chain.
1601 static __inline struct mbuf *
1602 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1607 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1608 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1609 m->m_data += ETHER_HDR_LEN;
1612 MGETHDR(n, M_NOWAIT, MT_DATA);
1614 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1615 m->m_data += ETHER_HDR_LEN;
1616 m->m_len -= ETHER_HDR_LEN;
1617 n->m_len = ETHER_HDR_LEN;
1618 M_MOVE_PKTHDR(n, m);
1631 * Helper; handle receive interrupts.
1634 stge_rxeof(struct stge_softc *sc)
1637 struct stge_rxdesc *rxd;
1638 struct mbuf *mp, *m;
1641 int cons, prog, rx_npkts;
1643 STGE_LOCK_ASSERT(sc);
1648 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1649 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1652 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1653 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1654 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1655 status = RFD_RxStatus(status64);
1656 if ((status & RFD_RFDDone) == 0)
1658 #ifdef DEVICE_POLLING
1659 if (ifp->if_capenable & IFCAP_POLLING) {
1660 if (sc->sc_cdata.stge_rxcycles <= 0)
1662 sc->sc_cdata.stge_rxcycles--;
1666 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1670 * If the packet had an error, drop it. Note we count
1671 * the error later in the periodic stats update.
1673 if ((status & RFD_FrameEnd) != 0 && (status &
1674 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1675 RFD_RxAlignmentError | RFD_RxFCSError |
1676 RFD_RxLengthError)) != 0) {
1677 stge_discard_rxbuf(sc, cons);
1678 if (sc->sc_cdata.stge_rxhead != NULL) {
1679 m_freem(sc->sc_cdata.stge_rxhead);
1680 STGE_RXCHAIN_RESET(sc);
1685 * Add a new receive buffer to the ring.
1687 if (stge_newbuf(sc, cons) != 0) {
1689 stge_discard_rxbuf(sc, cons);
1690 if (sc->sc_cdata.stge_rxhead != NULL) {
1691 m_freem(sc->sc_cdata.stge_rxhead);
1692 STGE_RXCHAIN_RESET(sc);
1697 if ((status & RFD_FrameEnd) != 0)
1698 mp->m_len = RFD_RxDMAFrameLen(status) -
1699 sc->sc_cdata.stge_rxlen;
1700 sc->sc_cdata.stge_rxlen += mp->m_len;
1703 if (sc->sc_cdata.stge_rxhead == NULL) {
1704 sc->sc_cdata.stge_rxhead = mp;
1705 sc->sc_cdata.stge_rxtail = mp;
1707 mp->m_flags &= ~M_PKTHDR;
1708 sc->sc_cdata.stge_rxtail->m_next = mp;
1709 sc->sc_cdata.stge_rxtail = mp;
1712 if ((status & RFD_FrameEnd) != 0) {
1713 m = sc->sc_cdata.stge_rxhead;
1714 m->m_pkthdr.rcvif = ifp;
1715 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1717 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1719 STGE_RXCHAIN_RESET(sc);
1723 * Set the incoming checksum information for
1726 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1727 if ((status & RFD_IPDetected) != 0) {
1728 m->m_pkthdr.csum_flags |=
1730 if ((status & RFD_IPError) == 0)
1731 m->m_pkthdr.csum_flags |=
1734 if (((status & RFD_TCPDetected) != 0 &&
1735 (status & RFD_TCPError) == 0) ||
1736 ((status & RFD_UDPDetected) != 0 &&
1737 (status & RFD_UDPError) == 0)) {
1738 m->m_pkthdr.csum_flags |=
1739 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1740 m->m_pkthdr.csum_data = 0xffff;
1744 #ifndef __NO_STRICT_ALIGNMENT
1745 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1746 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1747 STGE_RXCHAIN_RESET(sc);
1752 /* Check for VLAN tagged packets. */
1753 if ((status & RFD_VLANDetected) != 0 &&
1754 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1755 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1756 m->m_flags |= M_VLANTAG;
1761 (*ifp->if_input)(ifp, m);
1765 STGE_RXCHAIN_RESET(sc);
1770 /* Update the consumer index. */
1771 sc->sc_cdata.stge_rx_cons = cons;
1772 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1773 sc->sc_cdata.stge_rx_ring_map,
1774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1779 #ifdef DEVICE_POLLING
1781 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1783 struct stge_softc *sc;
1790 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1795 sc->sc_cdata.stge_rxcycles = count;
1796 rx_npkts = stge_rxeof(sc);
1799 if (cmd == POLL_AND_CHECK_STATUS) {
1800 status = CSR_READ_2(sc, STGE_IntStatus);
1801 status &= sc->sc_IntEnable;
1803 if ((status & IS_HostError) != 0) {
1804 device_printf(sc->sc_dev,
1805 "Host interface error, resetting...\n");
1806 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1807 stge_init_locked(sc);
1809 if ((status & IS_TxComplete) != 0) {
1810 if (stge_tx_error(sc) != 0) {
1811 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1812 stge_init_locked(sc);
1819 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1820 stge_start_locked(ifp);
1825 #endif /* DEVICE_POLLING */
1830 * One second timer, used to tick the MII.
1833 stge_tick(void *arg)
1835 struct stge_softc *sc;
1836 struct mii_data *mii;
1838 sc = (struct stge_softc *)arg;
1840 STGE_LOCK_ASSERT(sc);
1842 mii = device_get_softc(sc->sc_miibus);
1845 /* Update statistics counters. */
1846 stge_stats_update(sc);
1849 * Relcaim any pending Tx descriptors to release mbufs in a
1850 * timely manner as we don't generate Tx completion interrupts
1851 * for every frame. This limits the delay to a maximum of one
1854 if (sc->sc_cdata.stge_tx_cnt != 0)
1859 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1863 * stge_stats_update:
1865 * Read the TC9021 statistics counters.
1868 stge_stats_update(struct stge_softc *sc)
1872 STGE_LOCK_ASSERT(sc);
1876 CSR_READ_4(sc,STGE_OctetRcvOk);
1878 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1880 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1882 CSR_READ_4(sc, STGE_OctetXmtdOk);
1884 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1886 ifp->if_collisions +=
1887 CSR_READ_4(sc, STGE_LateCollisions) +
1888 CSR_READ_4(sc, STGE_MultiColFrames) +
1889 CSR_READ_4(sc, STGE_SingleColFrames);
1892 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1893 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1899 * Perform a soft reset on the TC9021.
1902 stge_reset(struct stge_softc *sc, uint32_t how)
1908 STGE_LOCK_ASSERT(sc);
1911 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1914 ac |= AC_TxReset | AC_FIFO;
1918 ac |= AC_RxReset | AC_FIFO;
1921 case STGE_RESET_FULL:
1924 * Only assert RstOut if we're fiber. We need GMII clocks
1925 * to be present in order for the reset to complete on fiber
1928 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1929 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1930 (sc->sc_usefiber ? AC_RstOut : 0);
1934 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1936 /* Account for reset problem at 10Mbps. */
1939 for (i = 0; i < STGE_TIMEOUT; i++) {
1940 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1945 if (i == STGE_TIMEOUT)
1946 device_printf(sc->sc_dev, "reset failed to complete\n");
1948 /* Set LED, from Linux IPG driver. */
1949 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1950 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1951 if ((sc->sc_led & 0x01) != 0)
1953 if ((sc->sc_led & 0x03) != 0)
1954 ac |= AC_LEDModeBit1;
1955 if ((sc->sc_led & 0x08) != 0)
1957 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1959 /* Set PHY, from Linux IPG driver */
1960 v = CSR_READ_1(sc, STGE_PhySet);
1961 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1962 v |= ((sc->sc_led & 0x70) >> 4);
1963 CSR_WRITE_1(sc, STGE_PhySet, v);
1967 * stge_init: [ ifnet interface function ]
1969 * Initialize the interface.
1972 stge_init(void *xsc)
1974 struct stge_softc *sc;
1976 sc = (struct stge_softc *)xsc;
1978 stge_init_locked(sc);
1983 stge_init_locked(struct stge_softc *sc)
1986 struct mii_data *mii;
1991 STGE_LOCK_ASSERT(sc);
1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1996 mii = device_get_softc(sc->sc_miibus);
1999 * Cancel any pending I/O.
2004 * Reset the chip to a known state.
2006 stge_reset(sc, STGE_RESET_FULL);
2008 /* Init descriptors. */
2009 error = stge_init_rx_ring(sc);
2011 device_printf(sc->sc_dev,
2012 "initialization failed: no memory for rx buffers\n");
2016 stge_init_tx_ring(sc);
2018 /* Set the station address. */
2019 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2020 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2021 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2022 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2025 * Set the statistics masks. Disable all the RMON stats,
2026 * and disable selected stats in the non-RMON stats registers.
2028 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2029 CSR_WRITE_4(sc, STGE_StatisticsMask,
2030 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2031 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2032 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2035 /* Set up the receive filter. */
2036 stge_set_filter(sc);
2037 /* Program multicast filter. */
2041 * Give the transmit and receive ring to the chip.
2043 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2044 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2045 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2046 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2048 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2049 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2050 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2051 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2054 * Initialize the Tx auto-poll period. It's OK to make this number
2055 * large (255 is the max, but we use 127) -- we explicitly kick the
2056 * transmit engine when there's actually a packet.
2058 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2060 /* ..and the Rx auto-poll period. */
2061 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2063 /* Initialize the Tx start threshold. */
2064 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2066 /* Rx DMA thresholds, from Linux */
2067 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2068 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2070 /* Rx early threhold, from Linux */
2071 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2073 /* Tx DMA thresholds, from Linux */
2074 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2075 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2078 * Initialize the Rx DMA interrupt control register. We
2079 * request an interrupt after every incoming packet, but
2080 * defer it for sc_rxint_dmawait us. When the number of
2081 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2082 * deferring the interrupt, and signal it immediately.
2084 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2085 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2086 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2089 * Initialize the interrupt mask.
2091 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2092 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2093 #ifdef DEVICE_POLLING
2094 /* Disable interrupts if we are polling. */
2095 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2096 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2099 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2102 * Configure the DMA engine.
2103 * XXX Should auto-tune TxBurstLimit.
2105 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2108 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2109 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2112 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2113 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2116 * Set the maximum frame size.
2118 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2119 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2122 * Initialize MacCtrl -- do it before setting the media,
2123 * as setting the media will actually program the register.
2125 * Note: We have to poke the IFS value before poking
2128 /* Tx/Rx MAC should be disabled before programming IFS.*/
2129 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2131 stge_vlan_setup(sc);
2133 if (sc->sc_rev >= 6) { /* >= B.2 */
2134 /* Multi-frag frame bug work-around. */
2135 CSR_WRITE_2(sc, STGE_DebugCtrl,
2136 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2138 /* Tx Poll Now bug work-around. */
2139 CSR_WRITE_2(sc, STGE_DebugCtrl,
2140 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2141 /* Tx Poll Now bug work-around. */
2142 CSR_WRITE_2(sc, STGE_DebugCtrl,
2143 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2146 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2147 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2148 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2150 * It seems that transmitting frames without checking the state of
2151 * Rx/Tx MAC wedge the hardware.
2158 * Set the current media.
2163 * Start the one second MII clock.
2165 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2170 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2171 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2175 device_printf(sc->sc_dev, "interface not running\n");
2179 stge_vlan_setup(struct stge_softc *sc)
2186 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2187 * MC_AutoVLANuntagging bit.
2188 * MC_AutoVLANtagging bit selects which VLAN source to use
2189 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2190 * bit has priority over MC_AutoVLANtagging bit. So we always
2191 * use TFC instead of STGE_VLANTag register.
2193 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2194 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2195 v |= MC_AutoVLANuntagging;
2197 v &= ~MC_AutoVLANuntagging;
2198 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2202 * Stop transmission on the interface.
2205 stge_stop(struct stge_softc *sc)
2208 struct stge_txdesc *txd;
2209 struct stge_rxdesc *rxd;
2213 STGE_LOCK_ASSERT(sc);
2215 * Stop the one second clock.
2217 callout_stop(&sc->sc_tick_ch);
2218 sc->sc_watchdog_timer = 0;
2221 * Disable interrupts.
2223 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2226 * Stop receiver, transmitter, and stats update.
2230 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2231 v |= MC_StatisticsDisable;
2232 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2235 * Stop the transmit and receive DMA.
2238 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2239 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2240 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2241 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2244 * Free RX and TX mbufs still in the queues.
2246 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2247 rxd = &sc->sc_cdata.stge_rxdesc[i];
2248 if (rxd->rx_m != NULL) {
2249 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2250 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2251 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2257 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2258 txd = &sc->sc_cdata.stge_txdesc[i];
2259 if (txd->tx_m != NULL) {
2260 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2261 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2262 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2270 * Mark the interface down and cancel the watchdog timer.
2273 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2278 stge_start_tx(struct stge_softc *sc)
2283 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2284 if ((v & MC_TxEnabled) != 0)
2287 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2288 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2289 for (i = STGE_TIMEOUT; i > 0; i--) {
2291 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2292 if ((v & MC_TxEnabled) != 0)
2296 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2300 stge_start_rx(struct stge_softc *sc)
2305 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2306 if ((v & MC_RxEnabled) != 0)
2309 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2310 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2311 for (i = STGE_TIMEOUT; i > 0; i--) {
2313 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2314 if ((v & MC_RxEnabled) != 0)
2318 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2322 stge_stop_tx(struct stge_softc *sc)
2327 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2328 if ((v & MC_TxEnabled) == 0)
2331 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2332 for (i = STGE_TIMEOUT; i > 0; i--) {
2334 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2335 if ((v & MC_TxEnabled) == 0)
2339 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2343 stge_stop_rx(struct stge_softc *sc)
2348 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2349 if ((v & MC_RxEnabled) == 0)
2352 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2353 for (i = STGE_TIMEOUT; i > 0; i--) {
2355 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2356 if ((v & MC_RxEnabled) == 0)
2360 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2364 stge_init_tx_ring(struct stge_softc *sc)
2366 struct stge_ring_data *rd;
2367 struct stge_txdesc *txd;
2371 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2372 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2374 sc->sc_cdata.stge_tx_prod = 0;
2375 sc->sc_cdata.stge_tx_cons = 0;
2376 sc->sc_cdata.stge_tx_cnt = 0;
2379 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2380 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2381 if (i == (STGE_TX_RING_CNT - 1))
2382 addr = STGE_TX_RING_ADDR(sc, 0);
2384 addr = STGE_TX_RING_ADDR(sc, i + 1);
2385 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2386 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2387 txd = &sc->sc_cdata.stge_txdesc[i];
2388 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2391 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2392 sc->sc_cdata.stge_tx_ring_map,
2393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2398 stge_init_rx_ring(struct stge_softc *sc)
2400 struct stge_ring_data *rd;
2404 sc->sc_cdata.stge_rx_cons = 0;
2405 STGE_RXCHAIN_RESET(sc);
2408 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2409 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2410 if (stge_newbuf(sc, i) != 0)
2412 if (i == (STGE_RX_RING_CNT - 1))
2413 addr = STGE_RX_RING_ADDR(sc, 0);
2415 addr = STGE_RX_RING_ADDR(sc, i + 1);
2416 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2417 rd->stge_rx_ring[i].rfd_status = 0;
2420 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2421 sc->sc_cdata.stge_rx_ring_map,
2422 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2430 * Add a receive buffer to the indicated descriptor.
2433 stge_newbuf(struct stge_softc *sc, int idx)
2435 struct stge_rxdesc *rxd;
2436 struct stge_rfd *rfd;
2438 bus_dma_segment_t segs[1];
2442 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2445 m->m_len = m->m_pkthdr.len = MCLBYTES;
2447 * The hardware requires 4bytes aligned DMA address when JUMBO
2450 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2451 m_adj(m, ETHER_ALIGN);
2453 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2454 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2458 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2460 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2461 if (rxd->rx_m != NULL) {
2462 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2463 BUS_DMASYNC_POSTREAD);
2464 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2466 map = rxd->rx_dmamap;
2467 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2468 sc->sc_cdata.stge_rx_sparemap = map;
2469 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2470 BUS_DMASYNC_PREREAD);
2473 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2474 rfd->rfd_frag.frag_word0 =
2475 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2476 rfd->rfd_status = 0;
2484 * Set up the receive filter.
2487 stge_set_filter(struct stge_softc *sc)
2492 STGE_LOCK_ASSERT(sc);
2496 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2497 mode |= RM_ReceiveUnicast;
2498 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2499 mode |= RM_ReceiveBroadcast;
2501 mode &= ~RM_ReceiveBroadcast;
2502 if ((ifp->if_flags & IFF_PROMISC) != 0)
2503 mode |= RM_ReceiveAllFrames;
2505 mode &= ~RM_ReceiveAllFrames;
2507 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2511 stge_set_multi(struct stge_softc *sc)
2514 struct ifmultiaddr *ifma;
2520 STGE_LOCK_ASSERT(sc);
2524 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2525 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2526 if ((ifp->if_flags & IFF_PROMISC) != 0)
2527 mode |= RM_ReceiveAllFrames;
2528 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2529 mode |= RM_ReceiveMulticast;
2530 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2534 /* clear existing filters. */
2535 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2536 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2539 * Set up the multicast address filter by passing all multicast
2540 * addresses through a CRC generator, and then using the low-order
2541 * 6 bits as an index into the 64 bit multicast hash table. The
2542 * high order bits select the register, while the rest of the bits
2543 * select the bit within the register.
2546 bzero(mchash, sizeof(mchash));
2549 if_maddr_rlock(sc->sc_ifp);
2550 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2551 if (ifma->ifma_addr->sa_family != AF_LINK)
2553 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2554 ifma->ifma_addr), ETHER_ADDR_LEN);
2556 /* Just want the 6 least significant bits. */
2559 /* Set the corresponding bit in the hash table. */
2560 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2563 if_maddr_runlock(ifp);
2565 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2567 mode |= RM_ReceiveMulticastHash;
2569 mode &= ~RM_ReceiveMulticastHash;
2571 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2572 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2573 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2577 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2583 value = *(int *)arg1;
2584 error = sysctl_handle_int(oidp, &value, 0, req);
2585 if (error || !req->newptr)
2587 if (value < low || value > high)
2589 *(int *)arg1 = value;
2595 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2597 return (sysctl_int_range(oidp, arg1, arg2, req,
2598 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2602 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2604 return (sysctl_int_range(oidp, arg1, arg2, req,
2605 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));