1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
40 * Device driver for the Sundance Tech. TC9021 10/100/1000
41 * Ethernet controller.
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #ifdef HAVE_KERNEL_OPTION_HEADERS
48 #include "opt_device_polling.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/endian.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/sysctl.h>
61 #include <sys/taskqueue.h>
64 #include <net/ethernet.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <machine/bus.h>
72 #include <machine/resource.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/mii_bitbang.h>
78 #include <dev/mii/miivar.h>
80 #include <dev/pci/pcireg.h>
81 #include <dev/pci/pcivar.h>
83 #include <dev/stge/if_stgereg.h>
85 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
87 MODULE_DEPEND(stge, pci, 1, 1, 1);
88 MODULE_DEPEND(stge, ether, 1, 1, 1);
89 MODULE_DEPEND(stge, miibus, 1, 1, 1);
91 /* "device miibus" required. See GENERIC if you get errors here. */
92 #include "miibus_if.h"
95 * Devices supported by this driver.
97 static const struct stge_product {
98 uint16_t stge_vendorid;
99 uint16_t stge_deviceid;
100 const char *stge_name;
101 } stge_products[] = {
102 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
103 "Sundance ST-1023 Gigabit Ethernet" },
105 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
106 "Sundance ST-2021 Gigabit Ethernet" },
108 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
109 "Tamarack TC9021 Gigabit Ethernet" },
111 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
112 "Tamarack TC9021 Gigabit Ethernet" },
115 * The Sundance sample boards use the Sundance vendor ID,
116 * but the Tamarack product ID.
118 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
119 "Sundance TC9021 Gigabit Ethernet" },
121 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
122 "Sundance TC9021 Gigabit Ethernet" },
124 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
125 "D-Link DL-4000 Gigabit Ethernet" },
127 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
128 "Antares Gigabit Ethernet" }
131 static int stge_probe(device_t);
132 static int stge_attach(device_t);
133 static int stge_detach(device_t);
134 static int stge_shutdown(device_t);
135 static int stge_suspend(device_t);
136 static int stge_resume(device_t);
138 static int stge_encap(struct stge_softc *, struct mbuf **);
139 static void stge_start(struct ifnet *);
140 static void stge_start_locked(struct ifnet *);
141 static void stge_watchdog(struct stge_softc *);
142 static int stge_ioctl(struct ifnet *, u_long, caddr_t);
143 static void stge_init(void *);
144 static void stge_init_locked(struct stge_softc *);
145 static void stge_vlan_setup(struct stge_softc *);
146 static void stge_stop(struct stge_softc *);
147 static void stge_start_tx(struct stge_softc *);
148 static void stge_start_rx(struct stge_softc *);
149 static void stge_stop_tx(struct stge_softc *);
150 static void stge_stop_rx(struct stge_softc *);
152 static void stge_reset(struct stge_softc *, uint32_t);
153 static int stge_eeprom_wait(struct stge_softc *);
154 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
155 static void stge_tick(void *);
156 static void stge_stats_update(struct stge_softc *);
157 static void stge_set_filter(struct stge_softc *);
158 static void stge_set_multi(struct stge_softc *);
160 static void stge_link_task(void *, int);
161 static void stge_intr(void *);
162 static __inline int stge_tx_error(struct stge_softc *);
163 static void stge_txeof(struct stge_softc *);
164 static int stge_rxeof(struct stge_softc *);
165 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
166 static int stge_newbuf(struct stge_softc *, int);
167 #ifndef __NO_STRICT_ALIGNMENT
168 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
171 static int stge_miibus_readreg(device_t, int, int);
172 static int stge_miibus_writereg(device_t, int, int, int);
173 static void stge_miibus_statchg(device_t);
174 static int stge_mediachange(struct ifnet *);
175 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
177 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
178 static int stge_dma_alloc(struct stge_softc *);
179 static void stge_dma_free(struct stge_softc *);
180 static void stge_dma_wait(struct stge_softc *);
181 static void stge_init_tx_ring(struct stge_softc *);
182 static int stge_init_rx_ring(struct stge_softc *);
183 #ifdef DEVICE_POLLING
184 static int stge_poll(struct ifnet *, enum poll_cmd, int);
187 static void stge_setwol(struct stge_softc *);
188 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
189 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
190 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
195 static uint32_t stge_mii_bitbang_read(device_t);
196 static void stge_mii_bitbang_write(device_t, uint32_t);
198 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
199 stge_mii_bitbang_read,
200 stge_mii_bitbang_write,
202 PC_MgmtData, /* MII_BIT_MDO */
203 PC_MgmtData, /* MII_BIT_MDI */
204 PC_MgmtClk, /* MII_BIT_MDC */
205 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
206 0, /* MII_BIT_DIR_PHY_HOST */
210 static device_method_t stge_methods[] = {
211 /* Device interface */
212 DEVMETHOD(device_probe, stge_probe),
213 DEVMETHOD(device_attach, stge_attach),
214 DEVMETHOD(device_detach, stge_detach),
215 DEVMETHOD(device_shutdown, stge_shutdown),
216 DEVMETHOD(device_suspend, stge_suspend),
217 DEVMETHOD(device_resume, stge_resume),
220 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
221 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
222 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
227 static driver_t stge_driver = {
230 sizeof(struct stge_softc)
233 static devclass_t stge_devclass;
235 DRIVER_MODULE(stge, pci, stge_driver, stge_devclass, 0, 0);
236 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, 0, 0);
238 static struct resource_spec stge_res_spec_io[] = {
239 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
240 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
244 static struct resource_spec stge_res_spec_mem[] = {
245 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
246 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
251 * stge_mii_bitbang_read: [mii bit-bang interface function]
253 * Read the MII serial port for the MII bit-bang module.
256 stge_mii_bitbang_read(device_t dev)
258 struct stge_softc *sc;
261 sc = device_get_softc(dev);
263 val = CSR_READ_1(sc, STGE_PhyCtrl);
264 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
265 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
270 * stge_mii_bitbang_write: [mii big-bang interface function]
272 * Write the MII serial port for the MII bit-bang module.
275 stge_mii_bitbang_write(device_t dev, uint32_t val)
277 struct stge_softc *sc;
279 sc = device_get_softc(dev);
281 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
282 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
283 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
287 * sc_miibus_readreg: [mii interface function]
289 * Read a PHY register on the MII of the TC9021.
292 stge_miibus_readreg(device_t dev, int phy, int reg)
294 struct stge_softc *sc;
297 sc = device_get_softc(dev);
299 if (reg == STGE_PhyCtrl) {
300 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
302 error = CSR_READ_1(sc, STGE_PhyCtrl);
308 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
314 * stge_miibus_writereg: [mii interface function]
316 * Write a PHY register on the MII of the TC9021.
319 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
321 struct stge_softc *sc;
323 sc = device_get_softc(dev);
326 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
332 * stge_miibus_statchg: [mii interface function]
334 * Callback from MII layer when media changes.
337 stge_miibus_statchg(device_t dev)
339 struct stge_softc *sc;
341 sc = device_get_softc(dev);
342 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
346 * stge_mediastatus: [ifmedia interface function]
348 * Get the current interface media status.
351 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
353 struct stge_softc *sc;
354 struct mii_data *mii;
357 mii = device_get_softc(sc->sc_miibus);
360 ifmr->ifm_status = mii->mii_media_status;
361 ifmr->ifm_active = mii->mii_media_active;
365 * stge_mediachange: [ifmedia interface function]
367 * Set hardware to newly-selected media.
370 stge_mediachange(struct ifnet *ifp)
372 struct stge_softc *sc;
373 struct mii_data *mii;
376 mii = device_get_softc(sc->sc_miibus);
383 stge_eeprom_wait(struct stge_softc *sc)
387 for (i = 0; i < STGE_TIMEOUT; i++) {
389 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
398 * Read data from the serial EEPROM.
401 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
404 if (stge_eeprom_wait(sc))
405 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
407 CSR_WRITE_2(sc, STGE_EepromCtrl,
408 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
409 if (stge_eeprom_wait(sc))
410 device_printf(sc->sc_dev, "EEPROM read timed out\n");
411 *data = CSR_READ_2(sc, STGE_EepromData);
416 stge_probe(device_t dev)
418 const struct stge_product *sp;
420 uint16_t vendor, devid;
422 vendor = pci_get_vendor(dev);
423 devid = pci_get_device(dev);
425 for (i = 0; i < sizeof(stge_products)/sizeof(stge_products[0]);
427 if (vendor == sp->stge_vendorid &&
428 devid == sp->stge_deviceid) {
429 device_set_desc(dev, sp->stge_name);
430 return (BUS_PROBE_DEFAULT);
438 stge_attach(device_t dev)
440 struct stge_softc *sc;
442 uint8_t enaddr[ETHER_ADDR_LEN];
448 sc = device_get_softc(dev);
451 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
453 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
454 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
455 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
460 pci_enable_busmaster(dev);
461 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
462 val = pci_read_config(dev, PCIR_BAR(1), 4);
463 if ((val & 0x01) != 0)
464 sc->sc_spec = stge_res_spec_mem;
466 val = pci_read_config(dev, PCIR_BAR(0), 4);
467 if ((val & 0x01) == 0) {
468 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
472 sc->sc_spec = stge_res_spec_io;
474 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
476 device_printf(dev, "couldn't allocate %s resources\n",
477 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
480 sc->sc_rev = pci_get_revid(dev);
482 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
483 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
484 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
485 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
489 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
490 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
492 /* Pull in device tunables. */
493 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
494 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
495 "rxint_nframe", &sc->sc_rxint_nframe);
497 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
498 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
499 device_printf(dev, "rxint_nframe value out of range; "
500 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
501 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
505 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
506 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
507 "rxint_dmawait", &sc->sc_rxint_dmawait);
509 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
510 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
511 device_printf(dev, "rxint_dmawait value out of range; "
512 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
513 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
517 if ((error = stge_dma_alloc(sc) != 0))
521 * Determine if we're copper or fiber. It affects how we
524 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
529 /* Load LED configuration from EEPROM. */
530 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
533 * Reset the chip to a known state.
536 stge_reset(sc, STGE_RESET_FULL);
540 * Reading the station address from the EEPROM doesn't seem
541 * to work, at least on my sample boards. Instead, since
542 * the reset sequence does AutoInit, read it from the station
543 * address registers. For Sundance 1023 you can only read it
546 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
549 v = CSR_READ_2(sc, STGE_StationAddress0);
550 enaddr[0] = v & 0xff;
552 v = CSR_READ_2(sc, STGE_StationAddress1);
553 enaddr[2] = v & 0xff;
555 v = CSR_READ_2(sc, STGE_StationAddress2);
556 enaddr[4] = v & 0xff;
560 uint16_t myaddr[ETHER_ADDR_LEN / 2];
561 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
562 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
564 myaddr[i] = le16toh(myaddr[i]);
566 bcopy(myaddr, enaddr, sizeof(enaddr));
570 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
572 device_printf(sc->sc_dev, "failed to if_alloc()\n");
578 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
580 ifp->if_ioctl = stge_ioctl;
581 ifp->if_start = stge_start;
582 ifp->if_init = stge_init;
583 ifp->if_mtu = ETHERMTU;
584 ifp->if_snd.ifq_drv_maxlen = STGE_TX_RING_CNT - 1;
585 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
586 IFQ_SET_READY(&ifp->if_snd);
587 /* Revision B3 and earlier chips have checksum bug. */
588 if (sc->sc_rev >= 0x0c) {
589 ifp->if_hwassist = STGE_CSUM_FEATURES;
590 ifp->if_capabilities = IFCAP_HWCSUM;
592 ifp->if_hwassist = 0;
593 ifp->if_capabilities = 0;
595 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
596 ifp->if_capenable = ifp->if_capabilities;
599 * Read some important bits from the PhyCtrl register.
601 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
602 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
604 /* Set up MII bus. */
605 flags = MIIF_DOPAUSE | MIIF_FORCEPAUSE;
606 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
607 flags |= MIIF_MACPRIV0;
608 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
609 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
612 device_printf(sc->sc_dev, "attaching PHYs failed\n");
616 ether_ifattach(ifp, enaddr);
618 /* VLAN capability setup */
619 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
620 if (sc->sc_rev >= 0x0c)
621 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
622 ifp->if_capenable = ifp->if_capabilities;
623 #ifdef DEVICE_POLLING
624 ifp->if_capabilities |= IFCAP_POLLING;
627 * Tell the upper layer(s) we support long frames.
628 * Must appear after the call to ether_ifattach() because
629 * ether_ifattach() sets ifi_hdrlen to the default value.
631 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
634 * The manual recommends disabling early transmit, so we
635 * do. It's disabled anyway, if using IP checksumming,
636 * since the entire packet must be in the FIFO in order
637 * for the chip to perform the checksum.
639 sc->sc_txthresh = 0x0fff;
642 * Disable MWI if the PCI layer tells us to.
645 if ((cmd & PCIM_CMD_MWRICEN) == 0)
646 sc->sc_DMACtrl |= DMAC_MWIDisable;
651 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
652 NULL, stge_intr, sc, &sc->sc_ih);
655 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
668 stge_detach(device_t dev)
670 struct stge_softc *sc;
673 sc = device_get_softc(dev);
676 #ifdef DEVICE_POLLING
677 if (ifp && ifp->if_capenable & IFCAP_POLLING)
678 ether_poll_deregister(ifp);
680 if (device_is_attached(dev)) {
686 callout_drain(&sc->sc_tick_ch);
687 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
691 if (sc->sc_miibus != NULL) {
692 device_delete_child(dev, sc->sc_miibus);
693 sc->sc_miibus = NULL;
695 bus_generic_detach(dev);
704 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
707 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
709 mtx_destroy(&sc->sc_mii_mtx);
710 mtx_destroy(&sc->sc_mtx);
715 struct stge_dmamap_arg {
716 bus_addr_t stge_busaddr;
720 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
722 struct stge_dmamap_arg *ctx;
727 ctx = (struct stge_dmamap_arg *)arg;
728 ctx->stge_busaddr = segs[0].ds_addr;
732 stge_dma_alloc(struct stge_softc *sc)
734 struct stge_dmamap_arg ctx;
735 struct stge_txdesc *txd;
736 struct stge_rxdesc *rxd;
739 /* create parent tag. */
740 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
741 1, 0, /* algnmnt, boundary */
742 STGE_DMA_MAXADDR, /* lowaddr */
743 BUS_SPACE_MAXADDR, /* highaddr */
744 NULL, NULL, /* filter, filterarg */
745 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
747 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
749 NULL, NULL, /* lockfunc, lockarg */
750 &sc->sc_cdata.stge_parent_tag);
752 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
755 /* create tag for Tx ring. */
756 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
757 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
758 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
759 BUS_SPACE_MAXADDR, /* highaddr */
760 NULL, NULL, /* filter, filterarg */
761 STGE_TX_RING_SZ, /* maxsize */
763 STGE_TX_RING_SZ, /* maxsegsize */
765 NULL, NULL, /* lockfunc, lockarg */
766 &sc->sc_cdata.stge_tx_ring_tag);
768 device_printf(sc->sc_dev,
769 "failed to allocate Tx ring DMA tag\n");
773 /* create tag for Rx ring. */
774 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
775 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
776 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
777 BUS_SPACE_MAXADDR, /* highaddr */
778 NULL, NULL, /* filter, filterarg */
779 STGE_RX_RING_SZ, /* maxsize */
781 STGE_RX_RING_SZ, /* maxsegsize */
783 NULL, NULL, /* lockfunc, lockarg */
784 &sc->sc_cdata.stge_rx_ring_tag);
786 device_printf(sc->sc_dev,
787 "failed to allocate Rx ring DMA tag\n");
791 /* create tag for Tx buffers. */
792 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
793 1, 0, /* algnmnt, boundary */
794 BUS_SPACE_MAXADDR, /* lowaddr */
795 BUS_SPACE_MAXADDR, /* highaddr */
796 NULL, NULL, /* filter, filterarg */
797 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
798 STGE_MAXTXSEGS, /* nsegments */
799 MCLBYTES, /* maxsegsize */
801 NULL, NULL, /* lockfunc, lockarg */
802 &sc->sc_cdata.stge_tx_tag);
804 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
808 /* create tag for Rx buffers. */
809 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
810 1, 0, /* algnmnt, boundary */
811 BUS_SPACE_MAXADDR, /* lowaddr */
812 BUS_SPACE_MAXADDR, /* highaddr */
813 NULL, NULL, /* filter, filterarg */
814 MCLBYTES, /* maxsize */
816 MCLBYTES, /* maxsegsize */
818 NULL, NULL, /* lockfunc, lockarg */
819 &sc->sc_cdata.stge_rx_tag);
821 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
825 /* allocate DMA'able memory and load the DMA map for Tx ring. */
826 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
827 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
828 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
830 device_printf(sc->sc_dev,
831 "failed to allocate DMA'able memory for Tx ring\n");
835 ctx.stge_busaddr = 0;
836 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
837 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
838 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
839 if (error != 0 || ctx.stge_busaddr == 0) {
840 device_printf(sc->sc_dev,
841 "failed to load DMA'able memory for Tx ring\n");
844 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
846 /* allocate DMA'able memory and load the DMA map for Rx ring. */
847 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
848 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
849 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
851 device_printf(sc->sc_dev,
852 "failed to allocate DMA'able memory for Rx ring\n");
856 ctx.stge_busaddr = 0;
857 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
858 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
859 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
860 if (error != 0 || ctx.stge_busaddr == 0) {
861 device_printf(sc->sc_dev,
862 "failed to load DMA'able memory for Rx ring\n");
865 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
867 /* create DMA maps for Tx buffers. */
868 for (i = 0; i < STGE_TX_RING_CNT; i++) {
869 txd = &sc->sc_cdata.stge_txdesc[i];
872 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
875 device_printf(sc->sc_dev,
876 "failed to create Tx dmamap\n");
880 /* create DMA maps for Rx buffers. */
881 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
882 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
883 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
886 for (i = 0; i < STGE_RX_RING_CNT; i++) {
887 rxd = &sc->sc_cdata.stge_rxdesc[i];
890 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
893 device_printf(sc->sc_dev,
894 "failed to create Rx dmamap\n");
904 stge_dma_free(struct stge_softc *sc)
906 struct stge_txdesc *txd;
907 struct stge_rxdesc *rxd;
911 if (sc->sc_cdata.stge_tx_ring_tag) {
912 if (sc->sc_cdata.stge_tx_ring_map)
913 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
914 sc->sc_cdata.stge_tx_ring_map);
915 if (sc->sc_cdata.stge_tx_ring_map &&
916 sc->sc_rdata.stge_tx_ring)
917 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
918 sc->sc_rdata.stge_tx_ring,
919 sc->sc_cdata.stge_tx_ring_map);
920 sc->sc_rdata.stge_tx_ring = NULL;
921 sc->sc_cdata.stge_tx_ring_map = 0;
922 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
923 sc->sc_cdata.stge_tx_ring_tag = NULL;
926 if (sc->sc_cdata.stge_rx_ring_tag) {
927 if (sc->sc_cdata.stge_rx_ring_map)
928 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
929 sc->sc_cdata.stge_rx_ring_map);
930 if (sc->sc_cdata.stge_rx_ring_map &&
931 sc->sc_rdata.stge_rx_ring)
932 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
933 sc->sc_rdata.stge_rx_ring,
934 sc->sc_cdata.stge_rx_ring_map);
935 sc->sc_rdata.stge_rx_ring = NULL;
936 sc->sc_cdata.stge_rx_ring_map = 0;
937 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
938 sc->sc_cdata.stge_rx_ring_tag = NULL;
941 if (sc->sc_cdata.stge_tx_tag) {
942 for (i = 0; i < STGE_TX_RING_CNT; i++) {
943 txd = &sc->sc_cdata.stge_txdesc[i];
944 if (txd->tx_dmamap) {
945 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
950 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
951 sc->sc_cdata.stge_tx_tag = NULL;
954 if (sc->sc_cdata.stge_rx_tag) {
955 for (i = 0; i < STGE_RX_RING_CNT; i++) {
956 rxd = &sc->sc_cdata.stge_rxdesc[i];
957 if (rxd->rx_dmamap) {
958 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
963 if (sc->sc_cdata.stge_rx_sparemap) {
964 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
965 sc->sc_cdata.stge_rx_sparemap);
966 sc->sc_cdata.stge_rx_sparemap = 0;
968 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
969 sc->sc_cdata.stge_rx_tag = NULL;
972 if (sc->sc_cdata.stge_parent_tag) {
973 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
974 sc->sc_cdata.stge_parent_tag = NULL;
981 * Make sure the interface is stopped at reboot time.
984 stge_shutdown(device_t dev)
987 return (stge_suspend(dev));
991 stge_setwol(struct stge_softc *sc)
996 STGE_LOCK_ASSERT(sc);
999 v = CSR_READ_1(sc, STGE_WakeEvent);
1000 /* Disable all WOL bits. */
1001 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1002 WE_WakeOnLanEnable);
1003 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1004 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
1005 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1006 /* Reset Tx and prevent transmission. */
1007 CSR_WRITE_4(sc, STGE_AsicCtrl,
1008 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1010 * TC9021 automatically reset link speed to 100Mbps when it's put
1011 * into sleep so there is no need to try to resetting link speed.
1016 stge_suspend(device_t dev)
1018 struct stge_softc *sc;
1020 sc = device_get_softc(dev);
1024 sc->sc_suspended = 1;
1032 stge_resume(device_t dev)
1034 struct stge_softc *sc;
1038 sc = device_get_softc(dev);
1042 * Clear WOL bits, so special frames wouldn't interfere
1043 * normal Rx operation anymore.
1045 v = CSR_READ_1(sc, STGE_WakeEvent);
1046 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1047 WE_WakeOnLanEnable);
1048 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1050 if (ifp->if_flags & IFF_UP)
1051 stge_init_locked(sc);
1053 sc->sc_suspended = 0;
1060 stge_dma_wait(struct stge_softc *sc)
1064 for (i = 0; i < STGE_TIMEOUT; i++) {
1066 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1070 if (i == STGE_TIMEOUT)
1071 device_printf(sc->sc_dev, "DMA wait timed out\n");
1075 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1077 struct stge_txdesc *txd;
1078 struct stge_tfd *tfd;
1080 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1081 int error, i, nsegs, si;
1082 uint64_t csum_flags, tfc;
1084 STGE_LOCK_ASSERT(sc);
1086 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1089 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1090 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1091 if (error == EFBIG) {
1092 m = m_collapse(*m_head, M_DONTWAIT, STGE_MAXTXSEGS);
1099 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1100 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1106 } else if (error != 0)
1116 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1117 if (m->m_pkthdr.csum_flags & CSUM_IP)
1118 csum_flags |= TFD_IPChecksumEnable;
1119 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1120 csum_flags |= TFD_TCPChecksumEnable;
1121 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1122 csum_flags |= TFD_UDPChecksumEnable;
1125 si = sc->sc_cdata.stge_tx_prod;
1126 tfd = &sc->sc_rdata.stge_tx_ring[si];
1127 for (i = 0; i < nsegs; i++)
1128 tfd->tfd_frags[i].frag_word0 =
1129 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1130 FRAG_LEN(txsegs[i].ds_len));
1131 sc->sc_cdata.stge_tx_cnt++;
1133 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1134 TFD_FragCount(nsegs) | csum_flags;
1135 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1136 tfc |= TFD_TxDMAIndicate;
1138 /* Update producer index. */
1139 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1141 /* Check if we have a VLAN tag to insert. */
1142 if (m->m_flags & M_VLANTAG)
1143 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1144 tfd->tfd_control = htole64(tfc);
1146 /* Update Tx Queue. */
1147 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1148 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1151 /* Sync descriptors. */
1152 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1153 BUS_DMASYNC_PREWRITE);
1154 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1155 sc->sc_cdata.stge_tx_ring_map,
1156 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1162 * stge_start: [ifnet interface function]
1164 * Start packet transmission on the interface.
1167 stge_start(struct ifnet *ifp)
1169 struct stge_softc *sc;
1173 stge_start_locked(ifp);
1178 stge_start_locked(struct ifnet *ifp)
1180 struct stge_softc *sc;
1181 struct mbuf *m_head;
1186 STGE_LOCK_ASSERT(sc);
1188 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1189 IFF_DRV_RUNNING || sc->sc_link == 0)
1192 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1193 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1194 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1198 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1202 * Pack the data into the transmit ring. If we
1203 * don't have room, set the OACTIVE flag and wait
1204 * for the NIC to drain the ring.
1206 if (stge_encap(sc, &m_head)) {
1209 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1210 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1216 * If there's a BPF listener, bounce a copy of this frame
1219 ETHER_BPF_MTAP(ifp, m_head);
1224 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1226 /* Set a timeout in case the chip goes out to lunch. */
1227 sc->sc_watchdog_timer = 5;
1234 * Watchdog timer handler.
1237 stge_watchdog(struct stge_softc *sc)
1241 STGE_LOCK_ASSERT(sc);
1243 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1247 if_printf(sc->sc_ifp, "device timeout\n");
1249 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1250 stge_init_locked(sc);
1251 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1252 stge_start_locked(ifp);
1256 * stge_ioctl: [ifnet interface function]
1258 * Handle control requests from the operator.
1261 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1263 struct stge_softc *sc;
1265 struct mii_data *mii;
1269 ifr = (struct ifreq *)data;
1273 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1275 else if (ifp->if_mtu != ifr->ifr_mtu) {
1276 ifp->if_mtu = ifr->ifr_mtu;
1278 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1280 stge_init_locked(sc);
1287 if ((ifp->if_flags & IFF_UP) != 0) {
1288 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1289 if (((ifp->if_flags ^ sc->sc_if_flags)
1290 & IFF_PROMISC) != 0)
1291 stge_set_filter(sc);
1293 if (sc->sc_detach == 0)
1294 stge_init_locked(sc);
1297 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1300 sc->sc_if_flags = ifp->if_flags;
1306 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1312 mii = device_get_softc(sc->sc_miibus);
1313 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1316 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1317 #ifdef DEVICE_POLLING
1318 if ((mask & IFCAP_POLLING) != 0) {
1319 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1320 error = ether_poll_register(stge_poll, ifp);
1324 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1325 ifp->if_capenable |= IFCAP_POLLING;
1328 error = ether_poll_deregister(ifp);
1332 CSR_WRITE_2(sc, STGE_IntEnable,
1334 ifp->if_capenable &= ~IFCAP_POLLING;
1339 if ((mask & IFCAP_HWCSUM) != 0) {
1340 ifp->if_capenable ^= IFCAP_HWCSUM;
1341 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1342 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1343 ifp->if_hwassist = STGE_CSUM_FEATURES;
1345 ifp->if_hwassist = 0;
1347 if ((mask & IFCAP_WOL) != 0 &&
1348 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1349 if ((mask & IFCAP_WOL_MAGIC) != 0)
1350 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1352 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1353 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1354 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1356 stge_vlan_setup(sc);
1360 VLAN_CAPABILITIES(ifp);
1363 error = ether_ioctl(ifp, cmd, data);
1371 stge_link_task(void *arg, int pending)
1373 struct stge_softc *sc;
1374 struct mii_data *mii;
1378 sc = (struct stge_softc *)arg;
1381 mii = device_get_softc(sc->sc_miibus);
1382 if (mii->mii_media_status & IFM_ACTIVE) {
1383 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1389 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1390 sc->sc_MACCtrl |= MC_DuplexSelect;
1391 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1392 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1393 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1394 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1396 * Update STGE_MACCtrl register depending on link status.
1397 * (duplex, flow control etc)
1399 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1400 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1401 v |= sc->sc_MACCtrl;
1402 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1403 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1404 /* Duplex setting changed, reset Tx/Rx functions. */
1405 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1406 ac |= AC_TxReset | AC_RxReset;
1407 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1408 for (i = 0; i < STGE_TIMEOUT; i++) {
1410 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1413 if (i == STGE_TIMEOUT)
1414 device_printf(sc->sc_dev, "reset failed to complete\n");
1420 stge_tx_error(struct stge_softc *sc)
1426 txstat = CSR_READ_4(sc, STGE_TxStatus);
1427 if ((txstat & TS_TxComplete) == 0)
1430 if ((txstat & TS_TxUnderrun) != 0) {
1433 * There should be a more better way to recover
1434 * from Tx underrun instead of a full reset.
1436 if (sc->sc_nerr++ < STGE_MAXERR)
1437 device_printf(sc->sc_dev, "Tx underrun, "
1439 if (sc->sc_nerr == STGE_MAXERR)
1440 device_printf(sc->sc_dev, "too many errors; "
1441 "not reporting any more\n");
1445 /* Maximum/Late collisions, Re-enable Tx MAC. */
1446 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1447 CSR_WRITE_4(sc, STGE_MACCtrl,
1448 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1458 * Interrupt service routine.
1461 stge_intr(void *arg)
1463 struct stge_softc *sc;
1468 sc = (struct stge_softc *)arg;
1473 #ifdef DEVICE_POLLING
1474 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1477 status = CSR_READ_2(sc, STGE_IntStatus);
1478 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1481 /* Disable interrupts. */
1482 for (reinit = 0;;) {
1483 status = CSR_READ_2(sc, STGE_IntStatusAck);
1484 status &= sc->sc_IntEnable;
1487 /* Host interface errors. */
1488 if ((status & IS_HostError) != 0) {
1489 device_printf(sc->sc_dev,
1490 "Host interface error, resetting...\n");
1495 /* Receive interrupts. */
1496 if ((status & IS_RxDMAComplete) != 0) {
1498 if ((status & IS_RFDListEnd) != 0)
1499 CSR_WRITE_4(sc, STGE_DMACtrl,
1503 /* Transmit interrupts. */
1504 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1507 /* Transmission errors.*/
1508 if ((status & IS_TxComplete) != 0) {
1509 if ((reinit = stge_tx_error(sc)) != 0)
1516 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1517 stge_init_locked(sc);
1520 /* Re-enable interrupts. */
1521 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1523 /* Try to get more packets going. */
1524 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1525 stge_start_locked(ifp);
1534 * Helper; handle transmit interrupts.
1537 stge_txeof(struct stge_softc *sc)
1540 struct stge_txdesc *txd;
1544 STGE_LOCK_ASSERT(sc);
1548 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1551 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1552 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1555 * Go through our Tx list and free mbufs for those
1556 * frames which have been transmitted.
1558 for (cons = sc->sc_cdata.stge_tx_cons;;
1559 cons = (cons + 1) % STGE_TX_RING_CNT) {
1560 if (sc->sc_cdata.stge_tx_cnt <= 0)
1562 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1563 if ((control & TFD_TFDDone) == 0)
1565 sc->sc_cdata.stge_tx_cnt--;
1566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1568 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1569 BUS_DMASYNC_POSTWRITE);
1570 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1572 /* Output counter is updated with statistics register */
1575 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1576 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1577 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1579 sc->sc_cdata.stge_tx_cons = cons;
1580 if (sc->sc_cdata.stge_tx_cnt == 0)
1581 sc->sc_watchdog_timer = 0;
1583 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1584 sc->sc_cdata.stge_tx_ring_map,
1585 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1588 static __inline void
1589 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1591 struct stge_rfd *rfd;
1593 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1594 rfd->rfd_status = 0;
1597 #ifndef __NO_STRICT_ALIGNMENT
1599 * It seems that TC9021's DMA engine has alignment restrictions in
1600 * DMA scatter operations. The first DMA segment has no address
1601 * alignment restrictins but the rest should be aligned on 4(?) bytes
1602 * boundary. Otherwise it would corrupt random memory. Since we don't
1603 * know which one is used for the first segment in advance we simply
1604 * don't align at all.
1605 * To avoid copying over an entire frame to align, we allocate a new
1606 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1607 * prepended into the existing mbuf chain.
1609 static __inline struct mbuf *
1610 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1615 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1616 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1617 m->m_data += ETHER_HDR_LEN;
1620 MGETHDR(n, M_DONTWAIT, MT_DATA);
1622 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1623 m->m_data += ETHER_HDR_LEN;
1624 m->m_len -= ETHER_HDR_LEN;
1625 n->m_len = ETHER_HDR_LEN;
1626 M_MOVE_PKTHDR(n, m);
1639 * Helper; handle receive interrupts.
1642 stge_rxeof(struct stge_softc *sc)
1645 struct stge_rxdesc *rxd;
1646 struct mbuf *mp, *m;
1649 int cons, prog, rx_npkts;
1651 STGE_LOCK_ASSERT(sc);
1656 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1657 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1660 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1661 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1662 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1663 status = RFD_RxStatus(status64);
1664 if ((status & RFD_RFDDone) == 0)
1666 #ifdef DEVICE_POLLING
1667 if (ifp->if_capenable & IFCAP_POLLING) {
1668 if (sc->sc_cdata.stge_rxcycles <= 0)
1670 sc->sc_cdata.stge_rxcycles--;
1674 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1678 * If the packet had an error, drop it. Note we count
1679 * the error later in the periodic stats update.
1681 if ((status & RFD_FrameEnd) != 0 && (status &
1682 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1683 RFD_RxAlignmentError | RFD_RxFCSError |
1684 RFD_RxLengthError)) != 0) {
1685 stge_discard_rxbuf(sc, cons);
1686 if (sc->sc_cdata.stge_rxhead != NULL) {
1687 m_freem(sc->sc_cdata.stge_rxhead);
1688 STGE_RXCHAIN_RESET(sc);
1693 * Add a new receive buffer to the ring.
1695 if (stge_newbuf(sc, cons) != 0) {
1697 stge_discard_rxbuf(sc, cons);
1698 if (sc->sc_cdata.stge_rxhead != NULL) {
1699 m_freem(sc->sc_cdata.stge_rxhead);
1700 STGE_RXCHAIN_RESET(sc);
1705 if ((status & RFD_FrameEnd) != 0)
1706 mp->m_len = RFD_RxDMAFrameLen(status) -
1707 sc->sc_cdata.stge_rxlen;
1708 sc->sc_cdata.stge_rxlen += mp->m_len;
1711 if (sc->sc_cdata.stge_rxhead == NULL) {
1712 sc->sc_cdata.stge_rxhead = mp;
1713 sc->sc_cdata.stge_rxtail = mp;
1715 mp->m_flags &= ~M_PKTHDR;
1716 sc->sc_cdata.stge_rxtail->m_next = mp;
1717 sc->sc_cdata.stge_rxtail = mp;
1720 if ((status & RFD_FrameEnd) != 0) {
1721 m = sc->sc_cdata.stge_rxhead;
1722 m->m_pkthdr.rcvif = ifp;
1723 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1725 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1727 STGE_RXCHAIN_RESET(sc);
1731 * Set the incoming checksum information for
1734 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1735 if ((status & RFD_IPDetected) != 0) {
1736 m->m_pkthdr.csum_flags |=
1738 if ((status & RFD_IPError) == 0)
1739 m->m_pkthdr.csum_flags |=
1742 if (((status & RFD_TCPDetected) != 0 &&
1743 (status & RFD_TCPError) == 0) ||
1744 ((status & RFD_UDPDetected) != 0 &&
1745 (status & RFD_UDPError) == 0)) {
1746 m->m_pkthdr.csum_flags |=
1747 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1748 m->m_pkthdr.csum_data = 0xffff;
1752 #ifndef __NO_STRICT_ALIGNMENT
1753 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1754 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1755 STGE_RXCHAIN_RESET(sc);
1760 /* Check for VLAN tagged packets. */
1761 if ((status & RFD_VLANDetected) != 0 &&
1762 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1763 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1764 m->m_flags |= M_VLANTAG;
1769 (*ifp->if_input)(ifp, m);
1773 STGE_RXCHAIN_RESET(sc);
1778 /* Update the consumer index. */
1779 sc->sc_cdata.stge_rx_cons = cons;
1780 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1781 sc->sc_cdata.stge_rx_ring_map,
1782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1787 #ifdef DEVICE_POLLING
1789 stge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1791 struct stge_softc *sc;
1798 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1803 sc->sc_cdata.stge_rxcycles = count;
1804 rx_npkts = stge_rxeof(sc);
1807 if (cmd == POLL_AND_CHECK_STATUS) {
1808 status = CSR_READ_2(sc, STGE_IntStatus);
1809 status &= sc->sc_IntEnable;
1811 if ((status & IS_HostError) != 0) {
1812 device_printf(sc->sc_dev,
1813 "Host interface error, resetting...\n");
1814 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1815 stge_init_locked(sc);
1817 if ((status & IS_TxComplete) != 0) {
1818 if (stge_tx_error(sc) != 0) {
1819 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1820 stge_init_locked(sc);
1827 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1828 stge_start_locked(ifp);
1833 #endif /* DEVICE_POLLING */
1838 * One second timer, used to tick the MII.
1841 stge_tick(void *arg)
1843 struct stge_softc *sc;
1844 struct mii_data *mii;
1846 sc = (struct stge_softc *)arg;
1848 STGE_LOCK_ASSERT(sc);
1850 mii = device_get_softc(sc->sc_miibus);
1853 /* Update statistics counters. */
1854 stge_stats_update(sc);
1857 * Relcaim any pending Tx descriptors to release mbufs in a
1858 * timely manner as we don't generate Tx completion interrupts
1859 * for every frame. This limits the delay to a maximum of one
1862 if (sc->sc_cdata.stge_tx_cnt != 0)
1867 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1871 * stge_stats_update:
1873 * Read the TC9021 statistics counters.
1876 stge_stats_update(struct stge_softc *sc)
1880 STGE_LOCK_ASSERT(sc);
1884 CSR_READ_4(sc,STGE_OctetRcvOk);
1886 ifp->if_ipackets += CSR_READ_4(sc, STGE_FramesRcvdOk);
1888 ifp->if_ierrors += CSR_READ_2(sc, STGE_FramesLostRxErrors);
1890 CSR_READ_4(sc, STGE_OctetXmtdOk);
1892 ifp->if_opackets += CSR_READ_4(sc, STGE_FramesXmtdOk);
1894 ifp->if_collisions +=
1895 CSR_READ_4(sc, STGE_LateCollisions) +
1896 CSR_READ_4(sc, STGE_MultiColFrames) +
1897 CSR_READ_4(sc, STGE_SingleColFrames);
1900 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1901 CSR_READ_2(sc, STGE_FramesWEXDeferal);
1907 * Perform a soft reset on the TC9021.
1910 stge_reset(struct stge_softc *sc, uint32_t how)
1916 STGE_LOCK_ASSERT(sc);
1919 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1922 ac |= AC_TxReset | AC_FIFO;
1926 ac |= AC_RxReset | AC_FIFO;
1929 case STGE_RESET_FULL:
1932 * Only assert RstOut if we're fiber. We need GMII clocks
1933 * to be present in order for the reset to complete on fiber
1936 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1937 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1938 (sc->sc_usefiber ? AC_RstOut : 0);
1942 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1944 /* Account for reset problem at 10Mbps. */
1947 for (i = 0; i < STGE_TIMEOUT; i++) {
1948 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1953 if (i == STGE_TIMEOUT)
1954 device_printf(sc->sc_dev, "reset failed to complete\n");
1956 /* Set LED, from Linux IPG driver. */
1957 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1958 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1959 if ((sc->sc_led & 0x01) != 0)
1961 if ((sc->sc_led & 0x03) != 0)
1962 ac |= AC_LEDModeBit1;
1963 if ((sc->sc_led & 0x08) != 0)
1965 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1967 /* Set PHY, from Linux IPG driver */
1968 v = CSR_READ_1(sc, STGE_PhySet);
1969 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1970 v |= ((sc->sc_led & 0x70) >> 4);
1971 CSR_WRITE_1(sc, STGE_PhySet, v);
1975 * stge_init: [ ifnet interface function ]
1977 * Initialize the interface.
1980 stge_init(void *xsc)
1982 struct stge_softc *sc;
1984 sc = (struct stge_softc *)xsc;
1986 stge_init_locked(sc);
1991 stge_init_locked(struct stge_softc *sc)
1994 struct mii_data *mii;
1999 STGE_LOCK_ASSERT(sc);
2002 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2004 mii = device_get_softc(sc->sc_miibus);
2007 * Cancel any pending I/O.
2012 * Reset the chip to a known state.
2014 stge_reset(sc, STGE_RESET_FULL);
2016 /* Init descriptors. */
2017 error = stge_init_rx_ring(sc);
2019 device_printf(sc->sc_dev,
2020 "initialization failed: no memory for rx buffers\n");
2024 stge_init_tx_ring(sc);
2026 /* Set the station address. */
2027 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2028 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2029 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2030 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2033 * Set the statistics masks. Disable all the RMON stats,
2034 * and disable selected stats in the non-RMON stats registers.
2036 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2037 CSR_WRITE_4(sc, STGE_StatisticsMask,
2038 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2039 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2040 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2043 /* Set up the receive filter. */
2044 stge_set_filter(sc);
2045 /* Program multicast filter. */
2049 * Give the transmit and receive ring to the chip.
2051 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2052 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2053 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2054 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2056 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2057 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2058 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2059 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2062 * Initialize the Tx auto-poll period. It's OK to make this number
2063 * large (255 is the max, but we use 127) -- we explicitly kick the
2064 * transmit engine when there's actually a packet.
2066 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2068 /* ..and the Rx auto-poll period. */
2069 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2071 /* Initialize the Tx start threshold. */
2072 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2074 /* Rx DMA thresholds, from Linux */
2075 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2076 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2078 /* Rx early threhold, from Linux */
2079 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2081 /* Tx DMA thresholds, from Linux */
2082 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2083 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2086 * Initialize the Rx DMA interrupt control register. We
2087 * request an interrupt after every incoming packet, but
2088 * defer it for sc_rxint_dmawait us. When the number of
2089 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2090 * deferring the interrupt, and signal it immediately.
2092 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2093 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2094 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2097 * Initialize the interrupt mask.
2099 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2100 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2101 #ifdef DEVICE_POLLING
2102 /* Disable interrupts if we are polling. */
2103 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
2104 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2107 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2110 * Configure the DMA engine.
2111 * XXX Should auto-tune TxBurstLimit.
2113 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2116 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2117 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2120 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2121 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2124 * Set the maximum frame size.
2126 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2127 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2130 * Initialize MacCtrl -- do it before setting the media,
2131 * as setting the media will actually program the register.
2133 * Note: We have to poke the IFS value before poking
2136 /* Tx/Rx MAC should be disabled before programming IFS.*/
2137 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2139 stge_vlan_setup(sc);
2141 if (sc->sc_rev >= 6) { /* >= B.2 */
2142 /* Multi-frag frame bug work-around. */
2143 CSR_WRITE_2(sc, STGE_DebugCtrl,
2144 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2146 /* Tx Poll Now bug work-around. */
2147 CSR_WRITE_2(sc, STGE_DebugCtrl,
2148 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2149 /* Tx Poll Now bug work-around. */
2150 CSR_WRITE_2(sc, STGE_DebugCtrl,
2151 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2154 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2155 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2156 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2158 * It seems that transmitting frames without checking the state of
2159 * Rx/Tx MAC wedge the hardware.
2166 * Set the current media.
2171 * Start the one second MII clock.
2173 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2178 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2179 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2183 device_printf(sc->sc_dev, "interface not running\n");
2187 stge_vlan_setup(struct stge_softc *sc)
2194 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2195 * MC_AutoVLANuntagging bit.
2196 * MC_AutoVLANtagging bit selects which VLAN source to use
2197 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2198 * bit has priority over MC_AutoVLANtagging bit. So we always
2199 * use TFC instead of STGE_VLANTag register.
2201 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2202 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2203 v |= MC_AutoVLANuntagging;
2205 v &= ~MC_AutoVLANuntagging;
2206 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2210 * Stop transmission on the interface.
2213 stge_stop(struct stge_softc *sc)
2216 struct stge_txdesc *txd;
2217 struct stge_rxdesc *rxd;
2221 STGE_LOCK_ASSERT(sc);
2223 * Stop the one second clock.
2225 callout_stop(&sc->sc_tick_ch);
2226 sc->sc_watchdog_timer = 0;
2229 * Disable interrupts.
2231 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2234 * Stop receiver, transmitter, and stats update.
2238 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2239 v |= MC_StatisticsDisable;
2240 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2243 * Stop the transmit and receive DMA.
2246 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2247 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2248 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2249 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2252 * Free RX and TX mbufs still in the queues.
2254 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2255 rxd = &sc->sc_cdata.stge_rxdesc[i];
2256 if (rxd->rx_m != NULL) {
2257 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2258 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2259 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2265 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2266 txd = &sc->sc_cdata.stge_txdesc[i];
2267 if (txd->tx_m != NULL) {
2268 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2269 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2270 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2278 * Mark the interface down and cancel the watchdog timer.
2281 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2286 stge_start_tx(struct stge_softc *sc)
2291 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2292 if ((v & MC_TxEnabled) != 0)
2295 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2296 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2297 for (i = STGE_TIMEOUT; i > 0; i--) {
2299 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2300 if ((v & MC_TxEnabled) != 0)
2304 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2308 stge_start_rx(struct stge_softc *sc)
2313 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2314 if ((v & MC_RxEnabled) != 0)
2317 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2318 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2319 for (i = STGE_TIMEOUT; i > 0; i--) {
2321 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2322 if ((v & MC_RxEnabled) != 0)
2326 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2330 stge_stop_tx(struct stge_softc *sc)
2335 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2336 if ((v & MC_TxEnabled) == 0)
2339 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2340 for (i = STGE_TIMEOUT; i > 0; i--) {
2342 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2343 if ((v & MC_TxEnabled) == 0)
2347 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2351 stge_stop_rx(struct stge_softc *sc)
2356 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2357 if ((v & MC_RxEnabled) == 0)
2360 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2361 for (i = STGE_TIMEOUT; i > 0; i--) {
2363 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2364 if ((v & MC_RxEnabled) == 0)
2368 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2372 stge_init_tx_ring(struct stge_softc *sc)
2374 struct stge_ring_data *rd;
2375 struct stge_txdesc *txd;
2379 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2380 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2382 sc->sc_cdata.stge_tx_prod = 0;
2383 sc->sc_cdata.stge_tx_cons = 0;
2384 sc->sc_cdata.stge_tx_cnt = 0;
2387 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2388 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2389 if (i == (STGE_TX_RING_CNT - 1))
2390 addr = STGE_TX_RING_ADDR(sc, 0);
2392 addr = STGE_TX_RING_ADDR(sc, i + 1);
2393 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2394 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2395 txd = &sc->sc_cdata.stge_txdesc[i];
2396 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2399 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2400 sc->sc_cdata.stge_tx_ring_map,
2401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2406 stge_init_rx_ring(struct stge_softc *sc)
2408 struct stge_ring_data *rd;
2412 sc->sc_cdata.stge_rx_cons = 0;
2413 STGE_RXCHAIN_RESET(sc);
2416 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2417 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2418 if (stge_newbuf(sc, i) != 0)
2420 if (i == (STGE_RX_RING_CNT - 1))
2421 addr = STGE_RX_RING_ADDR(sc, 0);
2423 addr = STGE_RX_RING_ADDR(sc, i + 1);
2424 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2425 rd->stge_rx_ring[i].rfd_status = 0;
2428 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2429 sc->sc_cdata.stge_rx_ring_map,
2430 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2438 * Add a receive buffer to the indicated descriptor.
2441 stge_newbuf(struct stge_softc *sc, int idx)
2443 struct stge_rxdesc *rxd;
2444 struct stge_rfd *rfd;
2446 bus_dma_segment_t segs[1];
2450 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2453 m->m_len = m->m_pkthdr.len = MCLBYTES;
2455 * The hardware requires 4bytes aligned DMA address when JUMBO
2458 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2459 m_adj(m, ETHER_ALIGN);
2461 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2462 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2466 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2468 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2469 if (rxd->rx_m != NULL) {
2470 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2471 BUS_DMASYNC_POSTREAD);
2472 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2474 map = rxd->rx_dmamap;
2475 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2476 sc->sc_cdata.stge_rx_sparemap = map;
2477 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2478 BUS_DMASYNC_PREREAD);
2481 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2482 rfd->rfd_frag.frag_word0 =
2483 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2484 rfd->rfd_status = 0;
2492 * Set up the receive filter.
2495 stge_set_filter(struct stge_softc *sc)
2500 STGE_LOCK_ASSERT(sc);
2504 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2505 mode |= RM_ReceiveUnicast;
2506 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2507 mode |= RM_ReceiveBroadcast;
2509 mode &= ~RM_ReceiveBroadcast;
2510 if ((ifp->if_flags & IFF_PROMISC) != 0)
2511 mode |= RM_ReceiveAllFrames;
2513 mode &= ~RM_ReceiveAllFrames;
2515 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2519 stge_set_multi(struct stge_softc *sc)
2522 struct ifmultiaddr *ifma;
2528 STGE_LOCK_ASSERT(sc);
2532 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2533 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2534 if ((ifp->if_flags & IFF_PROMISC) != 0)
2535 mode |= RM_ReceiveAllFrames;
2536 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2537 mode |= RM_ReceiveMulticast;
2538 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2542 /* clear existing filters. */
2543 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2544 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2547 * Set up the multicast address filter by passing all multicast
2548 * addresses through a CRC generator, and then using the low-order
2549 * 6 bits as an index into the 64 bit multicast hash table. The
2550 * high order bits select the register, while the rest of the bits
2551 * select the bit within the register.
2554 bzero(mchash, sizeof(mchash));
2557 if_maddr_rlock(sc->sc_ifp);
2558 TAILQ_FOREACH(ifma, &sc->sc_ifp->if_multiaddrs, ifma_link) {
2559 if (ifma->ifma_addr->sa_family != AF_LINK)
2561 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2562 ifma->ifma_addr), ETHER_ADDR_LEN);
2564 /* Just want the 6 least significant bits. */
2567 /* Set the corresponding bit in the hash table. */
2568 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2571 if_maddr_runlock(ifp);
2573 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2575 mode |= RM_ReceiveMulticastHash;
2577 mode &= ~RM_ReceiveMulticastHash;
2579 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2580 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2581 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2585 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2591 value = *(int *)arg1;
2592 error = sysctl_handle_int(oidp, &value, 0, req);
2593 if (error || !req->newptr)
2595 if (value < low || value > high)
2597 *(int *)arg1 = value;
2603 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2605 return (sysctl_int_range(oidp, arg1, arg2, req,
2606 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2610 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2612 return (sysctl_int_range(oidp, arg1, arg2, req,
2613 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));