4 * BY : C.L. Huang (ching@tekram.com.tw)
5 * Erich Chen (erich@tekram.com.tw)
6 * Description: Device Driver for Tekram SCSI adapters
7 * DC395U/UW/F ,DC315/U(TRM-S1040)
8 * DC395U2D/U2W(TRM-S2080)
9 * PCI SCSI Bus Master Host Adapter
10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080)
13 #include <sys/cdefs.h>
14 __FBSDID("$FreeBSD$");
19 * REV# DATE NAME DESCRIPTION
20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM)
21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI
22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free
23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x
24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim
25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug.
26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug.
30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
40 * 3. The name of the author may not be used to endorse or promote products
41 * derived from this software without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * Imported into FreeBSD source repository, and updated to compile under
58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17
62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard
63 * <doginou@ci0.org>, 2002-03-04
66 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/malloc.h>
70 #include <sys/queue.h>
71 #if __FreeBSD_version >= 500000
76 #include <sys/kernel.h>
77 #include <sys/module.h>
82 #include <dev/pci/pcivar.h>
83 #include <dev/pci/pcireg.h>
84 #include <machine/resource.h>
85 #include <machine/bus.h>
89 #include <cam/cam_ccb.h>
90 #include <cam/cam_sim.h>
91 #include <cam/cam_xpt_sim.h>
92 #include <cam/cam_debug.h>
94 #include <cam/scsi/scsi_all.h>
95 #include <cam/scsi/scsi_message.h>
97 #include <dev/trm/trm.h>
99 #define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg)
100 #define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg)
101 #define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg)
102 #define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\
104 #define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\
106 #define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\
109 #define PCI_Vendor_ID_TEKRAM 0x1DE1
110 #define PCI_Device_ID_TRM_S1040 0x0391
111 #define PCI_DEVICEID_TRMS1040 0x03911DE1
112 #define PCI_DEVICEID_TRMS2080 0x03921DE1
115 #define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg)
117 #define TRM_DPRINTF(fmt, arg...) {}
118 #endif /* TRM_DEBUG */
120 static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB);
121 static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
122 static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr);
123 static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB);
124 static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData);
125 static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr);
126 static void NVRAM_trm_wait_30us(PACB pACB);
128 static void trm_Interrupt(void *vpACB);
129 static void trm_DataOutPhase0(PACB pACB, PSRB pSRB,
130 u_int16_t * pscsi_status);
131 static void trm_DataInPhase0(PACB pACB, PSRB pSRB,
132 u_int16_t * pscsi_status);
133 static void trm_CommandPhase0(PACB pACB, PSRB pSRB,
134 u_int16_t * pscsi_status);
135 static void trm_StatusPhase0(PACB pACB, PSRB pSRB,
136 u_int16_t * pscsi_status);
137 static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB,
138 u_int16_t * pscsi_status);
139 static void trm_MsgInPhase0(PACB pACB, PSRB pSRB,
140 u_int16_t * pscsi_status);
141 static void trm_DataOutPhase1(PACB pACB, PSRB pSRB,
142 u_int16_t * pscsi_status);
143 static void trm_DataInPhase1(PACB pACB, PSRB pSRB,
144 u_int16_t * pscsi_status);
145 static void trm_CommandPhase1(PACB pACB, PSRB pSRB,
146 u_int16_t * pscsi_status);
147 static void trm_StatusPhase1(PACB pACB, PSRB pSRB,
148 u_int16_t * pscsi_status);
149 static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB,
150 u_int16_t * pscsi_status);
151 static void trm_MsgInPhase1(PACB pACB, PSRB pSRB,
152 u_int16_t * pscsi_status);
153 static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
154 static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status);
155 static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB);
156 static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir);
157 static void trm_Disconnect(PACB pACB);
158 static void trm_Reselect(PACB pACB);
159 static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB);
160 static void trm_DoingSRB_Done(PACB pACB);
161 static void trm_ScsiRstDetect(PACB pACB);
162 static void trm_ResetSCSIBus(PACB pACB);
163 static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB);
164 static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB);
165 static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB);
166 static void trm_SendSRB(PACB pACB, PSRB pSRB);
167 static int trm_probe(device_t tag);
168 static int trm_attach(device_t tag);
169 static void trm_reset(PACB pACB);
171 static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB);
173 static int trm_initAdapter(PACB pACB, u_int16_t unit);
174 static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,
175 u_int32_t i, u_int32_t j);
176 static int trm_initSRB(PACB pACB);
177 static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit);
178 /* CAM SIM entry points */
179 #define ccb_trmsrb_ptr spriv_ptr0
180 #define ccb_trmacb_ptr spriv_ptr1
181 static void trm_action(struct cam_sim *psim, union ccb *pccb);
182 static void trm_poll(struct cam_sim *psim);
185 static void * trm_SCSI_phase0[] = {
186 trm_DataOutPhase0, /* phase:0 */
187 trm_DataInPhase0, /* phase:1 */
188 trm_CommandPhase0, /* phase:2 */
189 trm_StatusPhase0, /* phase:3 */
190 trm_Nop0, /* phase:4 */
191 trm_Nop1, /* phase:5 */
192 trm_MsgOutPhase0, /* phase:6 */
193 trm_MsgInPhase0, /* phase:7 */
198 * stateV = (void *) trm_SCSI_phase1[phase]
201 static void * trm_SCSI_phase1[] = {
202 trm_DataOutPhase1, /* phase:0 */
203 trm_DataInPhase1, /* phase:1 */
204 trm_CommandPhase1, /* phase:2 */
205 trm_StatusPhase1, /* phase:3 */
206 trm_Nop0, /* phase:4 */
207 trm_Nop1, /* phase:5 */
208 trm_MsgOutPhase1, /* phase:6 */
209 trm_MsgInPhase1, /* phase:7 */
213 NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM];
215 *Fast20: 000 50ns, 20.0 Mbytes/s
216 * 001 75ns, 13.3 Mbytes/s
217 * 010 100ns, 10.0 Mbytes/s
218 * 011 125ns, 8.0 Mbytes/s
219 * 100 150ns, 6.6 Mbytes/s
220 * 101 175ns, 5.7 Mbytes/s
221 * 110 200ns, 5.0 Mbytes/s
222 * 111 250ns, 4.0 Mbytes/s
224 *Fast40: 000 25ns, 40.0 Mbytes/s
225 * 001 50ns, 20.0 Mbytes/s
226 * 010 75ns, 13.3 Mbytes/s
227 * 011 100ns, 10.0 Mbytes/s
228 * 100 125ns, 8.0 Mbytes/s
229 * 101 150ns, 6.6 Mbytes/s
230 * 110 175ns, 5.7 Mbytes/s
231 * 111 200ns, 5.0 Mbytes/s
234 u_int8_t dc395x_clock_period[] = {
235 12,/* 48 ns 20 MB/sec */
236 18,/* 72 ns 13.3 MB/sec */
237 25,/* 100 ns 10.0 MB/sec */
238 31,/* 124 ns 8.0 MB/sec */
239 37,/* 148 ns 6.6 MB/sec */
240 43,/* 172 ns 5.7 MB/sec */
241 50,/* 200 ns 5.0 MB/sec */
242 62 /* 248 ns 4.0 MB/sec */
245 u_int8_t dc395u2x_clock_period[]={
246 10,/* 25 ns 40.0 MB/sec */
247 12,/* 48 ns 20.0 MB/sec */
248 18,/* 72 ns 13.3 MB/sec */
249 25,/* 100 ns 10.0 MB/sec */
250 31,/* 124 ns 8.0 MB/sec */
251 37,/* 148 ns 6.6 MB/sec */
252 43,/* 172 ns 5.7 MB/sec */
253 50,/* 200 ns 5.0 MB/sec */
256 #define dc395x_tinfo_period dc395x_clock_period
257 #define dc395u2x_tinfo_period dc395u2x_clock_period
260 trm_GetSRB(PACB pACB)
266 pSRB = pACB->pFreeSRB;
268 pACB->pFreeSRB = pSRB->pNextSRB;
269 pSRB->pNextSRB = NULL;
276 trm_RewaitSRB0(PDCB pDCB, PSRB pSRB)
282 if ((psrb1 = pDCB->pWaitingSRB)) {
283 pSRB->pNextSRB = psrb1;
284 pDCB->pWaitingSRB = pSRB;
286 pSRB->pNextSRB = NULL;
287 pDCB->pWaitingSRB = pSRB;
288 pDCB->pWaitingLastSRB = pSRB;
294 trm_RewaitSRB(PDCB pDCB, PSRB pSRB)
301 psrb1 = pDCB->pGoingSRB;
304 * if this SRB is GoingSRB
305 * remove this SRB from GoingSRB Q
307 pDCB->pGoingSRB = psrb1->pNextSRB;
310 * if this SRB is not current GoingSRB
311 * remove this SRB from GoingSRB Q
313 while (pSRB != psrb1->pNextSRB)
314 psrb1 = psrb1->pNextSRB;
315 psrb1->pNextSRB = pSRB->pNextSRB;
316 if (pSRB == pDCB->pGoingLastSRB)
317 pDCB->pGoingLastSRB = psrb1;
319 if ((psrb1 = pDCB->pWaitingSRB)) {
321 * if WaitingSRB Q is not NULL
322 * Q back this SRB into WaitingSRB
325 pSRB->pNextSRB = psrb1;
326 pDCB->pWaitingSRB = pSRB;
328 pSRB->pNextSRB = NULL;
329 pDCB->pWaitingSRB = pSRB;
330 pDCB->pWaitingLastSRB = pSRB;
336 trm_DoWaitingSRB(PACB pACB)
343 if (!(pACB->pActiveDCB) &&
344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
345 ptr = pACB->pDCBRunRobin;
347 ptr = pACB->pLinkDCB;
348 pACB->pDCBRunRobin = ptr;
352 pACB->pDCBRunRobin = ptr1->pNextDCB;
353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt)
354 || !(pSRB = ptr1->pWaitingSRB)) {
355 if (pACB->pDCBRunRobin == ptr)
357 ptr1 = ptr1->pNextDCB;
359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) {
361 * If trm_StartSCSI return 0 :
362 * current interrupt status is interrupt enable
363 * It's said that SCSI processor is unoccupied
366 if (ptr1->pWaitingLastSRB == pSRB) {
367 ptr1->pWaitingSRB = NULL;
368 ptr1->pWaitingLastSRB = NULL;
370 ptr1->pWaitingSRB = pSRB->pNextSRB;
371 pSRB->pNextSRB = NULL;
373 ptr1->pGoingLastSRB->pNextSRB = pSRB;
375 ptr1->pGoingSRB = pSRB;
376 ptr1->pGoingLastSRB = pSRB;
387 trm_SRBwaiting(PDCB pDCB, PSRB pSRB)
390 if (pDCB->pWaitingSRB) {
391 pDCB->pWaitingLastSRB->pNextSRB = pSRB;
392 pDCB->pWaitingLastSRB = pSRB;
393 pSRB->pNextSRB = NULL;
395 pDCB->pWaitingSRB = pSRB;
396 pDCB->pWaitingLastSRB = pSRB;
401 trm_get_sense_bufaddr(PACB pACB, PSRB pSRB)
405 offset = pSRB->TagNumber;
406 return (pACB->sense_busaddr +
407 (offset * sizeof(struct scsi_sense_data)));
410 static struct scsi_sense_data *
411 trm_get_sense_buf(PACB pACB, PSRB pSRB)
415 offset = pSRB->TagNumber;
416 return (&pACB->sense_buffers[offset]);
419 trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
425 u_long totalxferlen=0;
430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr;
431 TRM_DPRINTF("trm_ExecuteSRB..........\n");
434 bus_dma_segment_t *end_seg;
437 /* Copy the segments into our SG list */
438 end_seg = dm_segs + nseg;
440 while (dm_segs < end_seg) {
441 psg->address = dm_segs->ds_addr;
442 psg->length = (u_long)dm_segs->ds_len;
443 totalxferlen += dm_segs->ds_len;
447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
448 op = BUS_DMASYNC_PREREAD;
450 op = BUS_DMASYNC_PREWRITE;
452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
455 pSRB->SRBTotalXferLength = totalxferlen;
456 pSRB->SRBSGCount = nseg;
457 pSRB->SRBSGIndex = 0;
458 pSRB->AdaptStatus = 0;
459 pSRB->TargetStatus = 0;
464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
466 if (ccb->ccb_h.status != CAM_REQ_INPROG) {
468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
469 pSRB->pNextSRB = pACB->pFreeSRB;
470 pACB->pFreeSRB = pSRB;
475 ccb->ccb_h.status |= CAM_SIM_QUEUED;
477 /* XXX Need a timeout handler */
478 ccb->ccb_h.timeout_ch = timeout(trmtimeout, (caddr_t)srb, (ccb->ccb_h.timeout * hz) / 1000);
480 trm_SendSRB(pACB, pSRB);
486 trm_SendSRB(PACB pACB, PSRB pSRB)
490 pDCB = pSRB->pSRBDCB;
491 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB)
492 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) {
493 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt);
494 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt);
495 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB);
496 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag);
497 trm_SRBwaiting(pDCB, pSRB);
501 if (pDCB->pWaitingSRB) {
502 trm_SRBwaiting(pDCB, pSRB);
503 pSRB = pDCB->pWaitingSRB;
504 pDCB->pWaitingSRB = pSRB->pNextSRB;
505 pSRB->pNextSRB = NULL;
508 if (!trm_StartSCSI(pACB, pDCB, pSRB)) {
510 * If trm_StartSCSI return 0 :
511 * current interrupt status is interrupt enable
512 * It's said that SCSI processor is unoccupied
514 pDCB->GoingSRBCnt++; /* stack waiting SRB*/
515 if (pDCB->pGoingSRB) {
516 pDCB->pGoingLastSRB->pNextSRB = pSRB;
517 pDCB->pGoingLastSRB = pSRB;
519 pDCB->pGoingSRB = pSRB;
520 pDCB->pGoingLastSRB = pSRB;
524 * If trm_StartSCSI return 1 :
525 * current interrupt status is interrupt disreenable
526 * It's said that SCSI processor has more one SRB need to do
528 trm_RewaitSRB0(pDCB, pSRB);
536 trm_action(struct cam_sim *psim, union ccb *pccb)
540 u_int target_id,target_lun;
542 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n"));
544 actionflags = splcam();
545 pACB = (PACB) cam_sim_softc(psim);
546 target_id = pccb->ccb_h.target_id;
547 target_lun = pccb->ccb_h.target_lun;
549 switch (pccb->ccb_h.func_code) {
551 TRM_DPRINTF(" XPT_NOOP \n");
552 pccb->ccb_h.status = CAM_REQ_INVALID;
556 * Execute the requested I/O operation
561 struct ccb_scsiio *pcsio;
564 TRM_DPRINTF(" XPT_SCSI_IO \n");
565 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n"
566 ,target_id, target_lun);
568 "pACB->scan_devices[target_id][target_lun]= %d \n"
569 ,pACB->scan_devices[target_id][target_lun]);
570 if ((pccb->ccb_h.status & CAM_STATUS_MASK) !=
576 pDCB = &pACB->DCBarray[target_id][target_lun];
577 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) {
578 pACB->scan_devices[target_id][target_lun] = 1;
579 trm_initDCB(pACB, pDCB, pACB->AdapterUnit,
580 target_id, target_lun);
583 * Assign an SRB and connect it with this ccb.
585 pSRB = trm_GetSRB(pACB);
588 pccb->ccb_h.status = CAM_RESRC_UNAVAIL;
593 pSRB->pSRBDCB = pDCB;
594 pccb->ccb_h.ccb_trmsrb_ptr = pSRB;
595 pccb->ccb_h.ccb_trmacb_ptr = pACB;
597 pSRB->ScsiCmdLen = pcsio->cdb_len;
599 * move layer of CAM command block to layer of SCSI
600 * Request Block for SCSI processor command doing
602 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
603 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
604 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock
607 pccb->ccb_h.status = CAM_REQ_INVALID;
608 pSRB->pNextSRB = pACB->pFreeSRB;
609 pACB->pFreeSRB= pSRB;
615 bcopy(pcsio->cdb_io.cdb_bytes,
616 pSRB->CmdBlock, pcsio->cdb_len);
617 if ((pccb->ccb_h.flags & CAM_DIR_MASK)
619 if ((pccb->ccb_h.flags &
620 CAM_SCATTER_VALID) == 0) {
621 if ((pccb->ccb_h.flags
622 & CAM_DATA_PHYS) == 0) {
626 vmflags = splsoftvm();
627 error = bus_dmamap_load(
635 if (error == EINPROGRESS) {
639 pccb->ccb_h.status |=
644 struct bus_dma_segment seg;
646 /* Pointer to physical buffer */
648 (bus_addr_t)pcsio->data_ptr;
649 seg.ds_len = pcsio->dxfer_len;
650 trm_ExecuteSRB(pSRB, &seg, 1,
654 /* CAM_SCATTER_VALID */
655 struct bus_dma_segment *segs;
657 if ((pccb->ccb_h.flags &
658 CAM_SG_LIST_PHYS) == 0 ||
660 & CAM_DATA_PHYS) != 0) {
661 pSRB->pNextSRB = pACB->pFreeSRB;
662 pACB->pFreeSRB = pSRB;
670 /* cam SG list is physical,
671 * cam data is virtual
673 segs = (struct bus_dma_segment *)
675 trm_ExecuteSRB(pSRB, segs,
676 pcsio->sglist_cnt, 1);
677 } /* CAM_SCATTER_VALID */
679 trm_ExecuteSRB(pSRB, NULL, 0, 0);
683 TRM_DPRINTF(" XPT_GDEV_TYPE \n");
684 pccb->ccb_h.status = CAM_REQ_INVALID;
688 TRM_DPRINTF(" XPT_GDEVLIST \n");
689 pccb->ccb_h.status = CAM_REQ_INVALID;
693 * Path routing inquiry
697 struct ccb_pathinq *cpi = &pccb->cpi;
699 TRM_DPRINTF(" XPT_PATH_INQ \n");
700 cpi->version_num = 1;
701 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16;
702 cpi->target_sprt = 0;
704 cpi->hba_eng_cnt = 0;
705 cpi->max_target = 15 ;
706 cpi->max_lun = pACB->max_lun; /* 7 or 0 */
707 cpi->initiator_id = pACB->AdaptSCSIID;
708 cpi->bus_id = cam_sim_bus(psim);
709 cpi->base_transfer_speed = 3300;
710 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
711 strncpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN);
712 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
713 cpi->unit_number = cam_sim_unit(psim);
714 cpi->transport = XPORT_SPI;
715 cpi->transport_version = 2;
716 cpi->protocol = PROTO_SCSI;
717 cpi->protocol_version = SCSI_REV_2;
718 cpi->ccb_h.status = CAM_REQ_CMP;
723 * Release a frozen SIM queue
727 TRM_DPRINTF(" XPT_REL_SIMQ \n");
728 pccb->ccb_h.status = CAM_REQ_INVALID;
732 * Set Asynchronous Callback Parameters
733 * Set Asynchronous Callback CCB
736 TRM_DPRINTF(" XPT_SASYNC_CB \n");
737 pccb->ccb_h.status = CAM_REQ_INVALID;
741 * Set device type information
742 * Set Device Type CCB
745 TRM_DPRINTF(" XPT_SDEV_TYPE \n");
746 pccb->ccb_h.status = CAM_REQ_INVALID;
750 * Get EDT entries matching the given pattern
753 TRM_DPRINTF(" XPT_DEV_MATCH \n");
754 pccb->ccb_h.status = CAM_REQ_INVALID;
758 * Turn on debugging for a bus, target or lun
761 TRM_DPRINTF(" XPT_DEBUG \n");
762 pccb->ccb_h.status = CAM_REQ_INVALID;
766 * XPT_ABORT = 0x10, Abort the specified CCB
767 * Abort XPT request CCB
770 TRM_DPRINTF(" XPT_ABORT \n");
771 pccb->ccb_h.status = CAM_REQ_INVALID;
775 * Reset the specified SCSI bus
778 case XPT_RESET_BUS: {
781 TRM_DPRINTF(" XPT_RESET_BUS \n");
784 for (i=0; i<500; i++)
786 pccb->ccb_h.status = CAM_REQ_CMP;
791 * Bus Device Reset the specified SCSI device
792 * Reset SCSI Device CCB
796 * Don't (yet?) support vendor
799 TRM_DPRINTF(" XPT_RESET_DEV \n");
800 pccb->ccb_h.status = CAM_REQ_INVALID;
804 * Terminate the I/O process
805 * Terminate I/O Process Request CCB
808 TRM_DPRINTF(" XPT_TERM_IO \n");
809 pccb->ccb_h.status = CAM_REQ_INVALID;
813 * Get/Set transfer rate/width/disconnection/tag queueing
815 * (GET) default/user transfer settings for the target
817 case XPT_GET_TRAN_SETTINGS: {
818 struct ccb_trans_settings *cts = &pccb->cts;
820 struct trm_transinfo *tinfo;
822 struct ccb_trans_settings_scsi *scsi =
823 &cts->proto_specific.scsi;
824 struct ccb_trans_settings_spi *spi =
825 &cts->xport_specific.spi;
827 cts->protocol = PROTO_SCSI;
828 cts->protocol_version = SCSI_REV_2;
829 cts->transport = XPORT_SPI;
830 cts->transport_version = 2;
832 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n");
833 pDCB = &pACB->DCBarray[target_id][target_lun];
838 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
839 /* current transfer settings */
840 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB)
841 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
843 spi->flags = 0;/* no tag & disconnect */
844 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB)
845 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
846 tinfo = &pDCB->tinfo.current;
847 TRM_DPRINTF("CURRENT: cts->flags= %2x \n",
850 /* default(user) transfer settings */
851 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB)
852 spi->flags = CTS_SPI_FLAGS_DISC_ENB;
855 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB)
856 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
857 tinfo = &pDCB->tinfo.user;
858 TRM_DPRINTF("USER: cts->flags= %2x \n",
861 spi->sync_period = tinfo->period;
862 spi->sync_offset = tinfo->offset;
863 spi->bus_width = tinfo->width;
864 TRM_DPRINTF("pDCB->SyncPeriod: %d \n",
866 TRM_DPRINTF("period: %d \n", tinfo->period);
867 TRM_DPRINTF("offset: %d \n", tinfo->offset);
868 TRM_DPRINTF("width: %d \n", tinfo->width);
871 spi->valid = CTS_SPI_VALID_SYNC_RATE |
872 CTS_SPI_VALID_SYNC_OFFSET |
873 CTS_SPI_VALID_BUS_WIDTH |
875 scsi->valid = CTS_SCSI_VALID_TQ;
876 pccb->ccb_h.status = CAM_REQ_CMP;
881 * Get/Set transfer rate/width/disconnection/tag queueing
883 * (Set) transfer rate/width negotiation settings
885 case XPT_SET_TRAN_SETTINGS: {
886 struct ccb_trans_settings *cts = &pccb->cts;
890 struct ccb_trans_settings_scsi *scsi =
891 &cts->proto_specific.scsi;
892 struct ccb_trans_settings_spi *spi =
893 &cts->xport_specific.spi;
895 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n");
897 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
898 update_type |= TRM_TRANS_GOAL;
899 if (cts->type == CTS_TYPE_USER_SETTINGS)
900 update_type |= TRM_TRANS_USER;
902 pDCB = &pACB->DCBarray[target_id][target_lun];
904 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
905 /*ccb disc enables */
906 if (update_type & TRM_TRANS_GOAL) {
907 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
912 pDCB->tinfo.disc_tag &=
915 if (update_type & TRM_TRANS_USER) {
916 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB)
921 pDCB->tinfo.disc_tag &=
925 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
926 /* if ccb tag q active */
927 if (update_type & TRM_TRANS_GOAL) {
928 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
930 pDCB->tinfo.disc_tag |=
933 pDCB->tinfo.disc_tag &=
936 if (update_type & TRM_TRANS_USER) {
937 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)
939 pDCB->tinfo.disc_tag |=
942 pDCB->tinfo.disc_tag &=
946 /* Minimum sync period factor */
948 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) {
949 /* if ccb sync active */
950 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */
951 if ((spi->sync_period != 0) &&
952 (spi->sync_period < 125))
953 spi->sync_period = 125;
954 /* 1/(125*4) minsync 2 MByte/sec */
955 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET)
957 if (spi->sync_offset == 0)
958 spi->sync_period = 0;
959 /* TRM-S1040 MaxSyncOffset = 15 bytes*/
960 if (spi->sync_offset > 15)
961 spi->sync_offset = 15;
964 if ((update_type & TRM_TRANS_USER) != 0) {
965 pDCB->tinfo.user.period = spi->sync_period;
966 pDCB->tinfo.user.offset = spi->sync_offset;
967 pDCB->tinfo.user.width = spi->bus_width;
969 if ((update_type & TRM_TRANS_GOAL) != 0) {
970 pDCB->tinfo.goal.period = spi->sync_period;
971 pDCB->tinfo.goal.offset = spi->sync_offset;
972 pDCB->tinfo.goal.width = spi->bus_width;
975 pccb->ccb_h.status = CAM_REQ_CMP;
980 * Calculate the geometry parameters for a device give
981 * the sector size and volume size.
983 case XPT_CALC_GEOMETRY:
984 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n");
985 cam_calc_geometry(&pccb->ccg, /*extended*/1);
989 TRM_DPRINTF(" XPT_ENG_INQ \n");
990 pccb->ccb_h.status = CAM_REQ_INVALID;
994 * HBA execute engine request
995 * This structure must match SCSIIO size
998 TRM_DPRINTF(" XPT_ENG_EXEC \n");
999 pccb->ccb_h.status = CAM_REQ_INVALID;
1003 * XPT_EN_LUN = 0x30, Enable LUN as a target
1004 * Target mode structures.
1008 * Don't (yet?) support vendor
1009 * specific commands.
1011 TRM_DPRINTF(" XPT_EN_LUN \n");
1012 pccb->ccb_h.status = CAM_REQ_INVALID;
1016 * Execute target I/O request
1020 * Don't (yet?) support vendor
1021 * specific commands.
1023 TRM_DPRINTF(" XPT_TARGET_IO \n");
1024 pccb->ccb_h.status = CAM_REQ_INVALID;
1028 * Accept Host Target Mode CDB
1030 case XPT_ACCEPT_TARGET_IO:
1032 * Don't (yet?) support vendor
1033 * specific commands.
1035 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n");
1036 pccb->ccb_h.status = CAM_REQ_INVALID;
1040 * Continue Host Target I/O Connection
1042 case XPT_CONT_TARGET_IO:
1044 * Don't (yet?) support vendor
1045 * specific commands.
1047 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n");
1048 pccb->ccb_h.status = CAM_REQ_INVALID;
1052 * Notify Host Target driver of event
1054 case XPT_IMMED_NOTIFY:
1055 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n");
1056 pccb->ccb_h.status = CAM_REQ_INVALID;
1060 * Acknowledgement of event
1062 case XPT_NOTIFY_ACK:
1063 TRM_DPRINTF(" XPT_NOTIFY_ACK \n");
1064 pccb->ccb_h.status = CAM_REQ_INVALID;
1068 * XPT_VUNIQUE = 0x80
1071 pccb->ccb_h.status = CAM_REQ_INVALID;
1075 pccb->ccb_h.status = CAM_REQ_INVALID;
1083 trm_poll(struct cam_sim *psim)
1085 trm_Interrupt(cam_sim_softc(psim));
1089 trm_ResetDevParam(PACB pACB)
1092 PNVRAMTYPE pEEpromBuf;
1093 u_int8_t PeriodIndex;
1095 pDCB = pACB->pLinkDCB;
1100 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE);
1101 pDCB->SyncPeriod = 0;
1102 pDCB->SyncOffset = 0;
1103 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit];
1105 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0;
1106 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
1108 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07;
1109 if (pACB->AdaptType == 1) /* is U2? */
1110 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex];
1112 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex];
1113 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
1114 (pACB->Config & HCC_WIDE_CARD))
1115 pDCB->SyncMode |= WIDE_NEGO_ENABLE;
1116 pDCB = pDCB->pNextDCB;
1118 while (pdcb != pDCB);
1122 trm_RecoverSRB(PACB pACB)
1128 pDCB = pACB->pLinkDCB;
1133 cnt = pdcb->GoingSRBCnt;
1134 psrb = pdcb->pGoingSRB;
1135 for (i = 0; i < cnt; i++) {
1137 psrb = psrb->pNextSRB;
1138 if (pdcb->pWaitingSRB) {
1139 psrb2->pNextSRB = pdcb->pWaitingSRB;
1140 pdcb->pWaitingSRB = psrb2;
1142 pdcb->pWaitingSRB = psrb2;
1143 pdcb->pWaitingLastSRB = psrb2;
1144 psrb2->pNextSRB = NULL;
1147 pdcb->GoingSRBCnt = 0;
1148 pdcb->pGoingSRB = NULL;
1149 pdcb = pdcb->pNextDCB;
1151 while (pdcb != pDCB);
1155 trm_reset(PACB pACB)
1160 TRM_DPRINTF("trm: RESET");
1162 trm_reg_write8(0x00, TRMREG_DMA_INTEN);
1163 trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
1165 trm_ResetSCSIBus(pACB);
1166 for (i = 0; i < 500; i++)
1168 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
1169 /* Enable DMA interrupt */
1170 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
1171 /* Clear DMA FIFO */
1172 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1173 /* Clear SCSI FIFO */
1174 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
1175 trm_ResetDevParam(pACB);
1176 trm_DoingSRB_Done(pACB);
1177 pACB->pActiveDCB = NULL;
1178 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */
1179 trm_DoWaitingSRB(pACB);
1180 /* Tell the XPT layer that a bus reset occured */
1181 if (pACB->ppath != NULL)
1182 xpt_async(AC_BUS_RESET, pACB->ppath, NULL);
1188 trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB)
1190 u_int16_t return_code;
1191 u_int8_t scsicommand, i,command,identify_message;
1194 struct ccb_scsiio *pcsio;
1197 pcsio = &pccb->csio;
1199 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID);
1200 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID);
1201 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC);
1202 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET);
1203 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */
1205 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1207 identify_message = pDCB->IdentifyMsg;
1209 if ((pSRB->CmdBlock[0] == INQUIRY) ||
1210 (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1211 (pSRB->SRBFlag & AUTO_REQSENSE)) {
1212 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) &&
1213 !(pDCB->SyncMode & WIDE_NEGO_DONE))
1214 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) &&
1215 !(pDCB->SyncMode & SYNC_NEGO_DONE))) {
1216 if (!(pDCB->IdentifyMsg & 7) ||
1217 (pSRB->CmdBlock[0] != INQUIRY)) {
1218 scsicommand = SCMD_SEL_ATNSTOP;
1219 pSRB->SRBState = SRB_MSGOUT;
1224 * Send identify message
1226 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO);
1227 scsicommand = SCMD_SEL_ATN;
1228 pSRB->SRBState = SRB_START_;
1230 /* not inquiry,request sense,auto request sense */
1232 * Send identify message
1234 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO);
1235 scsicommand = SCMD_SEL_ATN;
1236 pSRB->SRBState = SRB_START_;
1237 if (pDCB->SyncMode & EN_TAG_QUEUING) {
1238 /* Send Tag message */
1239 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO);
1240 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO);
1241 scsicommand = SCMD_SEL_ATN3;
1246 * Send CDB ..command block .........
1248 if (pSRB->SRBFlag & AUTO_REQSENSE) {
1249 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1250 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1251 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1252 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1253 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1254 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1256 ptr = (u_int8_t *) pSRB->CmdBlock;
1257 for (i = 0; i < pSRB->ScsiCmdLen ; i++) {
1259 trm_reg_write8(command,TRMREG_SCSI_FIFO);
1262 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) {
1264 * If trm_StartSCSI return 1 :
1265 * current interrupt status is interrupt disreenable
1266 * It's said that SCSI processor has more one SRB need to do,
1267 * SCSI processor has been occupied by one SRB.
1269 pSRB->SRBState = SRB_READY;
1273 * If trm_StartSCSI return 0 :
1274 * current interrupt status is interrupt enable
1275 * It's said that SCSI processor is unoccupied
1277 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */
1278 pACB->pActiveDCB = pDCB;
1279 pDCB->pActiveSRB = pSRB;
1281 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT,
1282 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
1286 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND);
1288 return (return_code);
1292 trm_Interrupt(vpACB)
1299 void (*stateV)(PACB, PSRB, u_int16_t *);
1300 u_int16_t scsi_status=0;
1301 u_int8_t scsi_intstatus;
1305 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS);
1306 if (!(scsi_status & SCSIINTERRUPT)) {
1307 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......");
1310 TRM_DPRINTF("scsi_status=%2x,",scsi_status);
1312 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS);
1314 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus);
1316 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) {
1317 trm_Disconnect(pACB);
1321 if (scsi_intstatus & INT_RESELECTED) {
1325 if (scsi_intstatus & INT_SCSIRESET) {
1326 trm_ScsiRstDetect(pACB);
1330 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) {
1331 pDCB = pACB->pActiveDCB;
1332 KASSERT(pDCB != NULL, ("no active DCB"));
1333 pSRB = pDCB->pActiveSRB;
1334 if (pDCB->DCBFlag & ABORT_DEV_)
1335 trm_EnableMsgOutAbort1(pACB, pSRB);
1336 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */
1337 stateV = (void *) trm_SCSI_phase0[phase];
1338 stateV(pACB, pSRB, &scsi_status);
1339 pSRB->ScsiPhase = scsi_status & PHASEMASK;
1340 /* phase:0,1,2,3,4,5,6,7 */
1341 phase = (u_int16_t) scsi_status & PHASEMASK;
1342 stateV = (void *) trm_SCSI_phase1[phase];
1343 stateV(pACB, pSRB, &scsi_status);
1348 trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1351 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT))
1352 *pscsi_status = PH_BUS_FREE;
1353 /*.. initial phase*/
1357 trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1364 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1365 pDCB = pACB->pActiveDCB;
1366 if (!(pSRB->SRBState & SRB_MSGOUT)) {
1369 ptr = (u_int8_t *) pSRB->MsgOutBuf;
1370 for (i = 0; i < cnt; i++) {
1371 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1375 if ((pDCB->DCBFlag & ABORT_DEV_) &&
1376 (pSRB->MsgOutBuf[0] == MSG_ABORT)) {
1377 pSRB->SRBState = SRB_ABORT_SENT;
1381 if ((pSRB->CmdBlock[0] == INQUIRY) ||
1382 (pSRB->CmdBlock[0] == REQUEST_SENSE) ||
1383 (pSRB->SRBFlag & AUTO_REQSENSE)) {
1384 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1388 trm_reg_write8(bval, TRMREG_SCSI_FIFO);
1391 mop1: /* message out phase */
1392 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO)
1393 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) {
1395 * WIDE DATA TRANSFER REQUEST code (03h)
1397 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP);
1398 trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1400 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1402 trm_reg_write8(2,TRMREG_SCSI_FIFO);
1403 /* Message length (02h) */
1404 trm_reg_write8(3,TRMREG_SCSI_FIFO);
1405 /* wide data xfer (03h) */
1406 trm_reg_write8(1,TRMREG_SCSI_FIFO);
1407 /* width:0(8bit),1(16bit),2(32bit) */
1408 pSRB->SRBState |= SRB_DO_WIDE_NEGO;
1409 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO)
1410 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) {
1412 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h)
1414 if (!(pDCB->SyncMode & WIDE_NEGO_DONE))
1415 trm_reg_write8((pDCB->IdentifyMsg & 0xBF),
1417 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO);
1419 trm_reg_write8(3,TRMREG_SCSI_FIFO);
1420 /* Message length (03h) */
1421 trm_reg_write8(1,TRMREG_SCSI_FIFO);
1422 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */
1423 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO);
1424 /* Transfer peeriod factor */
1425 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15,
1427 /* REQ/ACK offset */
1428 pSRB->SRBState |= SRB_DO_SYNC_NEGO;
1431 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1432 /* it's important for atn stop */
1436 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1440 trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1446 trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1452 struct ccb_scsiio *pcsio;
1455 pcsio = &pccb->csio;
1457 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL);
1458 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) {
1459 cnt = (u_int16_t) pSRB->ScsiCmdLen;
1460 ptr = (u_int8_t *) pSRB->CmdBlock;
1461 for (i = 0; i < cnt; i++) {
1462 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO);
1466 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO);
1467 pDCB = pACB->pActiveDCB;
1469 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO);
1470 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1471 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1472 /* sizeof(struct scsi_sense_data) */
1473 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO);
1474 trm_reg_write8(0, TRMREG_SCSI_FIFO);
1476 pSRB->SRBState = SRB_COMMAND;
1477 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1478 /* it's important for atn stop*/
1482 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND);
1486 trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1489 u_int8_t TempDMAstatus,SGIndexTemp;
1490 u_int16_t scsi_status;
1492 u_long TempSRBXferredLength,dLeftCounter=0;
1494 pDCB = pSRB->pSRBDCB;
1495 scsi_status = *pscsi_status;
1497 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1498 if (scsi_status & PARITYERROR)
1499 pSRB->SRBStatus |= PARITY_ERROR;
1500 if (!(scsi_status & SCSIXFERDONE)) {
1502 * when data transfer from DMA FIFO to SCSI FIFO
1503 * if there was some data left in SCSI FIFO
1505 dLeftCounter = (u_long)
1506 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F);
1507 if (pDCB->SyncPeriod & WIDE_SYNC) {
1509 * if WIDE scsi SCSI FIFOCNT unit is word
1516 * caculate all the residue data that not yet tranfered
1517 * SCSI transfer counter + left in SCSI FIFO data
1519 * .....TRM_SCSI_COUNTER (24bits)
1520 * The counter always decrement by one for every SCSI byte
1522 * .....TRM_SCSI_FIFOCNT (5bits)
1523 * The counter is SCSI FIFO offset counter
1525 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1526 if (dLeftCounter == 1) {
1528 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
1530 if ((dLeftCounter == 0) ||
1531 (scsi_status & SCSIXFERCNT_2_ZERO)) {
1532 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1533 while (!(TempDMAstatus & DMAXFERCOMP)) {
1535 trm_reg_read8(TRMREG_DMA_STATUS);
1537 pSRB->SRBTotalXferLength = 0;
1539 /* Update SG list */
1541 * if transfer not yet complete
1542 * there were some data residue in SCSI FIFO or
1543 * SCSI transfer counter not empty
1545 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1547 * data that had transferred length
1549 TempSRBXferredLength =
1550 pSRB->SRBTotalXferLength - dLeftCounter;
1552 * next time to be transferred length
1554 pSRB->SRBTotalXferLength = dLeftCounter;
1556 * parsing from last time disconnect SRBSGIndex
1559 pSRB->pSRBSGL + pSRB->SRBSGIndex;
1560 for (SGIndexTemp = pSRB->SRBSGIndex;
1561 SGIndexTemp < pSRB->SRBSGCount;
1564 * find last time which SG transfer be
1567 if (TempSRBXferredLength >=
1569 TempSRBXferredLength -=
1573 * update last time disconnected SG
1577 TempSRBXferredLength;
1578 /* residue data length */
1580 TempSRBXferredLength;
1581 /* residue data pointer */
1582 pSRB->SRBSGIndex = SGIndexTemp;
1590 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL);
1595 trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1599 * do prepare befor transfer when data out phase
1602 ioDir = XFERDATAOUT;
1603 trm_DataIO_transfer(pACB, pSRB, ioDir);
1607 trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1609 u_int8_t TempDMAstatus, SGIndexTemp;
1610 u_int16_t scsi_status;
1612 u_long TempSRBXferredLength,dLeftCounter = 0;
1614 scsi_status = *pscsi_status;
1615 if (!(pSRB->SRBState & SRB_XFERPAD)) {
1616 if (scsi_status & PARITYERROR)
1617 pSRB->SRBStatus |= PARITY_ERROR;
1618 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER);
1619 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) {
1620 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1621 while (!(TempDMAstatus & DMAXFERCOMP))
1622 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS);
1623 pSRB->SRBTotalXferLength = 0;
1627 * when a transfer not yet complete
1628 * but be disconnected by uper layer
1629 * if transfer not yet complete
1630 * there were some data residue in SCSI FIFO or
1631 * SCSI transfer counter not empty
1633 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1635 * data that had transferred length
1637 TempSRBXferredLength =
1638 pSRB->SRBTotalXferLength - dLeftCounter;
1640 * next time to be transferred length
1642 pSRB->SRBTotalXferLength = dLeftCounter;
1644 * parsing from last time disconnect SRBSGIndex
1646 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex;
1647 for (SGIndexTemp = pSRB->SRBSGIndex;
1648 SGIndexTemp < pSRB->SRBSGCount;
1651 * find last time which SG transfer be disconnect
1653 if (TempSRBXferredLength >= pseg->length)
1654 TempSRBXferredLength -= pseg->length;
1657 * update last time disconnected SG list
1659 pseg->length -= TempSRBXferredLength;
1660 /* residue data length */
1661 pseg->address += TempSRBXferredLength;
1662 /* residue data pointer */
1663 pSRB->SRBSGIndex = SGIndexTemp;
1674 trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1678 * do prepare befor transfer when data in phase
1682 trm_DataIO_transfer(pACB, pSRB, ioDir);
1686 trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir)
1691 pDCB = pSRB->pSRBDCB;
1692 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) {
1693 if (pSRB->SRBTotalXferLength != 0) {
1695 * load what physical address of Scatter/Gather list
1696 table want to be transfer
1698 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address);
1699 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length);
1700 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod);
1701 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL);
1702 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr);
1703 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex);
1704 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount);
1705 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength);
1707 pSRB->SRBState = SRB_DATA_XFER;
1708 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR);
1710 (pSRB->SRBSGPhyAddr +
1711 ((u_long)pSRB->SRBSGIndex << 3)),
1712 TRMREG_DMA_XLOWADDR);
1714 * load how many bytes in the Scatter/Gather
1718 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3),
1721 * load total transfer length (24bits) max value
1724 trm_reg_write32(pSRB->SRBTotalXferLength,
1725 TRMREG_SCSI_COUNTER);
1726 /* Start DMA transfer */
1727 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND);
1728 /* Start SCSI transfer */
1729 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1730 /* it's important for atn stop */
1734 bval = (ioDir == XFERDATAOUT) ?
1735 SCMD_DMA_OUT : SCMD_DMA_IN;
1736 trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1739 if (pSRB->SRBSGCount) {
1740 pSRB->AdaptStatus = H_OVER_UNDER_RUN;
1741 pSRB->SRBStatus |= OVER_RUN;
1743 if (pDCB->SyncPeriod & WIDE_SYNC)
1744 trm_reg_write32(2,TRMREG_SCSI_COUNTER);
1746 trm_reg_write32(1,TRMREG_SCSI_COUNTER);
1747 if (ioDir == XFERDATAOUT)
1748 trm_reg_write16(0, TRMREG_SCSI_FIFO);
1750 trm_reg_read16(TRMREG_SCSI_FIFO);
1751 pSRB->SRBState |= SRB_XFERPAD;
1752 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1753 /* it's important for atn stop */
1757 bval = (ioDir == XFERDATAOUT) ?
1758 SCMD_FIFO_OUT : SCMD_FIFO_IN;
1759 trm_reg_write8(bval, TRMREG_SCSI_COMMAND);
1765 trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1768 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO);
1769 pSRB->SRBState = SRB_COMPLETED;
1770 *pscsi_status = PH_BUS_FREE;
1771 /*.. initial phase*/
1772 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1773 /* it's important for atn stop */
1777 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1783 trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1786 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) {
1787 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1788 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1789 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1790 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1792 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000))
1793 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL);
1794 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40))
1795 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
1797 pSRB->SRBState = SRB_STATUS;
1798 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1799 /* it's important for atn stop */
1803 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND);
1808 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors
1809 * stateV = (void *) trm_SCSI_phase0[phase]
1811 * extended message codes:
1816 * 00h MODIFY DATA POINTER
1817 * 01h SYNCHRONOUS DATA TRANSFER REQUEST
1818 * 03h WIDE DATA TRANSFER REQUEST
1819 * 04h - 7Fh Reserved
1820 * 80h - FFh Vendor specific
1825 trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
1827 u_int8_t message_in_code,bIndex,message_in_tag_id;
1831 pDCB = pACB->pActiveDCB;
1833 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO);
1834 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) {
1835 if (message_in_code == MSG_DISCONNECT) {
1836 pSRB->SRBState = SRB_DISCONNECT;
1837 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1838 /* it's important for atn stop */
1839 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1843 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1845 } else if (message_in_code == MSG_SAVE_PTR) {
1846 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1847 /* it's important for atn stop */
1848 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1852 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1854 } else if ((message_in_code == MSG_EXTENDED) ||
1855 ((message_in_code >= MSG_SIMPLE_QTAG) &&
1856 (message_in_code <= MSG_ORDER_QTAG))) {
1857 pSRB->SRBState |= SRB_EXTEND_MSGIN;
1858 pSRB->MsgInBuf[0] = message_in_code;
1859 /* extended message (01h) */
1861 pSRB->pMsgPtr = &pSRB->MsgInBuf[1];
1862 /* extended message length (n) */
1863 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1864 /* it's important for atn stop */
1865 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1869 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1871 } else if (message_in_code == MSG_REJECT_) {
1872 /* Reject message */
1873 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
1874 /* do wide nego reject */
1875 pDCB = pSRB->pSRBDCB;
1876 pDCB->SyncMode |= WIDE_NEGO_DONE;
1877 pDCB->SyncMode &= ~(SYNC_NEGO_DONE |
1878 EN_ATN_STOP | WIDE_NEGO_ENABLE);
1879 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
1880 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE)
1881 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) {
1882 /* Set ATN, in case ATN was clear */
1883 pSRB->SRBState |= SRB_MSGOUT;
1886 TRMREG_SCSI_CONTROL);
1891 TRMREG_SCSI_CONTROL);
1893 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) {
1894 /* do sync nego reject */
1895 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL);
1896 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) {
1897 pDCB = pSRB->pSRBDCB;
1899 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
1900 pDCB->SyncPeriod = 0;
1901 pDCB->SyncOffset = 0;
1904 * program SCSI control register
1907 trm_reg_write8(pDCB->SyncPeriod,
1909 trm_reg_write8(pDCB->SyncOffset,
1910 TRMREG_SCSI_OFFSET);
1911 trm_SetXferRate(pACB,pSRB,pDCB);
1914 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1915 /* it's important for atn stop */
1916 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1920 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1922 } else if (message_in_code == MSG_IGNOREWIDE) {
1923 trm_reg_write32(1, TRMREG_SCSI_COUNTER);
1924 trm_reg_read8(TRMREG_SCSI_FIFO);
1925 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1926 /* it's important for atn stop */
1927 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1931 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1934 /* Restore data pointer message */
1935 /* Save data pointer message */
1936 /* Completion message */
1938 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
1939 /* it's important for atn stop */
1940 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
1944 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
1949 * Parsing incomming extented messages
1951 *pSRB->pMsgPtr = message_in_code;
1954 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]);
1955 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]);
1956 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]);
1957 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]);
1958 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]);
1959 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG)
1960 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) {
1962 * is QUEUE tag message :
1965 * HEAD QUEUE TAG (20h)
1966 * ORDERED QUEUE TAG (21h)
1967 * SIMPLE QUEUE TAG (22h)
1969 * Queue tag (00h - FFh)
1971 if (pSRB->MsgCnt == 2) {
1973 message_in_tag_id = pSRB->MsgInBuf[1];
1974 pSRB = pDCB->pGoingSRB;
1975 pSRBTemp = pDCB->pGoingLastSRB;
1978 if (pSRB->TagNumber !=
1979 message_in_tag_id) {
1980 if (pSRB == pSRBTemp) {
1983 pSRB = pSRB->pNextSRB;
1987 if (pDCB->DCBFlag & ABORT_DEV_) {
1988 pSRB->SRBState = SRB_ABORT_SENT;
1989 trm_EnableMsgOutAbort1(
1992 if (!(pSRB->SRBState & SRB_DISCONNECT)) {
1993 TRM_DPRINTF("SRB not yet disconnect........ \n ");
1996 pDCB->pActiveSRB = pSRB;
1997 pSRB->SRBState = SRB_DATA_XFER;
2000 pSRB = &pACB->TmpSRB;
2001 pSRB->SRBState = SRB_UNEXPECT_RESEL;
2002 pDCB->pActiveSRB = pSRB;
2003 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG;
2004 trm_EnableMsgOutAbort2(
2009 *pscsi_status = PH_BUS_FREE;
2010 /* .. initial phase */
2011 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2012 /* it's important for atn stop */
2016 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2018 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
2019 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) {
2021 * is Wide data xfer Extended message :
2022 * ======================================
2023 * WIDE DATA TRANSFER REQUEST
2024 * ======================================
2025 * byte 0 : Extended message (01h)
2026 * byte 1 : Extended message length (02h)
2027 * byte 2 : WIDE DATA TRANSFER code (03h)
2028 * byte 3 : Transfer width exponent
2030 pDCB = pSRB->pSRBDCB;
2031 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO);
2032 if ((pSRB->MsgInBuf[1] != 2)) {
2033 /* Length is wrong, reject it */
2035 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
2037 pSRB->MsgInBuf[0] = MSG_REJECT_;
2038 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2039 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
2040 /* it's important for atn stop */
2041 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2045 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2048 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) {
2049 /* Do wide negoniation */
2050 if (pSRB->MsgInBuf[3] > 2) {
2054 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE);
2056 pSRB->MsgInBuf[0] = MSG_REJECT_;
2057 trm_reg_write16(DO_SETATN,
2058 TRMREG_SCSI_CONTROL);
2059 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
2060 /* it's important for atn stop */
2061 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2065 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2068 if (pSRB->MsgInBuf[3] == 2) {
2069 pSRB->MsgInBuf[3] = 1;
2072 if (!(pDCB->SyncMode
2073 & WIDE_NEGO_DONE)) {
2075 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN);
2082 if (pSRB->MsgInBuf[3] != 0) {
2083 /* is Wide data xfer */
2086 pDCB->tinfo.current.width
2087 = MSG_EXT_WDTR_BUS_16_BIT;
2088 pDCB->tinfo.goal.width
2089 = MSG_EXT_WDTR_BUS_16_BIT;
2094 pSRB->MsgInBuf[3] = 0;
2095 pSRB->SRBState |= SRB_MSGOUT;
2096 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL);
2097 *pscsi_status = PH_BUS_FREE; /* .. initial phase */
2098 /* it's important for atn stop */
2099 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2103 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2105 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) &&
2106 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) {
2108 * is 8bit transfer Extended message :
2109 * =================================
2110 * SYNCHRONOUS DATA TRANSFER REQUEST
2111 * =================================
2112 * byte 0 : Extended message (01h)
2113 * byte 1 : Extended message length (03)
2114 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h)
2115 * byte 3 : Transfer period factor
2116 * byte 4 : REQ/ACK offset
2118 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO);
2119 if ((pSRB->MsgInBuf[1] != 3) ||
2120 (pSRB->MsgInBuf[2] != 1)) {
2123 pSRB->MsgInBuf[0] = MSG_REJECT_;
2124 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2125 *pscsi_status = PH_BUS_FREE;
2126 /* .. initial phase */
2127 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2128 /* it's important for atn stop */
2132 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2134 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) {
2136 pDCB = pSRB->pSRBDCB;
2137 /* disable sync & sync nego */
2139 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE);
2140 pDCB->SyncPeriod = 0;
2141 pDCB->SyncOffset = 0;
2142 pDCB->tinfo.goal.period = 0;
2143 pDCB->tinfo.goal.offset = 0;
2144 pDCB->tinfo.current.period = 0;
2145 pDCB->tinfo.current.offset = 0;
2146 pDCB->tinfo.current.width =
2147 MSG_EXT_WDTR_BUS_8_BIT;
2150 * program SCSI control register
2153 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
2154 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
2155 trm_SetXferRate(pACB,pSRB,pDCB);
2156 *pscsi_status = PH_BUS_FREE;
2157 /* .. initial phase */
2158 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2159 /* it's important for atn stop */
2163 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2167 pDCB = pSRB->pSRBDCB;
2169 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE;
2170 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3];
2171 /* Transfer period factor */
2172 pDCB->SyncOffset = pSRB->MsgInBuf[4];
2173 /* REQ/ACK offset */
2174 if (pACB->AdaptType == 1) {
2175 for(bIndex = 0; bIndex < 7; bIndex++) {
2176 if (pSRB->MsgInBuf[3] <=
2177 dc395u2x_clock_period[bIndex]) {
2178 pDCB->tinfo.goal.period =
2179 dc395u2x_tinfo_period[bIndex];
2180 pDCB->tinfo.current.period =
2181 dc395u2x_tinfo_period[bIndex];
2182 pDCB->tinfo.goal.offset =
2184 pDCB->tinfo.current.offset =
2186 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC);
2191 for(bIndex = 0; bIndex < 7; bIndex++) {
2192 if (pSRB->MsgInBuf[3] <=
2193 dc395x_clock_period[bIndex]) {
2194 pDCB->tinfo.goal.period =
2195 dc395x_tinfo_period[bIndex];
2196 pDCB->tinfo.current.period =
2197 dc395x_tinfo_period[bIndex];
2198 pDCB->tinfo.goal.offset =
2200 pDCB->tinfo.current.offset =
2210 * program SCSI control register
2213 trm_reg_write8(pDCB->SyncPeriod,
2215 trm_reg_write8(pDCB->SyncOffset,
2216 TRMREG_SCSI_OFFSET);
2217 trm_SetXferRate(pACB,pSRB,pDCB);
2218 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/
2219 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/
2223 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND);
2227 *pscsi_status = PH_BUS_FREE;
2228 /* .. initial phase */
2229 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2230 /* it's important for atn stop */
2234 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2239 trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2242 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL);
2243 trm_reg_write32(1,TRMREG_SCSI_COUNTER);
2244 if (!(pSRB->SRBState & SRB_MSGIN)) {
2245 pSRB->SRBState &= SRB_DISCONNECT;
2246 pSRB->SRBState |= SRB_MSGIN;
2248 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2249 /* it's important for atn stop*/
2253 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND);
2257 trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2263 trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status)
2269 trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB)
2272 struct ccb_trans_settings neg;
2278 * set all lun device's period , offset
2280 TRM_DPRINTF("trm_SetXferRate\n");
2282 memset(&neg, 0, sizeof (neg));
2283 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period;
2284 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset;
2285 neg.xport_specific.spi.valid =
2286 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET;
2287 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1);
2288 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg);
2289 if (!(pDCB->IdentifyMsg & 0x07)) {
2290 pDCBTemp = pACB->pLinkDCB;
2291 cnt = pACB->DeviceCnt;
2292 bval = pDCB->TargetID;
2293 for (i = 0; i < cnt; i++) {
2294 if (pDCBTemp->TargetID == bval) {
2295 pDCBTemp->SyncPeriod = pDCB->SyncPeriod;
2296 pDCBTemp->SyncOffset = pDCB->SyncOffset;
2297 pDCBTemp->SyncMode = pDCB->SyncMode;
2299 pDCBTemp = pDCBTemp->pNextDCB;
2312 * PH_DATA_OUT 0x00 Data out phase
2313 * PH_DATA_IN 0x01 Data in phase
2314 * PH_COMMAND 0x02 Command phase
2315 * PH_STATUS 0x03 Status phase
2316 * PH_BUS_FREE 0x04 Invalid phase used as bus free
2317 * PH_BUS_FREE 0x05 Invalid phase used as bus free
2318 * PH_MSG_OUT 0x06 Message out phase
2319 * PH_MSG_IN 0x07 Message in phase
2323 trm_Disconnect(PACB pACB)
2328 u_int target_id,target_lun;
2330 TRM_DPRINTF("trm_Disconnect...............\n ");
2332 pDCB = pACB->pActiveDCB;
2334 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n ");
2339 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT),
2340 TRMREG_SCSI_CONTROL);
2343 pSRB = pDCB->pActiveSRB;
2345 target_id = pSRB->pccb->ccb_h.target_id;
2346 target_lun = pSRB->pccb->ccb_h.target_lun;
2347 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB);
2348 pACB->pActiveDCB = 0;
2349 pSRB->ScsiPhase = PH_BUS_FREE;
2350 /* SCSI bus free Phase */
2351 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL);
2352 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) {
2354 trm_DoWaitingSRB(pACB);
2355 } else if (pSRB->SRBState & SRB_ABORT_SENT) {
2357 cnt = pDCB->GoingSRBCnt;
2358 pDCB->GoingSRBCnt = 0;
2359 pSRB = pDCB->pGoingSRB;
2360 for (i = 0; i < cnt; i++) {
2361 psrb = pSRB->pNextSRB;
2362 pSRB->pNextSRB = pACB->pFreeSRB;
2363 pACB->pFreeSRB = pSRB;
2366 pDCB->pGoingSRB = 0;
2367 trm_DoWaitingSRB(pACB);
2369 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) ||
2370 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) {
2371 /* Selection time out */
2372 if (!(pACB->scan_devices[target_id][target_lun]) &&
2373 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */
2374 pSRB->CmdBlock[0] != INQUIRY) {
2375 pSRB->SRBState = SRB_READY;
2376 trm_RewaitSRB(pDCB, pSRB);
2378 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT;
2381 } else if (pSRB->SRBState & SRB_DISCONNECT) {
2385 trm_DoWaitingSRB(pACB);
2386 } else if (pSRB->SRBState & SRB_COMPLETED) {
2391 pDCB->pActiveSRB = 0;
2392 pSRB->SRBState = SRB_FREE;
2393 trm_SRBdone(pACB, pDCB, pSRB);
2400 trm_Reselect(PACB pACB)
2404 u_int16_t RselTarLunId;
2406 TRM_DPRINTF("trm_Reselect................. \n");
2407 pDCB = pACB->pActiveDCB;
2409 /* Arbitration lost but Reselection win */
2410 pSRB = pDCB->pActiveSRB;
2411 pSRB->SRBState = SRB_READY;
2412 trm_RewaitSRB(pDCB, pSRB);
2414 /* Read Reselected Target Id and LUN */
2415 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF;
2416 pDCB = pACB->pLinkDCB;
2417 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) {
2418 /* get pDCB of the reselect id */
2419 pDCB = pDCB->pNextDCB;
2422 pACB->pActiveDCB = pDCB;
2423 if (pDCB->SyncMode & EN_TAG_QUEUING) {
2424 pSRB = &pACB->TmpSRB;
2425 pDCB->pActiveSRB = pSRB;
2427 pSRB = pDCB->pActiveSRB;
2428 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) {
2432 pSRB = &pACB->TmpSRB;
2433 pSRB->SRBState = SRB_UNEXPECT_RESEL;
2434 pDCB->pActiveSRB = pSRB;
2435 trm_EnableMsgOutAbort1(pACB, pSRB);
2437 if (pDCB->DCBFlag & ABORT_DEV_) {
2438 pSRB->SRBState = SRB_ABORT_SENT;
2439 trm_EnableMsgOutAbort1(pACB, pSRB);
2441 pSRB->SRBState = SRB_DATA_XFER;
2444 pSRB->ScsiPhase = PH_BUS_FREE;
2445 /* SCSI bus free Phase */
2447 * Program HA ID, target ID, period and offset
2449 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID);
2451 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID);
2453 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC);
2455 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET);
2457 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL);
2458 /* it's important for atn stop*/
2462 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND);
2463 /* to rls the /ACK signal */
2467 trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB)
2470 u_int8_t bval, bval1,status;
2472 struct ccb_scsiio *pcsio;
2475 u_int target_id,target_lun;
2481 pcsio = &pccb->csio;
2482 target_id = pSRB->pccb->ccb_h.target_id;
2483 target_lun = pSRB->pccb->ccb_h.target_lun;
2484 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2485 bus_dmasync_op_t op;
2486 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
2487 op = BUS_DMASYNC_POSTREAD;
2489 op = BUS_DMASYNC_POSTWRITE;
2490 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op);
2491 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap);
2498 status = pSRB->TargetStatus;
2499 pcsio->scsi_status=SCSI_STAT_GOOD;
2500 pccb->ccb_h.status = CAM_REQ_CMP;
2501 if (pSRB->SRBFlag & AUTO_REQSENSE) {
2503 * status of auto request sense
2505 pSRB->SRBFlag &= ~AUTO_REQSENSE;
2506 pSRB->AdaptStatus = 0;
2507 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND;
2509 if (status == SCSI_STATUS_CHECK_COND) {
2510 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2513 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0];
2514 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1];
2515 pSRB->SRBTotalXferLength = pSRB->Segment1[1];
2516 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address;
2517 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length;
2518 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2519 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data,
2521 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR
2522 | CAM_AUTOSNS_VALID;
2529 if (status == SCSI_STATUS_CHECK_COND) {
2530 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) {
2531 TRM_DPRINTF("trm_RequestSense..................\n");
2532 trm_RequestSense(pACB, pDCB, pSRB);
2535 pcsio->scsi_status = SCSI_STATUS_CHECK_COND;
2536 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2538 } else if (status == SCSI_STAT_QUEUEFULL) {
2539 bval = (u_int8_t) pDCB->GoingSRBCnt;
2541 pDCB->MaxActiveCommandCnt = bval;
2542 trm_RewaitSRB(pDCB, pSRB);
2543 pSRB->AdaptStatus = 0;
2544 pSRB->TargetStatus = 0;
2546 } else if (status == SCSI_STAT_SEL_TIMEOUT) {
2547 pSRB->AdaptStatus = H_SEL_TIMEOUT;
2548 pSRB->TargetStatus = 0;
2549 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT;
2550 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2551 } else if (status == SCSI_STAT_BUSY) {
2552 TRM_DPRINTF("trm: target busy at %s %d\n",
2553 __FILE__, __LINE__);
2554 pcsio->scsi_status = SCSI_STAT_BUSY;
2555 pccb->ccb_h.status = CAM_SCSI_BUSY;
2557 /* The device busy, try again later? */
2558 } else if (status == SCSI_STAT_RESCONFLICT) {
2559 TRM_DPRINTF("trm: target reserved at %s %d\n",
2560 __FILE__, __LINE__);
2561 pcsio->scsi_status = SCSI_STAT_RESCONFLICT;
2562 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/
2565 pSRB->AdaptStatus = 0;
2566 if (pSRB->RetryCnt) {
2568 pSRB->TargetStatus = 0;
2569 pSRB->SRBSGIndex = 0;
2570 if (trm_StartSCSI(pACB, pDCB, pSRB)) {
2572 * If trm_StartSCSI return 1 :
2573 * current interrupt status is interrupt
2575 * It's said that SCSI processor has more
2576 * one SRB need to do
2578 trm_RewaitSRB(pDCB, pSRB);
2582 TRM_DPRINTF("trm: driver stuffup at %s %d\n",
2583 __FILE__, __LINE__);
2584 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
2589 * process initiator status..........................
2590 * Adapter (initiator) status
2592 status = pSRB->AdaptStatus;
2593 if (status & H_OVER_UNDER_RUN) {
2594 pSRB->TargetStatus = 0;
2595 pccb->ccb_h.status = CAM_DATA_RUN_ERR;
2596 /* Illegal length (over/under run) */
2597 } else if (pSRB->SRBStatus & PARITY_ERROR) {
2598 TRM_DPRINTF("trm: driver stuffup %s %d\n",
2599 __FILE__, __LINE__);
2600 pDCB->tinfo.goal.period = 0;
2601 pDCB->tinfo.goal.offset = 0;
2602 /* Driver failed to perform operation */
2603 pccb->ccb_h.status = CAM_UNCOR_PARITY;
2606 pSRB->AdaptStatus = 0;
2607 pSRB->TargetStatus = 0;
2608 pccb->ccb_h.status = CAM_REQ_CMP;
2609 /* there is no error, (sense is invalid) */
2613 if (pACB->scan_devices[target_id][target_lun]) {
2615 * if SCSI command in "scan devices" duty
2617 if (pSRB->CmdBlock[0] == TEST_UNIT_READY)
2618 pACB->scan_devices[target_id][target_lun] = 0;
2619 /* SCSI command phase :test unit ready */
2620 else if (pSRB->CmdBlock[0] == INQUIRY) {
2622 * SCSI command phase :inquiry scsi device data
2623 * (type,capacity,manufacture....
2625 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT)
2627 ptr = (PSCSI_INQDATA) pcsio->data_ptr;
2629 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n",
2631 bval1 = ptr->DevType & SCSI_DEVTYPE;
2632 if (bval1 == SCSI_NODEV) {
2634 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n",
2638 pACB->scan_devices[target_id][target_lun] = 0;
2639 /* no device set scan device flag =0*/
2641 /* move the head of DCB to tempDCB*/
2642 pTempDCB=pACB->pLinkDCB;
2643 /* search current DCB for pass link */
2644 while (pTempDCB->pNextDCB != pDCB) {
2645 pTempDCB = pTempDCB->pNextDCB;
2648 * when the current DCB found than connect
2651 /* to the DCB tail that before current DCB */
2652 pTempDCB->pNextDCB = pDCB->pNextDCB;
2654 * if there was only one DCB ,connect his tail
2657 if (pACB->pLinkDCB == pDCB)
2658 pACB->pLinkDCB = pTempDCB->pNextDCB;
2659 if (pACB->pDCBRunRobin == pDCB)
2660 pACB->pDCBRunRobin = pTempDCB->pNextDCB;
2661 pDCB->DCBstatus &= ~DS_IN_QUEUE;
2663 if (pACB->DeviceCnt == 0) {
2664 pACB->pLinkDCB = NULL;
2665 pACB->pDCBRunRobin = NULL;
2671 for (j = 0; j < 28; j++) {
2672 TRM_DPRINTF("ptr=%2x ",
2673 ((u_int8_t *)ptr)[j]);
2676 pDCB->DevType = bval1;
2677 if (bval1 == SCSI_DASD ||
2678 bval1 == SCSI_OPTICAL) {
2679 if ((((ptr->Vers & 0x07) >= 2) ||
2680 ((ptr->RDF & 0x0F) == 2)) &&
2681 (ptr->Flags & SCSI_INQ_CMDQUEUE) &&
2682 (pDCB->DevMode & TAG_QUEUING_) &&
2683 (pDCB->DevMode & EN_DISCONNECT_)) {
2687 MaxActiveCommandCnt =
2691 pDCB->tinfo.disc_tag |=
2696 pDCB->tinfo.disc_tag &=
2702 /* pSRB->CmdBlock[0] == INQUIRY */
2704 /* pACB->scan_devices[target_id][target_lun] */
2707 /* ReleaseSRB(pDCB, pSRB); */
2708 if (pSRB == pDCB->pGoingSRB)
2709 pDCB->pGoingSRB = pSRB->pNextSRB;
2711 psrb = pDCB->pGoingSRB;
2712 while (psrb->pNextSRB != pSRB) {
2713 psrb = psrb->pNextSRB;
2715 psrb->pNextSRB = pSRB->pNextSRB;
2716 if (pSRB == pDCB->pGoingLastSRB) {
2717 pDCB->pGoingLastSRB = psrb;
2720 pSRB->pNextSRB = pACB->pFreeSRB;
2721 pACB->pFreeSRB = pSRB;
2722 pDCB->GoingSRBCnt--;
2723 trm_DoWaitingSRB(pACB);
2726 /* Notify cmd done */
2731 trm_DoingSRB_Done(PACB pACB)
2738 pDCB = pACB->pLinkDCB;
2743 cnt = pdcb->GoingSRBCnt;
2744 psrb = pdcb->pGoingSRB;
2745 for (i = 0; i < cnt; i++) {
2746 psrb2 = psrb->pNextSRB;
2748 pccb->ccb_h.status = CAM_SEL_TIMEOUT;
2749 /* ReleaseSRB(pDCB, pSRB); */
2750 psrb->pNextSRB = pACB->pFreeSRB;
2751 pACB->pFreeSRB = psrb;
2755 pdcb->GoingSRBCnt = 0;
2756 pdcb->pGoingSRB = NULL;
2757 pdcb = pdcb->pNextDCB;
2759 while (pdcb != pDCB);
2763 trm_ResetSCSIBus(PACB pACB)
2768 pACB->ACBFlag |= RESET_DEV;
2770 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL);
2771 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET));
2777 trm_ScsiRstDetect(PACB pACB)
2782 TRM_DPRINTF("trm_ScsiRstDetect \n");
2787 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL);
2789 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL);
2791 if (pACB->ACBFlag & RESET_DEV)
2792 pACB->ACBFlag |= RESET_DONE;
2794 pACB->ACBFlag |= RESET_DETECT;
2795 trm_ResetDevParam(pACB);
2796 /* trm_DoingSRB_Done(pACB); ???? */
2797 trm_RecoverSRB(pACB);
2798 pACB->pActiveDCB = NULL;
2800 trm_DoWaitingSRB(pACB);
2807 trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB)
2810 struct ccb_scsiio *pcsio;
2813 pcsio = &pccb->csio;
2815 pSRB->SRBFlag |= AUTO_REQSENSE;
2816 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0]));
2817 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4]));
2818 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) +
2820 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */
2822 /* $$$$$$ Status of initiator/target $$$$$$$$ */
2823 pSRB->AdaptStatus = 0;
2824 pSRB->TargetStatus = 0;
2825 /* $$$$$$ Status of initiator/target $$$$$$$$ */
2827 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data);
2828 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address;
2829 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length;
2830 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB);
2831 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data);
2832 pSRB->SRBSGCount = 1;
2833 pSRB->SRBSGIndex = 0;
2835 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003;
2836 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5;
2837 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len;
2838 pSRB->ScsiCmdLen = 6;
2840 if (trm_StartSCSI(pACB, pDCB, pSRB))
2842 * If trm_StartSCSI return 1 :
2843 * current interrupt status is interrupt disreenable
2844 * It's said that SCSI processor has more one SRB need to do
2846 trm_RewaitSRB(pDCB, pSRB);
2850 trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB)
2854 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL);
2858 trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB)
2861 pSRB->MsgOutBuf[0] = MSG_ABORT;
2862 trm_EnableMsgOutAbort2(pACB, pSRB);
2866 trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j)
2868 PNVRAMTYPE pEEpromBuf;
2869 u_int8_t bval,PeriodIndex;
2870 u_int target_id,target_lun;
2878 * Using the lun 0 device to init other DCB first, if the device
2879 * has been initialized.
2880 * I don't want init sync arguments one by one, it is the same.
2882 if (target_lun != 0 &&
2883 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2884 bcopy(&pACB->DCBarray[target_id][0], pDCB,
2887 if (pACB->pLinkDCB == 0) {
2888 pACB->pLinkDCB = pDCB;
2890 * RunRobin impersonate the role
2891 * that let each device had good proportion
2892 * about SCSI command proceeding
2894 pACB->pDCBRunRobin = pDCB;
2895 pDCB->pNextDCB = pDCB;
2897 pTempDCB=pACB->pLinkDCB;
2898 /* search the last nod of DCB link */
2899 while (pTempDCB->pNextDCB != pACB->pLinkDCB)
2900 pTempDCB = pTempDCB->pNextDCB;
2901 /* connect current DCB with last DCB tail */
2902 pTempDCB->pNextDCB = pDCB;
2903 /* connect current DCB tail to this DCB Q head */
2904 pDCB->pNextDCB=pACB->pLinkDCB;
2909 pDCB->TargetID = target_id;
2910 pDCB->TargetLUN = target_lun;
2911 pDCB->pWaitingSRB = NULL;
2912 pDCB->pGoingSRB = NULL;
2913 pDCB->GoingSRBCnt = 0;
2914 pDCB->pActiveSRB = NULL;
2915 pDCB->MaxActiveCommandCnt = 1;
2917 pDCB->DCBstatus |= DS_IN_QUEUE;
2919 pEEpromBuf = &trm_eepromBuf[unit];
2920 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0;
2921 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg;
2924 * disconnect enable ?
2926 if (pDCB->DevMode & NTC_DO_DISCONNECT) {
2928 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ;
2931 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB);
2934 pDCB->IdentifyMsg = bval;
2935 if (target_lun != 0 &&
2936 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE))
2942 if (pDCB->DevMode & TAG_QUEUING_) {
2943 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ;
2945 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB);
2948 * wide nego ,sync nego enable ?
2950 pDCB->SyncPeriod = 0;
2951 pDCB->SyncOffset = 0;
2952 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07;
2953 if (pACB->AdaptType==1) {/* is U2? */
2954 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ];
2955 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2956 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0;
2958 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ];
2959 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod;
2960 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0;
2963 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) &&
2964 (pACB->Config & HCC_WIDE_CARD))
2965 pDCB->SyncMode |= WIDE_NEGO_ENABLE;
2966 /* enable wide nego */
2967 if (pDCB->DevMode & NTC_DO_SYNC_NEGO)
2968 pDCB->SyncMode |= SYNC_NEGO_ENABLE;
2969 /* enable sync nego */
2972 * Fill in tinfo structure.
2974 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ?
2975 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT;
2977 pDCB->tinfo.current.period = 0;
2978 pDCB->tinfo.current.offset = 0;
2979 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT;
2983 trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2988 pSRB->SRBSGPhyAddr=segs->ds_addr;
2993 trm_destroySRB(PACB pACB)
2997 pSRB = pACB->pFreeSRB;
2999 if (pSRB->sg_dmamap) {
3000 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap);
3001 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL,
3003 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap);
3006 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap);
3007 pSRB = pSRB->pNextSRB;
3012 trm_initSRB(PACB pACB)
3018 for (i = 0; i < TRM_MAX_SRB_CNT; i++) {
3019 pSRB = (PSRB)&pACB->pFreeSRB[i];
3021 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL,
3022 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) {
3025 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL,
3026 TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
3027 trm_srbmapSG, pSRB, /*flags*/0);
3028 if (i != TRM_MAX_SRB_CNT - 1) {
3032 pSRB->pNextSRB = &pACB->pFreeSRB[i+1];
3035 * load NULL to NextSRB of the last SRB
3037 pSRB->pNextSRB = NULL;
3039 pSRB->TagNumber = i;
3042 * Create the dmamap. This is no longer optional!
3044 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0,
3045 &pSRB->dmamap)) != 0)
3056 trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit)
3058 PNVRAMTYPE pEEpromBuf;
3060 pEEpromBuf = &trm_eepromBuf[unit];
3063 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN)
3068 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n",
3069 pACB->max_id, pACB->max_lun);
3070 pACB->pLinkDCB = NULL;
3071 pACB->pDCBRunRobin = NULL;
3072 pACB->pActiveDCB = NULL;
3073 pACB->AdapterUnit = (u_int8_t)unit;
3074 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId;
3075 pACB->AdaptSCSILUN = 0;
3076 pACB->DeviceCnt = 0;
3077 pACB->AdaptType = adaptType;
3078 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag;
3084 NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB)
3086 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf;
3089 /* Enable SEEPROM */
3090 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
3091 TRMREG_GEN_CONTROL);
3095 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF);
3096 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3097 NVRAM_trm_wait_30us(pACB);
3098 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) {
3099 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom);
3104 NVRAM_trm_write_cmd(pACB, 0x04, 0x00);
3105 trm_reg_write8(0 , TRMREG_GEN_NVRAM);
3106 NVRAM_trm_wait_30us(pACB);
3107 /* Disable SEEPROM */
3108 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
3109 TRMREG_GEN_CONTROL);
3114 NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData)
3119 * Send write command & address
3122 NVRAM_trm_write_cmd(pACB, 0x05, bAddr);
3126 for (i = 0; i < 8; i++, bData <<= 1) {
3127 bSendData = NVR_SELECT;
3129 /* Start from bit 7 */
3130 bSendData |= NVR_BITOUT;
3131 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
3132 NVRAM_trm_wait_30us(pACB);
3133 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3134 NVRAM_trm_wait_30us(pACB);
3136 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
3137 NVRAM_trm_wait_30us(pACB);
3139 * Disable chip select
3141 trm_reg_write8(0 , TRMREG_GEN_NVRAM);
3142 NVRAM_trm_wait_30us(pACB);
3143 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM);
3144 NVRAM_trm_wait_30us(pACB);
3146 * Wait for write ready
3149 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM);
3150 NVRAM_trm_wait_30us(pACB);
3151 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
3152 NVRAM_trm_wait_30us(pACB);
3153 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) {
3158 * Disable chip select
3160 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3165 NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB)
3167 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf;
3173 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM),
3174 TRMREG_GEN_CONTROL);
3175 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
3176 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr);
3180 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM),
3181 TRMREG_GEN_CONTROL);
3186 NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr)
3189 u_int8_t bReadData, bData = 0;
3191 * Send read command & address
3194 NVRAM_trm_write_cmd(pACB, 0x06, bAddr);
3196 for (i = 0; i < 8; i++) {
3200 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM);
3201 NVRAM_trm_wait_30us(pACB);
3202 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM);
3204 * Get data bit while falling edge
3206 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM);
3208 if (bReadData & NVR_BITIN) {
3211 NVRAM_trm_wait_30us(pACB);
3214 * Disable chip select
3216 trm_reg_write8(0, TRMREG_GEN_NVRAM);
3221 NVRAM_trm_wait_30us(PACB pACB)
3224 /* ScsiPortStallExecution(30); wait 30 us */
3225 trm_reg_write8(5, TRMREG_GEN_TIMER);
3226 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT));
3231 NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr)
3236 for (i = 0; i < 3; i++, bCmd <<= 1) {
3238 * Program SB+OP code
3240 bSendData = NVR_SELECT;
3242 bSendData |= NVR_BITOUT;
3243 /* start from bit 2 */
3244 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM);
3245 NVRAM_trm_wait_30us(pACB);
3246 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3247 NVRAM_trm_wait_30us(pACB);
3249 for (i = 0; i < 7; i++, bAddr <<= 1) {
3253 bSendData = NVR_SELECT;
3255 /* Start from bit 6 */
3256 bSendData |= NVR_BITOUT;
3257 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM);
3258 NVRAM_trm_wait_30us(pACB);
3259 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM);
3260 NVRAM_trm_wait_30us(pACB);
3262 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM);
3263 NVRAM_trm_wait_30us(pACB);
3267 trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB)
3269 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf;
3270 u_int16_t wAddr, wCheckSum;
3271 u_long dAddr, *dpEeprom;
3273 NVRAM_trm_read_all(pEEpromBuf,pACB);
3275 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3276 wAddr < 64; wAddr++, wpEeprom++) {
3277 wCheckSum += *wpEeprom;
3279 if (wCheckSum != 0x1234) {
3281 * Checksum error, load default
3283 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3284 pEEpromBuf->NvramSubVendorID[1] =
3285 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3286 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3287 pEEpromBuf->NvramSubSysID[1] =
3288 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3289 pEEpromBuf->NvramSubClass = 0x00;
3290 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM;
3291 pEEpromBuf->NvramVendorID[1] =
3292 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8);
3293 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040;
3294 pEEpromBuf->NvramDeviceID[1] =
3295 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8);
3296 pEEpromBuf->NvramReserved = 0x00;
3298 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget;
3299 dAddr < 16; dAddr++, dpEeprom++) {
3300 *dpEeprom = 0x00000077;
3301 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */
3304 *dpEeprom++ = 0x04000F07;
3305 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */
3306 *dpEeprom++ = 0x00000015;
3307 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */
3308 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++)
3310 pEEpromBuf->NvramCheckSum = 0x00;
3311 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf;
3312 wAddr < 63; wAddr++, wpEeprom++)
3313 wCheckSum += *wpEeprom;
3314 *wpEeprom = 0x1234 - wCheckSum;
3315 NVRAM_trm_write_all(pEEpromBuf,pACB);
3320 trm_initAdapter(PACB pACB, u_int16_t unit)
3322 PNVRAMTYPE pEEpromBuf;
3326 pEEpromBuf = &trm_eepromBuf[unit];
3328 /* 250ms selection timeout */
3329 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT);
3330 /* Mask all the interrupt */
3331 trm_reg_write8(0x00, TRMREG_DMA_INTEN);
3332 trm_reg_write8(0x00, TRMREG_SCSI_INTEN);
3333 /* Reset SCSI module */
3334 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL);
3335 /* program configuration 0 */
3336 pACB->Config = HCC_AUTOTERM | HCC_PARITY;
3337 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI)
3338 pACB->Config |= HCC_WIDE_CARD;
3339 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET)
3340 pACB->Config |= HCC_SCSI_RESET;
3341 if (pACB->Config & HCC_PARITY)
3342 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK;
3344 bval = PHASELATCH | INITIATOR | BLOCKRST ;
3345 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0);
3346 /* program configuration 1 */
3347 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1);
3348 /* program Host ID */
3349 bval = pEEpromBuf->NvramScsiId;
3350 trm_reg_write8(bval, TRMREG_SCSI_HOSTID);
3351 /* set ansynchronous transfer */
3352 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET);
3353 /* Trun LED control off*/
3354 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F;
3355 trm_reg_write16(wval, TRMREG_GEN_CONTROL);
3357 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE;
3358 trm_reg_write16(wval, TRMREG_DMA_CONFIG);
3359 /* Clear pending interrupt status */
3360 trm_reg_read8(TRMREG_SCSI_INTSTATUS);
3361 /* Enable SCSI interrupt */
3362 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN);
3363 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN);
3368 trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3373 pACB->srb_physbase = segs->ds_addr;
3377 trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3381 baddr = (bus_addr_t *)arg;
3382 *baddr = segs->ds_addr;
3386 trm_init(u_int16_t unit, device_t dev)
3389 int rid = PCIR_BAR(0), i = 0, j = 0;
3390 u_int16_t adaptType = 0;
3392 pACB = (PACB) device_get_softc(dev);
3394 printf("trm%d: cannot allocate ACB !\n", unit);
3397 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
3399 if (pACB->iores == NULL) {
3400 printf("trm_init: bus_alloc_resource failed!\n");
3403 switch (pci_get_devid(dev)) {
3404 case PCI_DEVICEID_TRMS1040:
3407 case PCI_DEVICEID_TRMS2080:
3411 printf("trm_init %d: unknown adapter type!\n", unit);
3415 pACB->tag = rman_get_bustag(pACB->iores);
3416 pACB->bsh = rman_get_bushandle(pACB->iores);
3417 if (bus_dma_tag_create(
3418 /*parent_dmat*/ bus_get_dma_tag(dev),
3421 /*lowaddr*/ BUS_SPACE_MAXADDR,
3422 /*highaddr*/ BUS_SPACE_MAXADDR,
3425 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT,
3426 /*nsegments*/ BUS_SPACE_UNRESTRICTED,
3427 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT,
3431 /* dmat */ &pACB->parent_dmat) != 0)
3433 if (bus_dma_tag_create(
3434 /*parent_dmat*/ pACB->parent_dmat,
3437 /*lowaddr*/ BUS_SPACE_MAXADDR,
3438 /*highaddr*/ BUS_SPACE_MAXADDR,
3441 /*maxsize*/ MAXBSIZE,
3442 /*nsegments*/ TRM_NSEG,
3443 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3444 /*flags*/ BUS_DMA_ALLOCNOW,
3445 /*lockfunc*/ busdma_lock_mutex,
3447 /* dmat */ &pACB->buffer_dmat) != 0)
3449 /* DMA tag for our ccb structures */
3450 if (bus_dma_tag_create(
3451 /*parent_dmat*/pACB->parent_dmat,
3454 /*lowaddr*/ BUS_SPACE_MAXADDR,
3455 /*highaddr*/ BUS_SPACE_MAXADDR,
3458 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB),
3460 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3462 /*lockfunc*/ busdma_lock_mutex,
3464 /*dmat*/ &pACB->srb_dmat) != 0) {
3465 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit);
3468 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB,
3469 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) {
3470 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit);
3473 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB,
3474 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB,
3476 /* Create, allocate, and map DMA buffers for autosense data */
3477 if (bus_dma_tag_create(
3478 /*parent_dmat*/pACB->parent_dmat,
3481 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
3482 /*highaddr*/BUS_SPACE_MAXADDR,
3483 /*filter*/NULL, /*filterarg*/NULL,
3484 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3486 /*maxsegsz*/TRM_MAXTRANSFER_SIZE,
3487 /*flags*/0, /*lockfunc*/busdma_lock_mutex,
3488 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) {
3490 device_printf(dev, "cannot create sense buffer dmat\n");
3494 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers,
3495 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0)
3498 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap,
3499 pACB->sense_buffers,
3500 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT,
3501 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0);
3503 trm_check_eeprom(&trm_eepromBuf[unit],pACB);
3504 trm_initACB(pACB, adaptType, unit);
3505 for (i = 0; i < (pACB->max_id + 1); i++) {
3506 if (pACB->AdaptSCSIID == i)
3508 for(j = 0; j < (pACB->max_lun + 1); j++) {
3509 pACB->scan_devices[i][j] = 1;
3510 /* we assume we need to scan all devices */
3511 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j);
3514 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB));
3515 if (bus_dma_tag_create(
3516 /*parent_dmat*/pACB->parent_dmat,
3519 /*lowaddr*/ BUS_SPACE_MAXADDR,
3520 /*highaddr*/ BUS_SPACE_MAXADDR,
3523 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry),
3525 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE,
3527 /*lockfunc*/ busdma_lock_mutex,
3529 /*dmat*/ &pACB->sg_dmat) != 0)
3532 if (trm_initSRB(pACB)) {
3533 printf("trm_initSRB: error\n");
3536 if (trm_initAdapter(pACB, unit)) {
3537 printf("trm_initAdapter: initial ERROR\n");
3543 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3545 if (pACB->sense_dmamap) {
3546 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3547 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3548 pACB->sense_dmamap);
3549 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3551 if (pACB->sense_dmat)
3552 bus_dma_tag_destroy(pACB->sense_dmat);
3553 if (pACB->sg_dmat) {
3554 trm_destroySRB(pACB);
3555 bus_dma_tag_destroy(pACB->sg_dmat);
3557 if (pACB->srb_dmamap) {
3558 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3559 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3561 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3564 bus_dma_tag_destroy(pACB->srb_dmat);
3565 if (pACB->buffer_dmat)
3566 bus_dma_tag_destroy(pACB->buffer_dmat);
3567 if (pACB->parent_dmat)
3568 bus_dma_tag_destroy(pACB->parent_dmat);
3573 trm_attach(device_t dev)
3575 struct cam_devq *device_Q;
3579 int unit = device_get_unit(dev);
3581 device_id = pci_get_devid(dev);
3583 * These cards do not allow memory mapped accesses
3585 if ((pACB = trm_init((u_int16_t) unit,
3587 printf("trm%d: trm_init error!\n",unit);
3590 /* After setting up the adapter, map our interrupt */
3592 * Now let the CAM generic SCSI layer find the SCSI devices on the bus
3593 * start queue to reset to the idle loop.
3594 * Create device queue of SIM(s)
3595 * (MAX_START_JOB - 1) : max_sim_transactions
3597 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3598 RF_SHAREABLE | RF_ACTIVE);
3599 if (pACB->irq == NULL ||
3600 bus_setup_intr(dev, pACB->irq,
3601 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) {
3602 printf("trm%d: register Interrupt handler error!\n", unit);
3605 device_Q = cam_simq_alloc(TRM_MAX_START_JOB);
3606 if (device_Q == NULL){
3607 printf("trm%d: device_Q == NULL !\n",unit);
3611 * Now tell the generic SCSI layer
3613 * If this is the xpt layer creating a sim, then it's OK
3614 * to wait for an allocation.
3615 * XXX Should we pass in a flag to indicate that wait is OK?
3619 * SCSI Interface Modules
3620 * The sim driver creates a sim for each controller. The sim device
3621 * queue is separately created in order to allow resource sharing betwee
3622 * sims. For instance, a driver may create one sim for each channel of
3623 * a multi-channel controller and use the same queue for each channel.
3624 * In this way, the queue resources are shared across all the channels
3625 * of the multi-channel controller.
3626 * trm_action : sim_action_func
3627 * trm_poll : sim_poll_func
3628 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK
3629 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT
3631 * 1 : max_dev_transactions
3632 * MAX_TAGS : max_tagged_dev_transactions
3634 * *******Construct our first channel SIM entry
3636 pACB->psim = cam_sim_alloc(trm_action,
3643 TRM_MAX_TAGS_CMD_QUEUE,
3645 if (pACB->psim == NULL) {
3646 printf("trm%d: SIM allocate fault !\n",unit);
3647 cam_simq_free(device_Q); /* SIM allocate fault*/
3650 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) {
3651 printf("trm%d: xpt_bus_register fault !\n",unit);
3654 if (xpt_create_path(&pACB->ppath,
3656 cam_sim_path(pACB->psim),
3657 CAM_TARGET_WILDCARD,
3658 CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
3659 printf("trm%d: xpt_create_path fault !\n",unit);
3660 xpt_bus_deregister(cam_sim_path(pACB->psim));
3666 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0),
3668 if (pACB->sg_dmat) {
3669 trm_destroySRB(pACB);
3670 bus_dma_tag_destroy(pACB->sg_dmat);
3673 if (pACB->srb_dmamap) {
3674 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3675 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3677 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3680 bus_dma_tag_destroy(pACB->srb_dmat);
3681 if (pACB->sense_dmamap) {
3682 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3683 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3684 pACB->sense_dmamap);
3685 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3687 if (pACB->sense_dmat)
3688 bus_dma_tag_destroy(pACB->sense_dmat);
3689 if (pACB->buffer_dmat)
3690 bus_dma_tag_destroy(pACB->buffer_dmat);
3692 bus_teardown_intr(dev, pACB->irq, pACB->ih);
3694 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3696 cam_sim_free(pACB->psim, TRUE);
3704 * trm_probe (device_t tag, pcidi_t type)
3708 trm_probe(device_t dev)
3710 switch (pci_get_devid(dev)) {
3711 case PCI_DEVICEID_TRMS1040:
3712 device_set_desc(dev,
3713 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter");
3714 return (BUS_PROBE_DEFAULT);
3715 case PCI_DEVICEID_TRMS2080:
3716 device_set_desc(dev,
3717 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter");
3718 return (BUS_PROBE_DEFAULT);
3725 trm_detach(device_t dev)
3727 PACB pACB = device_get_softc(dev);
3729 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores);
3730 trm_destroySRB(pACB);
3731 bus_dma_tag_destroy(pACB->sg_dmat);
3732 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap);
3733 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB,
3735 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap);
3736 bus_dma_tag_destroy(pACB->srb_dmat);
3737 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap);
3738 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers,
3739 pACB->sense_dmamap);
3740 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap);
3741 bus_dma_tag_destroy(pACB->sense_dmat);
3742 bus_dma_tag_destroy(pACB->buffer_dmat);
3743 bus_teardown_intr(dev, pACB->irq, pACB->ih);
3744 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq);
3745 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL);
3746 xpt_free_path(pACB->ppath);
3747 xpt_bus_deregister(cam_sim_path(pACB->psim));
3748 cam_sim_free(pACB->psim, TRUE);
3751 static device_method_t trm_methods[] = {
3752 /* Device interface */
3753 DEVMETHOD(device_probe, trm_probe),
3754 DEVMETHOD(device_attach, trm_attach),
3755 DEVMETHOD(device_detach, trm_detach),
3759 static driver_t trm_driver = {
3760 "trm", trm_methods, sizeof(struct _ACB)
3763 static devclass_t trm_devclass;
3764 DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0);
3765 MODULE_DEPEND(trm, pci, 1, 1, 1);
3766 MODULE_DEPEND(trm, cam, 1, 1, 1);