2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * AMCC'S 3ware driver for 9000 series storage controllers.
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 * Modifications by: Manjunath Ranganathaiah
46 * Macros, structures and functions shared between OSL and CL,
50 #define TW_CL_NULL ((TW_VOID *)0)
54 #define TW_CL_VENDOR_ID 0x13C1 /* 3ware vendor id */
55 #define TW_CL_DEVICE_ID_9K 0x1002 /* 9000 PCI series device id */
56 #define TW_CL_DEVICE_ID_9K_X 0x1003 /* 9000 PCI-X series device id */
57 #define TW_CL_DEVICE_ID_9K_E 0x1004 /* 9000 PCIe series device id */
58 #define TW_CL_DEVICE_ID_9K_SA 0x1005 /* 9000 PCIe SAS series device id */
60 #define TW_CL_BAR_TYPE_IO 1 /* I/O base address */
61 #define TW_CL_BAR_TYPE_MEM 2 /* memory base address */
62 #define TW_CL_BAR_TYPE_SBUF 3 /* SBUF base address */
64 #ifdef TW_OSL_ENCLOSURE_SUPPORT
65 #define TW_CL_MAX_NUM_UNITS 65 /* max # of units we support
66 -- enclosure target id is 64 */
67 #else /* TW_OSL_ENCLOSURE_SUPPORT */
68 #define TW_CL_MAX_NUM_UNITS 32 /* max # of units we support */
69 #endif /* TW_OSL_ENCLOSURE_SUPPORT */
71 #define TW_CL_MAX_NUM_LUNS 16 /* max # of LUN's we support */
72 #define TW_CL_MAX_IO_SIZE 0x20000 /* 128K */
75 * Though we can support 256 simultaneous requests, we advertise as capable
76 * of supporting only 255, since we want to keep one CL internal request
77 * context packet always available for internal requests.
79 #define TW_CL_MAX_SIMULTANEOUS_REQUESTS 256 /* max simult reqs supported */
81 #define TW_CL_MAX_32BIT_SG_ELEMENTS 109 /* max 32-bit sg elements */
82 #define TW_CL_MAX_64BIT_SG_ELEMENTS 72 /* max 64-bit sg elements */
85 /* Possible values of ctlr->flags */
86 #define TW_CL_64BIT_ADDRESSES (1<<0) /* 64 bit cmdpkt & SG addresses */
87 #define TW_CL_64BIT_SG_LENGTH (1<<1) /* 64 bit SG length */
88 #define TW_CL_START_CTLR_ONLY (1<<2) /* Start ctlr only */
89 #define TW_CL_STOP_CTLR_ONLY (1<<3) /* Stop ctlr only */
90 #define TW_CL_DEFERRED_INTR_USED (1<<5) /* OS Layer uses deferred intr */
92 /* Possible error values from the Common Layer. */
93 #define TW_CL_ERR_REQ_SUCCESS 0
94 #define TW_CL_ERR_REQ_GENERAL_FAILURE (1<<0)
95 #define TW_CL_ERR_REQ_INVALID_TARGET (1<<1)
96 #define TW_CL_ERR_REQ_INVALID_LUN (1<<2)
97 #define TW_CL_ERR_REQ_SCSI_ERROR (1<<3)
98 #define TW_CL_ERR_REQ_AUTO_SENSE_VALID (1<<4)
99 #define TW_CL_ERR_REQ_BUS_RESET (1<<5)
100 #define TW_CL_ERR_REQ_UNABLE_TO_SUBMIT_COMMAND (1<<6)
103 /* Possible values of req_pkt->flags */
104 #define TW_CL_REQ_RETRY_ON_BUSY (1<<0)
105 #define TW_CL_REQ_CALLBACK_FOR_SGLIST (1<<1)
108 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_ERROR 3
109 #define TW_CL_MESSAGE_SOURCE_CONTROLLER_EVENT 4
110 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_ERROR 21
111 #define TW_CL_MESSAGE_SOURCE_COMMON_LAYER_EVENT 22
112 #define TW_CL_MESSAGE_SOURCE_FREEBSD_DRIVER 5
113 #define TW_CL_MESSAGE_SOURCE_FREEBSD_OS 8
114 #define TW_CL_MESSAGE_SOURCE_WINDOWS_DRIVER 7
115 #define TW_CL_MESSAGE_SOURCE_WINDOWS_OS 10
117 #define TW_CL_SEVERITY_ERROR 0x1
118 #define TW_CL_SEVERITY_WARNING 0x2
119 #define TW_CL_SEVERITY_INFO 0x3
120 #define TW_CL_SEVERITY_DEBUG 0x4
122 #define TW_CL_SEVERITY_ERROR_STRING "ERROR"
123 #define TW_CL_SEVERITY_WARNING_STRING "WARNING"
124 #define TW_CL_SEVERITY_INFO_STRING "INFO"
125 #define TW_CL_SEVERITY_DEBUG_STRING "DEBUG"
131 * Structure, a pointer to which is used as the controller handle in
132 * communications between the OS Layer and the Common Layer.
134 struct tw_cl_ctlr_handle {
135 TW_VOID *osl_ctlr_ctxt; /* OSL's ctlr context */
136 TW_VOID *cl_ctlr_ctxt; /* CL's ctlr context */
141 * Structure, a pointer to which is used as the request handle in
142 * communications between the OS Layer and the Common Layer.
144 struct tw_cl_req_handle {
145 TW_VOID *osl_req_ctxt; /* OSL's request context */
146 TW_VOID *cl_req_ctxt; /* CL's request context */
147 TW_UINT8 is_io; /* Only freeze/release simq for IOs */
151 /* Structure used to describe SCSI requests to CL. */
152 struct tw_cl_scsi_req_packet {
153 TW_UINT32 unit; /* unit # to send cmd to */
154 TW_UINT32 lun; /* LUN to send cmd to */
155 TW_UINT8 *cdb; /* ptr to SCSI cdb */
156 TW_UINT32 cdb_len; /* # of valid cdb bytes */
157 TW_UINT32 sense_len; /* # of bytes of valid sense info */
158 TW_UINT8 *sense_data; /* ptr to sense data, if any */
159 TW_UINT32 scsi_status; /* SCSI status returned by fw */
160 TW_UINT32 sgl_entries; /* # of SG descriptors */
161 TW_UINT8 *sg_list; /* ptr to SG list */
165 /* Structure used to describe pass through command packets to CL. */
166 struct tw_cl_passthru_req_packet {
167 TW_UINT8 *cmd_pkt; /* ptr to passthru cmd pkt */
168 TW_UINT32 cmd_pkt_length; /* size of cmd pkt */
169 TW_UINT32 sgl_entries; /* # of SG descriptors */
170 TW_UINT8 *sg_list; /* ptr to SG list */
174 /* Request packet submitted to the Common Layer, by the OS Layer. */
175 struct tw_cl_req_packet {
176 TW_UINT32 cmd; /* Common Layer cmd */
177 TW_UINT32 flags; /* flags describing request */
178 TW_UINT32 status; /* Common Layer returned status */
179 TW_VOID (*tw_osl_callback)(struct tw_cl_req_handle *req_handle);
180 /* OSL routine to be called by CL on req completion */
181 TW_VOID (*tw_osl_sgl_callback)(
182 struct tw_cl_req_handle *req_handle, TW_VOID *sg_list,
183 TW_UINT32 *num_sgl_entries);
184 /* OSL callback to get SG list. */
187 struct tw_cl_scsi_req_packet scsi_req; /* SCSI req */
188 struct tw_cl_passthru_req_packet pt_req;/*Passthru req*/
194 * Packet that describes an AEN/error generated by the controller,
195 * Common Layer, or even the OS Layer.
197 struct tw_cl_event_packet {
198 TW_UINT32 sequence_id;
199 TW_UINT32 time_stamp_sec;
203 TW_UINT8 repeat_count;
204 TW_UINT8 parameter_len;
205 TW_UINT8 parameter_data[98];
207 TW_UINT8 severity_str[20];
211 /* Structure to link 2 adjacent elements in a list. */
213 struct tw_cl_link *next;
214 struct tw_cl_link *prev;
218 /* Scatter/Gather list entry with 32 bit addresses. */
219 struct tw_cl_sg_desc32 {
225 /* Scatter/Gather list entry with 64 bit addresses. */
226 struct tw_cl_sg_desc64 {
234 /* Byte swap functions. Valid only if running on big endian platforms. */
235 #ifdef TW_OSL_BIG_ENDIAN
237 #define TW_CL_SWAP16_WITH_CAST(x) \
238 ((x << 8) | (x >> 8))
241 #define TW_CL_SWAP32_WITH_CAST(x) \
242 ((x << 24) | ((x << 8) & (0xFF0000)) | \
243 ((x >> 8) & (0xFF00)) | (x >> 24))
246 #define TW_CL_SWAP64_WITH_CAST(x) \
247 ((((TW_UINT64)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[1]))) << 32) |\
248 ((TW_UINT32)(TW_CL_SWAP32(((TW_UINT32 *)(&(x)))[0]))))
251 #else /* TW_OSL_BIG_ENDIAN */
253 #define TW_CL_SWAP16_WITH_CAST(x) x
254 #define TW_CL_SWAP32_WITH_CAST(x) x
255 #define TW_CL_SWAP64_WITH_CAST(x) x
257 #endif /* TW_OSL_BIG_ENDIAN */
259 #define TW_CL_SWAP16(x) TW_CL_SWAP16_WITH_CAST((TW_UINT16)(x))
260 #define TW_CL_SWAP32(x) TW_CL_SWAP32_WITH_CAST((TW_UINT32)(x))
261 #define TW_CL_SWAP64(x) TW_CL_SWAP64_WITH_CAST((TW_UINT64)(x))
264 /* Queue manipulation functions. */
266 /* Initialize a queue. */
267 #define TW_CL_Q_INIT(head) do { \
268 (head)->prev = (head)->next = head; \
272 /* Insert an item at the head of the queue. */
273 #define TW_CL_Q_INSERT_HEAD(head, item) do { \
274 (item)->next = (head)->next; \
275 (item)->prev = head; \
276 (head)->next->prev = item; \
277 (head)->next = item; \
281 /* Insert an item at the tail of the queue. */
282 #define TW_CL_Q_INSERT_TAIL(head, item) do { \
283 (item)->next = head; \
284 (item)->prev = (head)->prev; \
285 (head)->prev->next = item; \
286 (head)->prev = item; \
290 /* Remove an item from the head of the queue. */
291 #define TW_CL_Q_REMOVE_ITEM(head, item) do { \
292 (item)->prev->next = (item)->next; \
293 (item)->next->prev = (item)->prev; \
297 /* Retrieve the item at the head of the queue. */
298 #define TW_CL_Q_FIRST_ITEM(head) \
299 (((head)->next != head) ? ((head)->next) : TW_CL_NULL)
302 /* Retrieve the item at the tail of the queue. */
303 #define TW_CL_Q_LAST_ITEM(head) \
304 (((head)->prev != head) ? ((head)->prev) : TW_CL_NULL)
307 /* Retrieve the item next to a given item in the queue. */
308 #define TW_CL_Q_NEXT_ITEM(head, item) \
309 (((item)->next != head) ? ((item)->next) : TW_CL_NULL)
312 /* Retrieve the item previous to a given item in the queue. */
313 #define TW_CL_Q_PREV_ITEM(head, item) \
314 (((item)->prev != head) ? ((item)->prev) : TW_CL_NULL)
317 /* Determine the offset of a field from the head of the structure it is in. */
318 #define TW_CL_STRUCT_OFFSET(struct_type, field) \
319 (TW_INT8 *)(&((struct_type *)0)->field)
323 * Determine the address of the head of a structure, given the address of a
326 #define TW_CL_STRUCT_HEAD(addr, struct_type, field) \
327 (struct_type *)((TW_INT8 *)addr - \
328 TW_CL_STRUCT_OFFSET(struct_type, field))
332 #ifndef TW_BUILDING_API
334 #include "tw_osl_inline.h"
339 * The following are extern declarations of OS Layer defined functions called
340 * by the Common Layer. If any function has been defined as a macro in
341 * tw_osl_share.h, we will not make the extern declaration here.
344 #ifndef tw_osl_breakpoint
345 /* Allows setting breakpoints in the CL code for debugging purposes. */
346 extern TW_VOID tw_osl_breakpoint(TW_VOID);
350 #ifndef tw_osl_ctlr_busy
351 /* Called when CL is too busy to accept new requests. */
352 extern TW_VOID tw_osl_ctlr_busy(struct tw_cl_ctlr_handle *ctlr_handle,
353 struct tw_cl_req_handle *req_handle);
357 #ifndef tw_osl_cur_func
358 /* Text name of current function. */
359 extern TW_INT8 *tw_osl_cur_func(TW_VOID);
364 #ifndef tw_osl_dbg_printf
365 /* Print to syslog/event log/debug console, as applicable. */
366 extern TW_INT32 tw_osl_dbg_printf(struct tw_cl_ctlr_handle *ctlr_handle,
367 const TW_INT8 *fmt, ...);
369 #endif /* TW_OSL_DEBUG */
373 /* Cause a delay of usecs micro-seconds. */
374 extern TW_VOID tw_osl_delay(TW_INT32 usecs);
378 #ifndef tw_osl_destroy_lock
379 /* Create/initialize a lock for CL's use. */
380 extern TW_VOID tw_osl_destroy_lock(struct tw_cl_ctlr_handle *ctlr_handle,
381 TW_LOCK_HANDLE *lock);
385 #ifndef tw_osl_free_lock
386 /* Free a previously held lock. */
387 extern TW_VOID tw_osl_free_lock(struct tw_cl_ctlr_handle *ctlr_handle,
388 TW_LOCK_HANDLE *lock);
392 #ifndef tw_osl_get_local_time
393 /* Get local time. */
394 extern TW_TIME tw_osl_get_local_time(TW_VOID);
398 #ifndef tw_osl_get_lock
399 /* Acquire a lock. */
400 extern TW_VOID tw_osl_get_lock(struct tw_cl_ctlr_handle *ctlr_handle,
401 TW_LOCK_HANDLE *lock);
405 #ifndef tw_osl_init_lock
406 /* Create/initialize a lock for CL's use. */
407 extern TW_VOID tw_osl_init_lock(struct tw_cl_ctlr_handle *ctlr_handle,
408 TW_INT8 *lock_name, TW_LOCK_HANDLE *lock);
412 #ifndef tw_osl_memcpy
413 /* Copy 'size' bytes from 'src' to 'dest'. */
414 extern TW_VOID tw_osl_memcpy(TW_VOID *src, TW_VOID *dest, TW_INT32 size);
418 #ifndef tw_osl_memzero
419 /* Zero 'size' bytes starting at 'addr'. */
420 extern TW_VOID tw_osl_memzero(TW_VOID *addr, TW_INT32 size);
424 #ifndef tw_osl_notify_event
425 /* Notify OSL of a controller/CL (or even OSL) event. */
426 extern TW_VOID tw_osl_notify_event(struct tw_cl_ctlr_handle *ctlr_handle,
427 struct tw_cl_event_packet *event);
431 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
432 #ifndef tw_osl_read_pci_config
433 /* Read 'size' bytes from 'offset' in the PCI config space. */
434 extern TW_UINT32 tw_osl_read_pci_config(
435 struct tw_cl_ctlr_handle *ctlr_handle, TW_INT32 offset, TW_INT32 size);
437 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
440 #ifndef tw_osl_read_reg
441 /* Read 'size' bytes at 'offset' from base address of this controller. */
442 extern TW_UINT32 tw_osl_read_reg(struct tw_cl_ctlr_handle *ctlr_handle,
443 TW_INT32 offset, TW_INT32 size);
447 #ifndef tw_osl_scan_bus
448 /* Request OSL for a bus scan. */
449 extern TW_VOID tw_osl_scan_bus(struct tw_cl_ctlr_handle *ctlr_handle);
453 #ifdef TW_OSL_CAN_SLEEP
455 /* Sleep for 'timeout' ms or until woken up (by tw_osl_wakeup). */
456 extern TW_INT32 tw_osl_sleep(struct tw_cl_ctlr_handle *ctlr_handle,
457 TW_SLEEP_HANDLE *sleep_handle, TW_INT32 timeout);
459 #endif /* TW_OSL_CAN_SLEEP */
462 #ifndef tw_osl_sprintf
463 /* Standard sprintf. */
464 extern TW_INT32 tw_osl_sprintf(TW_INT8 *dest, const TW_INT8 *fmt, ...);
468 #ifndef tw_osl_strcpy
469 /* Copy string 'src' to 'dest'. */
470 extern TW_INT8 *tw_osl_strcpy(TW_INT8 *dest, TW_INT8 *src);
474 #ifndef tw_osl_strlen
475 /* Return length of string pointed at by 'str'. */
476 extern TW_INT32 tw_osl_strlen(TW_VOID *str);
479 #ifndef tw_osl_vsprintf
480 /* Standard vsprintf. */
481 extern TW_INT32 tw_osl_vsprintf(TW_INT8 *dest, const TW_INT8 *fmt, va_list ap);
485 #ifdef TW_OSL_CAN_SLEEP
486 #ifndef tw_osl_wakeup
487 /* Wake up a thread sleeping by a call to tw_osl_sleep. */
488 extern TW_VOID tw_osl_wakeup(struct tw_cl_ctlr_handle *ctlr_handle,
489 TW_SLEEP_HANDLE *sleep_handle);
491 #endif /* TW_OSL_CAN_SLEEP */
494 #ifdef TW_OSL_PCI_CONFIG_ACCESSIBLE
495 #ifndef tw_osl_write_pci_config
496 /* Write 'value' of 'size' bytes at 'offset' in the PCI config space. */
497 extern TW_VOID tw_osl_write_pci_config(struct tw_cl_ctlr_handle *ctlr_handle,
498 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
500 #endif /* TW_OSL_PCI_CONFIG_ACCESSIBLE */
503 #ifndef tw_osl_write_reg
505 * Write 'value' of 'size' (max 4) bytes at 'offset' from base address of
508 extern TW_VOID tw_osl_write_reg(struct tw_cl_ctlr_handle *ctlr_handle,
509 TW_INT32 offset, TW_INT32 value, TW_INT32 size);
514 /* Functions in the Common Layer */
516 /* Creates and queues AEN's. Also notifies OS Layer. */
517 extern TW_VOID tw_cl_create_event(struct tw_cl_ctlr_handle *ctlr_handle,
518 TW_UINT8 queue_event, TW_UINT8 event_src, TW_UINT16 event_code,
519 TW_UINT8 severity, TW_UINT8 *severity_str, TW_UINT8 *event_desc,
520 TW_UINT8 *event_specific_desc, ...);
522 /* Indicates whether a ctlr is supported by CL. */
523 extern TW_INT32 tw_cl_ctlr_supported(TW_INT32 vendor_id, TW_INT32 device_id);
526 /* Submit a firmware cmd packet. */
527 extern TW_INT32 tw_cl_fw_passthru(struct tw_cl_ctlr_handle *ctlr_handle,
528 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
531 /* Find out how much memory CL needs. */
532 extern TW_INT32 tw_cl_get_mem_requirements(
533 struct tw_cl_ctlr_handle *ctlr_handle, TW_UINT32 flags,
534 TW_INT32 device_id, TW_INT32 max_simult_reqs, TW_INT32 max_aens,
535 TW_UINT32 *alignment, TW_UINT32 *sg_size_factor,
536 TW_UINT32 *non_dma_mem_size, TW_UINT32 *dma_mem_size
540 /* Return PCI BAR info. */
541 extern TW_INT32 tw_cl_get_pci_bar_info(TW_INT32 device_id, TW_INT32 bar_type,
542 TW_INT32 *bar_num, TW_INT32 *bar0_offset, TW_INT32 *bar_size);
545 /* Initialize Common Layer for a given controller. */
546 extern TW_INT32 tw_cl_init_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
547 TW_UINT32 flags, TW_INT32 device_id, TW_INT32 max_simult_reqs,
548 TW_INT32 max_aens, TW_VOID *non_dma_mem, TW_VOID *dma_mem,
549 TW_UINT64 dma_mem_phys
553 /* CL's interrupt handler. */
554 extern TW_INT32 tw_cl_interrupt(struct tw_cl_ctlr_handle *ctlr_handle);
557 /* CL's ioctl handler. */
558 extern TW_INT32 tw_cl_ioctl(struct tw_cl_ctlr_handle *ctlr_handle,
559 TW_INT32 cmd, TW_VOID *buf);
563 /* Print CL's state/statistics for a controller. */
564 extern TW_VOID tw_cl_print_ctlr_stats(struct tw_cl_ctlr_handle *ctlr_handle);
566 /* Prints CL internal details of a given request. */
567 extern TW_VOID tw_cl_print_req_info(struct tw_cl_req_handle *req_handle);
568 #endif /* TW_OSL_DEBUG */
571 /* Soft reset controller. */
572 extern TW_INT32 tw_cl_reset_ctlr(struct tw_cl_ctlr_handle *ctlr_handle);
576 /* Reset CL's statistics for a controller. */
577 extern TW_VOID tw_cl_reset_stats(struct tw_cl_ctlr_handle *ctlr_handle);
578 #endif /* TW_OSL_DEBUG */
581 /* Stop a controller. */
582 extern TW_INT32 tw_cl_shutdown_ctlr(struct tw_cl_ctlr_handle *ctlr_handle,
586 /* Submit a SCSI I/O request. */
587 extern TW_INT32 tw_cl_start_io(struct tw_cl_ctlr_handle *ctlr_handle,
588 struct tw_cl_req_packet *req_pkt, struct tw_cl_req_handle *req_handle);
591 #endif /* TW_BUILDING_API */
593 #endif /* TW_CL_SHARE_H */