2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
35 #include <sys/fcntl.h>
36 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
41 #include <sys/reboot.h>
42 #include <machine/bus.h>
44 #include <sys/termios.h>
45 #include <machine/resource.h>
46 #include <machine/stdarg.h>
48 #include <dev/uart/uart.h>
49 #include <dev/uart/uart_bus.h>
50 #include <dev/uart/uart_cpu.h>
54 devclass_t uart_devclass;
55 char uart_driver_name[] = "uart";
57 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs =
58 SLIST_HEAD_INITIALIZER(uart_sysdevs);
60 MALLOC_DEFINE(M_UART, "UART", "UART driver");
63 uart_add_sysdev(struct uart_devinfo *di)
65 SLIST_INSERT_HEAD(&uart_sysdevs, di, next);
69 uart_getname(struct uart_class *uc)
71 return ((uc != NULL) ? uc->name : NULL);
75 uart_getops(struct uart_class *uc)
77 return ((uc != NULL) ? uc->uc_ops : NULL);
81 uart_getrange(struct uart_class *uc)
83 return ((uc != NULL) ? uc->uc_range : 0);
87 * Schedule a soft interrupt. We do this on the 0 to !0 transition
88 * of the TTY pending interrupt status.
91 uart_sched_softih(struct uart_softc *sc, uint32_t ipend)
98 } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
100 if ((old & SER_INT_MASK) == 0)
101 swi_sched(sc->sc_softih, 0);
105 * A break condition has been detected. We treat the break condition as
106 * a special case that should not happen during normal operation. When
107 * the break condition is to be passed to higher levels in the form of
108 * a NUL character, we really want the break to be in the right place in
109 * the input stream. The overhead to achieve that is not in relation to
110 * the exceptional nature of the break condition, so we permit ourselves
114 uart_intr_break(void *arg)
116 struct uart_softc *sc = arg;
119 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
125 uart_sched_softih(sc, SER_INT_BREAK);
130 * Handle a receiver overrun situation. We lost at least 1 byte in the
131 * input stream and it's our job to contain the situation. We grab as
132 * much of the data we can, but otherwise flush the receiver FIFO to
133 * create some breathing room. The net effect is that we avoid the
134 * overrun condition to happen for the next X characters, where X is
135 * related to the FIFO size at the cost of loosing data right away.
136 * So, instead of having multiple overrun interrupts in close proximity
137 * to each other and possibly pessimizing UART interrupt latency for
138 * other UARTs in a multiport configuration, we create a longer segment
139 * of missing characters by freeing up the FIFO.
140 * Each overrun condition is marked in the input buffer by a token. The
141 * token represents the loss of at least one, but possible more bytes in
145 uart_intr_overrun(void *arg)
147 struct uart_softc *sc = arg;
151 if (uart_rx_put(sc, UART_STAT_OVERRUN))
152 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
153 uart_sched_softih(sc, SER_INT_RXREADY);
155 UART_FLUSH(sc, UART_FLUSH_RECEIVER);
160 * Received data ready.
163 uart_intr_rxready(void *arg)
165 struct uart_softc *sc = arg;
171 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
172 while (rxp != sc->sc_rxput) {
173 kdb_alt_break(sc->sc_rxbuf[rxp++], &sc->sc_altbrk);
174 if (rxp == sc->sc_rxbufsz)
180 uart_sched_softih(sc, SER_INT_RXREADY);
182 sc->sc_rxput = sc->sc_rxget; /* Ignore received data. */
187 * Line or modem status change (OOB signalling).
188 * We pass the signals to the software interrupt handler for further
189 * processing. Note that we merge the delta bits, but set the state
190 * bits. This is to avoid loosing state transitions due to having more
191 * than 1 hardware interrupt between software interrupts.
194 uart_intr_sigchg(void *arg)
196 struct uart_softc *sc = arg;
199 sig = UART_GETSIG(sc);
201 if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
202 if (sig & UART_SIG_DPPS) {
203 pps_capture(&sc->sc_pps);
204 pps_event(&sc->sc_pps, (sig & UART_SIG_PPS) ?
205 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
210 * Keep track of signal changes, even when the device is not
211 * opened. This allows us to inform upper layers about a
212 * possible loss of DCD and thus the existence of a (possibly)
213 * different connection when we have DCD back, during the time
214 * that the device was closed.
217 old = sc->sc_ttypend;
218 new = old & ~SER_MASK_STATE;
219 new |= sig & SER_INT_SIGMASK;
220 } while (!atomic_cmpset_32(&sc->sc_ttypend, old, new));
223 uart_sched_softih(sc, SER_INT_SIGCHG);
228 * The transmitter can accept more data.
231 uart_intr_txidle(void *arg)
233 struct uart_softc *sc = arg;
237 uart_sched_softih(sc, SER_INT_TXIDLE);
245 struct uart_softc *sc = arg;
248 while (!sc->sc_leaving && (ipend = UART_IPEND(sc)) != 0) {
250 if (ipend & SER_INT_OVERRUN)
251 uart_intr_overrun(sc);
252 if (ipend & SER_INT_BREAK)
254 if (ipend & SER_INT_RXREADY)
255 uart_intr_rxready(sc);
256 if (ipend & SER_INT_SIGCHG)
257 uart_intr_sigchg(sc);
258 if (ipend & SER_INT_TXIDLE)
259 uart_intr_txidle(sc);
261 return((flag)?FILTER_HANDLED:FILTER_STRAY);
265 uart_bus_ihand(device_t dev, int ipend)
270 return (uart_intr_break);
271 case SER_INT_OVERRUN:
272 return (uart_intr_overrun);
273 case SER_INT_RXREADY:
274 return (uart_intr_rxready);
276 return (uart_intr_sigchg);
278 return (uart_intr_txidle);
284 uart_bus_ipend(device_t dev)
286 struct uart_softc *sc;
288 sc = device_get_softc(dev);
289 return (UART_IPEND(sc));
293 uart_bus_sysdev(device_t dev)
295 struct uart_softc *sc;
297 sc = device_get_softc(dev);
298 return ((sc->sc_sysdev != NULL) ? 1 : 0);
302 uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan)
304 struct uart_softc *sc;
305 struct uart_devinfo *sysdev;
308 sc = device_get_softc(dev);
311 * All uart_class references are weak. Check that the needed
312 * class has been compiled-in. Fail if not.
314 if (sc->sc_class == NULL)
318 * Initialize the instance. Note that the instance (=softc) does
319 * not necessarily match the hardware specific softc. We can't do
320 * anything about it now, because we may not attach to the device.
321 * Hardware drivers cannot use any of the class specific fields
324 kobj_init((kobj_t)sc, (kobj_class_t)sc->sc_class);
326 if (device_get_desc(dev) == NULL)
327 device_set_desc(dev, uart_getname(sc->sc_class));
330 * Allocate the register resource. We assume that all UARTs have
331 * a single register window in either I/O port space or memory
332 * mapped I/O space. Any UART that needs multiple windows will
333 * consequently not be supported by this driver as-is. We try I/O
334 * port space first because that's the common case.
337 sc->sc_rtype = SYS_RES_IOPORT;
338 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid,
339 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE);
340 if (sc->sc_rres == NULL) {
342 sc->sc_rtype = SYS_RES_MEMORY;
343 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype,
344 &sc->sc_rrid, 0, ~0, uart_getrange(sc->sc_class),
346 if (sc->sc_rres == NULL)
351 * Fill in the bus access structure and compare this device with
352 * a possible console device and/or a debug port. We set the flags
353 * in the softc so that the hardware dependent probe can adjust
354 * accordingly. In general, you don't want to permanently disrupt
357 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
358 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
359 sc->sc_bas.chan = chan;
360 sc->sc_bas.regshft = regshft;
361 sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk;
363 SLIST_FOREACH(sysdev, &uart_sysdevs, next) {
364 if (chan == sysdev->bas.chan &&
365 uart_cpu_eqres(&sc->sc_bas, &sysdev->bas)) {
366 /* XXX check if ops matches class. */
367 sc->sc_sysdev = sysdev;
368 sysdev->bas.rclk = sc->sc_bas.rclk;
372 error = UART_PROBE(sc);
373 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
374 return ((error) ? error : BUS_PROBE_DEFAULT);
378 uart_bus_attach(device_t dev)
380 struct uart_softc *sc, *sc0;
385 * The sc_class field defines the type of UART we're going to work
386 * with and thus the size of the softc. Replace the generic softc
387 * with one that matches the UART now that we're certain we handle
390 sc0 = device_get_softc(dev);
391 if (sc0->sc_class->size > sizeof(*sc)) {
392 sc = malloc(sc0->sc_class->size, M_UART, M_WAITOK|M_ZERO);
393 bcopy(sc0, sc, sizeof(*sc));
394 device_set_softc(dev, sc);
399 * Protect ourselves against interrupts while we're not completely
400 * finished attaching and initializing. We don't expect interrupts
401 * until after UART_ATTACH() though.
405 mtx_init(&sc->sc_hwmtx_s, "uart_hwmtx", NULL, MTX_SPIN);
406 if (sc->sc_hwmtx == NULL)
407 sc->sc_hwmtx = &sc->sc_hwmtx_s;
410 * Re-allocate. We expect that the softc contains the information
411 * collected by uart_bus_probe() intact.
413 sc->sc_rres = bus_alloc_resource(dev, sc->sc_rtype, &sc->sc_rrid,
414 0, ~0, uart_getrange(sc->sc_class), RF_ACTIVE);
415 if (sc->sc_rres == NULL) {
416 mtx_destroy(&sc->sc_hwmtx_s);
419 sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
420 sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
423 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
424 RF_ACTIVE | RF_SHAREABLE);
425 if (sc->sc_ires != NULL) {
426 error = bus_setup_intr(dev,
427 sc->sc_ires, INTR_TYPE_TTY,
428 uart_intr, NULL, sc, &sc->sc_icookie);
430 error = bus_setup_intr(dev,
431 sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE,
432 NULL, (driver_intr_t *)uart_intr, sc, &sc->sc_icookie);
437 device_printf(dev, "could not activate interrupt\n");
438 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
443 if (sc->sc_ires == NULL) {
444 /* XXX no interrupt resource. Force polled mode. */
448 sc->sc_rxbufsz = 384;
449 sc->sc_rxbuf = malloc(sc->sc_rxbufsz * sizeof(*sc->sc_rxbuf),
451 sc->sc_txbuf = malloc(sc->sc_txfifosz * sizeof(*sc->sc_txbuf),
454 error = UART_ATTACH(sc);
458 if (sc->sc_hwiflow || sc->sc_hwoflow) {
460 device_print_prettyname(dev);
461 if (sc->sc_hwiflow) {
462 printf("%sRTS iflow", sep);
465 if (sc->sc_hwoflow) {
466 printf("%sCTS oflow", sep);
472 if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) {
474 device_print_prettyname(dev);
475 if (sc->sc_fastintr) {
476 printf("%sfast interrupt", sep);
480 printf("%spolled mode", sep);
486 if (sc->sc_sysdev != NULL) {
487 if (sc->sc_sysdev->baudrate == 0) {
488 if (UART_IOCTL(sc, UART_IOCTL_BAUD,
489 (intptr_t)&sc->sc_sysdev->baudrate) != 0)
490 sc->sc_sysdev->baudrate = -1;
492 switch (sc->sc_sysdev->type) {
493 case UART_DEV_CONSOLE:
494 device_printf(dev, "console");
496 case UART_DEV_DBGPORT:
497 device_printf(dev, "debug port");
499 case UART_DEV_KEYBOARD:
500 device_printf(dev, "keyboard");
503 device_printf(dev, "unknown system device");
506 printf(" (%d,%c,%d,%d)\n", sc->sc_sysdev->baudrate,
507 "noems"[sc->sc_sysdev->parity], sc->sc_sysdev->databits,
508 sc->sc_sysdev->stopbits);
511 sc->sc_pps.ppscap = PPS_CAPTUREBOTH;
512 pps_init(&sc->sc_pps);
514 error = (sc->sc_sysdev != NULL && sc->sc_sysdev->attach != NULL)
515 ? (*sc->sc_sysdev->attach)(sc) : uart_tty_attach(sc);
519 if (sc->sc_sysdev != NULL)
520 sc->sc_sysdev->hwmtx = sc->sc_hwmtx;
527 free(sc->sc_txbuf, M_UART);
528 free(sc->sc_rxbuf, M_UART);
530 if (sc->sc_ires != NULL) {
531 bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
532 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
535 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
537 mtx_destroy(&sc->sc_hwmtx_s);
543 uart_bus_detach(device_t dev)
545 struct uart_softc *sc;
547 sc = device_get_softc(dev);
551 if (sc->sc_sysdev != NULL)
552 sc->sc_sysdev->hwmtx = NULL;
556 if (sc->sc_sysdev != NULL && sc->sc_sysdev->detach != NULL)
557 (*sc->sc_sysdev->detach)(sc);
561 free(sc->sc_txbuf, M_UART);
562 free(sc->sc_rxbuf, M_UART);
564 if (sc->sc_ires != NULL) {
565 bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
566 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
569 bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
571 mtx_destroy(&sc->sc_hwmtx_s);
573 if (sc->sc_class->size > sizeof(*sc)) {
574 device_set_softc(dev, NULL);
577 device_set_softc(dev, NULL);
583 uart_bus_resume(device_t dev)
585 struct uart_softc *sc;
587 sc = device_get_softc(dev);
588 return (UART_ATTACH(sc));