2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
41 #include <arm/lpc/lpcreg.h>
45 #define DEFAULT_RCLK (13 * 1000 * 1000)
46 #define LPC_UART_NO(_bas) (((_bas->bsh) - LPC_UART_BASE) >> 15)
48 #define lpc_ns8250_get_auxreg(_bas, _reg) \
49 bus_space_read_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg)
50 #define lpc_ns8250_set_auxreg(_bas, _reg, _val) \
51 bus_space_write_4((_bas)->bst, LPC_UART_CONTROL_BASE, _reg, _val);
52 #define lpc_ns8250_get_clkreg(_bas, _reg) \
53 bus_space_read_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg))
54 #define lpc_ns8250_set_clkreg(_bas, _reg, _val) \
55 bus_space_write_4((_bas)->bst, LPC_CLKPWR_BASE, (_reg), (_val))
58 * Clear pending interrupts. THRE is cleared by reading IIR. Data
59 * that may have been received gets lost here.
62 lpc_ns8250_clrint(struct uart_bas *bas)
66 iir = uart_getreg(bas, REG_IIR);
67 while ((iir & IIR_NOPEND) == 0) {
70 lsr = uart_getreg(bas, REG_LSR);
71 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
72 (void)uart_getreg(bas, REG_DATA);
73 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
74 (void)uart_getreg(bas, REG_DATA);
75 else if (iir == IIR_MLSC)
76 (void)uart_getreg(bas, REG_MSR);
78 iir = uart_getreg(bas, REG_IIR);
83 lpc_ns8250_delay(struct uart_bas *bas)
88 uclk = lpc_ns8250_get_clkreg(bas, LPC_CLKPWR_UART_U5CLK);
90 x = (uclk >> 8) & 0xff;
93 return (16000000 / (bas->rclk * x / y));
97 lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y)
142 lpc_ns8250_drain(struct uart_bas *bas, int what)
146 delay = lpc_ns8250_delay(bas);
148 if (what & UART_DRAIN_TRANSMITTER) {
150 * Pick an arbitrary high limit to avoid getting stuck in
151 * an infinite loop when the hardware is broken. Make the
152 * limit high enough to handle large FIFOs.
155 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
158 /* printf("lpc_ns8250: transmitter appears stuck... "); */
163 if (what & UART_DRAIN_RECEIVER) {
165 * Pick an arbitrary high limit to avoid getting stuck in
166 * an infinite loop when the hardware is broken. Make the
167 * limit high enough to handle large FIFOs and integrated
168 * UARTs. The HP rx2600 for example has 3 UARTs on the
169 * management board that tend to get a lot of data send
170 * to it when the UART is first activated.
173 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
174 (void)uart_getreg(bas, REG_DATA);
179 /* printf("lpc_ns8250: receiver appears broken... "); */
188 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
189 * drained. WARNING: this function clobbers the FIFO setting!
192 lpc_ns8250_flush(struct uart_bas *bas, int what)
197 if (what & UART_FLUSH_TRANSMITTER)
199 if (what & UART_FLUSH_RECEIVER)
201 uart_setreg(bas, REG_FCR, fcr);
206 lpc_ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
215 else if (databits == 7)
217 else if (databits == 6)
227 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
229 uart_setreg(bas, REG_DLL, 0x00);
230 uart_setreg(bas, REG_DLH, 0x00);
233 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv);
234 lpc_ns8250_set_clkreg(bas,
235 LPC_CLKPWR_UART_U5CLK,
236 LPC_CLKPWR_UART_UCLK_X(xdiv) |
237 LPC_CLKPWR_UART_UCLK_Y(ydiv));
240 /* Set LCR and clear DLAB. */
241 uart_setreg(bas, REG_LCR, lcr);
247 * Low-level UART interface.
249 static int lpc_ns8250_probe(struct uart_bas *bas);
250 static void lpc_ns8250_init(struct uart_bas *bas, int, int, int, int);
251 static void lpc_ns8250_term(struct uart_bas *bas);
252 static void lpc_ns8250_putc(struct uart_bas *bas, int);
253 static int lpc_ns8250_rxready(struct uart_bas *bas);
254 static int lpc_ns8250_getc(struct uart_bas *bas, struct mtx *);
256 static struct uart_ops uart_lpc_ns8250_ops = {
257 .probe = lpc_ns8250_probe,
258 .init = lpc_ns8250_init,
259 .term = lpc_ns8250_term,
260 .putc = lpc_ns8250_putc,
261 .rxready = lpc_ns8250_rxready,
262 .getc = lpc_ns8250_getc,
266 lpc_ns8250_probe(struct uart_bas *bas)
271 /* Check known 0 bits that don't depend on DLAB. */
272 val = uart_getreg(bas, REG_IIR);
276 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
277 * chip, but otherwise doesn't seem to have a function. In
278 * other words, uart(4) works regardless. Ignore that bit so
279 * the probe succeeds.
281 val = uart_getreg(bas, REG_MCR);
289 lpc_ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
295 /* Enable UART clock */
296 clkmode = lpc_ns8250_get_auxreg(bas, LPC_UART_CLKMODE);
297 lpc_ns8250_set_auxreg(bas, LPC_UART_CLKMODE,
298 clkmode | LPC_UART_CLKMODE_UART5(1));
300 /* Work around H/W bug */
301 uart_setreg(bas, REG_DATA, 0x00);
304 bas->rclk = DEFAULT_RCLK;
305 lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
307 /* Disable all interrupt sources. */
309 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
310 * UARTs split the receive time-out interrupt bit out separately as
311 * 0x10. This gets handled by ier_mask and ier_rxbits below.
313 ier = uart_getreg(bas, REG_IER) & 0xe0;
314 uart_setreg(bas, REG_IER, ier);
317 /* Disable the FIFO (if present). */
318 uart_setreg(bas, REG_FCR, 0);
322 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
325 lpc_ns8250_clrint(bas);
329 lpc_ns8250_term(struct uart_bas *bas)
332 /* Clear RTS & DTR. */
333 uart_setreg(bas, REG_MCR, MCR_IE);
338 lpc_ns8250_putc(struct uart_bas *bas, int c)
343 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
345 uart_setreg(bas, REG_DATA, c);
348 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
353 lpc_ns8250_rxready(struct uart_bas *bas)
356 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
360 lpc_ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
366 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
372 c = uart_getreg(bas, REG_DATA);
380 * High-level UART interface.
382 struct lpc_ns8250_softc {
383 struct uart_softc base;
392 static int lpc_ns8250_bus_attach(struct uart_softc *);
393 static int lpc_ns8250_bus_detach(struct uart_softc *);
394 static int lpc_ns8250_bus_flush(struct uart_softc *, int);
395 static int lpc_ns8250_bus_getsig(struct uart_softc *);
396 static int lpc_ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
397 static int lpc_ns8250_bus_ipend(struct uart_softc *);
398 static int lpc_ns8250_bus_param(struct uart_softc *, int, int, int, int);
399 static int lpc_ns8250_bus_probe(struct uart_softc *);
400 static int lpc_ns8250_bus_receive(struct uart_softc *);
401 static int lpc_ns8250_bus_setsig(struct uart_softc *, int);
402 static int lpc_ns8250_bus_transmit(struct uart_softc *);
404 static kobj_method_t lpc_ns8250_methods[] = {
405 KOBJMETHOD(uart_attach, lpc_ns8250_bus_attach),
406 KOBJMETHOD(uart_detach, lpc_ns8250_bus_detach),
407 KOBJMETHOD(uart_flush, lpc_ns8250_bus_flush),
408 KOBJMETHOD(uart_getsig, lpc_ns8250_bus_getsig),
409 KOBJMETHOD(uart_ioctl, lpc_ns8250_bus_ioctl),
410 KOBJMETHOD(uart_ipend, lpc_ns8250_bus_ipend),
411 KOBJMETHOD(uart_param, lpc_ns8250_bus_param),
412 KOBJMETHOD(uart_probe, lpc_ns8250_bus_probe),
413 KOBJMETHOD(uart_receive, lpc_ns8250_bus_receive),
414 KOBJMETHOD(uart_setsig, lpc_ns8250_bus_setsig),
415 KOBJMETHOD(uart_transmit, lpc_ns8250_bus_transmit),
419 struct uart_class uart_lpc_class = {
422 sizeof(struct lpc_ns8250_softc),
423 .uc_ops = &uart_lpc_ns8250_ops,
425 .uc_rclk = DEFAULT_RCLK
428 #define SIGCHG(c, i, s, d) \
430 i |= (i & s) ? s : s | d; \
432 i = (i & s) ? (i & ~s) | d : i; \
436 lpc_ns8250_bus_attach(struct uart_softc *sc)
438 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
439 struct uart_bas *bas;
444 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR);
445 lpc_ns8250->fcr = FCR_ENABLE | FCR_DMA;
446 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
448 if (UART_FLAGS_FCR_RX_LOW(ivar))
449 lpc_ns8250->fcr |= FCR_RX_LOW;
450 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
451 lpc_ns8250->fcr |= FCR_RX_MEDL;
452 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
453 lpc_ns8250->fcr |= FCR_RX_HIGH;
455 lpc_ns8250->fcr |= FCR_RX_MEDH;
457 lpc_ns8250->fcr |= FCR_RX_HIGH;
461 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
463 lpc_ns8250->ier_mask = (uint8_t)(ivar & 0xff);
465 /* Get IER RX interrupt bits */
466 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
467 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
469 lpc_ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
471 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
473 lpc_ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
475 if (lpc_ns8250->mcr & MCR_DTR)
476 sc->sc_hwsig |= SER_DTR;
477 if (lpc_ns8250->mcr & MCR_RTS)
478 sc->sc_hwsig |= SER_RTS;
479 lpc_ns8250_bus_getsig(sc);
481 lpc_ns8250_clrint(bas);
482 lpc_ns8250->ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
483 lpc_ns8250->ier |= lpc_ns8250->ier_rxbits;
484 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
491 lpc_ns8250_bus_detach(struct uart_softc *sc)
493 struct lpc_ns8250_softc *lpc_ns8250;
494 struct uart_bas *bas;
497 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
499 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
500 uart_setreg(bas, REG_IER, ier);
502 lpc_ns8250_clrint(bas);
507 lpc_ns8250_bus_flush(struct uart_softc *sc, int what)
509 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
510 struct uart_bas *bas;
514 uart_lock(sc->sc_hwmtx);
515 if (sc->sc_rxfifosz > 1) {
516 lpc_ns8250_flush(bas, what);
517 uart_setreg(bas, REG_FCR, lpc_ns8250->fcr);
521 error = lpc_ns8250_drain(bas, what);
522 uart_unlock(sc->sc_hwmtx);
527 lpc_ns8250_bus_getsig(struct uart_softc *sc)
529 uint32_t new, old, sig;
535 uart_lock(sc->sc_hwmtx);
536 msr = uart_getreg(&sc->sc_bas, REG_MSR);
537 uart_unlock(sc->sc_hwmtx);
538 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
539 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
540 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
541 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
542 new = sig & ~SER_MASK_DELTA;
543 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
548 lpc_ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
550 struct uart_bas *bas;
551 int baudrate, divisor, error;
556 uart_lock(sc->sc_hwmtx);
558 case UART_IOCTL_BREAK:
559 lcr = uart_getreg(bas, REG_LCR);
564 uart_setreg(bas, REG_LCR, lcr);
567 case UART_IOCTL_IFLOW:
568 lcr = uart_getreg(bas, REG_LCR);
570 uart_setreg(bas, REG_LCR, 0xbf);
572 efr = uart_getreg(bas, REG_EFR);
577 uart_setreg(bas, REG_EFR, efr);
579 uart_setreg(bas, REG_LCR, lcr);
582 case UART_IOCTL_OFLOW:
583 lcr = uart_getreg(bas, REG_LCR);
585 uart_setreg(bas, REG_LCR, 0xbf);
587 efr = uart_getreg(bas, REG_EFR);
592 uart_setreg(bas, REG_EFR, efr);
594 uart_setreg(bas, REG_LCR, lcr);
597 case UART_IOCTL_BAUD:
598 lcr = uart_getreg(bas, REG_LCR);
599 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
601 divisor = uart_getreg(bas, REG_DLL) |
602 (uart_getreg(bas, REG_DLH) << 8);
604 uart_setreg(bas, REG_LCR, lcr);
606 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
608 *(int*)data = baudrate;
616 uart_unlock(sc->sc_hwmtx);
621 lpc_ns8250_bus_ipend(struct uart_softc *sc)
623 struct uart_bas *bas;
624 struct lpc_ns8250_softc *lpc_ns8250;
628 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
630 uart_lock(sc->sc_hwmtx);
631 iir = uart_getreg(bas, REG_IIR);
632 if (iir & IIR_NOPEND) {
633 uart_unlock(sc->sc_hwmtx);
637 if (iir & IIR_RXRDY) {
638 lsr = uart_getreg(bas, REG_LSR);
640 ipend |= SER_INT_OVERRUN;
642 ipend |= SER_INT_BREAK;
644 ipend |= SER_INT_RXREADY;
646 if (iir & IIR_TXRDY) {
647 ipend |= SER_INT_TXIDLE;
648 uart_setreg(bas, REG_IER, lpc_ns8250->ier);
650 ipend |= SER_INT_SIGCHG;
653 lpc_ns8250_clrint(bas);
654 uart_unlock(sc->sc_hwmtx);
659 lpc_ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
660 int stopbits, int parity)
662 struct uart_bas *bas;
666 uart_lock(sc->sc_hwmtx);
667 error = lpc_ns8250_param(bas, baudrate, databits, stopbits, parity);
668 uart_unlock(sc->sc_hwmtx);
673 lpc_ns8250_bus_probe(struct uart_softc *sc)
675 struct lpc_ns8250_softc *lpc_ns8250;
676 struct uart_bas *bas;
677 int count, delay, error, limit;
678 uint8_t lsr, mcr, ier;
680 lpc_ns8250 = (struct lpc_ns8250_softc *)sc;
683 error = lpc_ns8250_probe(bas);
688 if (sc->sc_sysdev == NULL) {
689 /* By using lpc_ns8250_init() we also set DTR and RTS. */
690 lpc_ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
692 mcr |= MCR_DTR | MCR_RTS;
694 error = lpc_ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
699 * Set loopback mode. This avoids having garbage on the wire and
700 * also allows us send and receive data. We set DTR and RTS to
701 * avoid the possibility that automatic flow-control prevents
702 * any data from being sent.
704 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
708 * Enable FIFOs. And check that the UART has them. If not, we're
709 * done. Since this is the first time we enable the FIFOs, we reset
712 uart_setreg(bas, REG_FCR, FCR_ENABLE);
714 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
716 * NS16450 or INS8250. We don't bother to differentiate
717 * between them. They're too old to be interesting.
719 uart_setreg(bas, REG_MCR, mcr);
721 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
722 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
726 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
730 delay = lpc_ns8250_delay(bas);
732 /* We have FIFOs. Drain the transmitter and receiver. */
733 error = lpc_ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
735 uart_setreg(bas, REG_MCR, mcr);
736 uart_setreg(bas, REG_FCR, 0);
742 * We should have a sufficiently clean "pipe" to determine the
743 * size of the FIFOs. We send as much characters as is reasonable
744 * and wait for the overflow bit in the LSR register to be
745 * asserted, counting the characters as we send them. Based on
746 * that count we know the FIFO size.
749 uart_setreg(bas, REG_DATA, 0);
756 * LSR bits are cleared upon read, so we must accumulate
757 * them to be able to test LSR_OE below.
759 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
763 ier = uart_getreg(bas, REG_IER) & lpc_ns8250->ier_mask;
764 uart_setreg(bas, REG_IER, ier);
765 uart_setreg(bas, REG_MCR, mcr);
766 uart_setreg(bas, REG_FCR, 0);
771 } while ((lsr & LSR_OE) == 0 && count < 130);
774 uart_setreg(bas, REG_MCR, mcr);
777 lpc_ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
780 sc->sc_rxfifosz = 64;
781 device_set_desc(sc->sc_dev, "LPC32x0 UART with FIFOs");
784 * Force the Tx FIFO size to 16 bytes for now. We don't program the
785 * Tx trigger. Also, we assume that all data has been sent when the
788 sc->sc_txfifosz = 16;
792 * XXX there are some issues related to hardware flow control and
793 * it's likely that uart(4) is the cause. This basicly needs more
794 * investigation, but we avoid using for hardware flow control
797 /* 16650s or higher have automatic flow control. */
798 if (sc->sc_rxfifosz > 16) {
807 lpc_ns8250_bus_receive(struct uart_softc *sc)
809 struct uart_bas *bas;
814 uart_lock(sc->sc_hwmtx);
815 lsr = uart_getreg(bas, REG_LSR);
816 while (lsr & LSR_RXRDY) {
817 if (uart_rx_full(sc)) {
818 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
821 xc = uart_getreg(bas, REG_DATA);
823 xc |= UART_STAT_FRAMERR;
825 xc |= UART_STAT_PARERR;
827 lsr = uart_getreg(bas, REG_LSR);
829 /* Discard everything left in the Rx FIFO. */
830 while (lsr & LSR_RXRDY) {
831 (void)uart_getreg(bas, REG_DATA);
833 lsr = uart_getreg(bas, REG_LSR);
835 uart_unlock(sc->sc_hwmtx);
840 lpc_ns8250_bus_setsig(struct uart_softc *sc, int sig)
842 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
843 struct uart_bas *bas;
850 if (sig & SER_DDTR) {
851 SIGCHG(sig & SER_DTR, new, SER_DTR,
854 if (sig & SER_DRTS) {
855 SIGCHG(sig & SER_RTS, new, SER_RTS,
858 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
859 uart_lock(sc->sc_hwmtx);
860 lpc_ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
862 lpc_ns8250->mcr |= MCR_DTR;
864 lpc_ns8250->mcr |= MCR_RTS;
865 uart_setreg(bas, REG_MCR, lpc_ns8250->mcr);
867 uart_unlock(sc->sc_hwmtx);
872 lpc_ns8250_bus_transmit(struct uart_softc *sc)
874 struct lpc_ns8250_softc *lpc_ns8250 = (struct lpc_ns8250_softc*)sc;
875 struct uart_bas *bas;
879 uart_lock(sc->sc_hwmtx);
880 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
882 uart_setreg(bas, REG_IER, lpc_ns8250->ier | IER_ETXRDY);
884 for (i = 0; i < sc->sc_txdatasz; i++) {
885 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
889 uart_unlock(sc->sc_hwmtx);