2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/ns16550.h>
44 #define DEFAULT_RCLK 1843200
47 * Clear pending interrupts. THRE is cleared by reading IIR. Data
48 * that may have been received gets lost here.
51 ns8250_clrint(struct uart_bas *bas)
55 iir = uart_getreg(bas, REG_IIR);
56 while ((iir & IIR_NOPEND) == 0) {
59 lsr = uart_getreg(bas, REG_LSR);
60 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
61 (void)uart_getreg(bas, REG_DATA);
62 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
63 (void)uart_getreg(bas, REG_DATA);
64 else if (iir == IIR_MLSC)
65 (void)uart_getreg(bas, REG_MSR);
67 iir = uart_getreg(bas, REG_IIR);
72 ns8250_delay(struct uart_bas *bas)
77 lcr = uart_getreg(bas, REG_LCR);
78 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
80 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
82 uart_setreg(bas, REG_LCR, lcr);
85 /* 1/10th the time to transmit 1 character (estimate). */
87 return (16000000 * divisor / bas->rclk);
88 return (16000 * divisor / (bas->rclk / 1000));
92 ns8250_divisor(int rclk, int baudrate)
94 int actual_baud, divisor;
100 divisor = (rclk / (baudrate << 3) + 1) >> 1;
101 if (divisor == 0 || divisor >= 65536)
103 actual_baud = rclk / (divisor << 4);
105 /* 10 times error in percent: */
106 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
108 /* 3.0% maximum error tolerance: */
109 if (error < -30 || error > 30)
116 ns8250_drain(struct uart_bas *bas, int what)
120 delay = ns8250_delay(bas);
122 if (what & UART_DRAIN_TRANSMITTER) {
124 * Pick an arbitrary high limit to avoid getting stuck in
125 * an infinite loop when the hardware is broken. Make the
126 * limit high enough to handle large FIFOs.
129 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
132 /* printf("ns8250: transmitter appears stuck... "); */
137 if (what & UART_DRAIN_RECEIVER) {
139 * Pick an arbitrary high limit to avoid getting stuck in
140 * an infinite loop when the hardware is broken. Make the
141 * limit high enough to handle large FIFOs and integrated
142 * UARTs. The HP rx2600 for example has 3 UARTs on the
143 * management board that tend to get a lot of data send
144 * to it when the UART is first activated.
147 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
148 (void)uart_getreg(bas, REG_DATA);
153 /* printf("ns8250: receiver appears broken... "); */
162 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
163 * drained. WARNING: this function clobbers the FIFO setting!
166 ns8250_flush(struct uart_bas *bas, int what)
171 if (what & UART_FLUSH_TRANSMITTER)
173 if (what & UART_FLUSH_RECEIVER)
175 uart_setreg(bas, REG_FCR, fcr);
180 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
189 else if (databits == 7)
191 else if (databits == 6)
201 divisor = ns8250_divisor(bas->rclk, baudrate);
204 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
206 uart_setreg(bas, REG_DLL, divisor & 0xff);
207 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
211 /* Set LCR and clear DLAB. */
212 uart_setreg(bas, REG_LCR, lcr);
218 * Low-level UART interface.
220 static int ns8250_probe(struct uart_bas *bas);
221 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
222 static void ns8250_term(struct uart_bas *bas);
223 static void ns8250_putc(struct uart_bas *bas, int);
224 static int ns8250_rxready(struct uart_bas *bas);
225 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
227 static struct uart_ops uart_ns8250_ops = {
228 .probe = ns8250_probe,
232 .rxready = ns8250_rxready,
237 ns8250_probe(struct uart_bas *bas)
241 /* Check known 0 bits that don't depend on DLAB. */
242 val = uart_getreg(bas, REG_IIR);
246 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
247 * chip, but otherwise doesn't seem to have a function. In
248 * other words, uart(4) works regardless. Ignore that bit so
249 * the probe succeeds.
251 val = uart_getreg(bas, REG_MCR);
259 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
265 bas->rclk = DEFAULT_RCLK;
266 ns8250_param(bas, baudrate, databits, stopbits, parity);
268 /* Disable all interrupt sources. */
270 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
271 * UARTs split the receive time-out interrupt bit out separately as
272 * 0x10. This gets handled by ier_mask and ier_rxbits below.
274 ier = uart_getreg(bas, REG_IER) & 0xe0;
275 uart_setreg(bas, REG_IER, ier);
278 /* Disable the FIFO (if present). */
279 uart_setreg(bas, REG_FCR, 0);
283 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
290 ns8250_term(struct uart_bas *bas)
293 /* Clear RTS & DTR. */
294 uart_setreg(bas, REG_MCR, MCR_IE);
299 ns8250_putc(struct uart_bas *bas, int c)
304 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
306 uart_setreg(bas, REG_DATA, c);
309 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
314 ns8250_rxready(struct uart_bas *bas)
317 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
321 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
327 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
333 c = uart_getreg(bas, REG_DATA);
341 * High-level UART interface.
343 struct ns8250_softc {
344 struct uart_softc base;
353 static int ns8250_bus_attach(struct uart_softc *);
354 static int ns8250_bus_detach(struct uart_softc *);
355 static int ns8250_bus_flush(struct uart_softc *, int);
356 static int ns8250_bus_getsig(struct uart_softc *);
357 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
358 static int ns8250_bus_ipend(struct uart_softc *);
359 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
360 static int ns8250_bus_probe(struct uart_softc *);
361 static int ns8250_bus_receive(struct uart_softc *);
362 static int ns8250_bus_setsig(struct uart_softc *, int);
363 static int ns8250_bus_transmit(struct uart_softc *);
365 static kobj_method_t ns8250_methods[] = {
366 KOBJMETHOD(uart_attach, ns8250_bus_attach),
367 KOBJMETHOD(uart_detach, ns8250_bus_detach),
368 KOBJMETHOD(uart_flush, ns8250_bus_flush),
369 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
370 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
371 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
372 KOBJMETHOD(uart_param, ns8250_bus_param),
373 KOBJMETHOD(uart_probe, ns8250_bus_probe),
374 KOBJMETHOD(uart_receive, ns8250_bus_receive),
375 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
376 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
380 struct uart_class uart_ns8250_class = {
383 sizeof(struct ns8250_softc),
384 .uc_ops = &uart_ns8250_ops,
386 .uc_rclk = DEFAULT_RCLK
389 #define SIGCHG(c, i, s, d) \
391 i |= (i & s) ? s : s | d; \
393 i = (i & s) ? (i & ~s) | d : i; \
397 ns8250_bus_attach(struct uart_softc *sc)
399 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
400 struct uart_bas *bas;
405 ns8250->mcr = uart_getreg(bas, REG_MCR);
406 ns8250->fcr = FCR_ENABLE;
407 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
409 if (UART_FLAGS_FCR_RX_LOW(ivar))
410 ns8250->fcr |= FCR_RX_LOW;
411 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
412 ns8250->fcr |= FCR_RX_MEDL;
413 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
414 ns8250->fcr |= FCR_RX_HIGH;
416 ns8250->fcr |= FCR_RX_MEDH;
418 ns8250->fcr |= FCR_RX_MEDH;
422 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
424 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
426 /* Get IER RX interrupt bits */
427 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
428 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
430 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
432 uart_setreg(bas, REG_FCR, ns8250->fcr);
434 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
436 if (ns8250->mcr & MCR_DTR)
437 sc->sc_hwsig |= SER_DTR;
438 if (ns8250->mcr & MCR_RTS)
439 sc->sc_hwsig |= SER_RTS;
440 ns8250_bus_getsig(sc);
443 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
444 ns8250->ier |= ns8250->ier_rxbits;
445 uart_setreg(bas, REG_IER, ns8250->ier);
452 ns8250_bus_detach(struct uart_softc *sc)
454 struct ns8250_softc *ns8250;
455 struct uart_bas *bas;
458 ns8250 = (struct ns8250_softc *)sc;
460 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
461 uart_setreg(bas, REG_IER, ier);
468 ns8250_bus_flush(struct uart_softc *sc, int what)
470 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
471 struct uart_bas *bas;
475 uart_lock(sc->sc_hwmtx);
476 if (sc->sc_rxfifosz > 1) {
477 ns8250_flush(bas, what);
478 uart_setreg(bas, REG_FCR, ns8250->fcr);
482 error = ns8250_drain(bas, what);
483 uart_unlock(sc->sc_hwmtx);
488 ns8250_bus_getsig(struct uart_softc *sc)
490 uint32_t new, old, sig;
496 uart_lock(sc->sc_hwmtx);
497 msr = uart_getreg(&sc->sc_bas, REG_MSR);
498 uart_unlock(sc->sc_hwmtx);
499 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
500 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
501 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
502 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
503 new = sig & ~SER_MASK_DELTA;
504 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
509 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
511 struct uart_bas *bas;
512 int baudrate, divisor, error;
517 uart_lock(sc->sc_hwmtx);
519 case UART_IOCTL_BREAK:
520 lcr = uart_getreg(bas, REG_LCR);
525 uart_setreg(bas, REG_LCR, lcr);
528 case UART_IOCTL_IFLOW:
529 lcr = uart_getreg(bas, REG_LCR);
531 uart_setreg(bas, REG_LCR, 0xbf);
533 efr = uart_getreg(bas, REG_EFR);
538 uart_setreg(bas, REG_EFR, efr);
540 uart_setreg(bas, REG_LCR, lcr);
543 case UART_IOCTL_OFLOW:
544 lcr = uart_getreg(bas, REG_LCR);
546 uart_setreg(bas, REG_LCR, 0xbf);
548 efr = uart_getreg(bas, REG_EFR);
553 uart_setreg(bas, REG_EFR, efr);
555 uart_setreg(bas, REG_LCR, lcr);
558 case UART_IOCTL_BAUD:
559 lcr = uart_getreg(bas, REG_LCR);
560 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
562 divisor = uart_getreg(bas, REG_DLL) |
563 (uart_getreg(bas, REG_DLH) << 8);
565 uart_setreg(bas, REG_LCR, lcr);
567 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
569 *(int*)data = baudrate;
577 uart_unlock(sc->sc_hwmtx);
582 ns8250_bus_ipend(struct uart_softc *sc)
584 struct uart_bas *bas;
589 uart_lock(sc->sc_hwmtx);
590 iir = uart_getreg(bas, REG_IIR);
591 if (iir & IIR_NOPEND) {
592 uart_unlock(sc->sc_hwmtx);
596 if (iir & IIR_RXRDY) {
597 lsr = uart_getreg(bas, REG_LSR);
599 ipend |= SER_INT_OVERRUN;
601 ipend |= SER_INT_BREAK;
603 ipend |= SER_INT_RXREADY;
606 ipend |= SER_INT_TXIDLE;
608 ipend |= SER_INT_SIGCHG;
612 uart_unlock(sc->sc_hwmtx);
617 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
618 int stopbits, int parity)
620 struct uart_bas *bas;
624 uart_lock(sc->sc_hwmtx);
625 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
626 uart_unlock(sc->sc_hwmtx);
631 ns8250_bus_probe(struct uart_softc *sc)
633 struct ns8250_softc *ns8250;
634 struct uart_bas *bas;
635 int count, delay, error, limit;
636 uint8_t lsr, mcr, ier;
638 ns8250 = (struct ns8250_softc *)sc;
641 error = ns8250_probe(bas);
646 if (sc->sc_sysdev == NULL) {
647 /* By using ns8250_init() we also set DTR and RTS. */
648 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
650 mcr |= MCR_DTR | MCR_RTS;
652 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
657 * Set loopback mode. This avoids having garbage on the wire and
658 * also allows us send and receive data. We set DTR and RTS to
659 * avoid the possibility that automatic flow-control prevents
660 * any data from being sent.
662 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
666 * Enable FIFOs. And check that the UART has them. If not, we're
667 * done. Since this is the first time we enable the FIFOs, we reset
670 uart_setreg(bas, REG_FCR, FCR_ENABLE);
672 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
674 * NS16450 or INS8250. We don't bother to differentiate
675 * between them. They're too old to be interesting.
677 uart_setreg(bas, REG_MCR, mcr);
679 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
680 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
684 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
688 delay = ns8250_delay(bas);
690 /* We have FIFOs. Drain the transmitter and receiver. */
691 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
693 uart_setreg(bas, REG_MCR, mcr);
694 uart_setreg(bas, REG_FCR, 0);
700 * We should have a sufficiently clean "pipe" to determine the
701 * size of the FIFOs. We send as much characters as is reasonable
702 * and wait for the overflow bit in the LSR register to be
703 * asserted, counting the characters as we send them. Based on
704 * that count we know the FIFO size.
707 uart_setreg(bas, REG_DATA, 0);
714 * LSR bits are cleared upon read, so we must accumulate
715 * them to be able to test LSR_OE below.
717 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
721 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
722 uart_setreg(bas, REG_IER, ier);
723 uart_setreg(bas, REG_MCR, mcr);
724 uart_setreg(bas, REG_FCR, 0);
729 } while ((lsr & LSR_OE) == 0 && count < 130);
732 uart_setreg(bas, REG_MCR, mcr);
735 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
738 if (count >= 14 && count <= 16) {
739 sc->sc_rxfifosz = 16;
740 device_set_desc(sc->sc_dev, "16550 or compatible");
741 } else if (count >= 28 && count <= 32) {
742 sc->sc_rxfifosz = 32;
743 device_set_desc(sc->sc_dev, "16650 or compatible");
744 } else if (count >= 56 && count <= 64) {
745 sc->sc_rxfifosz = 64;
746 device_set_desc(sc->sc_dev, "16750 or compatible");
747 } else if (count >= 112 && count <= 128) {
748 sc->sc_rxfifosz = 128;
749 device_set_desc(sc->sc_dev, "16950 or compatible");
751 sc->sc_rxfifosz = 16;
752 device_set_desc(sc->sc_dev,
753 "Non-standard ns8250 class UART with FIFOs");
757 * Force the Tx FIFO size to 16 bytes for now. We don't program the
758 * Tx trigger. Also, we assume that all data has been sent when the
761 sc->sc_txfifosz = 16;
765 * XXX there are some issues related to hardware flow control and
766 * it's likely that uart(4) is the cause. This basicly needs more
767 * investigation, but we avoid using for hardware flow control
770 /* 16650s or higher have automatic flow control. */
771 if (sc->sc_rxfifosz > 16) {
781 ns8250_bus_receive(struct uart_softc *sc)
783 struct uart_bas *bas;
788 uart_lock(sc->sc_hwmtx);
789 lsr = uart_getreg(bas, REG_LSR);
790 while (lsr & LSR_RXRDY) {
791 if (uart_rx_full(sc)) {
792 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
795 xc = uart_getreg(bas, REG_DATA);
797 xc |= UART_STAT_FRAMERR;
799 xc |= UART_STAT_PARERR;
801 lsr = uart_getreg(bas, REG_LSR);
803 /* Discard everything left in the Rx FIFO. */
804 while (lsr & LSR_RXRDY) {
805 (void)uart_getreg(bas, REG_DATA);
807 lsr = uart_getreg(bas, REG_LSR);
809 uart_unlock(sc->sc_hwmtx);
814 ns8250_bus_setsig(struct uart_softc *sc, int sig)
816 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
817 struct uart_bas *bas;
824 if (sig & SER_DDTR) {
825 SIGCHG(sig & SER_DTR, new, SER_DTR,
828 if (sig & SER_DRTS) {
829 SIGCHG(sig & SER_RTS, new, SER_RTS,
832 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
833 uart_lock(sc->sc_hwmtx);
834 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
836 ns8250->mcr |= MCR_DTR;
838 ns8250->mcr |= MCR_RTS;
839 uart_setreg(bas, REG_MCR, ns8250->mcr);
841 uart_unlock(sc->sc_hwmtx);
846 ns8250_bus_transmit(struct uart_softc *sc)
848 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
849 struct uart_bas *bas;
853 uart_lock(sc->sc_hwmtx);
854 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
856 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
858 for (i = 0; i < sc->sc_txdatasz; i++) {
859 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
863 uart_unlock(sc->sc_hwmtx);