2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
49 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52 #include <dev/uart/uart_dev_ns8250.h>
53 #include <dev/uart/uart_ppstypes.h>
55 #include <dev/ic/ns16550.h>
59 #define DEFAULT_RCLK 1843200
61 static int broken_txfifo = 0;
62 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
63 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
64 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
67 * Clear pending interrupts. THRE is cleared by reading IIR. Data
68 * that may have been received gets lost here.
71 ns8250_clrint(struct uart_bas *bas)
75 iir = uart_getreg(bas, REG_IIR);
76 while ((iir & IIR_NOPEND) == 0) {
79 lsr = uart_getreg(bas, REG_LSR);
80 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
81 (void)uart_getreg(bas, REG_DATA);
82 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
83 (void)uart_getreg(bas, REG_DATA);
84 else if (iir == IIR_MLSC)
85 (void)uart_getreg(bas, REG_MSR);
87 iir = uart_getreg(bas, REG_IIR);
92 ns8250_delay(struct uart_bas *bas)
97 lcr = uart_getreg(bas, REG_LCR);
98 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
100 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
102 uart_setreg(bas, REG_LCR, lcr);
105 /* 1/10th the time to transmit 1 character (estimate). */
107 return (16000000 * divisor / bas->rclk);
108 return (16000 * divisor / (bas->rclk / 1000));
112 ns8250_divisor(int rclk, int baudrate)
114 int actual_baud, divisor;
120 divisor = (rclk / (baudrate << 3) + 1) >> 1;
121 if (divisor == 0 || divisor >= 65536)
123 actual_baud = rclk / (divisor << 4);
125 /* 10 times error in percent: */
126 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
128 /* 3.0% maximum error tolerance: */
129 if (error < -30 || error > 30)
136 ns8250_drain(struct uart_bas *bas, int what)
140 delay = ns8250_delay(bas);
142 if (what & UART_DRAIN_TRANSMITTER) {
144 * Pick an arbitrary high limit to avoid getting stuck in
145 * an infinite loop when the hardware is broken. Make the
146 * limit high enough to handle large FIFOs.
149 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
152 /* printf("ns8250: transmitter appears stuck... "); */
157 if (what & UART_DRAIN_RECEIVER) {
159 * Pick an arbitrary high limit to avoid getting stuck in
160 * an infinite loop when the hardware is broken. Make the
161 * limit high enough to handle large FIFOs and integrated
162 * UARTs. The HP rx2600 for example has 3 UARTs on the
163 * management board that tend to get a lot of data send
164 * to it when the UART is first activated.
167 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
168 (void)uart_getreg(bas, REG_DATA);
173 /* printf("ns8250: receiver appears broken... "); */
182 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
183 * drained. WARNING: this function clobbers the FIFO setting!
186 ns8250_flush(struct uart_bas *bas, int what)
194 if (what & UART_FLUSH_TRANSMITTER)
196 if (what & UART_FLUSH_RECEIVER)
198 uart_setreg(bas, REG_FCR, fcr);
203 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
212 else if (databits == 7)
214 else if (databits == 6)
224 divisor = ns8250_divisor(bas->rclk, baudrate);
227 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
229 uart_setreg(bas, REG_DLL, divisor & 0xff);
230 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
234 /* Set LCR and clear DLAB. */
235 uart_setreg(bas, REG_LCR, lcr);
241 * Low-level UART interface.
243 static int ns8250_probe(struct uart_bas *bas);
244 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
245 static void ns8250_term(struct uart_bas *bas);
246 static void ns8250_putc(struct uart_bas *bas, int);
247 static int ns8250_rxready(struct uart_bas *bas);
248 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
250 struct uart_ops uart_ns8250_ops = {
251 .probe = ns8250_probe,
255 .rxready = ns8250_rxready,
260 ns8250_probe(struct uart_bas *bas)
265 uart_setreg(bas, REG_FCR, FCR_UART_ON);
268 /* Check known 0 bits that don't depend on DLAB. */
269 val = uart_getreg(bas, REG_IIR);
273 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
274 * chip, but otherwise doesn't seem to have a function. In
275 * other words, uart(4) works regardless. Ignore that bit so
276 * the probe succeeds.
278 val = uart_getreg(bas, REG_MCR);
286 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
292 bas->rclk = DEFAULT_RCLK;
293 ns8250_param(bas, baudrate, databits, stopbits, parity);
295 /* Disable all interrupt sources. */
297 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
298 * UARTs split the receive time-out interrupt bit out separately as
299 * 0x10. This gets handled by ier_mask and ier_rxbits below.
301 ier = uart_getreg(bas, REG_IER) & 0xe0;
302 uart_setreg(bas, REG_IER, ier);
305 /* Disable the FIFO (if present). */
310 uart_setreg(bas, REG_FCR, val);
314 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
321 ns8250_term(struct uart_bas *bas)
324 /* Clear RTS & DTR. */
325 uart_setreg(bas, REG_MCR, MCR_IE);
330 ns8250_putc(struct uart_bas *bas, int c)
335 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
337 uart_setreg(bas, REG_DATA, c);
342 ns8250_rxready(struct uart_bas *bas)
345 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
349 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
355 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
361 c = uart_getreg(bas, REG_DATA);
368 static kobj_method_t ns8250_methods[] = {
369 KOBJMETHOD(uart_attach, ns8250_bus_attach),
370 KOBJMETHOD(uart_detach, ns8250_bus_detach),
371 KOBJMETHOD(uart_flush, ns8250_bus_flush),
372 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
373 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
374 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
375 KOBJMETHOD(uart_param, ns8250_bus_param),
376 KOBJMETHOD(uart_probe, ns8250_bus_probe),
377 KOBJMETHOD(uart_receive, ns8250_bus_receive),
378 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
379 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
380 KOBJMETHOD(uart_grab, ns8250_bus_grab),
381 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
385 struct uart_class uart_ns8250_class = {
388 sizeof(struct ns8250_softc),
389 .uc_ops = &uart_ns8250_ops,
391 .uc_rclk = DEFAULT_RCLK
395 static struct ofw_compat_data compat_data[] = {
396 {"ns16550", (uintptr_t)&uart_ns8250_class},
397 {NULL, (uintptr_t)NULL},
399 UART_FDT_CLASS_AND_DEVICE(compat_data);
402 /* Use token-pasting to form SER_ and MSR_ named constants. */
403 #define SER(sig) SER_##sig
404 #define SERD(sig) SER_D##sig
405 #define MSR(sig) MSR_##sig
406 #define MSRD(sig) MSR_D##sig
409 * Detect signal changes using software delta detection. The previous state of
410 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
411 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
412 * new state of both the signal and the delta bits.
414 #define SIGCHGSW(var, msr, sig) \
415 if ((msr) & MSR(sig)) { \
416 if ((var & SER(sig)) == 0) \
417 var |= SERD(sig) | SER(sig); \
419 if ((var & SER(sig)) != 0) \
420 var = SERD(sig) | (var & ~SER(sig)); \
424 * Detect signal changes using the hardware msr delta bits. This is currently
425 * used only when PPS timing information is being captured using the "narrow
426 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
427 * by time the interrupt handler is invoked. The hardware will latch the fact
428 * that it changed in the delta bits.
430 #define SIGCHGHW(var, msr, sig) \
431 if ((msr) & MSRD(sig)) { \
432 if (((msr) & MSR(sig)) != 0) \
433 var |= SERD(sig) | SER(sig); \
435 var = SERD(sig) | (var & ~SER(sig)); \
439 ns8250_bus_attach(struct uart_softc *sc)
441 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
442 struct uart_bas *bas;
449 ns8250->busy_detect = 0;
453 * Check whether uart requires to read USR reg when IIR_BUSY and
456 node = ofw_bus_get_node(sc->sc_dev);
457 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
458 ns8250->busy_detect = 1;
459 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
465 ns8250->mcr = uart_getreg(bas, REG_MCR);
466 ns8250->fcr = FCR_ENABLE;
468 ns8250->fcr |= FCR_UART_ON;
470 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
472 if (UART_FLAGS_FCR_RX_LOW(ivar))
473 ns8250->fcr |= FCR_RX_LOW;
474 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
475 ns8250->fcr |= FCR_RX_MEDL;
476 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
477 ns8250->fcr |= FCR_RX_HIGH;
479 ns8250->fcr |= FCR_RX_MEDH;
481 ns8250->fcr |= FCR_RX_MEDH;
485 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
487 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
489 /* Get IER RX interrupt bits */
490 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
491 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
493 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
495 uart_setreg(bas, REG_FCR, ns8250->fcr);
497 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
499 if (ns8250->mcr & MCR_DTR)
500 sc->sc_hwsig |= SER_DTR;
501 if (ns8250->mcr & MCR_RTS)
502 sc->sc_hwsig |= SER_RTS;
503 ns8250_bus_getsig(sc);
506 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
507 ns8250->ier |= ns8250->ier_rxbits;
508 uart_setreg(bas, REG_IER, ns8250->ier);
512 * Timing of the H/W access was changed with r253161 of uart_core.c
513 * It has been observed that an ITE IT8513E would signal a break
514 * condition with pretty much every character it received, unless
515 * it had enough time to settle between ns8250_bus_attach() and
516 * ns8250_bus_ipend() -- which it accidentally had before r253161.
517 * It's not understood why the UART chip behaves this way and it
518 * could very well be that the DELAY make the H/W work in the same
519 * accidental manner as before. More analysis is warranted, but
520 * at least now we fixed a known regression.
527 ns8250_bus_detach(struct uart_softc *sc)
529 struct ns8250_softc *ns8250;
530 struct uart_bas *bas;
533 ns8250 = (struct ns8250_softc *)sc;
535 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
536 uart_setreg(bas, REG_IER, ier);
543 ns8250_bus_flush(struct uart_softc *sc, int what)
545 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
546 struct uart_bas *bas;
550 uart_lock(sc->sc_hwmtx);
551 if (sc->sc_rxfifosz > 1) {
552 ns8250_flush(bas, what);
553 uart_setreg(bas, REG_FCR, ns8250->fcr);
557 error = ns8250_drain(bas, what);
558 uart_unlock(sc->sc_hwmtx);
563 ns8250_bus_getsig(struct uart_softc *sc)
569 * The delta bits are reputed to be broken on some hardware, so use
570 * software delta detection by default. Use the hardware delta bits
571 * when capturing PPS pulses which are too narrow for software detection
572 * to see the edges. Hardware delta for RI doesn't work like the
573 * others, so always use software for it. Other threads may be changing
574 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
575 * update without other changes happening. Note that the SIGCHGxx()
576 * macros carefully preserve the delta bits when we have to loop several
577 * times and a signal transitions between iterations.
582 uart_lock(sc->sc_hwmtx);
583 msr = uart_getreg(&sc->sc_bas, REG_MSR);
584 uart_unlock(sc->sc_hwmtx);
585 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
586 SIGCHGHW(sig, msr, DSR);
587 SIGCHGHW(sig, msr, CTS);
588 SIGCHGHW(sig, msr, DCD);
590 SIGCHGSW(sig, msr, DSR);
591 SIGCHGSW(sig, msr, CTS);
592 SIGCHGSW(sig, msr, DCD);
594 SIGCHGSW(sig, msr, RI);
595 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
600 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
602 struct uart_bas *bas;
603 int baudrate, divisor, error;
608 uart_lock(sc->sc_hwmtx);
610 case UART_IOCTL_BREAK:
611 lcr = uart_getreg(bas, REG_LCR);
616 uart_setreg(bas, REG_LCR, lcr);
619 case UART_IOCTL_IFLOW:
620 lcr = uart_getreg(bas, REG_LCR);
622 uart_setreg(bas, REG_LCR, 0xbf);
624 efr = uart_getreg(bas, REG_EFR);
629 uart_setreg(bas, REG_EFR, efr);
631 uart_setreg(bas, REG_LCR, lcr);
634 case UART_IOCTL_OFLOW:
635 lcr = uart_getreg(bas, REG_LCR);
637 uart_setreg(bas, REG_LCR, 0xbf);
639 efr = uart_getreg(bas, REG_EFR);
644 uart_setreg(bas, REG_EFR, efr);
646 uart_setreg(bas, REG_LCR, lcr);
649 case UART_IOCTL_BAUD:
650 lcr = uart_getreg(bas, REG_LCR);
651 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
653 divisor = uart_getreg(bas, REG_DLL) |
654 (uart_getreg(bas, REG_DLH) << 8);
656 uart_setreg(bas, REG_LCR, lcr);
658 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
660 *(int*)data = baudrate;
668 uart_unlock(sc->sc_hwmtx);
673 ns8250_bus_ipend(struct uart_softc *sc)
675 struct uart_bas *bas;
676 struct ns8250_softc *ns8250;
680 ns8250 = (struct ns8250_softc *)sc;
682 uart_lock(sc->sc_hwmtx);
683 iir = uart_getreg(bas, REG_IIR);
685 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
686 (void)uart_getreg(bas, DW_REG_USR);
687 uart_unlock(sc->sc_hwmtx);
690 if (iir & IIR_NOPEND) {
691 uart_unlock(sc->sc_hwmtx);
695 if (iir & IIR_RXRDY) {
696 lsr = uart_getreg(bas, REG_LSR);
698 ipend |= SER_INT_OVERRUN;
700 ipend |= SER_INT_BREAK;
702 ipend |= SER_INT_RXREADY;
704 if (iir & IIR_TXRDY) {
705 ipend |= SER_INT_TXIDLE;
706 uart_setreg(bas, REG_IER, ns8250->ier);
708 ipend |= SER_INT_SIGCHG;
712 uart_unlock(sc->sc_hwmtx);
717 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
718 int stopbits, int parity)
720 struct ns8250_softc *ns8250;
721 struct uart_bas *bas;
724 ns8250 = (struct ns8250_softc*)sc;
726 uart_lock(sc->sc_hwmtx);
728 * When using DW UART with BUSY detection it is necessary to wait
729 * until all serial transfers are finished before manipulating the
730 * line control. LCR will not be affected when UART is busy.
732 if (ns8250->busy_detect != 0) {
734 * Pick an arbitrary high limit to avoid getting stuck in
735 * an infinite loop in case when the hardware is broken.
738 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
743 /* UART appears to be stuck */
744 uart_unlock(sc->sc_hwmtx);
749 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
750 uart_unlock(sc->sc_hwmtx);
755 ns8250_bus_probe(struct uart_softc *sc)
757 struct ns8250_softc *ns8250;
758 struct uart_bas *bas;
759 int count, delay, error, limit;
760 uint8_t lsr, mcr, ier;
763 ns8250 = (struct ns8250_softc *)sc;
766 error = ns8250_probe(bas);
771 if (sc->sc_sysdev == NULL) {
772 /* By using ns8250_init() we also set DTR and RTS. */
773 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
775 mcr |= MCR_DTR | MCR_RTS;
777 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
782 * Set loopback mode. This avoids having garbage on the wire and
783 * also allows us send and receive data. We set DTR and RTS to
784 * avoid the possibility that automatic flow-control prevents
785 * any data from being sent.
787 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
791 * Enable FIFOs. And check that the UART has them. If not, we're
792 * done. Since this is the first time we enable the FIFOs, we reset
799 uart_setreg(bas, REG_FCR, val);
801 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
803 * NS16450 or INS8250. We don't bother to differentiate
804 * between them. They're too old to be interesting.
806 uart_setreg(bas, REG_MCR, mcr);
808 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
809 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
813 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
817 uart_setreg(bas, REG_FCR, val);
821 delay = ns8250_delay(bas);
823 /* We have FIFOs. Drain the transmitter and receiver. */
824 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
826 uart_setreg(bas, REG_MCR, mcr);
831 uart_setreg(bas, REG_FCR, val);
837 * We should have a sufficiently clean "pipe" to determine the
838 * size of the FIFOs. We send as much characters as is reasonable
839 * and wait for the overflow bit in the LSR register to be
840 * asserted, counting the characters as we send them. Based on
841 * that count we know the FIFO size.
844 uart_setreg(bas, REG_DATA, 0);
851 * LSR bits are cleared upon read, so we must accumulate
852 * them to be able to test LSR_OE below.
854 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
858 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
859 uart_setreg(bas, REG_IER, ier);
860 uart_setreg(bas, REG_MCR, mcr);
865 uart_setreg(bas, REG_FCR, val);
870 } while ((lsr & LSR_OE) == 0 && count < 130);
873 uart_setreg(bas, REG_MCR, mcr);
876 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
879 if (count >= 14 && count <= 16) {
880 sc->sc_rxfifosz = 16;
881 device_set_desc(sc->sc_dev, "16550 or compatible");
882 } else if (count >= 28 && count <= 32) {
883 sc->sc_rxfifosz = 32;
884 device_set_desc(sc->sc_dev, "16650 or compatible");
885 } else if (count >= 56 && count <= 64) {
886 sc->sc_rxfifosz = 64;
887 device_set_desc(sc->sc_dev, "16750 or compatible");
888 } else if (count >= 112 && count <= 128) {
889 sc->sc_rxfifosz = 128;
890 device_set_desc(sc->sc_dev, "16950 or compatible");
892 sc->sc_rxfifosz = 16;
893 device_set_desc(sc->sc_dev,
894 "Non-standard ns8250 class UART with FIFOs");
898 * Force the Tx FIFO size to 16 bytes for now. We don't program the
899 * Tx trigger. Also, we assume that all data has been sent when the
902 sc->sc_txfifosz = 16;
906 * XXX there are some issues related to hardware flow control and
907 * it's likely that uart(4) is the cause. This basicly needs more
908 * investigation, but we avoid using for hardware flow control
911 /* 16650s or higher have automatic flow control. */
912 if (sc->sc_rxfifosz > 16) {
922 ns8250_bus_receive(struct uart_softc *sc)
924 struct uart_bas *bas;
929 uart_lock(sc->sc_hwmtx);
930 lsr = uart_getreg(bas, REG_LSR);
931 while (lsr & LSR_RXRDY) {
932 if (uart_rx_full(sc)) {
933 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
936 xc = uart_getreg(bas, REG_DATA);
938 xc |= UART_STAT_FRAMERR;
940 xc |= UART_STAT_PARERR;
942 lsr = uart_getreg(bas, REG_LSR);
944 /* Discard everything left in the Rx FIFO. */
945 while (lsr & LSR_RXRDY) {
946 (void)uart_getreg(bas, REG_DATA);
948 lsr = uart_getreg(bas, REG_LSR);
950 uart_unlock(sc->sc_hwmtx);
955 ns8250_bus_setsig(struct uart_softc *sc, int sig)
957 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
958 struct uart_bas *bas;
965 if (sig & SER_DDTR) {
966 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
968 if (sig & SER_DRTS) {
969 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
971 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
972 uart_lock(sc->sc_hwmtx);
973 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
975 ns8250->mcr |= MCR_DTR;
977 ns8250->mcr |= MCR_RTS;
978 uart_setreg(bas, REG_MCR, ns8250->mcr);
980 uart_unlock(sc->sc_hwmtx);
985 ns8250_bus_transmit(struct uart_softc *sc)
987 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
988 struct uart_bas *bas;
992 uart_lock(sc->sc_hwmtx);
993 if (sc->sc_txdatasz > 1) {
994 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
995 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
997 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1000 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
1002 for (i = 0; i < sc->sc_txdatasz; i++) {
1003 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1007 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1010 uart_unlock(sc->sc_hwmtx);
1012 uart_sched_softih(sc, SER_INT_TXIDLE);
1017 ns8250_bus_grab(struct uart_softc *sc)
1019 struct uart_bas *bas = &sc->sc_bas;
1022 * turn off all interrupts to enter polling mode. Leave the
1023 * saved mask alone. We'll restore whatever it was in ungrab.
1024 * All pending interupt signals are reset when IER is set to 0.
1026 uart_lock(sc->sc_hwmtx);
1027 uart_setreg(bas, REG_IER, 0);
1029 uart_unlock(sc->sc_hwmtx);
1033 ns8250_bus_ungrab(struct uart_softc *sc)
1035 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1036 struct uart_bas *bas = &sc->sc_bas;
1039 * Restore previous interrupt mask
1041 uart_lock(sc->sc_hwmtx);
1042 uart_setreg(bas, REG_IER, ns8250->ier);
1044 uart_unlock(sc->sc_hwmtx);