2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/sysctl.h>
36 #include <machine/bus.h>
38 #include <dev/uart/uart.h>
39 #include <dev/uart/uart_cpu.h>
40 #include <dev/uart/uart_bus.h>
42 #include <dev/ic/ns16550.h>
46 #define DEFAULT_RCLK 1843200
49 * Clear pending interrupts. THRE is cleared by reading IIR. Data
50 * that may have been received gets lost here.
53 ns8250_clrint(struct uart_bas *bas)
57 iir = uart_getreg(bas, REG_IIR);
58 while ((iir & IIR_NOPEND) == 0) {
61 lsr = uart_getreg(bas, REG_LSR);
62 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
63 (void)uart_getreg(bas, REG_DATA);
64 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
65 (void)uart_getreg(bas, REG_DATA);
66 else if (iir == IIR_MLSC)
67 (void)uart_getreg(bas, REG_MSR);
69 iir = uart_getreg(bas, REG_IIR);
74 ns8250_delay(struct uart_bas *bas)
79 lcr = uart_getreg(bas, REG_LCR);
80 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
82 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
84 uart_setreg(bas, REG_LCR, lcr);
87 /* 1/10th the time to transmit 1 character (estimate). */
89 return (16000000 * divisor / bas->rclk);
90 return (16000 * divisor / (bas->rclk / 1000));
94 ns8250_divisor(int rclk, int baudrate)
96 int actual_baud, divisor;
102 divisor = (rclk / (baudrate << 3) + 1) >> 1;
103 if (divisor == 0 || divisor >= 65536)
105 actual_baud = rclk / (divisor << 4);
107 /* 10 times error in percent: */
108 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
110 /* 3.0% maximum error tolerance: */
111 if (error < -30 || error > 30)
118 ns8250_drain(struct uart_bas *bas, int what)
122 delay = ns8250_delay(bas);
124 if (what & UART_DRAIN_TRANSMITTER) {
126 * Pick an arbitrary high limit to avoid getting stuck in
127 * an infinite loop when the hardware is broken. Make the
128 * limit high enough to handle large FIFOs.
131 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
134 /* printf("ns8250: transmitter appears stuck... "); */
139 if (what & UART_DRAIN_RECEIVER) {
141 * Pick an arbitrary high limit to avoid getting stuck in
142 * an infinite loop when the hardware is broken. Make the
143 * limit high enough to handle large FIFOs and integrated
144 * UARTs. The HP rx2600 for example has 3 UARTs on the
145 * management board that tend to get a lot of data send
146 * to it when the UART is first activated.
149 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
150 (void)uart_getreg(bas, REG_DATA);
155 /* printf("ns8250: receiver appears broken... "); */
164 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
165 * drained. WARNING: this function clobbers the FIFO setting!
168 ns8250_flush(struct uart_bas *bas, int what)
173 if (what & UART_FLUSH_TRANSMITTER)
175 if (what & UART_FLUSH_RECEIVER)
177 uart_setreg(bas, REG_FCR, fcr);
182 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
191 else if (databits == 7)
193 else if (databits == 6)
203 divisor = ns8250_divisor(bas->rclk, baudrate);
206 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
208 uart_setreg(bas, REG_DLL, divisor & 0xff);
209 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
213 /* Set LCR and clear DLAB. */
214 uart_setreg(bas, REG_LCR, lcr);
220 * Low-level UART interface.
222 static int ns8250_probe(struct uart_bas *bas);
223 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
224 static void ns8250_term(struct uart_bas *bas);
225 static void ns8250_putc(struct uart_bas *bas, int);
226 static int ns8250_rxready(struct uart_bas *bas);
227 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
229 static struct uart_ops uart_ns8250_ops = {
230 .probe = ns8250_probe,
234 .rxready = ns8250_rxready,
239 ns8250_probe(struct uart_bas *bas)
243 /* Check known 0 bits that don't depend on DLAB. */
244 val = uart_getreg(bas, REG_IIR);
248 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
249 * chip, but otherwise doesn't seem to have a function. In
250 * other words, uart(4) works regardless. Ignore that bit so
251 * the probe succeeds.
253 val = uart_getreg(bas, REG_MCR);
261 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
267 bas->rclk = DEFAULT_RCLK;
268 ns8250_param(bas, baudrate, databits, stopbits, parity);
270 /* Disable all interrupt sources. */
272 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
273 * UARTs split the receive time-out interrupt bit out separately as
274 * 0x10. This gets handled by ier_mask and ier_rxbits below.
276 ier = uart_getreg(bas, REG_IER) & 0xe0;
277 uart_setreg(bas, REG_IER, ier);
280 /* Disable the FIFO (if present). */
281 uart_setreg(bas, REG_FCR, 0);
285 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
292 ns8250_term(struct uart_bas *bas)
295 /* Clear RTS & DTR. */
296 uart_setreg(bas, REG_MCR, MCR_IE);
301 ns8250_putc(struct uart_bas *bas, int c)
306 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
308 uart_setreg(bas, REG_DATA, c);
311 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
316 ns8250_rxready(struct uart_bas *bas)
319 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
323 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
329 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
335 c = uart_getreg(bas, REG_DATA);
343 * High-level UART interface.
345 struct ns8250_softc {
346 struct uart_softc base;
355 static int ns8250_bus_attach(struct uart_softc *);
356 static int ns8250_bus_detach(struct uart_softc *);
357 static int ns8250_bus_flush(struct uart_softc *, int);
358 static int ns8250_bus_getsig(struct uart_softc *);
359 static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t);
360 static int ns8250_bus_ipend(struct uart_softc *);
361 static int ns8250_bus_param(struct uart_softc *, int, int, int, int);
362 static int ns8250_bus_probe(struct uart_softc *);
363 static int ns8250_bus_receive(struct uart_softc *);
364 static int ns8250_bus_setsig(struct uart_softc *, int);
365 static int ns8250_bus_transmit(struct uart_softc *);
367 static kobj_method_t ns8250_methods[] = {
368 KOBJMETHOD(uart_attach, ns8250_bus_attach),
369 KOBJMETHOD(uart_detach, ns8250_bus_detach),
370 KOBJMETHOD(uart_flush, ns8250_bus_flush),
371 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
372 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
373 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
374 KOBJMETHOD(uart_param, ns8250_bus_param),
375 KOBJMETHOD(uart_probe, ns8250_bus_probe),
376 KOBJMETHOD(uart_receive, ns8250_bus_receive),
377 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
378 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
382 struct uart_class uart_ns8250_class = {
385 sizeof(struct ns8250_softc),
386 .uc_ops = &uart_ns8250_ops,
388 .uc_rclk = DEFAULT_RCLK
391 #define SIGCHG(c, i, s, d) \
393 i |= (i & s) ? s : s | d; \
395 i = (i & s) ? (i & ~s) | d : i; \
399 ns8250_bus_attach(struct uart_softc *sc)
401 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
402 struct uart_bas *bas;
407 ns8250->mcr = uart_getreg(bas, REG_MCR);
408 ns8250->fcr = FCR_ENABLE;
409 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
411 if (UART_FLAGS_FCR_RX_LOW(ivar))
412 ns8250->fcr |= FCR_RX_LOW;
413 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
414 ns8250->fcr |= FCR_RX_MEDL;
415 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
416 ns8250->fcr |= FCR_RX_HIGH;
418 ns8250->fcr |= FCR_RX_MEDH;
420 ns8250->fcr |= FCR_RX_MEDH;
424 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
426 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
428 /* Get IER RX interrupt bits */
429 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
430 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
432 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
434 uart_setreg(bas, REG_FCR, ns8250->fcr);
436 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
438 if (ns8250->mcr & MCR_DTR)
439 sc->sc_hwsig |= SER_DTR;
440 if (ns8250->mcr & MCR_RTS)
441 sc->sc_hwsig |= SER_RTS;
442 ns8250_bus_getsig(sc);
445 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
446 ns8250->ier |= ns8250->ier_rxbits;
447 uart_setreg(bas, REG_IER, ns8250->ier);
454 ns8250_bus_detach(struct uart_softc *sc)
456 struct ns8250_softc *ns8250;
457 struct uart_bas *bas;
460 ns8250 = (struct ns8250_softc *)sc;
462 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
463 uart_setreg(bas, REG_IER, ier);
470 ns8250_bus_flush(struct uart_softc *sc, int what)
472 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
473 struct uart_bas *bas;
477 uart_lock(sc->sc_hwmtx);
478 if (sc->sc_rxfifosz > 1) {
479 ns8250_flush(bas, what);
480 uart_setreg(bas, REG_FCR, ns8250->fcr);
484 error = ns8250_drain(bas, what);
485 uart_unlock(sc->sc_hwmtx);
490 ns8250_bus_getsig(struct uart_softc *sc)
492 uint32_t new, old, sig;
498 uart_lock(sc->sc_hwmtx);
499 msr = uart_getreg(&sc->sc_bas, REG_MSR);
500 uart_unlock(sc->sc_hwmtx);
501 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
502 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
503 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
504 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
505 new = sig & ~SER_MASK_DELTA;
506 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
511 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
513 struct uart_bas *bas;
514 int baudrate, divisor, error;
519 uart_lock(sc->sc_hwmtx);
521 case UART_IOCTL_BREAK:
522 lcr = uart_getreg(bas, REG_LCR);
527 uart_setreg(bas, REG_LCR, lcr);
530 case UART_IOCTL_IFLOW:
531 lcr = uart_getreg(bas, REG_LCR);
533 uart_setreg(bas, REG_LCR, 0xbf);
535 efr = uart_getreg(bas, REG_EFR);
540 uart_setreg(bas, REG_EFR, efr);
542 uart_setreg(bas, REG_LCR, lcr);
545 case UART_IOCTL_OFLOW:
546 lcr = uart_getreg(bas, REG_LCR);
548 uart_setreg(bas, REG_LCR, 0xbf);
550 efr = uart_getreg(bas, REG_EFR);
555 uart_setreg(bas, REG_EFR, efr);
557 uart_setreg(bas, REG_LCR, lcr);
560 case UART_IOCTL_BAUD:
561 lcr = uart_getreg(bas, REG_LCR);
562 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
564 divisor = uart_getreg(bas, REG_DLL) |
565 (uart_getreg(bas, REG_DLH) << 8);
567 uart_setreg(bas, REG_LCR, lcr);
569 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
571 *(int*)data = baudrate;
579 uart_unlock(sc->sc_hwmtx);
584 ns8250_bus_ipend(struct uart_softc *sc)
586 struct uart_bas *bas;
591 uart_lock(sc->sc_hwmtx);
592 iir = uart_getreg(bas, REG_IIR);
593 if (iir & IIR_NOPEND) {
594 uart_unlock(sc->sc_hwmtx);
598 if (iir & IIR_RXRDY) {
599 lsr = uart_getreg(bas, REG_LSR);
601 ipend |= SER_INT_OVERRUN;
603 ipend |= SER_INT_BREAK;
605 ipend |= SER_INT_RXREADY;
608 ipend |= SER_INT_TXIDLE;
610 ipend |= SER_INT_SIGCHG;
614 uart_unlock(sc->sc_hwmtx);
619 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
620 int stopbits, int parity)
622 struct uart_bas *bas;
626 uart_lock(sc->sc_hwmtx);
627 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
628 uart_unlock(sc->sc_hwmtx);
633 ns8250_bus_probe(struct uart_softc *sc)
635 struct ns8250_softc *ns8250;
636 struct uart_bas *bas;
637 int count, delay, error, limit;
638 uint8_t lsr, mcr, ier;
640 ns8250 = (struct ns8250_softc *)sc;
643 error = ns8250_probe(bas);
648 if (sc->sc_sysdev == NULL) {
649 /* By using ns8250_init() we also set DTR and RTS. */
650 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
652 mcr |= MCR_DTR | MCR_RTS;
654 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
659 * Set loopback mode. This avoids having garbage on the wire and
660 * also allows us send and receive data. We set DTR and RTS to
661 * avoid the possibility that automatic flow-control prevents
662 * any data from being sent.
664 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
668 * Enable FIFOs. And check that the UART has them. If not, we're
669 * done. Since this is the first time we enable the FIFOs, we reset
672 uart_setreg(bas, REG_FCR, FCR_ENABLE);
674 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
676 * NS16450 or INS8250. We don't bother to differentiate
677 * between them. They're too old to be interesting.
679 uart_setreg(bas, REG_MCR, mcr);
681 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
682 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
686 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
690 delay = ns8250_delay(bas);
692 /* We have FIFOs. Drain the transmitter and receiver. */
693 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
695 uart_setreg(bas, REG_MCR, mcr);
696 uart_setreg(bas, REG_FCR, 0);
702 * We should have a sufficiently clean "pipe" to determine the
703 * size of the FIFOs. We send as much characters as is reasonable
704 * and wait for the overflow bit in the LSR register to be
705 * asserted, counting the characters as we send them. Based on
706 * that count we know the FIFO size.
709 uart_setreg(bas, REG_DATA, 0);
716 * LSR bits are cleared upon read, so we must accumulate
717 * them to be able to test LSR_OE below.
719 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
723 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
724 uart_setreg(bas, REG_IER, ier);
725 uart_setreg(bas, REG_MCR, mcr);
726 uart_setreg(bas, REG_FCR, 0);
731 } while ((lsr & LSR_OE) == 0 && count < 130);
734 uart_setreg(bas, REG_MCR, mcr);
737 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
740 if (count >= 14 && count <= 16) {
741 sc->sc_rxfifosz = 16;
742 device_set_desc(sc->sc_dev, "16550 or compatible");
743 } else if (count >= 28 && count <= 32) {
744 sc->sc_rxfifosz = 32;
745 device_set_desc(sc->sc_dev, "16650 or compatible");
746 } else if (count >= 56 && count <= 64) {
747 sc->sc_rxfifosz = 64;
748 device_set_desc(sc->sc_dev, "16750 or compatible");
749 } else if (count >= 112 && count <= 128) {
750 sc->sc_rxfifosz = 128;
751 device_set_desc(sc->sc_dev, "16950 or compatible");
753 sc->sc_rxfifosz = 16;
754 device_set_desc(sc->sc_dev,
755 "Non-standard ns8250 class UART with FIFOs");
759 * Force the Tx FIFO size to 16 bytes for now. We don't program the
760 * Tx trigger. Also, we assume that all data has been sent when the
763 sc->sc_txfifosz = 16;
767 * XXX there are some issues related to hardware flow control and
768 * it's likely that uart(4) is the cause. This basicly needs more
769 * investigation, but we avoid using for hardware flow control
772 /* 16650s or higher have automatic flow control. */
773 if (sc->sc_rxfifosz > 16) {
783 ns8250_bus_receive(struct uart_softc *sc)
785 struct uart_bas *bas;
790 uart_lock(sc->sc_hwmtx);
791 lsr = uart_getreg(bas, REG_LSR);
792 while (lsr & LSR_RXRDY) {
793 if (uart_rx_full(sc)) {
794 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
797 xc = uart_getreg(bas, REG_DATA);
799 xc |= UART_STAT_FRAMERR;
801 xc |= UART_STAT_PARERR;
803 lsr = uart_getreg(bas, REG_LSR);
805 /* Discard everything left in the Rx FIFO. */
806 while (lsr & LSR_RXRDY) {
807 (void)uart_getreg(bas, REG_DATA);
809 lsr = uart_getreg(bas, REG_LSR);
811 uart_unlock(sc->sc_hwmtx);
816 ns8250_bus_setsig(struct uart_softc *sc, int sig)
818 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
819 struct uart_bas *bas;
826 if (sig & SER_DDTR) {
827 SIGCHG(sig & SER_DTR, new, SER_DTR,
830 if (sig & SER_DRTS) {
831 SIGCHG(sig & SER_RTS, new, SER_RTS,
834 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
835 uart_lock(sc->sc_hwmtx);
836 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
838 ns8250->mcr |= MCR_DTR;
840 ns8250->mcr |= MCR_RTS;
841 uart_setreg(bas, REG_MCR, ns8250->mcr);
843 uart_unlock(sc->sc_hwmtx);
847 static int broken_txfifo = 0;
848 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
849 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
850 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
853 ns8250_bus_transmit(struct uart_softc *sc)
855 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
856 struct uart_bas *bas;
860 uart_lock(sc->sc_hwmtx);
861 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
863 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
865 for (i = 0; i < sc->sc_txdatasz; i++) {
866 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
870 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
873 uart_unlock(sc->sc_hwmtx);
875 uart_sched_softih(sc, SER_INT_TXIDLE);