2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <dev/ic/z8530.h>
44 #define DEFAULT_RCLK 307200
50 #define UART_PCLK MCB2_PCLK
53 /* Multiplexed I/O. */
55 uart_setmreg(struct uart_bas *bas, int reg, int val)
58 uart_setreg(bas, REG_CTRL, reg);
60 uart_setreg(bas, REG_CTRL, val);
63 static __inline uint8_t
64 uart_getmreg(struct uart_bas *bas, int reg)
67 uart_setreg(bas, REG_CTRL, reg);
69 return (uart_getreg(bas, REG_CTRL));
73 z8530_divisor(int rclk, int baudrate)
75 int act_baud, divisor, error;
80 divisor = (rclk + baudrate) / (baudrate << 1) - 2;
81 if (divisor < 0 || divisor >= 65536)
83 act_baud = rclk / 2 / (divisor + 2);
85 /* 10 times error in percent: */
86 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
88 /* 3.0% maximum error tolerance: */
89 if (error < -30 || error > 30)
96 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
97 int parity, uint8_t *tpcp)
100 uint8_t mpm, rpc, tpc;
104 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS));
109 } else if (databits == 7) {
112 } else if (databits == 6) {
119 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
121 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
122 case UART_PARITY_NONE: break;
123 case UART_PARITY_ODD: mpm |= MPM_PE; break;
124 default: return (EINVAL);
128 divisor = z8530_divisor(bas->rclk, baudrate);
134 uart_setmreg(bas, WR_MCB2, UART_PCLK);
138 uart_setmreg(bas, WR_TCL, divisor & 0xff);
140 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
144 uart_setmreg(bas, WR_RPC, rpc);
146 uart_setmreg(bas, WR_MPM, mpm);
148 uart_setmreg(bas, WR_TPC, tpc);
150 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE);
157 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
163 bas->rclk = DEFAULT_RCLK;
165 /* Assume we don't need to perform a full hardware reset. */
168 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA);
171 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB);
175 /* Set clock sources. */
176 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
177 uart_setmreg(bas, WR_MCB2, UART_PCLK);
179 /* Set data encoding. */
180 uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
183 tpc = TPC_DTR | TPC_RTS;
184 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc);
189 * Low-level UART interface.
191 static int z8530_probe(struct uart_bas *bas);
192 static void z8530_init(struct uart_bas *bas, int, int, int, int);
193 static void z8530_term(struct uart_bas *bas);
194 static void z8530_putc(struct uart_bas *bas, int);
195 static int z8530_rxready(struct uart_bas *bas);
196 static int z8530_getc(struct uart_bas *bas, struct mtx *);
198 static struct uart_ops uart_z8530_ops = {
199 .probe = z8530_probe,
203 .rxready = z8530_rxready,
208 z8530_probe(struct uart_bas *bas)
215 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
219 z8530_setup(bas, baudrate, databits, stopbits, parity);
223 z8530_term(struct uart_bas *bas)
228 z8530_putc(struct uart_bas *bas, int c)
231 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE))
233 uart_setreg(bas, REG_DATA, c);
238 z8530_rxready(struct uart_bas *bas)
241 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0);
245 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx)
251 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) {
257 c = uart_getreg(bas, REG_DATA);
265 * High-level UART interface.
268 struct uart_softc base;
273 static int z8530_bus_attach(struct uart_softc *);
274 static int z8530_bus_detach(struct uart_softc *);
275 static int z8530_bus_flush(struct uart_softc *, int);
276 static int z8530_bus_getsig(struct uart_softc *);
277 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t);
278 static int z8530_bus_ipend(struct uart_softc *);
279 static int z8530_bus_param(struct uart_softc *, int, int, int, int);
280 static int z8530_bus_probe(struct uart_softc *);
281 static int z8530_bus_receive(struct uart_softc *);
282 static int z8530_bus_setsig(struct uart_softc *, int);
283 static int z8530_bus_transmit(struct uart_softc *);
285 static kobj_method_t z8530_methods[] = {
286 KOBJMETHOD(uart_attach, z8530_bus_attach),
287 KOBJMETHOD(uart_detach, z8530_bus_detach),
288 KOBJMETHOD(uart_flush, z8530_bus_flush),
289 KOBJMETHOD(uart_getsig, z8530_bus_getsig),
290 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl),
291 KOBJMETHOD(uart_ipend, z8530_bus_ipend),
292 KOBJMETHOD(uart_param, z8530_bus_param),
293 KOBJMETHOD(uart_probe, z8530_bus_probe),
294 KOBJMETHOD(uart_receive, z8530_bus_receive),
295 KOBJMETHOD(uart_setsig, z8530_bus_setsig),
296 KOBJMETHOD(uart_transmit, z8530_bus_transmit),
300 struct uart_class uart_z8530_class = {
303 sizeof(struct z8530_softc),
304 .uc_ops = &uart_z8530_ops,
306 .uc_rclk = DEFAULT_RCLK
309 #define SIGCHG(c, i, s, d) \
311 i |= (i & s) ? s : s | d; \
313 i = (i & s) ? (i & ~s) | d : i; \
317 z8530_bus_attach(struct uart_softc *sc)
319 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
320 struct uart_bas *bas;
321 struct uart_devinfo *di;
324 if (sc->sc_sysdev != NULL) {
326 z8530->tpc = TPC_DTR|TPC_RTS;
327 z8530_param(bas, di->baudrate, di->databits, di->stopbits,
328 di->parity, &z8530->tpc);
330 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
331 z8530->tpc &= ~(TPC_DTR|TPC_RTS);
333 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */
338 (void)z8530_bus_getsig(sc);
340 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
342 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA);
344 uart_setmreg(bas, WR_IV, 0);
346 uart_setmreg(bas, WR_TPC, z8530->tpc);
348 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE);
354 z8530_bus_detach(struct uart_softc *sc)
361 z8530_bus_flush(struct uart_softc *sc, int what)
368 z8530_bus_getsig(struct uart_softc *sc)
370 uint32_t new, old, sig;
376 uart_lock(sc->sc_hwmtx);
377 bes = uart_getmreg(&sc->sc_bas, RR_BES);
378 uart_unlock(sc->sc_hwmtx);
379 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
380 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
381 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
382 new = sig & ~SER_MASK_DELTA;
383 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
388 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
390 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
391 struct uart_bas *bas;
392 int baudrate, divisor, error;
396 uart_lock(sc->sc_hwmtx);
398 case UART_IOCTL_BREAK:
400 z8530->tpc |= TPC_BRK;
402 z8530->tpc &= ~TPC_BRK;
403 uart_setmreg(bas, WR_TPC, z8530->tpc);
406 case UART_IOCTL_BAUD:
407 divisor = uart_getmreg(bas, RR_TCH);
408 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL);
409 baudrate = bas->rclk / 2 / (divisor + 2);
410 *(int*)data = baudrate;
416 uart_unlock(sc->sc_hwmtx);
421 z8530_bus_ipend(struct uart_softc *sc)
423 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
424 struct uart_bas *bas;
427 uint8_t bes, ip, iv, src;
432 uart_lock(sc->sc_hwmtx);
435 ip = uart_getmreg(bas, RR_IP);
437 case 2: /* XXX hack!!! */
438 iv = uart_getmreg(bas, RR_IV) & 0x0E;
440 case IV_TEB: ip = IP_TIA; break;
441 case IV_XSB: ip = IP_SIA; break;
442 case IV_RAB: ip = IP_RIA; break;
443 default: ip = 0; break;
452 ipend |= SER_INT_RXREADY;
455 uart_setreg(bas, REG_CTRL, CR_RSTTXI);
458 ipend |= SER_INT_TXIDLE;
459 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */
464 uart_setreg(bas, REG_CTRL, CR_RSTXSI);
466 bes = uart_getmreg(bas, RR_BES);
468 ipend |= SER_INT_BREAK;
470 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
471 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
472 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR);
473 if (sig & SER_MASK_DELTA)
474 ipend |= SER_INT_SIGCHG;
475 src = uart_getmreg(bas, RR_SRC);
477 uart_setreg(bas, REG_CTRL, CR_RSTERR);
479 ipend |= SER_INT_OVERRUN;
484 uart_setreg(bas, REG_CTRL, CR_RSTIUS);
488 uart_unlock(sc->sc_hwmtx);
494 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
495 int stopbits, int parity)
497 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
500 uart_lock(sc->sc_hwmtx);
501 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity,
503 uart_unlock(sc->sc_hwmtx);
508 z8530_bus_probe(struct uart_softc *sc)
514 error = z8530_probe(&sc->sc_bas);
518 ch = sc->sc_bas.chan - 1 + 'A';
520 snprintf(buf, sizeof(buf), "z8530, channel %c", ch);
521 device_set_desc_copy(sc->sc_dev, buf);
526 z8530_bus_receive(struct uart_softc *sc)
528 struct uart_bas *bas;
533 uart_lock(sc->sc_hwmtx);
534 bes = uart_getmreg(bas, RR_BES);
535 while (bes & BES_RXA) {
536 if (uart_rx_full(sc)) {
537 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
540 xc = uart_getreg(bas, REG_DATA);
542 src = uart_getmreg(bas, RR_SRC);
544 xc |= UART_STAT_FRAMERR;
546 xc |= UART_STAT_PARERR;
548 xc |= UART_STAT_OVERRUN;
550 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
551 uart_setreg(bas, REG_CTRL, CR_RSTERR);
554 bes = uart_getmreg(bas, RR_BES);
556 /* Discard everything left in the Rx FIFO. */
557 while (bes & BES_RXA) {
558 (void)uart_getreg(bas, REG_DATA);
560 src = uart_getmreg(bas, RR_SRC);
561 if (src & (SRC_FE | SRC_PE | SRC_OVR)) {
562 uart_setreg(bas, REG_CTRL, CR_RSTERR);
565 bes = uart_getmreg(bas, RR_BES);
567 uart_unlock(sc->sc_hwmtx);
572 z8530_bus_setsig(struct uart_softc *sc, int sig)
574 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
575 struct uart_bas *bas;
582 if (sig & SER_DDTR) {
583 SIGCHG(sig & SER_DTR, new, SER_DTR,
586 if (sig & SER_DRTS) {
587 SIGCHG(sig & SER_RTS, new, SER_RTS,
590 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
592 uart_lock(sc->sc_hwmtx);
594 z8530->tpc |= TPC_DTR;
596 z8530->tpc &= ~TPC_DTR;
598 z8530->tpc |= TPC_RTS;
600 z8530->tpc &= ~TPC_RTS;
601 uart_setmreg(bas, WR_TPC, z8530->tpc);
603 uart_unlock(sc->sc_hwmtx);
608 z8530_bus_transmit(struct uart_softc *sc)
610 struct z8530_softc *z8530 = (struct z8530_softc*)sc;
611 struct uart_bas *bas;
614 uart_lock(sc->sc_hwmtx);
615 while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
617 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
620 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */
621 uart_unlock(sc->sc_hwmtx);