3 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * This file contains the driver for the AT91 series USB Device
33 * Thanks to "David Brownell" for helping out regarding the hardware
38 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is
41 * NOTE: When the chip detects BUS-reset it will also reset the
42 * endpoints, Function-address and more.
45 #ifdef USB_GLOBAL_INCLUDE_FILE
46 #include USB_GLOBAL_INCLUDE_FILE
48 #include <sys/stdint.h>
49 #include <sys/stddef.h>
50 #include <sys/param.h>
51 #include <sys/queue.h>
52 #include <sys/types.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
56 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/condvar.h>
60 #include <sys/sysctl.h>
62 #include <sys/unistd.h>
63 #include <sys/callout.h>
64 #include <sys/malloc.h>
67 #include <dev/usb/usb.h>
68 #include <dev/usb/usbdi.h>
70 #define USB_DEBUG_VAR at91dcidebug
72 #include <dev/usb/usb_core.h>
73 #include <dev/usb/usb_debug.h>
74 #include <dev/usb/usb_busdma.h>
75 #include <dev/usb/usb_process.h>
76 #include <dev/usb/usb_transfer.h>
77 #include <dev/usb/usb_device.h>
78 #include <dev/usb/usb_hub.h>
79 #include <dev/usb/usb_util.h>
81 #include <dev/usb/usb_controller.h>
82 #include <dev/usb/usb_bus.h>
83 #endif /* USB_GLOBAL_INCLUDE_FILE */
85 #include <dev/usb/controller/at91dci.h>
87 #define AT9100_DCI_BUS2SC(bus) \
88 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \
89 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus))))
91 #define AT9100_DCI_PC2SC(pc) \
92 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
95 static int at91dcidebug = 0;
97 static SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci");
98 SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW,
99 &at91dcidebug, 0, "at91dci debug level");
102 #define AT9100_DCI_INTR_ENDPT 1
106 struct usb_bus_methods at91dci_bus_methods;
107 struct usb_pipe_methods at91dci_device_bulk_methods;
108 struct usb_pipe_methods at91dci_device_ctrl_methods;
109 struct usb_pipe_methods at91dci_device_intr_methods;
110 struct usb_pipe_methods at91dci_device_isoc_fs_methods;
112 static at91dci_cmd_t at91dci_setup_rx;
113 static at91dci_cmd_t at91dci_data_rx;
114 static at91dci_cmd_t at91dci_data_tx;
115 static at91dci_cmd_t at91dci_data_tx_sync;
116 static void at91dci_device_done(struct usb_xfer *, usb_error_t);
117 static void at91dci_do_poll(struct usb_bus *);
118 static void at91dci_standard_done(struct usb_xfer *);
119 static void at91dci_root_intr(struct at91dci_softc *sc);
122 * NOTE: Some of the bits in the CSR register have inverse meaning so
123 * we need a helper macro when acknowledging events:
125 #define AT91_CSR_ACK(csr, what) do { \
126 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \
127 AT91_UDP_CSR_TXPKTRDY| \
128 AT91_UDP_CSR_RXBYTECNT) ^ (what));\
129 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \
130 AT91_UDP_CSR_RX_DATA_BK1| \
131 AT91_UDP_CSR_TXCOMP| \
132 AT91_UDP_CSR_RXSETUP| \
133 AT91_UDP_CSR_STALLSENT) ^ (what)); \
137 * Here is a list of what the chip supports.
138 * Probably it supports more than listed here!
140 static const struct usb_hw_ep_profile
141 at91dci_ep_profile[AT91_UDP_EP_MAX] = {
144 .max_in_frame_size = 8,
145 .max_out_frame_size = 8,
147 .support_control = 1,
150 .max_in_frame_size = 64,
151 .max_out_frame_size = 64,
153 .support_multi_buffer = 1,
155 .support_interrupt = 1,
156 .support_isochronous = 1,
161 .max_in_frame_size = 64,
162 .max_out_frame_size = 64,
164 .support_multi_buffer = 1,
166 .support_interrupt = 1,
167 .support_isochronous = 1,
172 /* can also do BULK */
173 .max_in_frame_size = 8,
174 .max_out_frame_size = 8,
176 .support_interrupt = 1,
181 .max_in_frame_size = 256,
182 .max_out_frame_size = 256,
184 .support_multi_buffer = 1,
186 .support_interrupt = 1,
187 .support_isochronous = 1,
192 .max_in_frame_size = 256,
193 .max_out_frame_size = 256,
195 .support_multi_buffer = 1,
197 .support_interrupt = 1,
198 .support_isochronous = 1,
205 at91dci_get_hw_ep_profile(struct usb_device *udev,
206 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
208 if (ep_addr < AT91_UDP_EP_MAX) {
209 *ppf = (at91dci_ep_profile + ep_addr);
216 at91dci_clocks_on(struct at91dci_softc *sc)
218 if (sc->sc_flags.clocks_off &&
219 sc->sc_flags.port_powered) {
223 if (sc->sc_clocks_on) {
224 (sc->sc_clocks_on) (sc->sc_clocks_arg);
226 sc->sc_flags.clocks_off = 0;
228 /* enable Transceiver */
229 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0);
234 at91dci_clocks_off(struct at91dci_softc *sc)
236 if (!sc->sc_flags.clocks_off) {
240 /* disable Transceiver */
241 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
243 if (sc->sc_clocks_off) {
244 (sc->sc_clocks_off) (sc->sc_clocks_arg);
246 sc->sc_flags.clocks_off = 1;
251 at91dci_pull_up(struct at91dci_softc *sc)
253 /* pullup D+, if possible */
255 if (!sc->sc_flags.d_pulled_up &&
256 sc->sc_flags.port_powered) {
257 sc->sc_flags.d_pulled_up = 1;
258 (sc->sc_pull_up) (sc->sc_pull_arg);
263 at91dci_pull_down(struct at91dci_softc *sc)
265 /* pulldown D+, if possible */
267 if (sc->sc_flags.d_pulled_up) {
268 sc->sc_flags.d_pulled_up = 0;
269 (sc->sc_pull_down) (sc->sc_pull_arg);
274 at91dci_wakeup_peer(struct at91dci_softc *sc)
276 if (!(sc->sc_flags.status_suspend)) {
280 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR);
282 /* wait 8 milliseconds */
283 /* Wait for reset to complete. */
284 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
286 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0);
290 at91dci_set_address(struct at91dci_softc *sc, uint8_t addr)
292 DPRINTFN(5, "addr=%d\n", addr);
294 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr |
299 at91dci_setup_rx(struct at91dci_td *td)
301 struct at91dci_softc *sc;
302 struct usb_device_request req;
307 /* read out FIFO status */
308 csr = bus_space_read_4(td->io_tag, td->io_hdl,
311 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
314 temp &= (AT91_UDP_CSR_RX_DATA_BK0 |
315 AT91_UDP_CSR_RX_DATA_BK1 |
316 AT91_UDP_CSR_STALLSENT |
317 AT91_UDP_CSR_RXSETUP |
318 AT91_UDP_CSR_TXCOMP);
320 if (!(csr & AT91_UDP_CSR_RXSETUP)) {
323 /* clear did stall */
326 /* get the packet byte count */
327 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
329 /* verify data length */
330 if (count != td->remainder) {
331 DPRINTFN(0, "Invalid SETUP packet "
332 "length, %d bytes\n", count);
335 if (count != sizeof(req)) {
336 DPRINTFN(0, "Unsupported SETUP packet "
337 "length, %d bytes\n", count);
341 bus_space_read_multi_1(td->io_tag, td->io_hdl,
342 td->fifo_reg, (void *)&req, sizeof(req));
344 /* copy data into real buffer */
345 usbd_copy_in(td->pc, 0, &req, sizeof(req));
347 td->offset = sizeof(req);
350 /* get pointer to softc */
351 sc = AT9100_DCI_PC2SC(td->pc);
353 /* sneak peek the set address */
354 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
355 (req.bRequest == UR_SET_ADDRESS)) {
356 sc->sc_dv_addr = req.wValue[0] & 0x7F;
358 sc->sc_dv_addr = 0xFF;
361 /* sneak peek the endpoint direction */
362 if (req.bmRequestType & UE_DIR_IN) {
363 csr |= AT91_UDP_CSR_DIR;
365 csr &= ~AT91_UDP_CSR_DIR;
368 /* write the direction of the control transfer */
369 AT91_CSR_ACK(csr, temp);
370 bus_space_write_4(td->io_tag, td->io_hdl,
371 td->status_reg, csr);
372 return (0); /* complete */
375 /* abort any ongoing transfer */
376 if (!td->did_stall) {
377 DPRINTFN(5, "stalling\n");
378 temp |= AT91_UDP_CSR_FORCESTALL;
382 /* clear interrupts, if any */
384 DPRINTFN(5, "clearing 0x%08x\n", temp);
385 AT91_CSR_ACK(csr, temp);
386 bus_space_write_4(td->io_tag, td->io_hdl,
387 td->status_reg, csr);
389 return (1); /* not complete */
394 at91dci_data_rx(struct at91dci_td *td)
396 struct usb_page_search buf_res;
403 to = 2; /* don't loop forever! */
406 /* check if any of the FIFO banks have data */
408 /* read out FIFO status */
409 csr = bus_space_read_4(td->io_tag, td->io_hdl,
412 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
414 if (csr & AT91_UDP_CSR_RXSETUP) {
415 if (td->remainder == 0) {
417 * We are actually complete and have
418 * received the next SETUP
420 DPRINTFN(5, "faking complete\n");
421 return (0); /* complete */
424 * USB Host Aborted the transfer.
427 return (0); /* complete */
429 /* Make sure that "STALLSENT" gets cleared */
431 temp &= AT91_UDP_CSR_STALLSENT;
434 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 |
435 AT91_UDP_CSR_RX_DATA_BK1))) {
438 AT91_CSR_ACK(csr, temp);
439 bus_space_write_4(td->io_tag, td->io_hdl,
440 td->status_reg, csr);
442 return (1); /* not complete */
444 /* get the packet byte count */
445 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
447 /* verify the packet byte count */
448 if (count != td->max_packet_size) {
449 if (count < td->max_packet_size) {
450 /* we have a short packet */
454 /* invalid USB packet */
456 return (0); /* we are complete */
459 /* verify the packet byte count */
460 if (count > td->remainder) {
461 /* invalid USB packet */
463 return (0); /* we are complete */
466 usbd_get_page(td->pc, td->offset, &buf_res);
468 /* get correct length */
469 if (buf_res.length > count) {
470 buf_res.length = count;
473 bus_space_read_multi_1(td->io_tag, td->io_hdl,
474 td->fifo_reg, buf_res.buffer, buf_res.length);
476 /* update counters */
477 count -= buf_res.length;
478 td->offset += buf_res.length;
479 td->remainder -= buf_res.length;
482 /* clear status bits */
483 if (td->support_multi_buffer) {
486 temp |= AT91_UDP_CSR_RX_DATA_BK1;
489 temp |= AT91_UDP_CSR_RX_DATA_BK0;
492 temp |= (AT91_UDP_CSR_RX_DATA_BK0 |
493 AT91_UDP_CSR_RX_DATA_BK1);
497 AT91_CSR_ACK(csr, temp);
498 bus_space_write_4(td->io_tag, td->io_hdl,
499 td->status_reg, csr);
502 * NOTE: We may have to delay a little bit before
503 * proceeding after clearing the DATA_BK bits.
506 /* check if we are complete */
507 if ((td->remainder == 0) || got_short) {
509 /* we are complete */
512 /* else need to receive a zero length packet */
517 return (1); /* not complete */
521 at91dci_data_tx(struct at91dci_td *td)
523 struct usb_page_search buf_res;
529 to = 2; /* don't loop forever! */
533 /* read out FIFO status */
534 csr = bus_space_read_4(td->io_tag, td->io_hdl,
537 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
539 if (csr & AT91_UDP_CSR_RXSETUP) {
541 * The current transfer was aborted
545 return (0); /* complete */
547 /* Make sure that "STALLSENT" gets cleared */
549 temp &= AT91_UDP_CSR_STALLSENT;
551 if (csr & AT91_UDP_CSR_TXPKTRDY) {
554 AT91_CSR_ACK(csr, temp);
555 bus_space_write_4(td->io_tag, td->io_hdl,
556 td->status_reg, csr);
558 return (1); /* not complete */
560 /* clear TXCOMP and set TXPKTRDY */
561 temp |= (AT91_UDP_CSR_TXCOMP |
562 AT91_UDP_CSR_TXPKTRDY);
565 count = td->max_packet_size;
566 if (td->remainder < count) {
567 /* we have a short packet */
569 count = td->remainder;
573 usbd_get_page(td->pc, td->offset, &buf_res);
575 /* get correct length */
576 if (buf_res.length > count) {
577 buf_res.length = count;
580 bus_space_write_multi_1(td->io_tag, td->io_hdl,
581 td->fifo_reg, buf_res.buffer, buf_res.length);
583 /* update counters */
584 count -= buf_res.length;
585 td->offset += buf_res.length;
586 td->remainder -= buf_res.length;
590 AT91_CSR_ACK(csr, temp);
591 bus_space_write_4(td->io_tag, td->io_hdl,
592 td->status_reg, csr);
594 /* check remainder */
595 if (td->remainder == 0) {
597 return (0); /* complete */
599 /* else we need to transmit a short packet */
604 return (1); /* not complete */
608 at91dci_data_tx_sync(struct at91dci_td *td)
610 struct at91dci_softc *sc;
618 /* read out FIFO status */
619 csr = bus_space_read_4(td->io_tag, td->io_hdl,
622 DPRINTFN(5, "csr=0x%08x\n", csr);
624 if (csr & AT91_UDP_CSR_RXSETUP) {
625 DPRINTFN(5, "faking complete\n");
627 return (0); /* complete */
630 temp &= (AT91_UDP_CSR_STALLSENT |
631 AT91_UDP_CSR_TXCOMP);
634 if (csr & AT91_UDP_CSR_TXPKTRDY) {
637 if (!(csr & AT91_UDP_CSR_TXCOMP)) {
640 sc = AT9100_DCI_PC2SC(td->pc);
641 if (sc->sc_dv_addr != 0xFF) {
643 * The AT91 has a special requirement with regard to
644 * setting the address and that is to write the new
645 * address before clearing TXCOMP:
647 at91dci_set_address(sc, sc->sc_dv_addr);
650 AT91_CSR_ACK(csr, temp);
651 bus_space_write_4(td->io_tag, td->io_hdl,
652 td->status_reg, csr);
654 return (0); /* complete */
659 AT91_CSR_ACK(csr, temp);
660 bus_space_write_4(td->io_tag, td->io_hdl,
661 td->status_reg, csr);
663 return (1); /* not complete */
667 at91dci_xfer_do_fifo(struct usb_xfer *xfer)
669 struct at91dci_softc *sc;
670 struct at91dci_td *td;
675 td = xfer->td_transfer_cache;
677 if ((td->func) (td)) {
678 /* operation in progress */
681 if (((void *)td) == xfer->td_transfer_last) {
686 } else if (td->remainder > 0) {
688 * We had a short transfer. If there is no alternate
689 * next, stop processing !
696 * Fetch the next transfer descriptor and transfer
697 * some flags to the next transfer descriptor
703 xfer->td_transfer_cache = td;
707 return (1); /* not complete */
710 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
711 temp = (xfer->endpointno & UE_ADDR);
713 /* update FIFO bank flag and multi buffer */
715 sc->sc_ep_flags[temp].fifo_bank = 1;
717 sc->sc_ep_flags[temp].fifo_bank = 0;
720 /* compute all actual lengths */
722 at91dci_standard_done(xfer);
724 return (0); /* complete */
728 at91dci_interrupt_poll(struct at91dci_softc *sc)
730 struct usb_xfer *xfer;
733 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
734 if (!at91dci_xfer_do_fifo(xfer)) {
735 /* queue has been modified */
742 at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on)
744 DPRINTFN(5, "vbus = %u\n", is_on);
747 if (!sc->sc_flags.status_vbus) {
748 sc->sc_flags.status_vbus = 1;
750 /* complete root HUB interrupt endpoint */
751 at91dci_root_intr(sc);
754 if (sc->sc_flags.status_vbus) {
755 sc->sc_flags.status_vbus = 0;
756 sc->sc_flags.status_bus_reset = 0;
757 sc->sc_flags.status_suspend = 0;
758 sc->sc_flags.change_suspend = 0;
759 sc->sc_flags.change_connect = 1;
761 /* complete root HUB interrupt endpoint */
762 at91dci_root_intr(sc);
768 at91dci_interrupt(struct at91dci_softc *sc)
772 USB_BUS_LOCK(&sc->sc_bus);
774 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
775 status &= AT91_UDP_INT_DEFAULT;
778 USB_BUS_UNLOCK(&sc->sc_bus);
781 /* acknowledge interrupts */
783 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status);
785 /* check for any bus state change interrupts */
787 if (status & AT91_UDP_INT_BUS) {
789 DPRINTFN(5, "real bus interrupt 0x%08x\n", status);
791 if (status & AT91_UDP_INT_END_BR) {
793 /* set correct state */
794 sc->sc_flags.status_bus_reset = 1;
795 sc->sc_flags.status_suspend = 0;
796 sc->sc_flags.change_suspend = 0;
797 sc->sc_flags.change_connect = 1;
799 /* disable resume interrupt */
800 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
802 /* enable suspend interrupt */
803 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
804 AT91_UDP_INT_RXSUSP);
807 * If RXRSM and RXSUSP is set at the same time we interpret
808 * that like RESUME. Resume is set when there is at least 3
809 * milliseconds of inactivity on the USB BUS.
811 if (status & AT91_UDP_INT_RXRSM) {
812 if (sc->sc_flags.status_suspend) {
813 sc->sc_flags.status_suspend = 0;
814 sc->sc_flags.change_suspend = 1;
816 /* disable resume interrupt */
817 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
819 /* enable suspend interrupt */
820 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
821 AT91_UDP_INT_RXSUSP);
823 } else if (status & AT91_UDP_INT_RXSUSP) {
824 if (!sc->sc_flags.status_suspend) {
825 sc->sc_flags.status_suspend = 1;
826 sc->sc_flags.change_suspend = 1;
828 /* disable suspend interrupt */
829 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
830 AT91_UDP_INT_RXSUSP);
832 /* enable resume interrupt */
833 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
837 /* complete root HUB interrupt endpoint */
838 at91dci_root_intr(sc);
840 /* check for any endpoint interrupts */
842 if (status & AT91_UDP_INT_EPS) {
844 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status);
846 at91dci_interrupt_poll(sc);
848 USB_BUS_UNLOCK(&sc->sc_bus);
852 at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp)
854 struct at91dci_td *td;
856 /* get current Transfer Descriptor */
860 /* prepare for next TD */
861 temp->td_next = td->obj_next;
863 /* fill out the Transfer Descriptor */
864 td->func = temp->func;
866 td->offset = temp->offset;
867 td->remainder = temp->len;
870 td->did_stall = temp->did_stall;
871 td->short_pkt = temp->short_pkt;
872 td->alt_next = temp->setup_alt_next;
876 at91dci_setup_standard_chain(struct usb_xfer *xfer)
878 struct at91dci_std_temp temp;
879 struct at91dci_softc *sc;
880 struct at91dci_td *td;
885 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
886 xfer->address, UE_GET_ADDR(xfer->endpointno),
887 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
889 temp.max_frame_size = xfer->max_frame_size;
891 td = xfer->td_start[0];
892 xfer->td_transfer_first = td;
893 xfer->td_transfer_cache = td;
899 temp.td_next = xfer->td_start[0];
901 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
902 temp.did_stall = !xfer->flags_int.control_stall;
904 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
905 ep_no = (xfer->endpointno & UE_ADDR);
907 /* check if we should prepend a setup message */
909 if (xfer->flags_int.control_xfr) {
910 if (xfer->flags_int.control_hdr) {
912 temp.func = &at91dci_setup_rx;
913 temp.len = xfer->frlengths[0];
914 temp.pc = xfer->frbuffers + 0;
915 temp.short_pkt = temp.len ? 1 : 0;
916 /* check for last frame */
917 if (xfer->nframes == 1) {
918 /* no STATUS stage yet, SETUP is last */
919 if (xfer->flags_int.control_act)
920 temp.setup_alt_next = 0;
923 at91dci_setup_standard_chain_sub(&temp);
930 if (x != xfer->nframes) {
931 if (xfer->endpointno & UE_DIR_IN) {
932 temp.func = &at91dci_data_tx;
935 temp.func = &at91dci_data_rx;
939 /* setup "pc" pointer */
940 temp.pc = xfer->frbuffers + x;
944 while (x != xfer->nframes) {
946 /* DATA0 / DATA1 message */
948 temp.len = xfer->frlengths[x];
952 if (x == xfer->nframes) {
953 if (xfer->flags_int.control_xfr) {
954 if (xfer->flags_int.control_act) {
955 temp.setup_alt_next = 0;
958 temp.setup_alt_next = 0;
963 /* make sure that we send an USB packet */
969 /* regular data transfer */
971 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
974 at91dci_setup_standard_chain_sub(&temp);
976 if (xfer->flags_int.isochronous_xfr) {
977 temp.offset += temp.len;
979 /* get next Page Cache pointer */
980 temp.pc = xfer->frbuffers + x;
984 /* check for control transfer */
985 if (xfer->flags_int.control_xfr) {
987 /* always setup a valid "pc" pointer for status and sync */
988 temp.pc = xfer->frbuffers + 0;
991 temp.setup_alt_next = 0;
993 /* check if we need to sync */
995 /* we need a SYNC point after TX */
996 temp.func = &at91dci_data_tx_sync;
997 at91dci_setup_standard_chain_sub(&temp);
1000 /* check if we should append a status stage */
1001 if (!xfer->flags_int.control_act) {
1004 * Send a DATA1 message and invert the current
1005 * endpoint direction.
1007 if (xfer->endpointno & UE_DIR_IN) {
1008 temp.func = &at91dci_data_rx;
1011 temp.func = &at91dci_data_tx;
1015 at91dci_setup_standard_chain_sub(&temp);
1017 /* we need a SYNC point after TX */
1018 temp.func = &at91dci_data_tx_sync;
1019 at91dci_setup_standard_chain_sub(&temp);
1024 /* must have at least one frame! */
1026 xfer->td_transfer_last = td;
1028 /* setup the correct fifo bank */
1029 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1030 td = xfer->td_transfer_first;
1036 at91dci_timeout(void *arg)
1038 struct usb_xfer *xfer = arg;
1040 DPRINTF("xfer=%p\n", xfer);
1042 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1044 /* transfer is transferred */
1045 at91dci_device_done(xfer, USB_ERR_TIMEOUT);
1049 at91dci_start_standard_chain(struct usb_xfer *xfer)
1054 if (at91dci_xfer_do_fifo(xfer)) {
1056 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1057 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1060 * Only enable the endpoint interrupt when we are actually
1061 * waiting for data, hence we are dealing with level
1062 * triggered interrupts !
1064 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no));
1066 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no);
1068 /* put transfer on interrupt queue */
1069 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1071 /* start timeout, if any */
1072 if (xfer->timeout != 0) {
1073 usbd_transfer_timeout_ms(xfer,
1074 &at91dci_timeout, xfer->timeout);
1080 at91dci_root_intr(struct at91dci_softc *sc)
1084 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1087 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
1089 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1090 sizeof(sc->sc_hub_idata));
1094 at91dci_standard_done_sub(struct usb_xfer *xfer)
1096 struct at91dci_td *td;
1102 td = xfer->td_transfer_cache;
1105 len = td->remainder;
1107 if (xfer->aframes != xfer->nframes) {
1109 * Verify the length and subtract
1110 * the remainder from "frlengths[]":
1112 if (len > xfer->frlengths[xfer->aframes]) {
1115 xfer->frlengths[xfer->aframes] -= len;
1118 /* Check for transfer error */
1120 /* the transfer is finished */
1125 /* Check for short transfer */
1127 if (xfer->flags_int.short_frames_ok) {
1128 /* follow alt next */
1135 /* the transfer is finished */
1143 /* this USB frame is complete */
1149 /* update transfer cache */
1151 xfer->td_transfer_cache = td;
1154 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1158 at91dci_standard_done(struct usb_xfer *xfer)
1160 usb_error_t err = 0;
1162 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1163 xfer, xfer->endpoint);
1167 xfer->td_transfer_cache = xfer->td_transfer_first;
1169 if (xfer->flags_int.control_xfr) {
1171 if (xfer->flags_int.control_hdr) {
1173 err = at91dci_standard_done_sub(xfer);
1177 if (xfer->td_transfer_cache == NULL) {
1181 while (xfer->aframes != xfer->nframes) {
1183 err = at91dci_standard_done_sub(xfer);
1186 if (xfer->td_transfer_cache == NULL) {
1191 if (xfer->flags_int.control_xfr &&
1192 !xfer->flags_int.control_act) {
1194 err = at91dci_standard_done_sub(xfer);
1197 at91dci_device_done(xfer, err);
1200 /*------------------------------------------------------------------------*
1201 * at91dci_device_done
1203 * NOTE: this function can be called more than one time on the
1204 * same USB transfer!
1205 *------------------------------------------------------------------------*/
1207 at91dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1209 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1212 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1214 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1215 xfer, xfer->endpoint, error);
1217 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1218 ep_no = (xfer->endpointno & UE_ADDR);
1220 /* disable endpoint interrupt */
1221 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no));
1223 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no);
1225 /* dequeue transfer and start next transfer */
1226 usbd_transfer_done(xfer, error);
1230 at91dci_xfer_stall(struct usb_xfer *xfer)
1232 at91dci_device_done(xfer, USB_ERR_STALLED);
1236 at91dci_set_stall(struct usb_device *udev,
1237 struct usb_endpoint *ep, uint8_t *did_stall)
1239 struct at91dci_softc *sc;
1243 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1245 DPRINTFN(5, "endpoint=%p\n", ep);
1247 /* set FORCESTALL */
1248 sc = AT9100_DCI_BUS2SC(udev->bus);
1249 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR);
1250 csr_reg = AT91_UDP_CSR(csr_reg);
1251 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1252 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL);
1253 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1257 at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no,
1258 uint8_t ep_type, uint8_t ep_dir)
1260 const struct usb_hw_ep_profile *pf;
1266 if (ep_type == UE_CONTROL) {
1267 /* clearing stall is not needed */
1270 /* compute CSR register offset */
1271 csr_reg = AT91_UDP_CSR(ep_no);
1273 /* compute default CSR value */
1275 AT91_CSR_ACK(csr_val, 0);
1277 /* disable endpoint */
1278 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1280 /* get endpoint profile */
1281 at91dci_get_hw_ep_profile(NULL, &pf, ep_no);
1284 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no));
1285 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0);
1288 * NOTE: One would assume that a FIFO reset would release the
1289 * FIFO banks aswell, but it doesn't! We have to do this
1293 /* release FIFO banks, if any */
1294 for (to = 0; to != 2; to++) {
1297 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1299 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 |
1300 AT91_UDP_CSR_RX_DATA_BK1)) {
1301 /* clear status bits */
1302 if (pf->support_multi_buffer) {
1303 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1304 sc->sc_ep_flags[ep_no].fifo_bank = 0;
1305 temp = AT91_UDP_CSR_RX_DATA_BK1;
1307 sc->sc_ep_flags[ep_no].fifo_bank = 1;
1308 temp = AT91_UDP_CSR_RX_DATA_BK0;
1311 temp = (AT91_UDP_CSR_RX_DATA_BK0 |
1312 AT91_UDP_CSR_RX_DATA_BK1);
1318 /* clear FORCESTALL */
1319 temp |= AT91_UDP_CSR_STALLSENT;
1321 AT91_CSR_ACK(csr_val, temp);
1322 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1325 /* compute default CSR value */
1327 AT91_CSR_ACK(csr_val, 0);
1329 /* enable endpoint */
1330 csr_val &= ~AT91_UDP_CSR_ET_MASK;
1331 csr_val |= AT91_UDP_CSR_EPEDS;
1333 if (ep_type == UE_CONTROL) {
1334 csr_val |= AT91_UDP_CSR_ET_CTRL;
1336 if (ep_type == UE_BULK) {
1337 csr_val |= AT91_UDP_CSR_ET_BULK;
1338 } else if (ep_type == UE_INTERRUPT) {
1339 csr_val |= AT91_UDP_CSR_ET_INT;
1341 csr_val |= AT91_UDP_CSR_ET_ISO;
1343 if (ep_dir & UE_DIR_IN) {
1344 csr_val |= AT91_UDP_CSR_ET_DIR_IN;
1348 /* enable endpoint */
1349 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val);
1353 at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1355 struct at91dci_softc *sc;
1356 struct usb_endpoint_descriptor *ed;
1358 DPRINTFN(5, "endpoint=%p\n", ep);
1360 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1363 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1368 sc = AT9100_DCI_BUS2SC(udev->bus);
1370 /* get endpoint descriptor */
1373 /* reset endpoint */
1374 at91dci_clear_stall_sub(sc,
1375 (ed->bEndpointAddress & UE_ADDR),
1376 (ed->bmAttributes & UE_XFERTYPE),
1377 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1381 at91dci_init(struct at91dci_softc *sc)
1388 /* set up the bus structure */
1389 sc->sc_bus.usbrev = USB_REV_1_1;
1390 sc->sc_bus.methods = &at91dci_bus_methods;
1392 USB_BUS_LOCK(&sc->sc_bus);
1394 /* turn on clocks */
1396 if (sc->sc_clocks_on) {
1397 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1399 /* wait a little for things to stabilise */
1400 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1402 /* disable and clear all interrupts */
1404 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1405 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1407 /* compute default CSR value */
1410 AT91_CSR_ACK(csr_val, 0);
1412 /* disable all endpoints */
1414 for (n = 0; n != AT91_UDP_EP_MAX; n++) {
1416 /* disable endpoint */
1417 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val);
1420 /* enable the control endpoint */
1422 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL |
1423 AT91_UDP_CSR_EPEDS);
1425 /* write to FIFO control register */
1427 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val);
1429 /* enable the interrupts we want */
1431 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS);
1433 /* turn off clocks */
1435 at91dci_clocks_off(sc);
1437 USB_BUS_UNLOCK(&sc->sc_bus);
1439 /* catch any lost interrupts */
1441 at91dci_do_poll(&sc->sc_bus);
1443 return (0); /* success */
1447 at91dci_uninit(struct at91dci_softc *sc)
1449 USB_BUS_LOCK(&sc->sc_bus);
1451 /* disable and clear all interrupts */
1452 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1453 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1455 sc->sc_flags.port_powered = 0;
1456 sc->sc_flags.status_vbus = 0;
1457 sc->sc_flags.status_bus_reset = 0;
1458 sc->sc_flags.status_suspend = 0;
1459 sc->sc_flags.change_suspend = 0;
1460 sc->sc_flags.change_connect = 1;
1462 at91dci_pull_down(sc);
1463 at91dci_clocks_off(sc);
1464 USB_BUS_UNLOCK(&sc->sc_bus);
1468 at91dci_suspend(struct at91dci_softc *sc)
1474 at91dci_resume(struct at91dci_softc *sc)
1480 at91dci_do_poll(struct usb_bus *bus)
1482 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
1484 USB_BUS_LOCK(&sc->sc_bus);
1485 at91dci_interrupt_poll(sc);
1486 USB_BUS_UNLOCK(&sc->sc_bus);
1489 /*------------------------------------------------------------------------*
1490 * at91dci bulk support
1491 *------------------------------------------------------------------------*/
1493 at91dci_device_bulk_open(struct usb_xfer *xfer)
1499 at91dci_device_bulk_close(struct usb_xfer *xfer)
1501 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1505 at91dci_device_bulk_enter(struct usb_xfer *xfer)
1511 at91dci_device_bulk_start(struct usb_xfer *xfer)
1514 at91dci_setup_standard_chain(xfer);
1515 at91dci_start_standard_chain(xfer);
1518 struct usb_pipe_methods at91dci_device_bulk_methods =
1520 .open = at91dci_device_bulk_open,
1521 .close = at91dci_device_bulk_close,
1522 .enter = at91dci_device_bulk_enter,
1523 .start = at91dci_device_bulk_start,
1526 /*------------------------------------------------------------------------*
1527 * at91dci control support
1528 *------------------------------------------------------------------------*/
1530 at91dci_device_ctrl_open(struct usb_xfer *xfer)
1536 at91dci_device_ctrl_close(struct usb_xfer *xfer)
1538 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1542 at91dci_device_ctrl_enter(struct usb_xfer *xfer)
1548 at91dci_device_ctrl_start(struct usb_xfer *xfer)
1551 at91dci_setup_standard_chain(xfer);
1552 at91dci_start_standard_chain(xfer);
1555 struct usb_pipe_methods at91dci_device_ctrl_methods =
1557 .open = at91dci_device_ctrl_open,
1558 .close = at91dci_device_ctrl_close,
1559 .enter = at91dci_device_ctrl_enter,
1560 .start = at91dci_device_ctrl_start,
1563 /*------------------------------------------------------------------------*
1564 * at91dci interrupt support
1565 *------------------------------------------------------------------------*/
1567 at91dci_device_intr_open(struct usb_xfer *xfer)
1573 at91dci_device_intr_close(struct usb_xfer *xfer)
1575 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1579 at91dci_device_intr_enter(struct usb_xfer *xfer)
1585 at91dci_device_intr_start(struct usb_xfer *xfer)
1588 at91dci_setup_standard_chain(xfer);
1589 at91dci_start_standard_chain(xfer);
1592 struct usb_pipe_methods at91dci_device_intr_methods =
1594 .open = at91dci_device_intr_open,
1595 .close = at91dci_device_intr_close,
1596 .enter = at91dci_device_intr_enter,
1597 .start = at91dci_device_intr_start,
1600 /*------------------------------------------------------------------------*
1601 * at91dci full speed isochronous support
1602 *------------------------------------------------------------------------*/
1604 at91dci_device_isoc_fs_open(struct usb_xfer *xfer)
1610 at91dci_device_isoc_fs_close(struct usb_xfer *xfer)
1612 at91dci_device_done(xfer, USB_ERR_CANCELLED);
1616 at91dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1618 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1622 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1623 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1625 /* get the current frame index */
1627 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM);
1630 * check if the frame index is within the window where the frames
1633 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK;
1635 if ((xfer->endpoint->is_synced == 0) ||
1636 (temp < xfer->nframes)) {
1638 * If there is data underflow or the endpoint queue is
1639 * empty we schedule the transfer a few frames ahead
1640 * of the current frame position. Else two isochronous
1641 * transfers might overlap.
1643 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK;
1644 xfer->endpoint->is_synced = 1;
1645 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1648 * compute how many milliseconds the insertion is ahead of the
1649 * current frame position:
1651 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK;
1654 * pre-compute when the isochronous transfer will be finished:
1656 xfer->isoc_time_complete =
1657 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1660 /* compute frame number for next insertion */
1661 xfer->endpoint->isoc_next += xfer->nframes;
1664 at91dci_setup_standard_chain(xfer);
1668 at91dci_device_isoc_fs_start(struct usb_xfer *xfer)
1670 /* start TD chain */
1671 at91dci_start_standard_chain(xfer);
1674 struct usb_pipe_methods at91dci_device_isoc_fs_methods =
1676 .open = at91dci_device_isoc_fs_open,
1677 .close = at91dci_device_isoc_fs_close,
1678 .enter = at91dci_device_isoc_fs_enter,
1679 .start = at91dci_device_isoc_fs_start,
1682 /*------------------------------------------------------------------------*
1683 * at91dci root control support
1684 *------------------------------------------------------------------------*
1685 * Simulate a hardware HUB by handling all the necessary requests.
1686 *------------------------------------------------------------------------*/
1688 static const struct usb_device_descriptor at91dci_devd = {
1689 .bLength = sizeof(struct usb_device_descriptor),
1690 .bDescriptorType = UDESC_DEVICE,
1691 .bcdUSB = {0x00, 0x02},
1692 .bDeviceClass = UDCLASS_HUB,
1693 .bDeviceSubClass = UDSUBCLASS_HUB,
1694 .bDeviceProtocol = UDPROTO_FSHUB,
1695 .bMaxPacketSize = 64,
1696 .bcdDevice = {0x00, 0x01},
1699 .bNumConfigurations = 1,
1702 static const struct at91dci_config_desc at91dci_confd = {
1704 .bLength = sizeof(struct usb_config_descriptor),
1705 .bDescriptorType = UDESC_CONFIG,
1706 .wTotalLength[0] = sizeof(at91dci_confd),
1708 .bConfigurationValue = 1,
1709 .iConfiguration = 0,
1710 .bmAttributes = UC_SELF_POWERED,
1714 .bLength = sizeof(struct usb_interface_descriptor),
1715 .bDescriptorType = UDESC_INTERFACE,
1717 .bInterfaceClass = UICLASS_HUB,
1718 .bInterfaceSubClass = UISUBCLASS_HUB,
1719 .bInterfaceProtocol = 0,
1722 .bLength = sizeof(struct usb_endpoint_descriptor),
1723 .bDescriptorType = UDESC_ENDPOINT,
1724 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT),
1725 .bmAttributes = UE_INTERRUPT,
1726 .wMaxPacketSize[0] = 8,
1731 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1733 static const struct usb_hub_descriptor_min at91dci_hubd = {
1734 .bDescLength = sizeof(at91dci_hubd),
1735 .bDescriptorType = UDESC_HUB,
1737 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1738 .bPwrOn2PwrGood = 50,
1739 .bHubContrCurrent = 0,
1740 .DeviceRemovable = {0}, /* port is removable */
1743 #define STRING_VENDOR \
1746 #define STRING_PRODUCT \
1747 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1749 USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor);
1750 USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product);
1753 at91dci_roothub_exec(struct usb_device *udev,
1754 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1756 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
1763 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1766 ptr = (const void *)&sc->sc_hub_temp;
1770 value = UGETW(req->wValue);
1771 index = UGETW(req->wIndex);
1773 /* demultiplex the control request */
1775 switch (req->bmRequestType) {
1776 case UT_READ_DEVICE:
1777 switch (req->bRequest) {
1778 case UR_GET_DESCRIPTOR:
1779 goto tr_handle_get_descriptor;
1781 goto tr_handle_get_config;
1783 goto tr_handle_get_status;
1789 case UT_WRITE_DEVICE:
1790 switch (req->bRequest) {
1791 case UR_SET_ADDRESS:
1792 goto tr_handle_set_address;
1794 goto tr_handle_set_config;
1795 case UR_CLEAR_FEATURE:
1796 goto tr_valid; /* nop */
1797 case UR_SET_DESCRIPTOR:
1798 goto tr_valid; /* nop */
1799 case UR_SET_FEATURE:
1805 case UT_WRITE_ENDPOINT:
1806 switch (req->bRequest) {
1807 case UR_CLEAR_FEATURE:
1808 switch (UGETW(req->wValue)) {
1809 case UF_ENDPOINT_HALT:
1810 goto tr_handle_clear_halt;
1811 case UF_DEVICE_REMOTE_WAKEUP:
1812 goto tr_handle_clear_wakeup;
1817 case UR_SET_FEATURE:
1818 switch (UGETW(req->wValue)) {
1819 case UF_ENDPOINT_HALT:
1820 goto tr_handle_set_halt;
1821 case UF_DEVICE_REMOTE_WAKEUP:
1822 goto tr_handle_set_wakeup;
1827 case UR_SYNCH_FRAME:
1828 goto tr_valid; /* nop */
1834 case UT_READ_ENDPOINT:
1835 switch (req->bRequest) {
1837 goto tr_handle_get_ep_status;
1843 case UT_WRITE_INTERFACE:
1844 switch (req->bRequest) {
1845 case UR_SET_INTERFACE:
1846 goto tr_handle_set_interface;
1847 case UR_CLEAR_FEATURE:
1848 goto tr_valid; /* nop */
1849 case UR_SET_FEATURE:
1855 case UT_READ_INTERFACE:
1856 switch (req->bRequest) {
1857 case UR_GET_INTERFACE:
1858 goto tr_handle_get_interface;
1860 goto tr_handle_get_iface_status;
1866 case UT_WRITE_CLASS_INTERFACE:
1867 case UT_WRITE_VENDOR_INTERFACE:
1871 case UT_READ_CLASS_INTERFACE:
1872 case UT_READ_VENDOR_INTERFACE:
1876 case UT_WRITE_CLASS_DEVICE:
1877 switch (req->bRequest) {
1878 case UR_CLEAR_FEATURE:
1880 case UR_SET_DESCRIPTOR:
1881 case UR_SET_FEATURE:
1888 case UT_WRITE_CLASS_OTHER:
1889 switch (req->bRequest) {
1890 case UR_CLEAR_FEATURE:
1891 goto tr_handle_clear_port_feature;
1892 case UR_SET_FEATURE:
1893 goto tr_handle_set_port_feature;
1894 case UR_CLEAR_TT_BUFFER:
1904 case UT_READ_CLASS_OTHER:
1905 switch (req->bRequest) {
1906 case UR_GET_TT_STATE:
1907 goto tr_handle_get_tt_state;
1909 goto tr_handle_get_port_status;
1915 case UT_READ_CLASS_DEVICE:
1916 switch (req->bRequest) {
1917 case UR_GET_DESCRIPTOR:
1918 goto tr_handle_get_class_descriptor;
1920 goto tr_handle_get_class_status;
1931 tr_handle_get_descriptor:
1932 switch (value >> 8) {
1937 len = sizeof(at91dci_devd);
1938 ptr = (const void *)&at91dci_devd;
1944 len = sizeof(at91dci_confd);
1945 ptr = (const void *)&at91dci_confd;
1948 switch (value & 0xff) {
1949 case 0: /* Language table */
1950 len = sizeof(usb_string_lang_en);
1951 ptr = (const void *)&usb_string_lang_en;
1954 case 1: /* Vendor */
1955 len = sizeof(at91dci_vendor);
1956 ptr = (const void *)&at91dci_vendor;
1959 case 2: /* Product */
1960 len = sizeof(at91dci_product);
1961 ptr = (const void *)&at91dci_product;
1972 tr_handle_get_config:
1974 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1977 tr_handle_get_status:
1979 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1982 tr_handle_set_address:
1983 if (value & 0xFF00) {
1986 sc->sc_rt_addr = value;
1989 tr_handle_set_config:
1993 sc->sc_conf = value;
1996 tr_handle_get_interface:
1998 sc->sc_hub_temp.wValue[0] = 0;
2001 tr_handle_get_tt_state:
2002 tr_handle_get_class_status:
2003 tr_handle_get_iface_status:
2004 tr_handle_get_ep_status:
2006 USETW(sc->sc_hub_temp.wValue, 0);
2010 tr_handle_set_interface:
2011 tr_handle_set_wakeup:
2012 tr_handle_clear_wakeup:
2013 tr_handle_clear_halt:
2016 tr_handle_clear_port_feature:
2020 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2023 case UHF_PORT_SUSPEND:
2024 at91dci_wakeup_peer(sc);
2027 case UHF_PORT_ENABLE:
2028 sc->sc_flags.port_enabled = 0;
2032 case UHF_PORT_INDICATOR:
2033 case UHF_C_PORT_ENABLE:
2034 case UHF_C_PORT_OVER_CURRENT:
2035 case UHF_C_PORT_RESET:
2038 case UHF_PORT_POWER:
2039 sc->sc_flags.port_powered = 0;
2040 at91dci_pull_down(sc);
2041 at91dci_clocks_off(sc);
2043 case UHF_C_PORT_CONNECTION:
2044 sc->sc_flags.change_connect = 0;
2046 case UHF_C_PORT_SUSPEND:
2047 sc->sc_flags.change_suspend = 0;
2050 err = USB_ERR_IOERROR;
2055 tr_handle_set_port_feature:
2059 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2062 case UHF_PORT_ENABLE:
2063 sc->sc_flags.port_enabled = 1;
2065 case UHF_PORT_SUSPEND:
2066 case UHF_PORT_RESET:
2068 case UHF_PORT_INDICATOR:
2071 case UHF_PORT_POWER:
2072 sc->sc_flags.port_powered = 1;
2075 err = USB_ERR_IOERROR;
2080 tr_handle_get_port_status:
2082 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2087 if (sc->sc_flags.status_vbus) {
2088 at91dci_clocks_on(sc);
2089 at91dci_pull_up(sc);
2091 at91dci_pull_down(sc);
2092 at91dci_clocks_off(sc);
2095 /* Select FULL-speed and Device Side Mode */
2097 value = UPS_PORT_MODE_DEVICE;
2099 if (sc->sc_flags.port_powered) {
2100 value |= UPS_PORT_POWER;
2102 if (sc->sc_flags.port_enabled) {
2103 value |= UPS_PORT_ENABLED;
2105 if (sc->sc_flags.status_vbus &&
2106 sc->sc_flags.status_bus_reset) {
2107 value |= UPS_CURRENT_CONNECT_STATUS;
2109 if (sc->sc_flags.status_suspend) {
2110 value |= UPS_SUSPEND;
2112 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2116 if (sc->sc_flags.change_connect) {
2117 value |= UPS_C_CONNECT_STATUS;
2119 if (sc->sc_flags.status_vbus &&
2120 sc->sc_flags.status_bus_reset) {
2121 /* reset endpoint flags */
2122 memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags));
2125 if (sc->sc_flags.change_suspend) {
2126 value |= UPS_C_SUSPEND;
2128 USETW(sc->sc_hub_temp.ps.wPortChange, value);
2129 len = sizeof(sc->sc_hub_temp.ps);
2132 tr_handle_get_class_descriptor:
2136 ptr = (const void *)&at91dci_hubd;
2137 len = sizeof(at91dci_hubd);
2141 err = USB_ERR_STALLED;
2150 at91dci_xfer_setup(struct usb_setup_params *parm)
2152 const struct usb_hw_ep_profile *pf;
2153 struct at91dci_softc *sc;
2154 struct usb_xfer *xfer;
2160 sc = AT9100_DCI_BUS2SC(parm->udev->bus);
2161 xfer = parm->curr_xfer;
2164 * NOTE: This driver does not use any of the parameters that
2165 * are computed from the following values. Just set some
2166 * reasonable dummies:
2168 parm->hc_max_packet_size = 0x500;
2169 parm->hc_max_packet_count = 1;
2170 parm->hc_max_frame_size = 0x500;
2172 usbd_transfer_setup_sub(parm);
2175 * compute maximum number of TDs
2177 if (parm->methods == &at91dci_device_ctrl_methods) {
2179 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2182 } else if (parm->methods == &at91dci_device_bulk_methods) {
2184 ntd = xfer->nframes + 1 /* SYNC */ ;
2186 } else if (parm->methods == &at91dci_device_intr_methods) {
2188 ntd = xfer->nframes + 1 /* SYNC */ ;
2190 } else if (parm->methods == &at91dci_device_isoc_fs_methods) {
2192 ntd = xfer->nframes + 1 /* SYNC */ ;
2200 * check if "usbd_transfer_setup_sub" set an error
2206 * allocate transfer descriptors
2215 ep_no = xfer->endpointno & UE_ADDR;
2216 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2219 /* should not happen */
2220 parm->err = USB_ERR_INVAL;
2229 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2231 for (n = 0; n != ntd; n++) {
2233 struct at91dci_td *td;
2237 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2240 td->io_tag = sc->sc_io_tag;
2241 td->io_hdl = sc->sc_io_hdl;
2242 td->max_packet_size = xfer->max_packet_size;
2243 td->status_reg = AT91_UDP_CSR(ep_no);
2244 td->fifo_reg = AT91_UDP_FDR(ep_no);
2245 if (pf->support_multi_buffer) {
2246 td->support_multi_buffer = 1;
2248 td->obj_next = last_obj;
2252 parm->size[0] += sizeof(*td);
2255 xfer->td_start[0] = last_obj;
2259 at91dci_xfer_unsetup(struct usb_xfer *xfer)
2265 at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2266 struct usb_endpoint *ep)
2268 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
2270 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2272 edesc->bEndpointAddress, udev->flags.usb_mode,
2275 if (udev->device_index != sc->sc_rt_addr) {
2277 if (udev->speed != USB_SPEED_FULL) {
2281 switch (edesc->bmAttributes & UE_XFERTYPE) {
2283 ep->methods = &at91dci_device_ctrl_methods;
2286 ep->methods = &at91dci_device_intr_methods;
2288 case UE_ISOCHRONOUS:
2289 ep->methods = &at91dci_device_isoc_fs_methods;
2292 ep->methods = &at91dci_device_bulk_methods;
2302 at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2304 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
2307 case USB_HW_POWER_SUSPEND:
2308 at91dci_suspend(sc);
2310 case USB_HW_POWER_SHUTDOWN:
2313 case USB_HW_POWER_RESUME:
2321 struct usb_bus_methods at91dci_bus_methods =
2323 .endpoint_init = &at91dci_ep_init,
2324 .xfer_setup = &at91dci_xfer_setup,
2325 .xfer_unsetup = &at91dci_xfer_unsetup,
2326 .get_hw_ep_profile = &at91dci_get_hw_ep_profile,
2327 .set_stall = &at91dci_set_stall,
2328 .xfer_stall = &at91dci_xfer_stall,
2329 .clear_stall = &at91dci_clear_stall,
2330 .roothub_exec = &at91dci_roothub_exec,
2331 .xfer_poll = &at91dci_do_poll,
2332 .set_hw_power_sleep = &at91dci_set_hw_power_sleep,