3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * This file contains the driver for the ATMEGA series USB OTG Controller. This
29 * driver currently only supports the DCI mode of the USB hardware.
33 * NOTE: When the chip detects BUS-reset it will also reset the
34 * endpoints, Function-address and more.
37 #ifdef USB_GLOBAL_INCLUDE_FILE
38 #include USB_GLOBAL_INCLUDE_FILE
40 #include <sys/stdint.h>
41 #include <sys/stddef.h>
42 #include <sys/param.h>
43 #include <sys/queue.h>
44 #include <sys/types.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/condvar.h>
52 #include <sys/sysctl.h>
54 #include <sys/unistd.h>
55 #include <sys/callout.h>
56 #include <sys/malloc.h>
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
62 #define USB_DEBUG_VAR atmegadci_debug
64 #include <dev/usb/usb_core.h>
65 #include <dev/usb/usb_debug.h>
66 #include <dev/usb/usb_busdma.h>
67 #include <dev/usb/usb_process.h>
68 #include <dev/usb/usb_transfer.h>
69 #include <dev/usb/usb_device.h>
70 #include <dev/usb/usb_hub.h>
71 #include <dev/usb/usb_util.h>
73 #include <dev/usb/usb_controller.h>
74 #include <dev/usb/usb_bus.h>
75 #endif /* USB_GLOBAL_INCLUDE_FILE */
77 #include <dev/usb/controller/atmegadci.h>
79 #define ATMEGA_BUS2SC(bus) \
80 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
81 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
83 #define ATMEGA_PC2SC(pc) \
84 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
87 static int atmegadci_debug = 0;
89 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0,
91 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW,
92 &atmegadci_debug, 0, "ATMEGA DCI debug level");
95 #define ATMEGA_INTR_ENDPT 1
99 struct usb_bus_methods atmegadci_bus_methods;
100 struct usb_pipe_methods atmegadci_device_non_isoc_methods;
101 struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
103 static atmegadci_cmd_t atmegadci_setup_rx;
104 static atmegadci_cmd_t atmegadci_data_rx;
105 static atmegadci_cmd_t atmegadci_data_tx;
106 static atmegadci_cmd_t atmegadci_data_tx_sync;
107 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
108 static void atmegadci_do_poll(struct usb_bus *);
109 static void atmegadci_standard_done(struct usb_xfer *);
110 static void atmegadci_root_intr(struct atmegadci_softc *sc);
113 * Here is a list of what the chip supports:
115 static const struct usb_hw_ep_profile
116 atmegadci_ep_profile[2] = {
119 .max_in_frame_size = 64,
120 .max_out_frame_size = 64,
122 .support_control = 1,
125 .max_in_frame_size = 64,
126 .max_out_frame_size = 64,
129 .support_interrupt = 1,
130 .support_isochronous = 1,
137 atmegadci_get_hw_ep_profile(struct usb_device *udev,
138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
141 *ppf = atmegadci_ep_profile;
142 else if (ep_addr < ATMEGA_EP_MAX)
143 *ppf = atmegadci_ep_profile + 1;
149 atmegadci_clocks_on(struct atmegadci_softc *sc)
151 if (sc->sc_flags.clocks_off &&
152 sc->sc_flags.port_powered) {
157 (sc->sc_clocks_on) (&sc->sc_bus);
159 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
161 ATMEGA_USBCON_OTGPADE |
162 ATMEGA_USBCON_VBUSTE);
164 sc->sc_flags.clocks_off = 0;
166 /* enable transceiver ? */
171 atmegadci_clocks_off(struct atmegadci_softc *sc)
173 if (!sc->sc_flags.clocks_off) {
177 /* disable Transceiver ? */
179 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
181 ATMEGA_USBCON_OTGPADE |
182 ATMEGA_USBCON_FRZCLK |
183 ATMEGA_USBCON_VBUSTE);
185 /* turn clocks off */
186 (sc->sc_clocks_off) (&sc->sc_bus);
188 sc->sc_flags.clocks_off = 1;
193 atmegadci_pull_up(struct atmegadci_softc *sc)
195 /* pullup D+, if possible */
197 if (!sc->sc_flags.d_pulled_up &&
198 sc->sc_flags.port_powered) {
199 sc->sc_flags.d_pulled_up = 1;
200 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
205 atmegadci_pull_down(struct atmegadci_softc *sc)
207 /* pulldown D+, if possible */
209 if (sc->sc_flags.d_pulled_up) {
210 sc->sc_flags.d_pulled_up = 0;
211 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
216 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
220 if (!sc->sc_flags.status_suspend) {
224 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
225 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
227 /* wait 8 milliseconds */
228 /* Wait for reset to complete. */
229 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
231 /* hardware should have cleared RMWKUP bit */
235 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
237 DPRINTFN(5, "addr=%d\n", addr);
239 addr |= ATMEGA_UDADDR_ADDEN;
241 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
245 atmegadci_setup_rx(struct atmegadci_td *td)
247 struct atmegadci_softc *sc;
248 struct usb_device_request req;
252 /* get pointer to softc */
253 sc = ATMEGA_PC2SC(td->pc);
255 /* select endpoint number */
256 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
258 /* check endpoint status */
259 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
261 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
263 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
266 /* clear did stall */
268 /* get the packet byte count */
270 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
271 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
273 /* mask away undefined bits */
276 /* verify data length */
277 if (count != td->remainder) {
278 DPRINTFN(0, "Invalid SETUP packet "
279 "length, %d bytes\n", count);
282 if (count != sizeof(req)) {
283 DPRINTFN(0, "Unsupported SETUP packet "
284 "length, %d bytes\n", count);
288 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
289 (void *)&req, sizeof(req));
291 /* copy data into real buffer */
292 usbd_copy_in(td->pc, 0, &req, sizeof(req));
294 td->offset = sizeof(req);
297 /* sneak peek the set address */
298 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
299 (req.bRequest == UR_SET_ADDRESS)) {
300 sc->sc_dv_addr = req.wValue[0] & 0x7F;
301 /* must write address before ZLP */
302 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
304 sc->sc_dv_addr = 0xFF;
307 /* Clear SETUP packet interrupt and all other previous interrupts */
308 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
309 return (0); /* complete */
312 /* abort any ongoing transfer */
313 if (!td->did_stall) {
314 DPRINTFN(5, "stalling\n");
315 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
317 ATMEGA_UECONX_STALLRQ);
320 if (temp & ATMEGA_UEINTX_RXSTPI) {
321 /* clear SETUP packet interrupt */
322 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
324 /* we only want to know if there is a SETUP packet */
325 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
326 return (1); /* not complete */
330 atmegadci_data_rx(struct atmegadci_td *td)
332 struct atmegadci_softc *sc;
333 struct usb_page_search buf_res;
339 to = 3; /* don't loop forever! */
342 /* get pointer to softc */
343 sc = ATMEGA_PC2SC(td->pc);
345 /* select endpoint number */
346 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
349 /* check if any of the FIFO banks have data */
350 /* check endpoint status */
351 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
353 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
355 if (temp & ATMEGA_UEINTX_RXSTPI) {
356 if (td->remainder == 0) {
358 * We are actually complete and have
359 * received the next SETUP
361 DPRINTFN(5, "faking complete\n");
362 return (0); /* complete */
365 * USB Host Aborted the transfer.
368 return (0); /* complete */
371 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
372 ATMEGA_UEINTX_RXOUTI))) {
376 /* get the packet byte count */
378 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
379 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
381 /* mask away undefined bits */
384 /* verify the packet byte count */
385 if (count != td->max_packet_size) {
386 if (count < td->max_packet_size) {
387 /* we have a short packet */
391 /* invalid USB packet */
393 return (0); /* we are complete */
396 /* verify the packet byte count */
397 if (count > td->remainder) {
398 /* invalid USB packet */
400 return (0); /* we are complete */
403 usbd_get_page(td->pc, td->offset, &buf_res);
405 /* get correct length */
406 if (buf_res.length > count) {
407 buf_res.length = count;
410 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
411 buf_res.buffer, buf_res.length);
413 /* update counters */
414 count -= buf_res.length;
415 td->offset += buf_res.length;
416 td->remainder -= buf_res.length;
419 /* clear OUT packet interrupt */
420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
422 /* release FIFO bank */
423 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
425 /* check if we are complete */
426 if ((td->remainder == 0) || got_short) {
428 /* we are complete */
431 /* else need to receive a zero length packet */
437 /* we only want to know if there is a SETUP packet or OUT packet */
438 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
439 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
440 return (1); /* not complete */
444 atmegadci_data_tx(struct atmegadci_td *td)
446 struct atmegadci_softc *sc;
447 struct usb_page_search buf_res;
452 to = 3; /* don't loop forever! */
454 /* get pointer to softc */
455 sc = ATMEGA_PC2SC(td->pc);
457 /* select endpoint number */
458 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
462 /* check endpoint status */
463 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
465 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
467 if (temp & ATMEGA_UEINTX_RXSTPI) {
469 * The current transfer was aborted
473 return (0); /* complete */
476 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
478 /* cannot write any data - a bank is busy */
482 count = td->max_packet_size;
483 if (td->remainder < count) {
484 /* we have a short packet */
486 count = td->remainder;
490 usbd_get_page(td->pc, td->offset, &buf_res);
492 /* get correct length */
493 if (buf_res.length > count) {
494 buf_res.length = count;
497 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
498 buf_res.buffer, buf_res.length);
500 /* update counters */
501 count -= buf_res.length;
502 td->offset += buf_res.length;
503 td->remainder -= buf_res.length;
506 /* clear IN packet interrupt */
507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
509 /* allocate FIFO bank */
510 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
512 /* check remainder */
513 if (td->remainder == 0) {
515 return (0); /* complete */
517 /* else we need to transmit a short packet */
523 /* we only want to know if there is a SETUP packet or free IN packet */
524 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
525 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
526 return (1); /* not complete */
530 atmegadci_data_tx_sync(struct atmegadci_td *td)
532 struct atmegadci_softc *sc;
535 /* get pointer to softc */
536 sc = ATMEGA_PC2SC(td->pc);
538 /* select endpoint number */
539 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
541 /* check endpoint status */
542 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
544 DPRINTFN(5, "temp=0x%02x\n", temp);
546 if (temp & ATMEGA_UEINTX_RXSTPI) {
547 DPRINTFN(5, "faking complete\n");
549 return (0); /* complete */
552 * The control endpoint has only got one bank, so if that bank
553 * is free the packet has been transferred!
555 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
557 /* cannot write any data - a bank is busy */
560 if (sc->sc_dv_addr != 0xFF) {
561 /* set new address */
562 atmegadci_set_address(sc, sc->sc_dv_addr);
564 return (0); /* complete */
567 /* we only want to know if there is a SETUP packet or free IN packet */
568 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
569 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
570 return (1); /* not complete */
574 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
576 struct atmegadci_td *td;
580 td = xfer->td_transfer_cache;
582 if ((td->func) (td)) {
583 /* operation in progress */
586 if (((void *)td) == xfer->td_transfer_last) {
591 } else if (td->remainder > 0) {
593 * We had a short transfer. If there is no alternate
594 * next, stop processing !
601 * Fetch the next transfer descriptor and transfer
602 * some flags to the next transfer descriptor
605 xfer->td_transfer_cache = td;
607 return (1); /* not complete */
610 /* compute all actual lengths */
612 atmegadci_standard_done(xfer);
613 return (0); /* complete */
617 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
619 struct usb_xfer *xfer;
622 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
623 if (!atmegadci_xfer_do_fifo(xfer)) {
624 /* queue has been modified */
631 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
633 DPRINTFN(5, "vbus = %u\n", is_on);
636 if (!sc->sc_flags.status_vbus) {
637 sc->sc_flags.status_vbus = 1;
639 /* complete root HUB interrupt endpoint */
641 atmegadci_root_intr(sc);
644 if (sc->sc_flags.status_vbus) {
645 sc->sc_flags.status_vbus = 0;
646 sc->sc_flags.status_bus_reset = 0;
647 sc->sc_flags.status_suspend = 0;
648 sc->sc_flags.change_suspend = 0;
649 sc->sc_flags.change_connect = 1;
651 /* complete root HUB interrupt endpoint */
653 atmegadci_root_intr(sc);
659 atmegadci_interrupt(struct atmegadci_softc *sc)
663 USB_BUS_LOCK(&sc->sc_bus);
665 /* read interrupt status */
666 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
668 /* clear all set interrupts */
669 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
671 DPRINTFN(14, "UDINT=0x%02x\n", status);
673 /* check for any bus state change interrupts */
674 if (status & ATMEGA_UDINT_EORSTI) {
676 DPRINTFN(5, "end of reset\n");
678 /* set correct state */
679 sc->sc_flags.status_bus_reset = 1;
680 sc->sc_flags.status_suspend = 0;
681 sc->sc_flags.change_suspend = 0;
682 sc->sc_flags.change_connect = 1;
684 /* disable resume interrupt */
685 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
687 ATMEGA_UDINT_EORSTE);
689 /* complete root HUB interrupt endpoint */
690 atmegadci_root_intr(sc);
693 * If resume and suspend is set at the same time we interpret
694 * that like RESUME. Resume is set when there is at least 3
695 * milliseconds of inactivity on the USB BUS.
697 if (status & ATMEGA_UDINT_WAKEUPI) {
699 DPRINTFN(5, "resume interrupt\n");
701 if (sc->sc_flags.status_suspend) {
702 /* update status bits */
703 sc->sc_flags.status_suspend = 0;
704 sc->sc_flags.change_suspend = 1;
706 /* disable resume interrupt */
707 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
709 ATMEGA_UDINT_EORSTE);
711 /* complete root HUB interrupt endpoint */
712 atmegadci_root_intr(sc);
714 } else if (status & ATMEGA_UDINT_SUSPI) {
716 DPRINTFN(5, "suspend interrupt\n");
718 if (!sc->sc_flags.status_suspend) {
719 /* update status bits */
720 sc->sc_flags.status_suspend = 1;
721 sc->sc_flags.change_suspend = 1;
723 /* disable suspend interrupt */
724 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
725 ATMEGA_UDINT_WAKEUPE |
726 ATMEGA_UDINT_EORSTE);
728 /* complete root HUB interrupt endpoint */
729 atmegadci_root_intr(sc);
733 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
735 /* clear all set interrupts */
736 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
738 if (status & ATMEGA_USBINT_VBUSTI) {
741 DPRINTFN(5, "USBINT=0x%02x\n", status);
743 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
744 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
746 /* check for any endpoint interrupts */
747 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
748 /* the hardware will clear the UEINT bits automatically */
751 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
753 atmegadci_interrupt_poll(sc);
755 USB_BUS_UNLOCK(&sc->sc_bus);
759 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
761 struct atmegadci_td *td;
763 /* get current Transfer Descriptor */
767 /* prepare for next TD */
768 temp->td_next = td->obj_next;
770 /* fill out the Transfer Descriptor */
771 td->func = temp->func;
773 td->offset = temp->offset;
774 td->remainder = temp->len;
776 td->did_stall = temp->did_stall;
777 td->short_pkt = temp->short_pkt;
778 td->alt_next = temp->setup_alt_next;
782 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
784 struct atmegadci_std_temp temp;
785 struct atmegadci_softc *sc;
786 struct atmegadci_td *td;
791 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
792 xfer->address, UE_GET_ADDR(xfer->endpointno),
793 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
795 temp.max_frame_size = xfer->max_frame_size;
797 td = xfer->td_start[0];
798 xfer->td_transfer_first = td;
799 xfer->td_transfer_cache = td;
805 temp.td_next = xfer->td_start[0];
807 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
808 temp.did_stall = !xfer->flags_int.control_stall;
810 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
811 ep_no = (xfer->endpointno & UE_ADDR);
813 /* check if we should prepend a setup message */
815 if (xfer->flags_int.control_xfr) {
816 if (xfer->flags_int.control_hdr) {
818 temp.func = &atmegadci_setup_rx;
819 temp.len = xfer->frlengths[0];
820 temp.pc = xfer->frbuffers + 0;
821 temp.short_pkt = temp.len ? 1 : 0;
822 /* check for last frame */
823 if (xfer->nframes == 1) {
824 /* no STATUS stage yet, SETUP is last */
825 if (xfer->flags_int.control_act)
826 temp.setup_alt_next = 0;
829 atmegadci_setup_standard_chain_sub(&temp);
836 if (x != xfer->nframes) {
837 if (xfer->endpointno & UE_DIR_IN) {
838 temp.func = &atmegadci_data_tx;
841 temp.func = &atmegadci_data_rx;
845 /* setup "pc" pointer */
846 temp.pc = xfer->frbuffers + x;
850 while (x != xfer->nframes) {
852 /* DATA0 / DATA1 message */
854 temp.len = xfer->frlengths[x];
858 if (x == xfer->nframes) {
859 if (xfer->flags_int.control_xfr) {
860 if (xfer->flags_int.control_act) {
861 temp.setup_alt_next = 0;
864 temp.setup_alt_next = 0;
869 /* make sure that we send an USB packet */
875 /* regular data transfer */
877 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
880 atmegadci_setup_standard_chain_sub(&temp);
882 if (xfer->flags_int.isochronous_xfr) {
883 temp.offset += temp.len;
885 /* get next Page Cache pointer */
886 temp.pc = xfer->frbuffers + x;
890 if (xfer->flags_int.control_xfr) {
892 /* always setup a valid "pc" pointer for status and sync */
893 temp.pc = xfer->frbuffers + 0;
896 temp.setup_alt_next = 0;
898 /* check if we need to sync */
900 /* we need a SYNC point after TX */
901 temp.func = &atmegadci_data_tx_sync;
902 atmegadci_setup_standard_chain_sub(&temp);
905 /* check if we should append a status stage */
906 if (!xfer->flags_int.control_act) {
909 * Send a DATA1 message and invert the current
910 * endpoint direction.
912 if (xfer->endpointno & UE_DIR_IN) {
913 temp.func = &atmegadci_data_rx;
916 temp.func = &atmegadci_data_tx;
920 atmegadci_setup_standard_chain_sub(&temp);
922 /* we need a SYNC point after TX */
923 temp.func = &atmegadci_data_tx_sync;
924 atmegadci_setup_standard_chain_sub(&temp);
928 /* must have at least one frame! */
930 xfer->td_transfer_last = td;
934 atmegadci_timeout(void *arg)
936 struct usb_xfer *xfer = arg;
938 DPRINTF("xfer=%p\n", xfer);
940 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
942 /* transfer is transferred */
943 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
947 atmegadci_start_standard_chain(struct usb_xfer *xfer)
951 /* poll one time - will turn on interrupts */
952 if (atmegadci_xfer_do_fifo(xfer)) {
954 /* put transfer on interrupt queue */
955 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
957 /* start timeout, if any */
958 if (xfer->timeout != 0) {
959 usbd_transfer_timeout_ms(xfer,
960 &atmegadci_timeout, xfer->timeout);
966 atmegadci_root_intr(struct atmegadci_softc *sc)
970 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
973 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
975 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
976 sizeof(sc->sc_hub_idata));
980 atmegadci_standard_done_sub(struct usb_xfer *xfer)
982 struct atmegadci_td *td;
988 td = xfer->td_transfer_cache;
993 if (xfer->aframes != xfer->nframes) {
995 * Verify the length and subtract
996 * the remainder from "frlengths[]":
998 if (len > xfer->frlengths[xfer->aframes]) {
1001 xfer->frlengths[xfer->aframes] -= len;
1004 /* Check for transfer error */
1006 /* the transfer is finished */
1011 /* Check for short transfer */
1013 if (xfer->flags_int.short_frames_ok) {
1014 /* follow alt next */
1021 /* the transfer is finished */
1029 /* this USB frame is complete */
1035 /* update transfer cache */
1037 xfer->td_transfer_cache = td;
1040 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1044 atmegadci_standard_done(struct usb_xfer *xfer)
1046 usb_error_t err = 0;
1048 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1049 xfer, xfer->endpoint);
1053 xfer->td_transfer_cache = xfer->td_transfer_first;
1055 if (xfer->flags_int.control_xfr) {
1057 if (xfer->flags_int.control_hdr) {
1059 err = atmegadci_standard_done_sub(xfer);
1063 if (xfer->td_transfer_cache == NULL) {
1067 while (xfer->aframes != xfer->nframes) {
1069 err = atmegadci_standard_done_sub(xfer);
1072 if (xfer->td_transfer_cache == NULL) {
1077 if (xfer->flags_int.control_xfr &&
1078 !xfer->flags_int.control_act) {
1080 err = atmegadci_standard_done_sub(xfer);
1083 atmegadci_device_done(xfer, err);
1086 /*------------------------------------------------------------------------*
1087 * atmegadci_device_done
1089 * NOTE: this function can be called more than one time on the
1090 * same USB transfer!
1091 *------------------------------------------------------------------------*/
1093 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1095 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1098 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1100 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1101 xfer, xfer->endpoint, error);
1103 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1104 ep_no = (xfer->endpointno & UE_ADDR);
1106 /* select endpoint number */
1107 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1109 /* disable endpoint interrupt */
1110 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1112 DPRINTFN(15, "disabled interrupts!\n");
1114 /* dequeue transfer and start next transfer */
1115 usbd_transfer_done(xfer, error);
1119 atmegadci_xfer_stall(struct usb_xfer *xfer)
1121 atmegadci_device_done(xfer, USB_ERR_STALLED);
1125 atmegadci_set_stall(struct usb_device *udev,
1126 struct usb_endpoint *ep, uint8_t *did_stall)
1128 struct atmegadci_softc *sc;
1131 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1133 DPRINTFN(5, "endpoint=%p\n", ep);
1135 sc = ATMEGA_BUS2SC(udev->bus);
1136 /* get endpoint number */
1137 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1138 /* select endpoint number */
1139 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1141 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1142 ATMEGA_UECONX_EPEN |
1143 ATMEGA_UECONX_STALLRQ);
1147 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1148 uint8_t ep_type, uint8_t ep_dir)
1152 if (ep_type == UE_CONTROL) {
1153 /* clearing stall is not needed */
1156 /* select endpoint number */
1157 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1159 /* set endpoint reset */
1160 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1162 /* clear endpoint reset */
1163 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1166 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1167 ATMEGA_UECONX_EPEN |
1168 ATMEGA_UECONX_STALLRQ);
1170 /* reset data toggle */
1171 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1172 ATMEGA_UECONX_EPEN |
1173 ATMEGA_UECONX_RSTDT);
1176 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1177 ATMEGA_UECONX_EPEN |
1178 ATMEGA_UECONX_STALLRQC);
1181 if (ep_type == UE_BULK) {
1182 temp = ATMEGA_UECFG0X_EPTYPE2;
1183 } else if (ep_type == UE_INTERRUPT) {
1184 temp = ATMEGA_UECFG0X_EPTYPE3;
1186 temp = ATMEGA_UECFG0X_EPTYPE1;
1188 if (ep_dir & UE_DIR_IN) {
1189 temp |= ATMEGA_UECFG0X_EPDIR;
1191 /* two banks, 64-bytes wMaxPacket */
1192 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1193 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1194 ATMEGA_UECFG1X_ALLOC |
1195 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1196 ATMEGA_UECFG1X_EPSIZE(3));
1198 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1199 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1200 device_printf(sc->sc_bus.bdev,
1201 "Chip rejected configuration\n");
1207 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1209 struct atmegadci_softc *sc;
1210 struct usb_endpoint_descriptor *ed;
1212 DPRINTFN(5, "endpoint=%p\n", ep);
1214 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1217 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1222 sc = ATMEGA_BUS2SC(udev->bus);
1224 /* get endpoint descriptor */
1227 /* reset endpoint */
1228 atmegadci_clear_stall_sub(sc,
1229 (ed->bEndpointAddress & UE_ADDR),
1230 (ed->bmAttributes & UE_XFERTYPE),
1231 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1235 atmegadci_init(struct atmegadci_softc *sc)
1241 /* set up the bus structure */
1242 sc->sc_bus.usbrev = USB_REV_1_1;
1243 sc->sc_bus.methods = &atmegadci_bus_methods;
1245 USB_BUS_LOCK(&sc->sc_bus);
1247 /* make sure USB is enabled */
1248 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1249 ATMEGA_USBCON_USBE |
1250 ATMEGA_USBCON_FRZCLK);
1252 /* enable USB PAD regulator */
1253 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1254 ATMEGA_UHWCON_UVREGE |
1255 ATMEGA_UHWCON_UIMOD);
1257 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1258 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1260 /* wait for PLL to lock */
1261 for (n = 0; n != 20; n++) {
1262 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1264 /* wait a little bit for PLL to start */
1265 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1268 /* make sure USB is enabled */
1269 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1270 ATMEGA_USBCON_USBE |
1271 ATMEGA_USBCON_OTGPADE |
1272 ATMEGA_USBCON_VBUSTE);
1274 /* turn on clocks */
1275 (sc->sc_clocks_on) (&sc->sc_bus);
1277 /* make sure device is re-enumerated */
1278 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1280 /* wait a little for things to stabilise */
1281 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1283 /* enable interrupts */
1284 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1285 ATMEGA_UDINT_SUSPE |
1286 ATMEGA_UDINT_EORSTE);
1288 /* reset all endpoints */
1289 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1290 (1 << ATMEGA_EP_MAX) - 1);
1293 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1295 /* disable all endpoints */
1296 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1298 /* select endpoint */
1299 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1301 /* disable endpoint interrupt */
1302 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1304 /* disable endpoint */
1305 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1308 /* turn off clocks */
1310 atmegadci_clocks_off(sc);
1312 /* read initial VBUS state */
1314 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1315 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1317 USB_BUS_UNLOCK(&sc->sc_bus);
1319 /* catch any lost interrupts */
1321 atmegadci_do_poll(&sc->sc_bus);
1323 return (0); /* success */
1327 atmegadci_uninit(struct atmegadci_softc *sc)
1329 USB_BUS_LOCK(&sc->sc_bus);
1331 /* turn on clocks */
1332 (sc->sc_clocks_on) (&sc->sc_bus);
1334 /* disable interrupts */
1335 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1337 /* reset all endpoints */
1338 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1339 (1 << ATMEGA_EP_MAX) - 1);
1342 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1344 sc->sc_flags.port_powered = 0;
1345 sc->sc_flags.status_vbus = 0;
1346 sc->sc_flags.status_bus_reset = 0;
1347 sc->sc_flags.status_suspend = 0;
1348 sc->sc_flags.change_suspend = 0;
1349 sc->sc_flags.change_connect = 1;
1351 atmegadci_pull_down(sc);
1352 atmegadci_clocks_off(sc);
1354 /* disable USB PAD regulator */
1355 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1357 USB_BUS_UNLOCK(&sc->sc_bus);
1361 atmegadci_suspend(struct atmegadci_softc *sc)
1367 atmegadci_resume(struct atmegadci_softc *sc)
1373 atmegadci_do_poll(struct usb_bus *bus)
1375 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1377 USB_BUS_LOCK(&sc->sc_bus);
1378 atmegadci_interrupt_poll(sc);
1379 USB_BUS_UNLOCK(&sc->sc_bus);
1382 /*------------------------------------------------------------------------*
1383 * at91dci bulk support
1384 * at91dci control support
1385 * at91dci interrupt support
1386 *------------------------------------------------------------------------*/
1388 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1394 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1396 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1400 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1406 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1409 atmegadci_setup_standard_chain(xfer);
1410 atmegadci_start_standard_chain(xfer);
1413 struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1415 .open = atmegadci_device_non_isoc_open,
1416 .close = atmegadci_device_non_isoc_close,
1417 .enter = atmegadci_device_non_isoc_enter,
1418 .start = atmegadci_device_non_isoc_start,
1421 /*------------------------------------------------------------------------*
1422 * at91dci full speed isochronous support
1423 *------------------------------------------------------------------------*/
1425 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1431 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1433 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1437 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1439 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1443 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1444 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1446 /* get the current frame index */
1449 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1450 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1452 nframes &= ATMEGA_FRAME_MASK;
1455 * check if the frame index is within the window where the frames
1458 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1460 if ((xfer->endpoint->is_synced == 0) ||
1461 (temp < xfer->nframes)) {
1463 * If there is data underflow or the pipe queue is
1464 * empty we schedule the transfer a few frames ahead
1465 * of the current frame position. Else two isochronous
1466 * transfers might overlap.
1468 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1469 xfer->endpoint->is_synced = 1;
1470 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1473 * compute how many milliseconds the insertion is ahead of the
1474 * current frame position:
1476 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1479 * pre-compute when the isochronous transfer will be finished:
1481 xfer->isoc_time_complete =
1482 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1485 /* compute frame number for next insertion */
1486 xfer->endpoint->isoc_next += xfer->nframes;
1489 atmegadci_setup_standard_chain(xfer);
1493 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1495 /* start TD chain */
1496 atmegadci_start_standard_chain(xfer);
1499 struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1501 .open = atmegadci_device_isoc_fs_open,
1502 .close = atmegadci_device_isoc_fs_close,
1503 .enter = atmegadci_device_isoc_fs_enter,
1504 .start = atmegadci_device_isoc_fs_start,
1507 /*------------------------------------------------------------------------*
1508 * at91dci root control support
1509 *------------------------------------------------------------------------*
1510 * Simulate a hardware HUB by handling all the necessary requests.
1511 *------------------------------------------------------------------------*/
1513 static const struct usb_device_descriptor atmegadci_devd = {
1514 .bLength = sizeof(struct usb_device_descriptor),
1515 .bDescriptorType = UDESC_DEVICE,
1516 .bcdUSB = {0x00, 0x02},
1517 .bDeviceClass = UDCLASS_HUB,
1518 .bDeviceSubClass = UDSUBCLASS_HUB,
1519 .bDeviceProtocol = UDPROTO_FSHUB,
1520 .bMaxPacketSize = 64,
1521 .bcdDevice = {0x00, 0x01},
1524 .bNumConfigurations = 1,
1527 static const struct atmegadci_config_desc atmegadci_confd = {
1529 .bLength = sizeof(struct usb_config_descriptor),
1530 .bDescriptorType = UDESC_CONFIG,
1531 .wTotalLength[0] = sizeof(atmegadci_confd),
1533 .bConfigurationValue = 1,
1534 .iConfiguration = 0,
1535 .bmAttributes = UC_SELF_POWERED,
1539 .bLength = sizeof(struct usb_interface_descriptor),
1540 .bDescriptorType = UDESC_INTERFACE,
1542 .bInterfaceClass = UICLASS_HUB,
1543 .bInterfaceSubClass = UISUBCLASS_HUB,
1544 .bInterfaceProtocol = 0,
1547 .bLength = sizeof(struct usb_endpoint_descriptor),
1548 .bDescriptorType = UDESC_ENDPOINT,
1549 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1550 .bmAttributes = UE_INTERRUPT,
1551 .wMaxPacketSize[0] = 8,
1556 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1558 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1559 .bDescLength = sizeof(atmegadci_hubd),
1560 .bDescriptorType = UDESC_HUB,
1562 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1563 .bPwrOn2PwrGood = 50,
1564 .bHubContrCurrent = 0,
1565 .DeviceRemovable = {0}, /* port is removable */
1568 #define STRING_VENDOR \
1571 #define STRING_PRODUCT \
1572 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1574 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1575 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1578 atmegadci_roothub_exec(struct usb_device *udev,
1579 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1581 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1589 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1592 ptr = (const void *)&sc->sc_hub_temp;
1596 value = UGETW(req->wValue);
1597 index = UGETW(req->wIndex);
1599 /* demultiplex the control request */
1601 switch (req->bmRequestType) {
1602 case UT_READ_DEVICE:
1603 switch (req->bRequest) {
1604 case UR_GET_DESCRIPTOR:
1605 goto tr_handle_get_descriptor;
1607 goto tr_handle_get_config;
1609 goto tr_handle_get_status;
1615 case UT_WRITE_DEVICE:
1616 switch (req->bRequest) {
1617 case UR_SET_ADDRESS:
1618 goto tr_handle_set_address;
1620 goto tr_handle_set_config;
1621 case UR_CLEAR_FEATURE:
1622 goto tr_valid; /* nop */
1623 case UR_SET_DESCRIPTOR:
1624 goto tr_valid; /* nop */
1625 case UR_SET_FEATURE:
1631 case UT_WRITE_ENDPOINT:
1632 switch (req->bRequest) {
1633 case UR_CLEAR_FEATURE:
1634 switch (UGETW(req->wValue)) {
1635 case UF_ENDPOINT_HALT:
1636 goto tr_handle_clear_halt;
1637 case UF_DEVICE_REMOTE_WAKEUP:
1638 goto tr_handle_clear_wakeup;
1643 case UR_SET_FEATURE:
1644 switch (UGETW(req->wValue)) {
1645 case UF_ENDPOINT_HALT:
1646 goto tr_handle_set_halt;
1647 case UF_DEVICE_REMOTE_WAKEUP:
1648 goto tr_handle_set_wakeup;
1653 case UR_SYNCH_FRAME:
1654 goto tr_valid; /* nop */
1660 case UT_READ_ENDPOINT:
1661 switch (req->bRequest) {
1663 goto tr_handle_get_ep_status;
1669 case UT_WRITE_INTERFACE:
1670 switch (req->bRequest) {
1671 case UR_SET_INTERFACE:
1672 goto tr_handle_set_interface;
1673 case UR_CLEAR_FEATURE:
1674 goto tr_valid; /* nop */
1675 case UR_SET_FEATURE:
1681 case UT_READ_INTERFACE:
1682 switch (req->bRequest) {
1683 case UR_GET_INTERFACE:
1684 goto tr_handle_get_interface;
1686 goto tr_handle_get_iface_status;
1692 case UT_WRITE_CLASS_INTERFACE:
1693 case UT_WRITE_VENDOR_INTERFACE:
1697 case UT_READ_CLASS_INTERFACE:
1698 case UT_READ_VENDOR_INTERFACE:
1702 case UT_WRITE_CLASS_DEVICE:
1703 switch (req->bRequest) {
1704 case UR_CLEAR_FEATURE:
1706 case UR_SET_DESCRIPTOR:
1707 case UR_SET_FEATURE:
1714 case UT_WRITE_CLASS_OTHER:
1715 switch (req->bRequest) {
1716 case UR_CLEAR_FEATURE:
1717 goto tr_handle_clear_port_feature;
1718 case UR_SET_FEATURE:
1719 goto tr_handle_set_port_feature;
1720 case UR_CLEAR_TT_BUFFER:
1730 case UT_READ_CLASS_OTHER:
1731 switch (req->bRequest) {
1732 case UR_GET_TT_STATE:
1733 goto tr_handle_get_tt_state;
1735 goto tr_handle_get_port_status;
1741 case UT_READ_CLASS_DEVICE:
1742 switch (req->bRequest) {
1743 case UR_GET_DESCRIPTOR:
1744 goto tr_handle_get_class_descriptor;
1746 goto tr_handle_get_class_status;
1757 tr_handle_get_descriptor:
1758 switch (value >> 8) {
1763 len = sizeof(atmegadci_devd);
1764 ptr = (const void *)&atmegadci_devd;
1770 len = sizeof(atmegadci_confd);
1771 ptr = (const void *)&atmegadci_confd;
1774 switch (value & 0xff) {
1775 case 0: /* Language table */
1776 len = sizeof(usb_string_lang_en);
1777 ptr = (const void *)&usb_string_lang_en;
1780 case 1: /* Vendor */
1781 len = sizeof(atmegadci_vendor);
1782 ptr = (const void *)&atmegadci_vendor;
1785 case 2: /* Product */
1786 len = sizeof(atmegadci_product);
1787 ptr = (const void *)&atmegadci_product;
1798 tr_handle_get_config:
1800 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1803 tr_handle_get_status:
1805 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1808 tr_handle_set_address:
1809 if (value & 0xFF00) {
1812 sc->sc_rt_addr = value;
1815 tr_handle_set_config:
1819 sc->sc_conf = value;
1822 tr_handle_get_interface:
1824 sc->sc_hub_temp.wValue[0] = 0;
1827 tr_handle_get_tt_state:
1828 tr_handle_get_class_status:
1829 tr_handle_get_iface_status:
1830 tr_handle_get_ep_status:
1832 USETW(sc->sc_hub_temp.wValue, 0);
1836 tr_handle_set_interface:
1837 tr_handle_set_wakeup:
1838 tr_handle_clear_wakeup:
1839 tr_handle_clear_halt:
1842 tr_handle_clear_port_feature:
1846 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1849 case UHF_PORT_SUSPEND:
1850 atmegadci_wakeup_peer(sc);
1853 case UHF_PORT_ENABLE:
1854 sc->sc_flags.port_enabled = 0;
1858 case UHF_PORT_INDICATOR:
1859 case UHF_C_PORT_ENABLE:
1860 case UHF_C_PORT_OVER_CURRENT:
1861 case UHF_C_PORT_RESET:
1864 case UHF_PORT_POWER:
1865 sc->sc_flags.port_powered = 0;
1866 atmegadci_pull_down(sc);
1867 atmegadci_clocks_off(sc);
1869 case UHF_C_PORT_CONNECTION:
1870 /* clear connect change flag */
1871 sc->sc_flags.change_connect = 0;
1873 if (!sc->sc_flags.status_bus_reset) {
1874 /* we are not connected */
1878 /* configure the control endpoint */
1880 /* select endpoint number */
1881 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1883 /* set endpoint reset */
1884 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1886 /* clear endpoint reset */
1887 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1889 /* enable and stall endpoint */
1890 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1891 ATMEGA_UECONX_EPEN |
1892 ATMEGA_UECONX_STALLRQ);
1894 /* one bank, 64-bytes wMaxPacket */
1895 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1896 ATMEGA_UECFG0X_EPTYPE0);
1897 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1898 ATMEGA_UECFG1X_ALLOC |
1899 ATMEGA_UECFG1X_EPBK0 |
1900 ATMEGA_UECFG1X_EPSIZE(3));
1902 /* check valid config */
1903 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1904 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1905 device_printf(sc->sc_bus.bdev,
1906 "Chip rejected EP0 configuration\n");
1909 case UHF_C_PORT_SUSPEND:
1910 sc->sc_flags.change_suspend = 0;
1913 err = USB_ERR_IOERROR;
1918 tr_handle_set_port_feature:
1922 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1925 case UHF_PORT_ENABLE:
1926 sc->sc_flags.port_enabled = 1;
1928 case UHF_PORT_SUSPEND:
1929 case UHF_PORT_RESET:
1931 case UHF_PORT_INDICATOR:
1934 case UHF_PORT_POWER:
1935 sc->sc_flags.port_powered = 1;
1938 err = USB_ERR_IOERROR;
1943 tr_handle_get_port_status:
1945 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1950 if (sc->sc_flags.status_vbus) {
1951 atmegadci_clocks_on(sc);
1952 atmegadci_pull_up(sc);
1954 atmegadci_pull_down(sc);
1955 atmegadci_clocks_off(sc);
1958 /* Select FULL-speed and Device Side Mode */
1960 value = UPS_PORT_MODE_DEVICE;
1962 if (sc->sc_flags.port_powered) {
1963 value |= UPS_PORT_POWER;
1965 if (sc->sc_flags.port_enabled) {
1966 value |= UPS_PORT_ENABLED;
1968 if (sc->sc_flags.status_vbus &&
1969 sc->sc_flags.status_bus_reset) {
1970 value |= UPS_CURRENT_CONNECT_STATUS;
1972 if (sc->sc_flags.status_suspend) {
1973 value |= UPS_SUSPEND;
1975 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1979 if (sc->sc_flags.change_connect) {
1980 value |= UPS_C_CONNECT_STATUS;
1982 if (sc->sc_flags.change_suspend) {
1983 value |= UPS_C_SUSPEND;
1985 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1986 len = sizeof(sc->sc_hub_temp.ps);
1989 tr_handle_get_class_descriptor:
1993 ptr = (const void *)&atmegadci_hubd;
1994 len = sizeof(atmegadci_hubd);
1998 err = USB_ERR_STALLED;
2007 atmegadci_xfer_setup(struct usb_setup_params *parm)
2009 const struct usb_hw_ep_profile *pf;
2010 struct atmegadci_softc *sc;
2011 struct usb_xfer *xfer;
2017 sc = ATMEGA_BUS2SC(parm->udev->bus);
2018 xfer = parm->curr_xfer;
2021 * NOTE: This driver does not use any of the parameters that
2022 * are computed from the following values. Just set some
2023 * reasonable dummies:
2025 parm->hc_max_packet_size = 0x500;
2026 parm->hc_max_packet_count = 1;
2027 parm->hc_max_frame_size = 0x500;
2029 usbd_transfer_setup_sub(parm);
2032 * compute maximum number of TDs
2034 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2036 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2040 ntd = xfer->nframes + 1 /* SYNC */ ;
2044 * check if "usbd_transfer_setup_sub" set an error
2050 * allocate transfer descriptors
2057 ep_no = xfer->endpointno & UE_ADDR;
2058 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2061 /* should not happen */
2062 parm->err = USB_ERR_INVAL;
2067 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2069 for (n = 0; n != ntd; n++) {
2071 struct atmegadci_td *td;
2075 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2078 td->max_packet_size = xfer->max_packet_size;
2080 if (pf->support_multi_buffer) {
2081 td->support_multi_buffer = 1;
2083 td->obj_next = last_obj;
2087 parm->size[0] += sizeof(*td);
2090 xfer->td_start[0] = last_obj;
2094 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2100 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2101 struct usb_endpoint *ep)
2103 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2105 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2107 edesc->bEndpointAddress, udev->flags.usb_mode,
2108 sc->sc_rt_addr, udev->device_index);
2110 if (udev->device_index != sc->sc_rt_addr) {
2112 if (udev->speed != USB_SPEED_FULL) {
2116 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2117 ep->methods = &atmegadci_device_isoc_fs_methods;
2119 ep->methods = &atmegadci_device_non_isoc_methods;
2124 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2126 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2129 case USB_HW_POWER_SUSPEND:
2130 atmegadci_suspend(sc);
2132 case USB_HW_POWER_SHUTDOWN:
2133 atmegadci_uninit(sc);
2135 case USB_HW_POWER_RESUME:
2136 atmegadci_resume(sc);
2143 struct usb_bus_methods atmegadci_bus_methods =
2145 .endpoint_init = &atmegadci_ep_init,
2146 .xfer_setup = &atmegadci_xfer_setup,
2147 .xfer_unsetup = &atmegadci_xfer_unsetup,
2148 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2149 .xfer_stall = &atmegadci_xfer_stall,
2150 .set_stall = &atmegadci_set_stall,
2151 .clear_stall = &atmegadci_clear_stall,
2152 .roothub_exec = &atmegadci_roothub_exec,
2153 .xfer_poll = &atmegadci_do_poll,
2154 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,