sys/dev/usb/controller/dwc_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2015 Daisuke Aoyama. All rights reserved.
   4  * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved.
   5  * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the DesignWare series USB 2.0 OTG
  31  * Controller.
  32  */
  33
  34 /*
  35  * LIMITATION: Drivers must be bound to all OUT endpoints in the
  36  * active configuration for this driver to work properly. Blocking any
  37  * OUT endpoint will block all OUT endpoints including the control
  38  * endpoint. Usually this is not a problem.
  39  */
  40
  41 /*
  42  * NOTE: Writing to non-existing registers appears to cause an
  43  * internal reset.
  44  */
  45
  46 #ifdef USB_GLOBAL_INCLUDE_FILE
  47 #include USB_GLOBAL_INCLUDE_FILE
  48 #else
  49 #include <sys/stdint.h>
  50 #include <sys/stddef.h>
  51 #include <sys/param.h>
  52 #include <sys/queue.h>
  53 #include <sys/types.h>
  54 #include <sys/systm.h>
  55 #include <sys/kernel.h>
  56 #include <sys/bus.h>
  57 #include <sys/module.h>
  58 #include <sys/lock.h>
  59 #include <sys/mutex.h>
  60 #include <sys/condvar.h>
  61 #include <sys/sysctl.h>
  62 #include <sys/sx.h>
  63 #include <sys/unistd.h>
  64 #include <sys/callout.h>
  65 #include <sys/malloc.h>
  66 #include <sys/priv.h>
  67
  68 #include <dev/usb/usb.h>
  69 #include <dev/usb/usbdi.h>
  70
  71 #define USB_DEBUG_VAR dwc_otg_debug
  72
  73 #include <dev/usb/usb_core.h>
  74 #include <dev/usb/usb_debug.h>
  75 #include <dev/usb/usb_busdma.h>
  76 #include <dev/usb/usb_process.h>
  77 #include <dev/usb/usb_transfer.h>
  78 #include <dev/usb/usb_device.h>
  79 #include <dev/usb/usb_hub.h>
  80 #include <dev/usb/usb_util.h>
  81
  82 #include <dev/usb/usb_controller.h>
  83 #include <dev/usb/usb_bus.h>
  84 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  85
  86 #include <dev/usb/controller/dwc_otg.h>
  87 #include <dev/usb/controller/dwc_otgreg.h>
  88
  89 #define DWC_OTG_BUS2SC(bus) \
  90    ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \
  91     ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus))))
  92
  93 #define DWC_OTG_PC2UDEV(pc) \
  94    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  95
  96 #define DWC_OTG_MSK_GINT_THREAD_IRQ                             \
  97    (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT |        \
  98    GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK |      \
  99    GINTSTS_SESSREQINT)
 100
 101 #define DWC_OTG_PHY_ULPI 0
 102 #define DWC_OTG_PHY_HSIC 1
 103 #define DWC_OTG_PHY_INTERNAL 2
 104
 105 #ifndef DWC_OTG_PHY_DEFAULT
 106 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
 107 #endif
 108
 109 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
 110
 111 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG");
 112 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
 113     &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL");
 114 TUNABLE_INT("hw.usb.dwc_otg.phy_type", &dwc_otg_phy_type);
 115
 116 #ifdef USB_DEBUG
 117 static int dwc_otg_debug;
 118
 119 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW,
 120     &dwc_otg_debug, 0, "DWC OTG debug level");
 121 #endif
 122
 123 #define DWC_OTG_INTR_ENDPT 1
 124
 125 /* prototypes */
 126
 127 struct usb_bus_methods dwc_otg_bus_methods;
 128 struct usb_pipe_methods dwc_otg_device_non_isoc_methods;
 129 struct usb_pipe_methods dwc_otg_device_isoc_methods;
 130
 131 static dwc_otg_cmd_t dwc_otg_setup_rx;
 132 static dwc_otg_cmd_t dwc_otg_data_rx;
 133 static dwc_otg_cmd_t dwc_otg_data_tx;
 134 static dwc_otg_cmd_t dwc_otg_data_tx_sync;
 135
 136 static dwc_otg_cmd_t dwc_otg_host_setup_tx;
 137 static dwc_otg_cmd_t dwc_otg_host_data_tx;
 138 static dwc_otg_cmd_t dwc_otg_host_data_rx;
 139
 140 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t);
 141 static void dwc_otg_do_poll(struct usb_bus *);
 142 static void dwc_otg_standard_done(struct usb_xfer *);
 143 static void dwc_otg_root_intr(struct dwc_otg_softc *);
 144 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *);
 145
 146 /*
 147  * Here is a configuration that the chip supports.
 148  */
 149 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = {
 150
 151         [0] = {
 152                 .max_in_frame_size = 64,/* fixed */
 153                 .max_out_frame_size = 64,       /* fixed */
 154                 .is_simplex = 1,
 155                 .support_control = 1,
 156         }
 157 };
 158
 159 static void
 160 dwc_otg_get_hw_ep_profile(struct usb_device *udev,
 161     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 162 {
 163         struct dwc_otg_softc *sc;
 164
 165         sc = DWC_OTG_BUS2SC(udev->bus);
 166
 167         if (ep_addr < sc->sc_dev_ep_max)
 168                 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
 169         else
 170                 *ppf = NULL;
 171 }
 172
 173 static void
 174 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
 175     uint32_t offset, uint32_t fifo, uint32_t count)
 176 {
 177         uint32_t temp;
 178
 179         /* round down length to nearest 4-bytes */
 180         temp = count & ~3;
 181
 182         /* check if we can write the data directly */
 183         if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
 184                 struct usb_page_search buf_res;
 185
 186                 /* pre-subtract length */
 187                 count -= temp;
 188
 189                 /* iterate buffer list */
 190                 do {
 191                         /* get current buffer pointer */
 192                         usbd_get_page(pc, offset, &buf_res);
 193
 194                         if (buf_res.length > temp)
 195                                 buf_res.length = temp;
 196
 197                         /* transfer data into FIFO */
 198                         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 199                             fifo, buf_res.buffer, buf_res.length / 4);
 200
 201                         offset += buf_res.length;
 202                         fifo += buf_res.length;
 203                         temp -= buf_res.length;
 204                 } while (temp != 0);
 205         }
 206
 207         /* check for remainder */
 208         if (count != 0) {
 209                 /* clear topmost word before copy */
 210                 sc->sc_bounce_buffer[(count - 1) / 4] = 0;
 211
 212                 /* copy out data */
 213                 usbd_copy_out(pc, offset,
 214                     sc->sc_bounce_buffer, count);
 215
 216                 /* transfer data into FIFO */
 217                 bus_space_write_region_4(sc->sc_io_tag,
 218                     sc->sc_io_hdl, fifo, sc->sc_bounce_buffer,
 219                     (count + 3) / 4);
 220         }
 221 }
 222
 223 static void
 224 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
 225     uint32_t offset, uint32_t count)
 226 {
 227         uint32_t temp;
 228
 229         /* round down length to nearest 4-bytes */
 230         temp = count & ~3;
 231
 232         /* check if we can read the data directly */
 233         if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
 234                 struct usb_page_search buf_res;
 235
 236                 /* pre-subtract length */
 237                 count -= temp;
 238
 239                 /* iterate buffer list */
 240                 do {
 241                         /* get current buffer pointer */
 242                         usbd_get_page(pc, offset, &buf_res);
 243
 244                         if (buf_res.length > temp)
 245                                 buf_res.length = temp;
 246
 247                         /* transfer data from FIFO */
 248                         bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 249                             sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4);
 250
 251                         offset += buf_res.length;
 252                         sc->sc_current_rx_fifo += buf_res.length;
 253                         sc->sc_current_rx_bytes -= buf_res.length;
 254                         temp -= buf_res.length;
 255                 } while (temp != 0);
 256         }
 257
 258         /* check for remainder */
 259         if (count != 0) {
 260                 /* read data into bounce buffer */
 261                 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 262                         sc->sc_current_rx_fifo,
 263                         sc->sc_bounce_buffer, (count + 3) / 4);
 264
 265                 /* store data into proper buffer */
 266                 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count);
 267
 268                 /* round length up to nearest 4 bytes */
 269                 count = (count + 3) & ~3;
 270
 271                 /* update counters */
 272                 sc->sc_current_rx_bytes -= count;
 273                 sc->sc_current_rx_fifo += count;
 274         }
 275 }
 276
 277 static void
 278 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
 279 {
 280         uint32_t temp;
 281
 282         /* reset FIFO */
 283         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
 284
 285         /* wait for reset to complete */
 286         for (temp = 0; temp != 16; temp++) {
 287                 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
 288                 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
 289                         break;
 290         }
 291 }
 292
 293 static int
 294 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
 295 {
 296         struct dwc_otg_profile *pf;
 297         uint32_t fifo_size;
 298         uint32_t fifo_regs;
 299         uint32_t tx_start;
 300         uint8_t x;
 301
 302         fifo_size = sc->sc_fifo_size;
 303
 304         /*
 305          * NOTE: Reserved fixed size area at end of RAM, which must
 306          * not be allocated to the FIFOs:
 307          */
 308         fifo_regs = 4 * 16;
 309
 310         if (fifo_size < fifo_regs) {
 311                 DPRINTF("Too little FIFO\n");
 312                 return (EINVAL);
 313         }
 314
 315         /* subtract FIFO regs from total once */
 316         fifo_size -= fifo_regs;
 317
 318         /* split equally for IN and OUT */
 319         fifo_size /= 2;
 320
 321         /* Align to 4 bytes boundary (refer to PGM) */
 322         fifo_size &= ~3;
 323
 324         /* set global receive FIFO size */
 325         DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
 326
 327         tx_start = fifo_size;
 328
 329         if (fifo_size < 64) {
 330                 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
 331                 return (EINVAL);
 332         }
 333
 334         if (mode == DWC_MODE_HOST) {
 335
 336                 /* reset active endpoints */
 337                 sc->sc_active_rx_ep = 0;
 338
 339                 /* split equally for periodic and non-periodic */
 340                 fifo_size /= 2;
 341
 342                 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size);
 343
 344                 /* align to 4 bytes boundary */
 345                 fifo_size &= ~3;
 346
 347                 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 348                     ((fifo_size / 4) << 16) |
 349                     (tx_start / 4));
 350
 351                 tx_start += fifo_size;
 352
 353                 for (x = 0; x != sc->sc_host_ch_max; x++) {
 354                         /* enable all host interrupts */
 355                         DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x),
 356                             HCINT_DEFAULT_MASK);
 357                 }
 358
 359                 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ,
 360                     ((fifo_size / 4) << 16) |
 361                     (tx_start / 4));
 362
 363                 /* reset host channel state */
 364                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 365
 366                 /* enable all host channel interrupts */
 367                 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK,
 368                     (1U << sc->sc_host_ch_max) - 1U);
 369
 370                 /* enable proper host channel interrupts */
 371                 sc->sc_irq_mask |= GINTMSK_HCHINTMSK;
 372                 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK;
 373                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 374         }
 375
 376         if (mode == DWC_MODE_DEVICE) {
 377
 378             DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 379                 (0x10 << 16) | (tx_start / 4));
 380             fifo_size -= 0x40;
 381             tx_start += 0x40;
 382
 383             /* setup control endpoint profile */
 384             sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
 385
 386             /* reset active endpoints */
 387             sc->sc_active_rx_ep = 1;
 388
 389             for (x = 1; x != sc->sc_dev_ep_max; x++) {
 390
 391                 pf = sc->sc_hw_ep_profile + x;
 392
 393                 pf->usb.max_out_frame_size = 1024 * 3;
 394                 pf->usb.is_simplex = 0; /* assume duplex */
 395                 pf->usb.support_bulk = 1;
 396                 pf->usb.support_interrupt = 1;
 397                 pf->usb.support_isochronous = 1;
 398                 pf->usb.support_out = 1;
 399
 400                 if (x < sc->sc_dev_in_ep_max) {
 401                         uint32_t limit;
 402
 403                         limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE,
 404                             DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2,
 405                             DWC_OTG_TX_MAX_FIFO_SIZE);
 406
 407                         /* see if there is enough FIFO space */
 408                         if (limit <= fifo_size) {
 409                                 pf->max_buffer = limit;
 410                                 pf->usb.support_in = 1;
 411                         } else {
 412                                 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40);
 413                                 if (limit <= fifo_size) {
 414                                         pf->usb.support_in = 1;
 415                                 } else {
 416                                         pf->usb.is_simplex = 1;
 417                                         limit = 0;
 418                                 }
 419                         }
 420                         /* set FIFO size */
 421                         DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 422                             ((limit / 4) << 16) | (tx_start / 4));
 423                         tx_start += limit;
 424                         fifo_size -= limit;
 425                         pf->usb.max_in_frame_size = limit;
 426                 } else {
 427                         pf->usb.is_simplex = 1;
 428                 }
 429
 430                 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x,
 431                     pf->usb.max_in_frame_size,
 432                     pf->usb.max_out_frame_size);
 433             }
 434
 435             /* enable proper device channel interrupts */
 436             sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK;
 437             sc->sc_irq_mask |= GINTMSK_IEPINTMSK;
 438             DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 439         }
 440
 441         /* reset RX FIFO */
 442         dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
 443
 444         if (mode != DWC_MODE_OTG) {
 445                 /* reset all TX FIFOs */
 446                 dwc_otg_tx_fifo_reset(sc,
 447                     GRSTCTL_TXFIFO(0x10) |
 448                     GRSTCTL_TXFFLSH);
 449         } else {
 450                 /* reset active endpoints */
 451                 sc->sc_active_rx_ep = 0;
 452
 453                 /* reset host channel state */
 454                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 455         }
 456         return (0);
 457 }
 458
 459 static uint8_t
 460 dwc_otg_uses_split(struct usb_device *udev)
 461 {
 462         /*
 463          * When a LOW or FULL speed device is connected directly to
 464          * the USB port we don't use split transactions:
 465          */
 466         return (udev->speed != USB_SPEED_HIGH &&
 467             udev->parent_hs_hub != NULL &&
 468             udev->parent_hs_hub->parent_hub != NULL);
 469 }
 470
 471 static void
 472 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc)
 473 {
 474
 475   /*
 476    * Disabled until further. Assuming that the register is already
 477    * programmed correctly by the boot loader.
 478    */
 479 #if 0
 480         uint32_t temp;
 481
 482         /* setup HOST frame interval register, based on existing value */
 483         temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
 484         if (temp >= 10000)
 485                 temp /= 1000;
 486         else
 487                 temp /= 125;
 488
 489         /* figure out nearest X-tal value */
 490         if (temp >= 54)
 491                 temp = 60;      /* MHz */
 492         else if (temp >= 39)
 493                 temp = 48;      /* MHz */
 494         else
 495                 temp = 30;      /* MHz */
 496
 497         if (sc->sc_flags.status_high_speed)
 498                 temp *= 125;
 499         else
 500                 temp *= 1000;
 501
 502         DPRINTF("HFIR=0x%08x\n", temp);
 503
 504         DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
 505 #endif
 506 }
 507
 508 static void
 509 dwc_otg_clocks_on(struct dwc_otg_softc *sc)
 510 {
 511         if (sc->sc_flags.clocks_off &&
 512             sc->sc_flags.port_powered) {
 513
 514                 DPRINTFN(5, "\n");
 515
 516                 /* TODO - platform specific */
 517
 518                 sc->sc_flags.clocks_off = 0;
 519         }
 520 }
 521
 522 static void
 523 dwc_otg_clocks_off(struct dwc_otg_softc *sc)
 524 {
 525         if (!sc->sc_flags.clocks_off) {
 526
 527                 DPRINTFN(5, "\n");
 528
 529                 /* TODO - platform specific */
 530
 531                 sc->sc_flags.clocks_off = 1;
 532         }
 533 }
 534
 535 static void
 536 dwc_otg_pull_up(struct dwc_otg_softc *sc)
 537 {
 538         uint32_t temp;
 539
 540         /* pullup D+, if possible */
 541
 542         if (!sc->sc_flags.d_pulled_up &&
 543             sc->sc_flags.port_powered) {
 544                 sc->sc_flags.d_pulled_up = 1;
 545
 546                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 547                 temp &= ~DCTL_SFTDISCON;
 548                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 549         }
 550 }
 551
 552 static void
 553 dwc_otg_pull_down(struct dwc_otg_softc *sc)
 554 {
 555         uint32_t temp;
 556
 557         /* pulldown D+, if possible */
 558
 559         if (sc->sc_flags.d_pulled_up) {
 560                 sc->sc_flags.d_pulled_up = 0;
 561
 562                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 563                 temp |= DCTL_SFTDISCON;
 564                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 565         }
 566 }
 567
 568 static void
 569 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc)
 570 {
 571         /* In device mode we don't use the SOF interrupt */
 572         if (sc->sc_flags.status_device_mode != 0)
 573                 return;
 574         /* Ensure the SOF interrupt is not disabled */
 575         sc->sc_needsof = 1;
 576         /* Check if the SOF interrupt is already enabled */
 577         if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
 578                 return;
 579         sc->sc_irq_mask |= GINTMSK_SOFMSK;
 580         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 581 }
 582
 583 static void
 584 dwc_otg_resume_irq(struct dwc_otg_softc *sc)
 585 {
 586         if (sc->sc_flags.status_suspend) {
 587                 /* update status bits */
 588                 sc->sc_flags.status_suspend = 0;
 589                 sc->sc_flags.change_suspend = 1;
 590
 591                 if (sc->sc_flags.status_device_mode) {
 592                         /*
 593                          * Disable resume interrupt and enable suspend
 594                          * interrupt:
 595                          */
 596                         sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
 597                         sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
 598                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 599                 }
 600
 601                 /* complete root HUB interrupt endpoint */
 602                 dwc_otg_root_intr(sc);
 603         }
 604 }
 605
 606 static void
 607 dwc_otg_suspend_irq(struct dwc_otg_softc *sc)
 608 {
 609         if (!sc->sc_flags.status_suspend) {
 610                 /* update status bits */
 611                 sc->sc_flags.status_suspend = 1;
 612                 sc->sc_flags.change_suspend = 1;
 613
 614                 if (sc->sc_flags.status_device_mode) {
 615                         /*
 616                          * Disable suspend interrupt and enable resume
 617                          * interrupt:
 618                          */
 619                         sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
 620                         sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
 621                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 622                 }
 623
 624                 /* complete root HUB interrupt endpoint */
 625                 dwc_otg_root_intr(sc);
 626         }
 627 }
 628
 629 static void
 630 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
 631 {
 632         if (!sc->sc_flags.status_suspend)
 633                 return;
 634
 635         DPRINTFN(5, "Remote wakeup\n");
 636
 637         if (sc->sc_flags.status_device_mode) {
 638                 uint32_t temp;
 639
 640                 /* enable remote wakeup signalling */
 641                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 642                 temp |= DCTL_RMTWKUPSIG;
 643                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 644
 645                 /* Wait 8ms for remote wakeup to complete. */
 646                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 647
 648                 temp &= ~DCTL_RMTWKUPSIG;
 649                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 650         } else {
 651                 /* enable USB port */
 652                 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
 653
 654                 /* wait 10ms */
 655                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
 656
 657                 /* resume port */
 658                 sc->sc_hprt_val |= HPRT_PRTRES;
 659                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 660
 661                 /* Wait 100ms for resume signalling to complete. */
 662                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
 663
 664                 /* clear suspend and resume */
 665                 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
 666                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 667
 668                 /* Wait 4ms */
 669                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
 670         }
 671
 672         /* need to fake resume IRQ */
 673         dwc_otg_resume_irq(sc);
 674 }
 675
 676 static void
 677 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
 678 {
 679         uint32_t temp;
 680
 681         DPRINTFN(5, "addr=%d\n", addr);
 682
 683         temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
 684         temp &= ~DCFG_DEVADDR_SET(0x7F);
 685         temp |= DCFG_DEVADDR_SET(addr);
 686         DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
 687 }
 688
 689 static void
 690 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
 691 {
 692         DPRINTFN(5, "RX status clear\n");
 693
 694         /* enable RX FIFO level interrupt */
 695         sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
 696         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 697
 698         if (sc->sc_current_rx_bytes != 0) {
 699                 /* need to dump remaining data */
 700                 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 701                     sc->sc_current_rx_fifo, sc->sc_bounce_buffer,
 702                     sc->sc_current_rx_bytes / 4);
 703                 /* clear number of active bytes to receive */
 704                 sc->sc_current_rx_bytes = 0;
 705         }
 706         /* clear cached status */
 707         sc->sc_last_rx_status = 0;
 708 }
 709
 710 static void
 711 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
 712 {
 713         uint32_t hcint;
 714
 715         /* clear all pending interrupts */
 716         hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
 717         DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint);
 718
 719         /* clear buffered interrupts */
 720         sc->sc_chan_state[x].hcint = 0;
 721 }
 722
 723 static uint8_t
 724 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 725 {
 726         uint32_t temp;
 727
 728         temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
 729
 730         if (td->ep_type == UE_ISOCHRONOUS) {
 731                 /*
 732                  * NOTE: USB INTERRUPT transactions are executed like
 733                  * USB CONTROL transactions! See the setup standard
 734                  * chain function for more information.
 735                  */
 736                 if (!(temp & GINTSTS_PTXFEMP)) {
 737                         DPRINTF("Periodic TX FIFO is not empty\n");
 738                         if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
 739                                 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
 740                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 741                         }
 742                         return (1);     /* busy */
 743                 }
 744         } else {
 745                 if (!(temp & GINTSTS_NPTXFEMP)) {
 746                         DPRINTF("Non-periodic TX FIFO is not empty\n");
 747                         if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
 748                                 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
 749                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 750                         }
 751                         return (1);     /* busy */
 752                 }
 753         }
 754         return (0);     /* ready for transmit */
 755 }
 756
 757 static uint8_t
 758 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc,
 759     struct dwc_otg_td *td, uint8_t is_out)
 760 {
 761         uint8_t x;
 762         uint8_t y;
 763         uint8_t z;
 764
 765         if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
 766                 return (0);             /* already allocated */
 767
 768         /* check if device is suspended */
 769         if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 770                 return (1);             /* busy - cannot transfer data */
 771
 772         /* compute needed TX FIFO size */
 773         if (is_out != 0) {
 774                 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0)
 775                         return (1);     /* busy - cannot transfer data */
 776         }
 777         z = td->max_packet_count;
 778         for (x = y = 0; x != sc->sc_host_ch_max; x++) {
 779                 /* check if channel is allocated */
 780                 if (sc->sc_chan_state[x].allocated != 0)
 781                         continue;
 782                 /* check if channel is still enabled */
 783                 if (sc->sc_chan_state[x].wait_halted != 0)
 784                         continue;
 785                 /* store channel number */
 786                 td->channel[y++] = x;
 787                 /* check if we got all channels */
 788                 if (y == z)
 789                         break;
 790         }
 791         if (y != z) {
 792                 /* reset channel variable */
 793                 td->channel[0] = DWC_OTG_MAX_CHANNELS;
 794                 td->channel[1] = DWC_OTG_MAX_CHANNELS;
 795                 td->channel[2] = DWC_OTG_MAX_CHANNELS;
 796                 /* wait a bit */
 797                 dwc_otg_enable_sof_irq(sc);
 798                 return (1);     /* busy - not enough channels */
 799         }
 800
 801         for (y = 0; y != z; y++) {
 802                 x = td->channel[y];
 803
 804                 /* set allocated */
 805                 sc->sc_chan_state[x].allocated = 1;
 806
 807                 /* set wait halted */
 808                 sc->sc_chan_state[x].wait_halted = 1;
 809
 810                 /* clear interrupts */
 811                 dwc_otg_clear_hcint(sc, x);
 812
 813                 DPRINTF("CH=%d HCCHAR=0x%08x "
 814                     "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
 815
 816                 /* set active channel */
 817                 sc->sc_active_rx_ep |= (1 << x);
 818         }
 819         return (0);     /* allocated */
 820 }
 821
 822 static void
 823 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index)
 824 {
 825         uint32_t hcchar;
 826         uint8_t x;
 827
 828         if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
 829                 return;         /* already freed */
 830
 831         /* free channel */
 832         x = td->channel[index];
 833         td->channel[index] = DWC_OTG_MAX_CHANNELS;
 834
 835         DPRINTF("CH=%d\n", x);
 836
 837         /*
 838          * We need to let programmed host channels run till complete
 839          * else the host channel will stop functioning.
 840          */
 841         sc->sc_chan_state[x].allocated = 0;
 842
 843         /* ack any pending messages */
 844         if (sc->sc_last_rx_status != 0 &&
 845             GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
 846                 dwc_otg_common_rx_ack(sc);
 847         }
 848
 849         /* clear active channel */
 850         sc->sc_active_rx_ep &= ~(1 << x);
 851
 852         /* check if already halted */
 853         if (sc->sc_chan_state[x].wait_halted == 0)
 854                 return;
 855
 856         /* disable host channel */
 857         hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
 858         if (hcchar & HCCHAR_CHENA) {
 859                 DPRINTF("Halting channel %d\n", x);
 860                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
 861                     hcchar | HCCHAR_CHDIS);
 862                 /* don't write HCCHAR until the channel is halted */
 863         } else {
 864                 sc->sc_chan_state[x].wait_halted = 0;
 865         }
 866 }
 867
 868 static void
 869 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 870 {
 871         uint8_t x;
 872         for (x = 0; x != td->max_packet_count; x++)
 873                 dwc_otg_host_channel_free_sub(sc, td, x);
 874 }
 875
 876 static void
 877 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 878 {
 879         uint8_t x;
 880         /* dump any pending messages */
 881         if (sc->sc_last_rx_status == 0)
 882                 return;
 883         for (x = 0; x != td->max_packet_count; x++) {
 884                 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
 885                     td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
 886                         continue;
 887                 dwc_otg_common_rx_ack(sc);
 888                 break;
 889         }
 890 }
 891
 892 static uint8_t
 893 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 894 {
 895         struct usb_device_request req __aligned(4);
 896         uint32_t hcint;
 897         uint32_t hcchar;
 898         uint8_t delta;
 899
 900         dwc_otg_host_dump_rx(sc, td);
 901
 902         if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
 903                 hcint = sc->sc_chan_state[td->channel[0]].hcint;
 904
 905                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
 906                     td->channel[0], td->state, hcint,
 907                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
 908                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
 909         } else {
 910                 hcint = 0;
 911                 goto check_state;
 912         }
 913
 914         if (hcint & (HCINT_RETRY |
 915             HCINT_ACK | HCINT_NYET)) {
 916                 /* give success bits priority over failure bits */
 917         } else if (hcint & HCINT_STALL) {
 918                 DPRINTF("CH=%d STALL\n", td->channel[0]);
 919                 td->error_stall = 1;
 920                 td->error_any = 1;
 921                 goto complete;
 922         } else if (hcint & HCINT_ERRORS) {
 923                 DPRINTF("CH=%d ERROR\n", td->channel[0]);
 924                 td->errcnt++;
 925                 if (td->hcsplt != 0 || td->errcnt >= 3) {
 926                         td->error_any = 1;
 927                         goto complete;
 928                 }
 929         }
 930
 931         if (hcint & (HCINT_ERRORS | HCINT_RETRY |
 932             HCINT_ACK | HCINT_NYET)) {
 933                 if (!(hcint & HCINT_ERRORS))
 934                         td->errcnt = 0;
 935         }
 936
 937 check_state:
 938         switch (td->state) {
 939         case DWC_CHAN_ST_START:
 940                 goto send_pkt;
 941
 942         case DWC_CHAN_ST_WAIT_ANE:
 943                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 944                         td->did_nak = 1;
 945                         td->tt_scheduled = 0;
 946                         goto send_pkt;
 947                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 948                         td->offset += td->tx_bytes;
 949                         td->remainder -= td->tx_bytes;
 950                         td->toggle = 1;
 951                         td->tt_scheduled = 0;
 952                         goto complete;
 953                 }
 954                 break;
 955
 956         case DWC_CHAN_ST_WAIT_S_ANE:
 957                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 958                         td->did_nak = 1;
 959                         td->tt_scheduled = 0;
 960                         goto send_pkt;
 961                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 962                         goto send_cpkt;
 963                 }
 964                 break;
 965
 966         case DWC_CHAN_ST_WAIT_C_ANE:
 967                 if (hcint & HCINT_NYET) {
 968                         goto send_cpkt;
 969                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 970                         td->did_nak = 1;
 971                         td->tt_scheduled = 0;
 972                         goto send_pkt;
 973                 } else if (hcint & HCINT_ACK) {
 974                         td->offset += td->tx_bytes;
 975                         td->remainder -= td->tx_bytes;
 976                         td->toggle = 1;
 977                         goto complete;
 978                 }
 979                 break;
 980
 981         case DWC_CHAN_ST_WAIT_C_PKT:
 982                 goto send_cpkt;
 983
 984         default:
 985                 break;
 986         }
 987         goto busy;
 988
 989 send_pkt:
 990         /* free existing channel, if any */
 991         dwc_otg_host_channel_free(sc, td);
 992
 993         if (sizeof(req) != td->remainder) {
 994                 td->error_any = 1;
 995                 goto complete;
 996         }
 997
 998         if (td->hcsplt != 0) {
 999                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1000                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1001                         td->state = DWC_CHAN_ST_START;
1002                         goto busy;
1003                 }
1004                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1005                 if (delta > 5) {
1006                         /* missed it */
1007                         td->tt_scheduled = 0;
1008                         td->state = DWC_CHAN_ST_START;
1009                         goto busy;
1010                 }
1011         }
1012
1013         /* allocate a new channel */
1014         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1015                 td->state = DWC_CHAN_ST_START;
1016                 goto busy;
1017         }
1018
1019         if (td->hcsplt != 0) {
1020                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1021                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1022         } else {
1023                 td->state = DWC_CHAN_ST_WAIT_ANE;
1024         }
1025
1026         /* copy out control request */
1027         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1028
1029         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1030             (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) |
1031             (1 << HCTSIZ_PKTCNT_SHIFT) |
1032             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1033
1034         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1035
1036         hcchar = td->hcchar;
1037         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1038         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1039
1040         /* must enable channel before writing data to FIFO */
1041         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1042
1043         /* transfer data into FIFO */
1044         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1045             DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1046
1047         /* wait until next slot before trying complete split */
1048         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1049
1050         /* store number of bytes transmitted */
1051         td->tx_bytes = sizeof(req);
1052         goto busy;
1053
1054 send_cpkt:
1055         /* free existing channel, if any */
1056         dwc_otg_host_channel_free(sc, td);
1057
1058         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1059         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1060                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1061                 goto busy;
1062         }
1063         delta = sc->sc_last_frame_num - td->tt_start_slot;
1064         if (delta > DWC_OTG_TT_SLOT_MAX) {
1065                 /* we missed the service interval */
1066                 if (td->ep_type != UE_ISOCHRONOUS)
1067                         td->error_any = 1;
1068                 goto complete;
1069         }
1070         /* allocate a new channel */
1071         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1072                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1073                 goto busy;
1074         }
1075
1076         /* wait until next slot before trying complete split */
1077         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1078
1079         td->hcsplt |= HCSPLT_COMPSPLT;
1080         td->state = DWC_CHAN_ST_WAIT_C_ANE;
1081
1082         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1083             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1084
1085         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1086
1087         hcchar = td->hcchar;
1088         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1089         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1090
1091         /* must enable channel before writing data to FIFO */
1092         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1093
1094 busy:
1095         return (1);     /* busy */
1096
1097 complete:
1098         dwc_otg_host_channel_free(sc, td);
1099         return (0);     /* complete */
1100 }
1101
1102 static uint8_t
1103 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1104 {
1105         struct usb_device_request req __aligned(4);
1106         uint32_t temp;
1107         uint16_t count;
1108
1109         /* check endpoint status */
1110
1111         if (sc->sc_last_rx_status == 0)
1112                 goto not_complete;
1113
1114         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
1115                 goto not_complete;
1116
1117         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1118             GRXSTSRD_STP_DATA) {
1119                 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1120                     GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
1121                         /* release FIFO */
1122                         dwc_otg_common_rx_ack(sc);
1123                         goto not_complete;
1124                 }
1125                 /* release FIFO */
1126                 dwc_otg_common_rx_ack(sc);
1127                 return (0);     /* complete */
1128         }
1129
1130         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1131             GRXSTSRD_DPID_DATA0) {
1132                 /* release FIFO */
1133                 dwc_otg_common_rx_ack(sc);
1134                 goto not_complete;
1135         }
1136
1137         DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
1138
1139         /* clear did stall */
1140         td->did_stall = 0;
1141
1142         /* get the packet byte count */
1143         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1144
1145         if (count != sizeof(req)) {
1146                 DPRINTFN(0, "Unsupported SETUP packet "
1147                     "length, %d bytes\n", count);
1148                 /* release FIFO */
1149                 dwc_otg_common_rx_ack(sc);
1150                 goto not_complete;
1151         }
1152
1153         /* read FIFO */
1154         dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req));
1155
1156         /* copy out control request */
1157         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1158
1159         td->offset = sizeof(req);
1160         td->remainder = 0;
1161
1162         /* sneak peek the set address */
1163         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1164             (req.bRequest == UR_SET_ADDRESS)) {
1165                 /* must write address before ZLP */
1166                 dwc_otg_set_address(sc, req.wValue[0] & 0x7F);
1167         }
1168
1169         /* don't send any data by default */
1170         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
1171         DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
1172
1173         /* reset IN endpoint buffer */
1174         dwc_otg_tx_fifo_reset(sc,
1175             GRSTCTL_TXFIFO(0) |
1176             GRSTCTL_TXFFLSH);
1177
1178         /* acknowledge RX status */
1179         dwc_otg_common_rx_ack(sc);
1180         td->did_stall = 1;
1181
1182 not_complete:
1183         /* abort any ongoing transfer, before enabling again */
1184         if (!td->did_stall) {
1185                 td->did_stall = 1;
1186
1187                 DPRINTFN(5, "stalling IN and OUT direction\n");
1188
1189                 temp = sc->sc_out_ctl[0];
1190
1191                 /* set stall after enabling endpoint */
1192                 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
1193                     temp | DOEPCTL_STALL);
1194
1195                 temp = sc->sc_in_ctl[0];
1196
1197                 /* set stall assuming endpoint is enabled */
1198                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
1199                     temp | DIEPCTL_STALL);
1200         }
1201         return (1);                     /* not complete */
1202 }
1203
1204 static uint8_t
1205 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1206 {
1207         uint8_t delta;
1208
1209         delta = sc->sc_tmr_val - td->tmr_val;
1210         if (delta >= 128)
1211                 return (1);     /* busy */
1212
1213         td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1214
1215         /* set toggle, if any */
1216         if (td->set_toggle) {
1217                 td->set_toggle = 0;
1218                 td->toggle = 1;
1219         }
1220         return (0);
1221 }
1222
1223 static uint8_t
1224 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1225 {
1226         uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1227
1228         if (td->ep_type == UE_ISOCHRONOUS) {
1229                 /* non TT isochronous traffic */
1230                 if (frame_num & (td->tmr_res - 1))
1231                         goto busy;
1232                 if ((frame_num ^ td->tmr_val) & td->tmr_res)
1233                         goto busy;
1234                 td->tmr_val = td->tmr_res + sc->sc_last_frame_num;
1235                 td->toggle = 0;
1236                 return (0);
1237         } else if (td->ep_type == UE_INTERRUPT) {
1238                 if (!td->tt_scheduled)
1239                         goto busy;
1240                 td->tt_scheduled = 0;
1241                 return (0);
1242         } else if (td->did_nak != 0) {
1243                 /* check if we should pause sending queries for 125us */
1244                 if (td->tmr_res == frame_num) {
1245                         /* wait a bit */
1246                         dwc_otg_enable_sof_irq(sc);
1247                         goto busy;
1248                 }
1249         } else if (td->set_toggle) {
1250                 td->set_toggle = 0;
1251                 td->toggle = 1;
1252         }
1253         /* query for data one more time */
1254         td->tmr_res = frame_num;
1255         td->did_nak = 0;
1256         return (0);
1257 busy:
1258         return (1);
1259 }
1260
1261 static uint8_t
1262 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td,
1263     uint8_t channel)
1264 {
1265         uint32_t count;
1266
1267         /* check endpoint status */
1268         if (sc->sc_last_rx_status == 0)
1269                 goto busy;
1270
1271         if (channel >= DWC_OTG_MAX_CHANNELS)
1272                 goto busy;
1273
1274         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1275                 goto busy;
1276
1277         switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1278         case GRXSTSRH_IN_DATA:
1279
1280                 DPRINTF("DATA ST=%d STATUS=0x%08x\n",
1281                     (int)td->state, (int)sc->sc_last_rx_status);
1282
1283                 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1284                         /*
1285                          * When using SPLIT transactions on interrupt
1286                          * endpoints, sometimes data occurs twice.
1287                          */
1288                         DPRINTF("Data already received\n");
1289                         break;
1290                 }
1291
1292                 /* get the packet byte count */
1293                 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1294
1295                 /* check for ISOCHRONOUS endpoint */
1296                 if (td->ep_type == UE_ISOCHRONOUS) {
1297                         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1298                             GRXSTSRD_DPID_DATA0) {
1299                                 /* more data to be received */
1300                                 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1301                         } else {
1302                                 /* all data received */
1303                                 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1304                                 /* verify the packet byte count */
1305                                 if (count != td->remainder) {
1306                                         /* we have a short packet */
1307                                         td->short_pkt = 1;
1308                                         td->got_short = 1;
1309                                 }
1310                         }
1311                 } else {
1312                         /* verify the packet byte count */
1313                         if (count != td->max_packet_size) {
1314                                 if (count < td->max_packet_size) {
1315                                         /* we have a short packet */
1316                                         td->short_pkt = 1;
1317                                         td->got_short = 1;
1318                                 } else {
1319                                         /* invalid USB packet */
1320                                         td->error_any = 1;
1321
1322                                         /* release FIFO */
1323                                         dwc_otg_common_rx_ack(sc);
1324                                         goto complete;
1325                                 }
1326                         }
1327                         td->toggle ^= 1;
1328                         td->tt_scheduled = 0;
1329                 }
1330
1331                 /* verify the packet byte count */
1332                 if (count > td->remainder) {
1333                         /* invalid USB packet */
1334                         td->error_any = 1;
1335
1336                         /* release FIFO */
1337                         dwc_otg_common_rx_ack(sc);
1338                         goto complete;
1339                 }
1340
1341                 /* read data from FIFO */
1342                 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1343
1344                 td->remainder -= count;
1345                 td->offset += count;
1346                 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1347                 break;
1348         default:
1349                 break;
1350         }
1351         /* release FIFO */
1352         dwc_otg_common_rx_ack(sc);
1353 busy:
1354         return (0);
1355 complete:
1356         return (1);
1357 }
1358
1359 static uint8_t
1360 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1361 {
1362         uint32_t hcint = 0;
1363         uint32_t hcchar;
1364         uint8_t delta;
1365         uint8_t channel;
1366         uint8_t x;
1367
1368         for (x = 0; x != td->max_packet_count; x++) {
1369                 channel = td->channel[x];
1370                 if (channel >= DWC_OTG_MAX_CHANNELS)
1371                         continue;
1372                 hcint |= sc->sc_chan_state[channel].hcint;
1373
1374                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1375                     channel, td->state, hcint,
1376                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1377                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1378
1379                 /* check interrupt bits */
1380                 if (hcint & (HCINT_RETRY |
1381                     HCINT_ACK | HCINT_NYET)) {
1382                         /* give success bits priority over failure bits */
1383                 } else if (hcint & HCINT_STALL) {
1384                         DPRINTF("CH=%d STALL\n", channel);
1385                         td->error_stall = 1;
1386                         td->error_any = 1;
1387                         goto complete;
1388                 } else if (hcint & HCINT_ERRORS) {
1389                         DPRINTF("CH=%d ERROR\n", channel);
1390                         td->errcnt++;
1391                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1392                                 if (td->ep_type != UE_ISOCHRONOUS) {
1393                                         td->error_any = 1;
1394                                         goto complete;
1395                                 }
1396                         }
1397                 }
1398
1399                 /* check channels for data, if any */
1400                 if (dwc_otg_host_data_rx_sub(sc, td, channel))
1401                         goto complete;
1402
1403                 /* refresh interrupt status */
1404                 hcint |= sc->sc_chan_state[channel].hcint;
1405
1406                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1407                     HCINT_ACK | HCINT_NYET)) {
1408                         if (!(hcint & HCINT_ERRORS))
1409                                 td->errcnt = 0;
1410                 }
1411         }
1412
1413         switch (td->state) {
1414         case DWC_CHAN_ST_START:
1415                 if (td->hcsplt != 0)
1416                         goto receive_spkt;
1417                 else
1418                         goto receive_pkt;
1419
1420         case DWC_CHAN_ST_WAIT_ANE:
1421                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1422                         if (td->ep_type == UE_INTERRUPT) {
1423                                 /*
1424                                  * The USB specification does not
1425                                  * mandate a particular data toggle
1426                                  * value for USB INTERRUPT
1427                                  * transfers. Switch the data toggle
1428                                  * value to receive the packet
1429                                  * correctly:
1430                                  */
1431                                 if (hcint & HCINT_DATATGLERR) {
1432                                         DPRINTF("Retrying packet due to "
1433                                             "data toggle error\n");
1434                                         td->toggle ^= 1;
1435                                         goto receive_pkt;
1436                                 }
1437                         } else if (td->ep_type == UE_ISOCHRONOUS) {
1438                                 if (td->hcsplt != 0) {
1439                                         /*
1440                                          * Sometimes the complete
1441                                          * split packet may be queued
1442                                          * too early and the
1443                                          * transaction translator will
1444                                          * return a NAK. Ignore
1445                                          * this message and retry the
1446                                          * complete split instead.
1447                                          */
1448                                         DPRINTF("Retrying complete split\n");
1449                                         goto receive_pkt;
1450                                 }
1451                                 goto complete;
1452                         }
1453                         td->did_nak = 1;
1454                         td->tt_scheduled = 0;
1455                         if (td->hcsplt != 0)
1456                                 goto receive_spkt;
1457                         else
1458                                 goto receive_pkt;
1459                 } else if (hcint & HCINT_NYET) {
1460                         if (td->hcsplt != 0) {
1461                                 /* try again */
1462                                 goto receive_pkt;
1463                         } else {
1464                                 /* not a valid token for IN endpoints */
1465                                 td->error_any = 1;
1466                                 goto complete;
1467                         }
1468                 } else if (hcint & HCINT_ACK) {
1469                         /* wait for data - ACK arrived first */
1470                         if (!(hcint & HCINT_SOFTWARE_ONLY))
1471                                 goto busy;
1472
1473                         if (td->ep_type == UE_ISOCHRONOUS) {
1474                                 /* check if we are complete */
1475                                 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) {
1476                                         goto complete;
1477                                 } else if (td->hcsplt != 0) {
1478                                         goto receive_pkt;
1479                                 } else {
1480                                         /* get more packets */
1481                                         goto busy;
1482                                 }
1483                         } else {
1484                                 /* check if we are complete */
1485                                 if ((td->remainder == 0) || (td->got_short != 0)) {
1486                                         if (td->short_pkt)
1487                                                 goto complete;
1488
1489                                         /*
1490                                          * Else need to receive a zero length
1491                                          * packet.
1492                                          */
1493                                 }
1494                                 td->tt_scheduled = 0;
1495                                 td->did_nak = 0;
1496                                 if (td->hcsplt != 0)
1497                                         goto receive_spkt;
1498                                 else
1499                                         goto receive_pkt;
1500                         }
1501                 }
1502                 break;
1503
1504         case DWC_CHAN_ST_WAIT_S_ANE:
1505                 /*
1506                  * NOTE: The DWC OTG hardware provides a fake ACK in
1507                  * case of interrupt and isochronous transfers:
1508                  */
1509                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1510                         td->did_nak = 1;
1511                         td->tt_scheduled = 0;
1512                         goto receive_spkt;
1513                 } else if (hcint & HCINT_NYET) {
1514                         td->tt_scheduled = 0;
1515                         goto receive_spkt;
1516                 } else if (hcint & HCINT_ACK) {
1517                         td->did_nak = 0;
1518                         goto receive_pkt;
1519                 }
1520                 break;
1521
1522         case DWC_CHAN_ST_WAIT_C_PKT:
1523                 goto receive_pkt;
1524
1525         default:
1526                 break;
1527         }
1528         goto busy;
1529
1530 receive_pkt:
1531         /* free existing channel, if any */
1532         dwc_otg_host_channel_free(sc, td);
1533
1534         if (td->hcsplt != 0) {
1535                 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1536                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1537                         if (td->ep_type != UE_ISOCHRONOUS) {
1538                                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1539                                 goto busy;
1540                         }
1541                 }
1542                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1543                 if (delta > DWC_OTG_TT_SLOT_MAX) {
1544                         if (td->ep_type != UE_ISOCHRONOUS) {
1545                                 /* we missed the service interval */
1546                                 td->error_any = 1;
1547                         }
1548                         goto complete;
1549                 }
1550                 /* complete split */
1551                 td->hcsplt |= HCSPLT_COMPSPLT;
1552         } else if (dwc_otg_host_rate_check(sc, td)) {
1553                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1554                 goto busy;
1555         }
1556
1557         /* allocate a new channel */
1558         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1559                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1560                 goto busy;
1561         }
1562
1563         /* set toggle, if any */
1564         if (td->set_toggle) {
1565                 td->set_toggle = 0;
1566                 td->toggle = 1;
1567         }
1568
1569         td->state = DWC_CHAN_ST_WAIT_ANE;
1570
1571         for (x = 0; x != td->max_packet_count; x++) {
1572                 channel = td->channel[x];
1573
1574                 /* receive one packet */
1575                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1576                     (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1577                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1578                     (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1579                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1580
1581                 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1582
1583                 hcchar = td->hcchar;
1584                 hcchar |= HCCHAR_EPDIR_IN;
1585
1586                 if (td->ep_type == UE_ISOCHRONOUS) {
1587                         if (td->hcsplt != 0) {
1588                                 /* continously buffer */
1589                                 if (sc->sc_last_frame_num & 1)
1590                                         hcchar &= ~HCCHAR_ODDFRM;
1591                                 else
1592                                         hcchar |= HCCHAR_ODDFRM;
1593                         } else {
1594                                 /* multi buffer, if any */
1595                                 if (sc->sc_last_frame_num & 1)
1596                                         hcchar |= HCCHAR_ODDFRM;
1597                                 else
1598                                         hcchar &= ~HCCHAR_ODDFRM;
1599                         }
1600                 } else {
1601                         hcchar &= ~HCCHAR_ODDFRM;
1602                 }
1603
1604                 /* must enable channel before data can be received */
1605                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1606         }
1607         /* wait until next slot before trying complete split */
1608         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1609
1610         goto busy;
1611
1612 receive_spkt:
1613         /* free existing channel(s), if any */
1614         dwc_otg_host_channel_free(sc, td);
1615
1616         delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1617         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1618                 td->state = DWC_CHAN_ST_START;
1619                 goto busy;
1620         }
1621         delta = sc->sc_last_frame_num - td->tt_start_slot;
1622         if (delta > 5) {
1623                 /* missed it */
1624                 td->tt_scheduled = 0;
1625                 td->state = DWC_CHAN_ST_START;
1626                 goto busy;
1627         }
1628
1629         /* allocate a new channel */
1630         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1631                 td->state = DWC_CHAN_ST_START;
1632                 goto busy;
1633         }
1634
1635         channel = td->channel[0];
1636
1637         td->hcsplt &= ~HCSPLT_COMPSPLT;
1638         td->state = DWC_CHAN_ST_WAIT_S_ANE;
1639
1640         /* receive one packet */
1641         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1642             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1643
1644         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1645
1646         /* send after next SOF event */
1647         if ((sc->sc_last_frame_num & 1) == 0 &&
1648             td->ep_type == UE_ISOCHRONOUS)
1649                 td->hcchar |= HCCHAR_ODDFRM;
1650         else
1651                 td->hcchar &= ~HCCHAR_ODDFRM;
1652
1653         hcchar = td->hcchar;
1654         hcchar |= HCCHAR_EPDIR_IN;
1655
1656         /* wait until next slot before trying complete split */
1657         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1658
1659         /* must enable channel before data can be received */
1660         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1661 busy:
1662         return (1);     /* busy */
1663
1664 complete:
1665         dwc_otg_host_channel_free(sc, td);
1666         return (0);     /* complete */
1667 }
1668
1669 static uint8_t
1670 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1671 {
1672         uint32_t temp;
1673         uint16_t count;
1674         uint8_t got_short;
1675
1676         got_short = 0;
1677
1678         /* check endpoint status */
1679         if (sc->sc_last_rx_status == 0)
1680                 goto not_complete;
1681
1682         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1683                 goto not_complete;
1684
1685         /* check for SETUP packet */
1686         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1687             GRXSTSRD_STP_DATA ||
1688             (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1689             GRXSTSRD_STP_COMPLETE) {
1690                 if (td->remainder == 0) {
1691                         /*
1692                          * We are actually complete and have
1693                          * received the next SETUP
1694                          */
1695                         DPRINTFN(5, "faking complete\n");
1696                         return (0);     /* complete */
1697                 }
1698                 /*
1699                  * USB Host Aborted the transfer.
1700                  */
1701                 td->error_any = 1;
1702                 return (0);             /* complete */
1703         }
1704
1705         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1706             GRXSTSRD_OUT_DATA) {
1707                 /* release FIFO */
1708                 dwc_otg_common_rx_ack(sc);
1709                 goto not_complete;
1710         }
1711
1712         /* get the packet byte count */
1713         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1714
1715         /* verify the packet byte count */
1716         if (count != td->max_packet_size) {
1717                 if (count < td->max_packet_size) {
1718                         /* we have a short packet */
1719                         td->short_pkt = 1;
1720                         got_short = 1;
1721                 } else {
1722                         /* invalid USB packet */
1723                         td->error_any = 1;
1724
1725                         /* release FIFO */
1726                         dwc_otg_common_rx_ack(sc);
1727                         return (0);     /* we are complete */
1728                 }
1729         }
1730         /* verify the packet byte count */
1731         if (count > td->remainder) {
1732                 /* invalid USB packet */
1733                 td->error_any = 1;
1734
1735                 /* release FIFO */
1736                 dwc_otg_common_rx_ack(sc);
1737                 return (0);             /* we are complete */
1738         }
1739
1740         /* read data from FIFO */
1741         dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1742
1743         td->remainder -= count;
1744         td->offset += count;
1745
1746         /* release FIFO */
1747         dwc_otg_common_rx_ack(sc);
1748
1749         temp = sc->sc_out_ctl[td->ep_no];
1750
1751         /* check for isochronous mode */
1752         if ((temp & DIEPCTL_EPTYPE_MASK) ==
1753             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
1754                 /* toggle odd or even frame bit */
1755                 if (temp & DIEPCTL_SETD1PID) {
1756                         temp &= ~DIEPCTL_SETD1PID;
1757                         temp |= DIEPCTL_SETD0PID;
1758                 } else {
1759                         temp &= ~DIEPCTL_SETD0PID;
1760                         temp |= DIEPCTL_SETD1PID;
1761                 }
1762                 sc->sc_out_ctl[td->ep_no] = temp;
1763         }
1764
1765         /* check if we are complete */
1766         if ((td->remainder == 0) || got_short) {
1767                 if (td->short_pkt) {
1768                         /* we are complete */
1769                         return (0);
1770                 }
1771                 /* else need to receive a zero length packet */
1772         }
1773
1774 not_complete:
1775
1776         /* enable SETUP and transfer complete interrupt */
1777         if (td->ep_no == 0) {
1778                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
1779                     DXEPTSIZ_SET_MULTI(3) |
1780                     DXEPTSIZ_SET_NPKT(1) |
1781                     DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1782         } else {
1783                 /* allow reception of multiple packets */
1784                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1785                     DXEPTSIZ_SET_MULTI(1) |
1786                     DXEPTSIZ_SET_NPKT(4) |
1787                     DXEPTSIZ_SET_NBYTES(4 *
1788                         ((td->max_packet_size + 3) & ~3)));
1789         }
1790         temp = sc->sc_out_ctl[td->ep_no];
1791         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1792             DOEPCTL_EPENA | DOEPCTL_CNAK);
1793
1794         return (1);                     /* not complete */
1795 }
1796
1797 static uint8_t
1798 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1799 {
1800         uint32_t count;
1801         uint32_t hcint;
1802         uint32_t hcchar;
1803         uint8_t delta;
1804         uint8_t channel;
1805         uint8_t x;
1806
1807         dwc_otg_host_dump_rx(sc, td);
1808
1809         /* check that last channel is complete */
1810         channel = td->channel[td->npkt];
1811
1812         if (channel < DWC_OTG_MAX_CHANNELS) {
1813                 hcint = sc->sc_chan_state[channel].hcint;
1814
1815                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1816                     channel, td->state, hcint,
1817                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1818                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1819
1820                 if (hcint & (HCINT_RETRY |
1821                     HCINT_ACK | HCINT_NYET)) {
1822                         /* give success bits priority over failure bits */
1823                 } else if (hcint & HCINT_STALL) {
1824                         DPRINTF("CH=%d STALL\n", channel);
1825                         td->error_stall = 1;
1826                         td->error_any = 1;
1827                         goto complete;
1828                 } else if (hcint & HCINT_ERRORS) {
1829                         DPRINTF("CH=%d ERROR\n", channel);
1830                         td->errcnt++;
1831                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1832                                 td->error_any = 1;
1833                                 goto complete;
1834                         }
1835                 }
1836
1837                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1838                     HCINT_ACK | HCINT_NYET)) {
1839
1840                         if (!(hcint & HCINT_ERRORS))
1841                                 td->errcnt = 0;
1842                 }
1843         } else {
1844                 hcint = 0;
1845         }
1846
1847         switch (td->state) {
1848         case DWC_CHAN_ST_START:
1849                 goto send_pkt;
1850
1851         case DWC_CHAN_ST_WAIT_ANE:
1852                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1853                         td->did_nak = 1;
1854                         td->tt_scheduled = 0;
1855                         goto send_pkt;
1856                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1857                         td->offset += td->tx_bytes;
1858                         td->remainder -= td->tx_bytes;
1859                         td->toggle ^= 1;
1860                         /* check if next response will be a NAK */
1861                         if (hcint & HCINT_NYET)
1862                                 td->did_nak = 1;
1863                         else
1864                                 td->did_nak = 0;
1865                         td->tt_scheduled = 0;
1866
1867                         /* check remainder */
1868                         if (td->remainder == 0) {
1869                                 if (td->short_pkt)
1870                                         goto complete;
1871
1872                                 /*
1873                                  * Else we need to transmit a short
1874                                  * packet:
1875                                  */
1876                         }
1877                         goto send_pkt;
1878                 }
1879                 break;
1880
1881         case DWC_CHAN_ST_WAIT_S_ANE:
1882                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1883                         td->did_nak = 1;
1884                         td->tt_scheduled = 0;
1885                         goto send_pkt;
1886                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1887                         td->did_nak = 0;
1888                         goto send_cpkt;
1889                 }
1890                 break;
1891
1892         case DWC_CHAN_ST_WAIT_C_ANE:
1893                 if (hcint & HCINT_NYET) {
1894                         goto send_cpkt;
1895                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1896                         td->did_nak = 1;
1897                         td->tt_scheduled = 0;
1898                         goto send_pkt;
1899                 } else if (hcint & HCINT_ACK) {
1900                         td->offset += td->tx_bytes;
1901                         td->remainder -= td->tx_bytes;
1902                         td->toggle ^= 1;
1903                         td->did_nak = 0;
1904                         td->tt_scheduled = 0;
1905
1906                         /* check remainder */
1907                         if (td->remainder == 0) {
1908                                 if (td->short_pkt)
1909                                         goto complete;
1910
1911                                 /* else we need to transmit a short packet */
1912                         }
1913                         goto send_pkt;
1914                 }
1915                 break;
1916
1917         case DWC_CHAN_ST_WAIT_C_PKT:
1918                 goto send_cpkt;
1919
1920         case DWC_CHAN_ST_TX_WAIT_ISOC:
1921                 /* Check if ISOCHRONOUS OUT traffic is complete */
1922                 if ((hcint & HCINT_HCH_DONE_MASK) == 0)
1923                         break;
1924
1925                 td->offset += td->tx_bytes;
1926                 td->remainder -= td->tx_bytes;
1927                 goto complete;
1928         default:
1929                 break;
1930         }
1931         goto busy;
1932
1933 send_pkt:
1934         /* free existing channel(s), if any */
1935         dwc_otg_host_channel_free(sc, td);
1936
1937         if (td->hcsplt != 0) {
1938                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1939                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1940                         td->state = DWC_CHAN_ST_START;
1941                         goto busy;
1942                 }
1943                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1944                 if (delta > 5) {
1945                         /* missed it */
1946                         td->tt_scheduled = 0;
1947                         td->state = DWC_CHAN_ST_START;
1948                         goto busy;
1949                 }
1950         } else if (dwc_otg_host_rate_check(sc, td)) {
1951                 td->state = DWC_CHAN_ST_START;
1952                 goto busy;
1953         }
1954
1955         /* allocate a new channel */
1956         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1957                 td->state = DWC_CHAN_ST_START;
1958                 goto busy;
1959         }
1960
1961         /* set toggle, if any */
1962         if (td->set_toggle) {
1963                 td->set_toggle = 0;
1964                 td->toggle = 1;
1965         }
1966
1967         if (td->ep_type == UE_ISOCHRONOUS) {
1968                 /* ISOCHRONOUS OUT transfers don't have any ACKs */
1969                 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1970                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1971                 if (td->hcsplt != 0) {
1972                         /* get maximum transfer length */
1973                         count = td->remainder;
1974                         if (count > HCSPLT_XACTLEN_BURST) {
1975                                 DPRINTF("TT overflow\n");
1976                                 td->error_any = 1;
1977                                 goto complete;
1978                         }
1979                         /* Update transaction position */
1980                         td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1981                         td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1982                 }
1983         } else if (td->hcsplt != 0) {
1984                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1985                 /* Wait for ACK/NAK/ERR from TT */
1986                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1987         } else {
1988                 /* Wait for ACK/NAK/STALL from device */
1989                 td->state = DWC_CHAN_ST_WAIT_ANE;
1990         }
1991
1992         td->tx_bytes = 0;
1993
1994         for (x = 0; x != td->max_packet_count; x++) {
1995                 uint32_t rem_bytes;
1996
1997                 channel = td->channel[x];
1998
1999                 /* send one packet at a time */
2000                 count = td->max_packet_size;
2001                 rem_bytes = td->remainder - td->tx_bytes;
2002                 if (rem_bytes < count) {
2003                         /* we have a short packet */
2004                         td->short_pkt = 1;
2005                         count = rem_bytes;
2006                 }
2007                 if (count == rem_bytes) {
2008                         /* last packet */
2009                         switch (x) {
2010                         case 0:
2011                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2012                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2013                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2014                                     (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2015                                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2016                                 break;
2017                         case 1:
2018                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2019                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2020                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2021                                     (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT));
2022                                 break;
2023                         default:
2024                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2025                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2026                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2027                                     (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT));
2028                                 break;
2029                         }
2030                 } else if (td->ep_type == UE_ISOCHRONOUS &&
2031                            td->max_packet_count > 1) {
2032                         /* ISOCHRONOUS multi packet */
2033                         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2034                             (count << HCTSIZ_XFERSIZE_SHIFT) |
2035                             (1 << HCTSIZ_PKTCNT_SHIFT) |
2036                             (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT));
2037                 } else {
2038                         /* TODO: HCTSIZ_DOPNG */
2039                         /* standard BULK/INTERRUPT/CONTROL packet */
2040                         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2041                             (count << HCTSIZ_XFERSIZE_SHIFT) |
2042                             (1 << HCTSIZ_PKTCNT_SHIFT) |
2043                             (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2044                             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2045                 }
2046
2047                 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2048
2049                 hcchar = td->hcchar;
2050                 hcchar &= ~HCCHAR_EPDIR_IN;
2051
2052                 /* send after next SOF event */
2053                 if ((sc->sc_last_frame_num & 1) == 0 &&
2054                     td->ep_type == UE_ISOCHRONOUS)
2055                         hcchar |= HCCHAR_ODDFRM;
2056                 else
2057                         hcchar &= ~HCCHAR_ODDFRM;
2058
2059                 /* must enable before writing data to FIFO */
2060                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2061
2062                 if (count != 0) {
2063                         /* write data into FIFO */
2064                         dwc_otg_write_fifo(sc, td->pc, td->offset +
2065                             td->tx_bytes, DOTG_DFIFO(channel), count);
2066                 }
2067
2068                 /* store number of bytes transmitted */
2069                 td->tx_bytes += count;
2070
2071                 /* store last packet index */
2072                 td->npkt = x;
2073
2074                 /* check for last packet */
2075                 if (count == rem_bytes)
2076                         break;
2077         }
2078         goto busy;
2079
2080 send_cpkt:
2081         /* free existing channel, if any */
2082         dwc_otg_host_channel_free(sc, td);
2083
2084         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
2085         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
2086                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2087                 goto busy;
2088         }
2089         delta = sc->sc_last_frame_num - td->tt_start_slot;
2090         if (delta > DWC_OTG_TT_SLOT_MAX) {
2091                 /* we missed the service interval */
2092                 if (td->ep_type != UE_ISOCHRONOUS)
2093                         td->error_any = 1;
2094                 goto complete;
2095         }
2096
2097         /* allocate a new channel */
2098         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
2099                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2100                 goto busy;
2101         }
2102
2103         channel = td->channel[0];
2104
2105         td->hcsplt |= HCSPLT_COMPSPLT;
2106         td->state = DWC_CHAN_ST_WAIT_C_ANE;
2107
2108         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2109             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
2110
2111         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2112
2113         hcchar = td->hcchar;
2114         hcchar &= ~HCCHAR_EPDIR_IN;
2115
2116         /* receive complete split ASAP */
2117         if ((sc->sc_last_frame_num & 1) != 0 &&
2118             td->ep_type == UE_ISOCHRONOUS)
2119                 hcchar |= HCCHAR_ODDFRM;
2120         else
2121                 hcchar &= ~HCCHAR_ODDFRM;
2122
2123         /* must enable channel before data can be received */
2124         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2125
2126         /* wait until next slot before trying complete split */
2127         td->tt_complete_slot = sc->sc_last_frame_num + 1;
2128 busy:
2129         return (1);     /* busy */
2130
2131 complete:
2132         dwc_otg_host_channel_free(sc, td);
2133         return (0);     /* complete */
2134 }
2135
2136 static uint8_t
2137 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2138 {
2139         uint32_t max_buffer;
2140         uint32_t count;
2141         uint32_t fifo_left;
2142         uint32_t mpkt;
2143         uint32_t temp;
2144         uint8_t to;
2145
2146         to = 3;                         /* don't loop forever! */
2147
2148         max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
2149
2150 repeat:
2151         /* check for for endpoint 0 data */
2152
2153         temp = sc->sc_last_rx_status;
2154
2155         if ((td->ep_no == 0) && (temp != 0) &&
2156             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2157
2158                 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2159                     GRXSTSRD_STP_DATA &&
2160                     (temp & GRXSTSRD_PKTSTS_MASK) !=
2161                     GRXSTSRD_STP_COMPLETE) {
2162
2163                         /* dump data - wrong direction */
2164                         dwc_otg_common_rx_ack(sc);
2165                 } else {
2166                         /*
2167                          * The current transfer was cancelled
2168                          * by the USB Host:
2169                          */
2170                         td->error_any = 1;
2171                         return (0);             /* complete */
2172                 }
2173         }
2174
2175         /* fill in more TX data, if possible */
2176         if (td->tx_bytes != 0) {
2177
2178                 uint16_t cpkt;
2179
2180                 /* check if packets have been transferred */
2181                 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2182
2183                 /* get current packet number */
2184                 cpkt = DXEPTSIZ_GET_NPKT(temp);
2185
2186                 if (cpkt >= td->npkt) {
2187                         fifo_left = 0;
2188                 } else {
2189                         if (max_buffer != 0) {
2190                                 fifo_left = (td->npkt - cpkt) *
2191                                     td->max_packet_size;
2192
2193                                 if (fifo_left > max_buffer)
2194                                         fifo_left = max_buffer;
2195                         } else {
2196                                 fifo_left = td->max_packet_size;
2197                         }
2198                 }
2199
2200                 count = td->tx_bytes;
2201                 if (count > fifo_left)
2202                         count = fifo_left;
2203
2204                 if (count != 0) {
2205                         /* write data into FIFO */
2206                         dwc_otg_write_fifo(sc, td->pc, td->offset,
2207                             DOTG_DFIFO(td->ep_no), count);
2208
2209                         td->tx_bytes -= count;
2210                         td->remainder -= count;
2211                         td->offset += count;
2212                         td->npkt = cpkt;
2213                 }
2214                 if (td->tx_bytes != 0)
2215                         goto not_complete;
2216
2217                 /* check remainder */
2218                 if (td->remainder == 0) {
2219                         if (td->short_pkt)
2220                                 return (0);     /* complete */
2221
2222                         /* else we need to transmit a short packet */
2223                 }
2224         }
2225
2226         if (!to--)
2227                 goto not_complete;
2228
2229         /* check if not all packets have been transferred */
2230         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2231
2232         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2233
2234                 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
2235                     "DIEPCTL=0x%08x\n", td->ep_no,
2236                     DXEPTSIZ_GET_NPKT(temp),
2237                     temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2238
2239                 goto not_complete;
2240         }
2241
2242         DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2243
2244         /* try to optimise by sending more data */
2245         if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2246
2247                 /* send multiple packets at the same time */
2248                 mpkt = max_buffer / td->max_packet_size;
2249
2250                 if (mpkt > 0x3FE)
2251                         mpkt = 0x3FE;
2252
2253                 count = td->remainder;
2254                 if (count > 0x7FFFFF)
2255                         count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2256
2257                 td->npkt = count / td->max_packet_size;
2258
2259                 /*
2260                  * NOTE: We could use 0x3FE instead of "mpkt" in the
2261                  * check below to get more throughput, but then we
2262                  * have a dependency towards non-generic chip features
2263                  * to disable the TX-FIFO-EMPTY interrupts on a per
2264                  * endpoint basis. Increase the maximum buffer size of
2265                  * the IN endpoint to increase the performance.
2266                  */
2267                 if (td->npkt > mpkt) {
2268                         td->npkt = mpkt;
2269                         count = td->max_packet_size * mpkt;
2270                 } else if ((count == 0) || (count % td->max_packet_size)) {
2271                         /* we are transmitting a short packet */
2272                         td->npkt++;
2273                         td->short_pkt = 1;
2274                 }
2275         } else {
2276                 /* send one packet at a time */
2277                 mpkt = 1;
2278                 count = td->max_packet_size;
2279                 if (td->remainder < count) {
2280                         /* we have a short packet */
2281                         td->short_pkt = 1;
2282                         count = td->remainder;
2283                 }
2284                 td->npkt = 1;
2285         }
2286         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2287             DXEPTSIZ_SET_MULTI(1) |
2288             DXEPTSIZ_SET_NPKT(td->npkt) |
2289             DXEPTSIZ_SET_NBYTES(count));
2290
2291         /* make room for buffering */
2292         td->npkt += mpkt;
2293
2294         temp = sc->sc_in_ctl[td->ep_no];
2295
2296         /* check for isochronous mode */
2297         if ((temp & DIEPCTL_EPTYPE_MASK) ==
2298             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
2299                 /* toggle odd or even frame bit */
2300                 if (temp & DIEPCTL_SETD1PID) {
2301                         temp &= ~DIEPCTL_SETD1PID;
2302                         temp |= DIEPCTL_SETD0PID;
2303                 } else {
2304                         temp &= ~DIEPCTL_SETD0PID;
2305                         temp |= DIEPCTL_SETD1PID;
2306                 }
2307                 sc->sc_in_ctl[td->ep_no] = temp;
2308         }
2309
2310         /* must enable before writing data to FIFO */
2311         DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2312             DIEPCTL_EPENA | DIEPCTL_CNAK);
2313
2314         td->tx_bytes = count;
2315
2316         /* check remainder */
2317         if (td->tx_bytes == 0 &&
2318             td->remainder == 0) {
2319                 if (td->short_pkt)
2320                         return (0);     /* complete */
2321
2322                 /* else we need to transmit a short packet */
2323         }
2324         goto repeat;
2325
2326 not_complete:
2327         return (1);                     /* not complete */
2328 }
2329
2330 static uint8_t
2331 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2332 {
2333         uint32_t temp;
2334
2335         /*
2336          * If all packets are transferred we are complete:
2337          */
2338         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2339
2340         /* check that all packets have been transferred */
2341         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2342                 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2343                 goto not_complete;
2344         }
2345         return (0);
2346
2347 not_complete:
2348
2349         /* we only want to know if there is a SETUP packet or free IN packet */
2350
2351         temp = sc->sc_last_rx_status;
2352
2353         if ((td->ep_no == 0) && (temp != 0) &&
2354             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2355
2356                 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2357                     GRXSTSRD_STP_DATA ||
2358                     (temp & GRXSTSRD_PKTSTS_MASK) ==
2359                     GRXSTSRD_STP_COMPLETE) {
2360                         DPRINTFN(5, "faking complete\n");
2361                         /*
2362                          * Race condition: We are complete!
2363                          */
2364                         return (0);
2365                 } else {
2366                         /* dump data - wrong direction */
2367                         dwc_otg_common_rx_ack(sc);
2368                 }
2369         }
2370         return (1);                     /* not complete */
2371 }
2372
2373 static void
2374 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2375 {
2376         struct dwc_otg_td *td;
2377         uint8_t toggle;
2378         uint8_t tmr_val;
2379         uint8_t tmr_res;
2380
2381         DPRINTFN(9, "\n");
2382
2383         td = xfer->td_transfer_cache;
2384         if (td == NULL)
2385                 return;
2386
2387         while (1) {
2388                 if ((td->func) (sc, td)) {
2389                         /* operation in progress */
2390                         break;
2391                 }
2392                 if (((void *)td) == xfer->td_transfer_last) {
2393                         goto done;
2394                 }
2395                 if (td->error_any) {
2396                         goto done;
2397                 } else if (td->remainder > 0) {
2398                         /*
2399                          * We had a short transfer. If there is no alternate
2400                          * next, stop processing !
2401                          */
2402                         if (!td->alt_next)
2403                                 goto done;
2404                 }
2405
2406                 /*
2407                  * Fetch the next transfer descriptor and transfer
2408                  * some flags to the next transfer descriptor
2409                  */
2410                 tmr_res = td->tmr_res;
2411                 tmr_val = td->tmr_val;
2412                 toggle = td->toggle;
2413                 td = td->obj_next;
2414                 xfer->td_transfer_cache = td;
2415                 td->toggle = toggle;    /* transfer toggle */
2416                 td->tmr_res = tmr_res;
2417                 td->tmr_val = tmr_val;
2418         }
2419         return;
2420
2421 done:
2422         xfer->td_transfer_cache = NULL;
2423         sc->sc_xfer_complete = 1;
2424 }
2425
2426 static uint8_t
2427 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2428 {
2429         struct dwc_otg_td *td;
2430
2431         DPRINTFN(9, "\n");
2432
2433         td = xfer->td_transfer_cache;
2434         if (td == NULL) {
2435                 /* compute all actual lengths */
2436                 dwc_otg_standard_done(xfer);
2437                 return (1);
2438         }
2439         return (0);
2440 }
2441
2442 static void
2443 dwc_otg_timer(void *_sc)
2444 {
2445         struct dwc_otg_softc *sc = _sc;
2446
2447         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2448
2449         DPRINTF("\n");
2450
2451         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2452
2453         /* increment timer value */
2454         sc->sc_tmr_val++;
2455
2456         /* enable SOF interrupt, which will poll jobs */
2457         dwc_otg_enable_sof_irq(sc);
2458
2459         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2460
2461         if (sc->sc_timer_active) {
2462                 /* restart timer */
2463                 usb_callout_reset(&sc->sc_timer,
2464                     hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2465                     &dwc_otg_timer, sc);
2466         }
2467 }
2468
2469 static void
2470 dwc_otg_timer_start(struct dwc_otg_softc *sc)
2471 {
2472         if (sc->sc_timer_active != 0)
2473                 return;
2474
2475         sc->sc_timer_active = 1;
2476
2477         /* restart timer */
2478         usb_callout_reset(&sc->sc_timer,
2479             hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2480             &dwc_otg_timer, sc);
2481 }
2482
2483 static void
2484 dwc_otg_timer_stop(struct dwc_otg_softc *sc)
2485 {
2486         if (sc->sc_timer_active == 0)
2487                 return;
2488
2489         sc->sc_timer_active = 0;
2490
2491         /* stop timer */
2492         usb_callout_stop(&sc->sc_timer);
2493 }
2494
2495 static uint16_t
2496 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo)
2497 {
2498         if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2499                 pinfo->slot_index++;
2500         return (pinfo->slot_index);
2501 }
2502
2503 static uint8_t
2504 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc)
2505 {
2506         TAILQ_HEAD(, usb_xfer) head;
2507         struct usb_xfer *xfer;
2508         struct usb_xfer *xfer_next;
2509         struct dwc_otg_td *td;
2510         uint16_t temp;
2511         uint16_t slot;
2512
2513         temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2514
2515         if (sc->sc_last_frame_num == temp)
2516                 return (0);
2517
2518         sc->sc_last_frame_num = temp;
2519
2520         TAILQ_INIT(&head);
2521
2522         if ((temp & 7) == 0) {
2523
2524                 /* reset the schedule */
2525                 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2526
2527                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2528                         td = xfer->td_transfer_cache;
2529                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2530                                 continue;
2531
2532                         /* check for IN direction */
2533                         if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2534                                 continue;
2535
2536                         sc->sc_needsof = 1;
2537
2538                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2539                                 continue;
2540
2541                         /* compute slot */
2542                         slot = dwc_otg_compute_isoc_rx_tt_slot(
2543                             sc->sc_tt_info + td->tt_index);
2544                         if (slot > 3) {
2545                                 /*
2546                                  * Not enough time to get complete
2547                                  * split executed.
2548                                  */
2549                                 continue;
2550                         }
2551                         /* Delayed start */
2552                         td->tt_start_slot = temp + slot;
2553                         td->tt_scheduled = 1;
2554                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2555                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2556                 }
2557
2558                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2559                         td = xfer->td_transfer_cache;
2560                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2561                                 continue;
2562
2563                         /* check for OUT direction */
2564                         if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2565                                 continue;
2566
2567                         sc->sc_needsof = 1;
2568
2569                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2570                                 continue;
2571
2572                         /* Start ASAP */
2573                         td->tt_start_slot = temp;
2574                         td->tt_scheduled = 1;
2575                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2576                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2577                 }
2578
2579                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2580                         td = xfer->td_transfer_cache;
2581                         if (td == NULL || td->ep_type != UE_INTERRUPT)
2582                                 continue;
2583
2584                         if (td->tt_scheduled != 0) {
2585                                 sc->sc_needsof = 1;
2586                                 continue;
2587                         }
2588
2589                         if (dwc_otg_host_rate_check_interrupt(sc, td))
2590                                 continue;
2591
2592                         if (td->hcsplt == 0) {
2593                                 sc->sc_needsof = 1;
2594                                 td->tt_scheduled = 1;
2595                                 continue;
2596                         }
2597
2598                         /* start ASAP */
2599                         td->tt_start_slot = temp;
2600                         sc->sc_needsof = 1;
2601                         td->tt_scheduled = 1;
2602                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2603                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2604                 }
2605
2606                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2607                         td = xfer->td_transfer_cache;
2608                         if (td == NULL ||
2609                             td->ep_type != UE_CONTROL) {
2610                                 continue;
2611                         }
2612
2613                         sc->sc_needsof = 1;
2614
2615                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2616                                 continue;
2617
2618                         /* start ASAP */
2619                         td->tt_start_slot = temp;
2620                         td->tt_scheduled = 1;
2621                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2622                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2623                 }
2624         }
2625         if ((temp & 7) < 6) {
2626                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2627                         td = xfer->td_transfer_cache;
2628                         if (td == NULL ||
2629                             td->ep_type != UE_BULK) {
2630                                 continue;
2631                         }
2632
2633                         sc->sc_needsof = 1;
2634
2635                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2636                                 continue;
2637
2638                         /* start ASAP */
2639                         td->tt_start_slot = temp;
2640                         td->tt_scheduled = 1;
2641                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2642                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2643                 }
2644         }
2645
2646         /* Put TT transfers in execution order at the end */
2647         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2648
2649         /* move all TT transfers in front, keeping the current order */
2650         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2651                 td = xfer->td_transfer_cache;
2652                 if (td == NULL || td->hcsplt == 0)
2653                         continue;
2654                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2655                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2656         }
2657         TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2658         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2659
2660         /* put non-TT non-ISOCHRONOUS transfers last */
2661         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2662                 td = xfer->td_transfer_cache;
2663                 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS)
2664                         continue;
2665                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2666                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2667         }
2668         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2669
2670         if ((temp & 7) == 0) {
2671
2672                 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n",
2673                     (int)temp, (int)sc->sc_needsof);
2674
2675                 /* update SOF IRQ mask */
2676                 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2677                         if (sc->sc_needsof == 0) {
2678                                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2679                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2680                         }
2681                 } else {
2682                         if (sc->sc_needsof != 0) {
2683                                 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2684                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2685                         }
2686                 }
2687
2688                 /* clear need SOF flag */
2689                 sc->sc_needsof = 0;
2690         }
2691         return (1);
2692 }
2693
2694 static void
2695 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
2696 {
2697         struct usb_xfer *xfer;
2698         uint32_t count;
2699         uint32_t temp;
2700         uint32_t haint;
2701         uint8_t got_rx_status;
2702         uint8_t x;
2703
2704         if (sc->sc_flags.status_device_mode == 0) {
2705                 /*
2706                  * Update host transfer schedule, so that new
2707                  * transfers can be issued:
2708                  */
2709                 dwc_otg_update_host_transfer_schedule_locked(sc);
2710         }
2711         count = 0;
2712 repeat:
2713         if (++count == 16) {
2714                 /* give other interrupts a chance */
2715                 DPRINTF("Yield\n");
2716                 return;
2717         }
2718
2719         /* get all host channel interrupts */
2720         haint = DWC_OTG_READ_4(sc, DOTG_HAINT);
2721         while (1) {
2722                 x = ffs(haint) - 1;
2723                 if (x >= sc->sc_host_ch_max)
2724                         break;
2725                 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2726                 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2727                 temp &= ~HCINT_SOFTWARE_ONLY;
2728                 sc->sc_chan_state[x].hcint |= temp;
2729                 haint &= ~(1U << x);
2730         }
2731
2732         if (sc->sc_last_rx_status == 0) {
2733
2734                 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2735                 if (temp & GINTSTS_RXFLVL) {
2736                         /* pop current status */
2737                         sc->sc_last_rx_status =
2738                             DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
2739                 }
2740
2741                 if (sc->sc_last_rx_status != 0) {
2742
2743                         uint8_t ep_no;
2744
2745                         temp = sc->sc_last_rx_status &
2746                             GRXSTSRD_PKTSTS_MASK;
2747
2748                         /* non-data messages we simply skip */
2749                         if (temp != GRXSTSRD_STP_DATA &&
2750                             temp != GRXSTSRD_STP_COMPLETE &&
2751                             temp != GRXSTSRD_OUT_DATA) {
2752                                 /* check for halted channel */
2753                                 if (temp == GRXSTSRH_HALTED) {
2754                                         ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2755                                         sc->sc_chan_state[ep_no].wait_halted = 0;
2756                                         DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
2757                                 }
2758                                 /* store bytes and FIFO offset */
2759                                 sc->sc_current_rx_bytes = 0;
2760                                 sc->sc_current_rx_fifo = 0;
2761
2762                                 /* acknowledge status */
2763                                 dwc_otg_common_rx_ack(sc);
2764                                 goto repeat;
2765                         }
2766
2767                         temp = GRXSTSRD_BCNT_GET(
2768                             sc->sc_last_rx_status);
2769                         ep_no = GRXSTSRD_CHNUM_GET(
2770                             sc->sc_last_rx_status);
2771
2772                         /* store bytes and FIFO offset */
2773                         sc->sc_current_rx_bytes = (temp + 3) & ~3;
2774                         sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no);
2775
2776                         DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2777
2778                         /* check if we should dump the data */
2779                         if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2780                                 dwc_otg_common_rx_ack(sc);
2781                                 goto repeat;
2782                         }
2783
2784                         got_rx_status = 1;
2785
2786                         DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
2787                             sc->sc_last_rx_status, ep_no,
2788                             (sc->sc_last_rx_status >> 15) & 3,
2789                             GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2790                             (sc->sc_last_rx_status >> 17) & 15);
2791                 } else {
2792                         got_rx_status = 0;
2793                 }
2794         } else {
2795                 uint8_t ep_no;
2796
2797                 ep_no = GRXSTSRD_CHNUM_GET(
2798                     sc->sc_last_rx_status);
2799
2800                 /* check if we should dump the data */
2801                 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2802                         dwc_otg_common_rx_ack(sc);
2803                         goto repeat;
2804                 }
2805
2806                 got_rx_status = 1;
2807         }
2808
2809         /* execute FIFOs */
2810         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2811                 dwc_otg_xfer_do_fifo(sc, xfer);
2812
2813         if (got_rx_status) {
2814                 /* check if data was consumed */
2815                 if (sc->sc_last_rx_status == 0)
2816                         goto repeat;
2817
2818                 /* disable RX FIFO level interrupt */
2819                 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2820                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2821         }
2822 }
2823
2824 static void
2825 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc)
2826 {
2827         struct usb_xfer *xfer;
2828 repeat:
2829         /* scan for completion events */
2830         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2831                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
2832                         goto repeat;
2833         }
2834 }
2835
2836 static void
2837 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on)
2838 {
2839         DPRINTFN(5, "vbus = %u\n", is_on);
2840
2841         if (is_on) {
2842                 if (!sc->sc_flags.status_vbus) {
2843                         sc->sc_flags.status_vbus = 1;
2844
2845                         /* complete root HUB interrupt endpoint */
2846
2847                         dwc_otg_root_intr(sc);
2848                 }
2849         } else {
2850                 if (sc->sc_flags.status_vbus) {
2851                         sc->sc_flags.status_vbus = 0;
2852                         sc->sc_flags.status_bus_reset = 0;
2853                         sc->sc_flags.status_suspend = 0;
2854                         sc->sc_flags.change_suspend = 0;
2855                         sc->sc_flags.change_connect = 1;
2856
2857                         /* complete root HUB interrupt endpoint */
2858
2859                         dwc_otg_root_intr(sc);
2860                 }
2861         }
2862 }
2863
2864 int
2865 dwc_otg_filter_interrupt(void *arg)
2866 {
2867         struct dwc_otg_softc *sc = arg;
2868         int retval = FILTER_HANDLED;
2869         uint32_t status;
2870
2871         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2872
2873         /* read and clear interrupt status */
2874         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2875
2876         /* clear interrupts we are handling here */
2877         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ);
2878
2879         /* check for USB state change interrupts */
2880         if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0)
2881                 retval = FILTER_SCHEDULE_THREAD;
2882
2883         /* clear FIFO empty interrupts */
2884         if (status & sc->sc_irq_mask &
2885             (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) {
2886                 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2887                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2888         }
2889         /* clear all IN endpoint interrupts */
2890         if (status & GINTSTS_IEPINT) {
2891                 uint32_t temp;
2892                 uint8_t x;
2893
2894                 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2895                         temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2896                         /*
2897                          * NOTE: Need to clear all interrupt bits,
2898                          * because some appears to be unmaskable and
2899                          * can cause an interrupt loop:
2900                          */
2901                         if (temp != 0)
2902                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2903                 }
2904         }
2905
2906         /* poll FIFOs, if any */
2907         dwc_otg_interrupt_poll_locked(sc);
2908
2909         if (sc->sc_xfer_complete != 0)
2910                 retval = FILTER_SCHEDULE_THREAD;
2911
2912         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2913
2914         return (retval);
2915 }
2916
2917 void
2918 dwc_otg_interrupt(void *arg)
2919 {
2920         struct dwc_otg_softc *sc = arg;
2921         uint32_t status;
2922
2923         USB_BUS_LOCK(&sc->sc_bus);
2924         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2925
2926         /* read and clear interrupt status */
2927         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2928
2929         /* clear interrupts we are handling here */
2930         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ);
2931
2932         DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n",
2933             status, DWC_OTG_READ_4(sc, DOTG_HAINT),
2934             DWC_OTG_READ_4(sc, DOTG_HFNUM));
2935
2936         if (status & GINTSTS_USBRST) {
2937
2938                 /* set correct state */
2939                 sc->sc_flags.status_device_mode = 1;
2940                 sc->sc_flags.status_bus_reset = 0;
2941                 sc->sc_flags.status_suspend = 0;
2942                 sc->sc_flags.change_suspend = 0;
2943                 sc->sc_flags.change_connect = 1;
2944
2945                 /* Disable SOF interrupt */
2946                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2947                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2948
2949                 /* complete root HUB interrupt endpoint */
2950                 dwc_otg_root_intr(sc);
2951         }
2952
2953         /* check for any bus state change interrupts */
2954         if (status & GINTSTS_ENUMDONE) {
2955
2956                 uint32_t temp;
2957
2958                 DPRINTFN(5, "end of reset\n");
2959
2960                 /* set correct state */
2961                 sc->sc_flags.status_device_mode = 1;
2962                 sc->sc_flags.status_bus_reset = 1;
2963                 sc->sc_flags.status_suspend = 0;
2964                 sc->sc_flags.change_suspend = 0;
2965                 sc->sc_flags.change_connect = 1;
2966                 sc->sc_flags.status_low_speed = 0;
2967                 sc->sc_flags.port_enabled = 1;
2968
2969                 /* reset FIFOs */
2970                 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE);
2971
2972                 /* reset function address */
2973                 dwc_otg_set_address(sc, 0);
2974
2975                 /* figure out enumeration speed */
2976                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2977                 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2978                         sc->sc_flags.status_high_speed = 1;
2979                 else
2980                         sc->sc_flags.status_high_speed = 0;
2981
2982                 /*
2983                  * Disable resume and SOF interrupt, and enable
2984                  * suspend and RX frame interrupt:
2985                  */
2986                 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2987                 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2988                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2989
2990                 /* complete root HUB interrupt endpoint */
2991                 dwc_otg_root_intr(sc);
2992         }
2993
2994         if (status & GINTSTS_PRTINT) {
2995                 uint32_t hprt;
2996
2997                 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT);
2998
2999                 /* clear change bits */
3000                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & (
3001                     HPRT_PRTPWR | HPRT_PRTENCHNG |
3002                     HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) |
3003                     sc->sc_hprt_val);
3004
3005                 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt);
3006
3007                 sc->sc_flags.status_device_mode = 0;
3008
3009                 if (hprt & HPRT_PRTCONNSTS)
3010                         sc->sc_flags.status_bus_reset = 1;
3011                 else
3012                         sc->sc_flags.status_bus_reset = 0;
3013
3014                 if ((hprt & HPRT_PRTENCHNG) &&
3015                     (hprt & HPRT_PRTENA) == 0)
3016                         sc->sc_flags.change_enabled = 1;
3017
3018                 if (hprt & HPRT_PRTENA)
3019                         sc->sc_flags.port_enabled = 1;
3020                 else
3021                         sc->sc_flags.port_enabled = 0;
3022
3023                 if (hprt & HPRT_PRTOVRCURRCHNG)
3024                         sc->sc_flags.change_over_current = 1;
3025
3026                 if (hprt & HPRT_PRTOVRCURRACT)
3027                         sc->sc_flags.port_over_current = 1;
3028                 else
3029                         sc->sc_flags.port_over_current = 0;
3030
3031                 if (hprt & HPRT_PRTPWR)
3032                         sc->sc_flags.port_powered = 1;
3033                 else
3034                         sc->sc_flags.port_powered = 0;
3035
3036                 if (((hprt & HPRT_PRTSPD_MASK)
3037                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW)
3038                         sc->sc_flags.status_low_speed = 1;
3039                 else
3040                         sc->sc_flags.status_low_speed = 0;
3041
3042                 if (((hprt & HPRT_PRTSPD_MASK)
3043                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH)
3044                         sc->sc_flags.status_high_speed = 1;
3045                 else
3046                         sc->sc_flags.status_high_speed = 0;
3047
3048                 if (hprt & HPRT_PRTCONNDET)
3049                         sc->sc_flags.change_connect = 1;
3050
3051                 if (hprt & HPRT_PRTSUSP)
3052                         dwc_otg_suspend_irq(sc);
3053                 else
3054                         dwc_otg_resume_irq(sc);
3055
3056                 /* complete root HUB interrupt endpoint */
3057                 dwc_otg_root_intr(sc);
3058
3059                 /* update host frame interval */
3060                 dwc_otg_update_host_frame_interval(sc);
3061         }
3062
3063         /*
3064          * If resume and suspend is set at the same time we interpret
3065          * that like RESUME. Resume is set when there is at least 3
3066          * milliseconds of inactivity on the USB BUS.
3067          */
3068         if (status & GINTSTS_WKUPINT) {
3069
3070                 DPRINTFN(5, "resume interrupt\n");
3071
3072                 dwc_otg_resume_irq(sc);
3073
3074         } else if (status & GINTSTS_USBSUSP) {
3075
3076                 DPRINTFN(5, "suspend interrupt\n");
3077
3078                 dwc_otg_suspend_irq(sc);
3079         }
3080         /* check VBUS */
3081         if (status & (GINTSTS_USBSUSP |
3082             GINTSTS_USBRST |
3083             GINTMSK_OTGINTMSK |
3084             GINTSTS_SESSREQINT)) {
3085                 uint32_t temp;
3086
3087                 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3088
3089                 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3090
3091                 dwc_otg_vbus_interrupt(sc,
3092                     (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3093         }
3094
3095         if (sc->sc_xfer_complete != 0) {
3096                 sc->sc_xfer_complete = 0;
3097
3098                 /* complete FIFOs, if any */
3099                 dwc_otg_interrupt_complete_locked(sc);
3100         }
3101         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3102         USB_BUS_UNLOCK(&sc->sc_bus);
3103 }
3104
3105 static void
3106 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3107 {
3108         struct dwc_otg_td *td;
3109
3110         /* get current Transfer Descriptor */
3111         td = temp->td_next;
3112         temp->td = td;
3113
3114         /* prepare for next TD */
3115         temp->td_next = td->obj_next;
3116
3117         /* fill out the Transfer Descriptor */
3118         td->func = temp->func;
3119         td->pc = temp->pc;
3120         td->offset = temp->offset;
3121         td->remainder = temp->len;
3122         td->tx_bytes = 0;
3123         td->error_any = 0;
3124         td->error_stall = 0;
3125         td->npkt = 0;
3126         td->did_stall = temp->did_stall;
3127         td->short_pkt = temp->short_pkt;
3128         td->alt_next = temp->setup_alt_next;
3129         td->set_toggle = 0;
3130         td->got_short = 0;
3131         td->did_nak = 0;
3132         td->channel[0] = DWC_OTG_MAX_CHANNELS;
3133         td->channel[1] = DWC_OTG_MAX_CHANNELS;
3134         td->channel[2] = DWC_OTG_MAX_CHANNELS;
3135         td->state = 0;
3136         td->errcnt = 0;
3137         td->tt_scheduled = 0;
3138         td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
3139 }
3140
3141 static void
3142 dwc_otg_setup_standard_chain(struct usb_xfer *xfer)
3143 {
3144         struct dwc_otg_std_temp temp;
3145         struct dwc_otg_td *td;
3146         uint32_t x;
3147         uint8_t need_sync;
3148         uint8_t is_host;
3149
3150         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
3151             xfer->address, UE_GET_ADDR(xfer->endpointno),
3152             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
3153
3154         temp.max_frame_size = xfer->max_frame_size;
3155
3156         td = xfer->td_start[0];
3157         xfer->td_transfer_first = td;
3158         xfer->td_transfer_cache = td;
3159
3160         /* setup temp */
3161
3162         temp.pc = NULL;
3163         temp.td = NULL;
3164         temp.td_next = xfer->td_start[0];
3165         temp.offset = 0;
3166         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3167             xfer->flags_int.isochronous_xfr;
3168         temp.did_stall = !xfer->flags_int.control_stall;
3169
3170         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3171
3172         /* check if we should prepend a setup message */
3173
3174         if (xfer->flags_int.control_xfr) {
3175                 if (xfer->flags_int.control_hdr) {
3176
3177                         if (is_host)
3178                                 temp.func = &dwc_otg_host_setup_tx;
3179                         else
3180                                 temp.func = &dwc_otg_setup_rx;
3181
3182                         temp.len = xfer->frlengths[0];
3183                         temp.pc = xfer->frbuffers + 0;
3184                         temp.short_pkt = temp.len ? 1 : 0;
3185
3186                         /* check for last frame */
3187                         if (xfer->nframes == 1) {
3188                                 /* no STATUS stage yet, SETUP is last */
3189                                 if (xfer->flags_int.control_act)
3190                                         temp.setup_alt_next = 0;
3191                         }
3192
3193                         dwc_otg_setup_standard_chain_sub(&temp);
3194                 }
3195                 x = 1;
3196         } else {
3197                 x = 0;
3198         }
3199
3200         if (x != xfer->nframes) {
3201                 if (xfer->endpointno & UE_DIR_IN) {
3202                         if (is_host) {
3203                                 temp.func = &dwc_otg_host_data_rx;
3204                                 need_sync = 0;
3205                         } else {
3206                                 temp.func = &dwc_otg_data_tx;
3207                                 need_sync = 1;
3208                         }
3209                 } else {
3210                         if (is_host) {
3211                                 temp.func = &dwc_otg_host_data_tx;
3212                                 need_sync = 0;
3213                         } else {
3214                                 temp.func = &dwc_otg_data_rx;
3215                                 need_sync = 0;
3216                         }
3217                 }
3218
3219                 /* setup "pc" pointer */
3220                 temp.pc = xfer->frbuffers + x;
3221         } else {
3222                 need_sync = 0;
3223         }
3224         while (x != xfer->nframes) {
3225
3226                 /* DATA0 / DATA1 message */
3227
3228                 temp.len = xfer->frlengths[x];
3229
3230                 x++;
3231
3232                 if (x == xfer->nframes) {
3233                         if (xfer->flags_int.control_xfr) {
3234                                 if (xfer->flags_int.control_act) {
3235                                         temp.setup_alt_next = 0;
3236                                 }
3237                         } else {
3238                                 temp.setup_alt_next = 0;
3239                         }
3240                 }
3241                 if (temp.len == 0) {
3242
3243                         /* make sure that we send an USB packet */
3244
3245                         temp.short_pkt = 0;
3246
3247                 } else {
3248
3249                         /* regular data transfer */
3250
3251                         temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3252                 }
3253
3254                 dwc_otg_setup_standard_chain_sub(&temp);
3255
3256                 if (xfer->flags_int.isochronous_xfr) {
3257                         temp.offset += temp.len;
3258                 } else {
3259                         /* get next Page Cache pointer */
3260                         temp.pc = xfer->frbuffers + x;
3261                 }
3262         }
3263
3264         if (xfer->flags_int.control_xfr) {
3265
3266                 /* always setup a valid "pc" pointer for status and sync */
3267                 temp.pc = xfer->frbuffers + 0;
3268                 temp.len = 0;
3269                 temp.short_pkt = 0;
3270                 temp.setup_alt_next = 0;
3271
3272                 /* check if we need to sync */
3273                 if (need_sync) {
3274                         /* we need a SYNC point after TX */
3275                         temp.func = &dwc_otg_data_tx_sync;
3276                         dwc_otg_setup_standard_chain_sub(&temp);
3277                 }
3278
3279                 /* check if we should append a status stage */
3280                 if (!xfer->flags_int.control_act) {
3281
3282                         /*
3283                          * Send a DATA1 message and invert the current
3284                          * endpoint direction.
3285                          */
3286                         if (xfer->endpointno & UE_DIR_IN) {
3287                                 if (is_host) {
3288                                         temp.func = &dwc_otg_host_data_tx;
3289                                         need_sync = 0;
3290                                 } else {
3291                                         temp.func = &dwc_otg_data_rx;
3292                                         need_sync = 0;
3293                                 }
3294                         } else {
3295                                 if (is_host) {
3296                                         temp.func = &dwc_otg_host_data_rx;
3297                                         need_sync = 0;
3298                                 } else {
3299                                         temp.func = &dwc_otg_data_tx;
3300                                         need_sync = 1;
3301                                 }
3302                         }
3303
3304                         dwc_otg_setup_standard_chain_sub(&temp);
3305
3306                         /* data toggle should be DATA1 */
3307                         td = temp.td;
3308                         td->set_toggle = 1;
3309
3310                         if (need_sync) {
3311                                 /* we need a SYNC point after TX */
3312                                 temp.func = &dwc_otg_data_tx_sync;
3313                                 dwc_otg_setup_standard_chain_sub(&temp);
3314                         }
3315                 }
3316         } else {
3317                 /* check if we need to sync */
3318                 if (need_sync) {
3319
3320                         temp.pc = xfer->frbuffers + 0;
3321                         temp.len = 0;
3322                         temp.short_pkt = 0;
3323                         temp.setup_alt_next = 0;
3324
3325                         /* we need a SYNC point after TX */
3326                         temp.func = &dwc_otg_data_tx_sync;
3327                         dwc_otg_setup_standard_chain_sub(&temp);
3328                 }
3329         }
3330
3331         /* must have at least one frame! */
3332         td = temp.td;
3333         xfer->td_transfer_last = td;
3334
3335         if (is_host) {
3336
3337                 struct dwc_otg_softc *sc;
3338                 uint32_t hcchar;
3339                 uint32_t hcsplt;
3340
3341                 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3342
3343                 /* get first again */
3344                 td = xfer->td_transfer_first;
3345                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3346
3347                 hcchar =
3348                         (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3349                         ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3350                         (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3351                         HCCHAR_CHENA;
3352
3353                 /*
3354                  * We are not always able to meet the timing
3355                  * requirements of the USB interrupt endpoint's
3356                  * complete split token, when doing transfers going
3357                  * via a transaction translator. Use the CONTROL
3358                  * transfer type instead of the INTERRUPT transfer
3359                  * type in general, as a means to workaround
3360                  * that. This trick should work for both FULL and LOW
3361                  * speed USB traffic going through a TT. For non-TT
3362                  * traffic it works aswell. The reason for using
3363                  * CONTROL type instead of BULK is that some TTs might
3364                  * reject LOW speed BULK traffic.
3365                  */
3366                 if (td->ep_type == UE_INTERRUPT)
3367                         hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT);
3368                 else
3369                         hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3370
3371                 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3372                         hcchar |= HCCHAR_EPDIR_IN;
3373
3374                 switch (xfer->xroot->udev->speed) {
3375                 case USB_SPEED_LOW:
3376                         hcchar |= HCCHAR_LSPDDEV;
3377                         /* FALLTHROUGH */
3378                 case USB_SPEED_FULL:
3379                         /* check if root HUB port is running High Speed */
3380                         if (dwc_otg_uses_split(xfer->xroot->udev)) {
3381                                 hcsplt = HCSPLT_SPLTENA |
3382                                     (xfer->xroot->udev->hs_port_no <<
3383                                     HCSPLT_PRTADDR_SHIFT) |
3384                                     (xfer->xroot->udev->hs_hub_addr <<
3385                                     HCSPLT_HUBADDR_SHIFT);
3386                         } else {
3387                                 hcsplt = 0;
3388                         }
3389                         if (td->ep_type == UE_INTERRUPT) {
3390                                 uint32_t ival;
3391                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3392                                 if (ival == 0)
3393                                         ival = 1;
3394                                 else if (ival > 127)
3395                                         ival = 127;
3396                                 td->tmr_val = sc->sc_tmr_val + ival;
3397                                 td->tmr_res = ival;
3398                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3399                                 td->tmr_res = 1;
3400                                 td->tmr_val = sc->sc_last_frame_num;
3401                                 if (td->hcchar & HCCHAR_EPDIR_IN)
3402                                         td->tmr_val++;
3403                         } else {
3404                                 td->tmr_val = 0;
3405                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3406                         }
3407                         break;
3408                 case USB_SPEED_HIGH:
3409                         hcsplt = 0;
3410                         if (td->ep_type == UE_INTERRUPT) {
3411                                 uint32_t ival;
3412                                 hcchar |= ((xfer->max_packet_count & 3)
3413                                     << HCCHAR_MC_SHIFT);
3414                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3415                                 if (ival == 0)
3416                                         ival = 1;
3417                                 else if (ival > 127)
3418                                         ival = 127;
3419                                 td->tmr_val = sc->sc_tmr_val + ival;
3420                                 td->tmr_res = ival;
3421                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3422                                 hcchar |= ((xfer->max_packet_count & 3)
3423                                     << HCCHAR_MC_SHIFT);
3424                                 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3425                                 td->tmr_val = sc->sc_last_frame_num;
3426                                 if (td->hcchar & HCCHAR_EPDIR_IN)
3427                                         td->tmr_val += td->tmr_res;
3428
3429                         } else {
3430                                 td->tmr_val = 0;
3431                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3432                         }
3433                         break;
3434                 default:
3435                         hcsplt = 0;
3436                         td->tmr_val = 0;
3437                         td->tmr_res = 0;
3438                         break;
3439                 }
3440
3441                 /* store configuration in all TD's */
3442                 while (1) {
3443                         td->hcchar = hcchar;
3444                         td->hcsplt = hcsplt;
3445
3446                         if (((void *)td) == xfer->td_transfer_last)
3447                                 break;
3448
3449                         td = td->obj_next;
3450                 }
3451         }
3452 }
3453
3454 static void
3455 dwc_otg_timeout(void *arg)
3456 {
3457         struct usb_xfer *xfer = arg;
3458
3459         DPRINTF("xfer=%p\n", xfer);
3460
3461         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3462
3463         /* transfer is transferred */
3464         dwc_otg_device_done(xfer, USB_ERR_TIMEOUT);
3465 }
3466
3467 static void
3468 dwc_otg_start_standard_chain(struct usb_xfer *xfer)
3469 {
3470         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3471
3472         DPRINTFN(9, "\n");
3473
3474         /*
3475          * Poll one time in device mode, which will turn on the
3476          * endpoint interrupts. Else wait for SOF interrupt in host
3477          * mode.
3478          */
3479         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3480
3481         if (sc->sc_flags.status_device_mode != 0) {
3482                 dwc_otg_xfer_do_fifo(sc, xfer);
3483                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3484                         goto done;
3485         } else {
3486                 struct dwc_otg_td *td = xfer->td_transfer_cache;
3487                 if (td->ep_type == UE_ISOCHRONOUS &&
3488                     (td->hcchar & HCCHAR_EPDIR_IN) == 0) {
3489                         /*
3490                          * Need to start ISOCHRONOUS OUT transfer ASAP
3491                          * because execution is delayed by one 125us
3492                          * microframe:
3493                          */
3494                         dwc_otg_xfer_do_fifo(sc, xfer);
3495                         if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3496                                 goto done;
3497                 }
3498         }
3499
3500         /* put transfer on interrupt queue */
3501         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3502
3503         /* start timeout, if any */
3504         if (xfer->timeout != 0) {
3505                 usbd_transfer_timeout_ms(xfer,
3506                     &dwc_otg_timeout, xfer->timeout);
3507         }
3508
3509         if (sc->sc_flags.status_device_mode != 0)
3510                 goto done;
3511
3512         /* enable SOF interrupt, if any */
3513         dwc_otg_enable_sof_irq(sc);
3514 done:
3515         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3516 }
3517
3518 static void
3519 dwc_otg_root_intr(struct dwc_otg_softc *sc)
3520 {
3521         DPRINTFN(9, "\n");
3522
3523         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3524
3525         /* set port bit */
3526         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
3527
3528         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3529             sizeof(sc->sc_hub_idata));
3530 }
3531
3532 static usb_error_t
3533 dwc_otg_standard_done_sub(struct usb_xfer *xfer)
3534 {
3535         struct dwc_otg_td *td;
3536         uint32_t len;
3537         usb_error_t error;
3538
3539         DPRINTFN(9, "\n");
3540
3541         td = xfer->td_transfer_cache;
3542
3543         do {
3544                 len = td->remainder;
3545
3546                 /* store last data toggle */
3547                 xfer->endpoint->toggle_next = td->toggle;
3548
3549                 if (xfer->aframes != xfer->nframes) {
3550                         /*
3551                          * Verify the length and subtract
3552                          * the remainder from "frlengths[]":
3553                          */
3554                         if (len > xfer->frlengths[xfer->aframes]) {
3555                                 td->error_any = 1;
3556                         } else {
3557                                 xfer->frlengths[xfer->aframes] -= len;
3558                         }
3559                 }
3560                 /* Check for transfer error */
3561                 if (td->error_any) {
3562                         /* the transfer is finished */
3563                         error = (td->error_stall ?
3564                             USB_ERR_STALLED : USB_ERR_IOERROR);
3565                         td = NULL;
3566                         break;
3567                 }
3568                 /* Check for short transfer */
3569                 if (len > 0) {
3570                         if (xfer->flags_int.short_frames_ok ||
3571                             xfer->flags_int.isochronous_xfr) {
3572                                 /* follow alt next */
3573                                 if (td->alt_next) {
3574                                         td = td->obj_next;
3575                                 } else {
3576                                         td = NULL;
3577                                 }
3578                         } else {
3579                                 /* the transfer is finished */
3580                                 td = NULL;
3581                         }
3582                         error = 0;
3583                         break;
3584                 }
3585                 td = td->obj_next;
3586
3587                 /* this USB frame is complete */
3588                 error = 0;
3589                 break;
3590
3591         } while (0);
3592
3593         /* update transfer cache */
3594
3595         xfer->td_transfer_cache = td;
3596
3597         return (error);
3598 }
3599
3600 static void
3601 dwc_otg_standard_done(struct usb_xfer *xfer)
3602 {
3603         usb_error_t err = 0;
3604
3605         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
3606             xfer, xfer->endpoint);
3607
3608         /* reset scanner */
3609
3610         xfer->td_transfer_cache = xfer->td_transfer_first;
3611
3612         if (xfer->flags_int.control_xfr) {
3613
3614                 if (xfer->flags_int.control_hdr) {
3615
3616                         err = dwc_otg_standard_done_sub(xfer);
3617                 }
3618                 xfer->aframes = 1;
3619
3620                 if (xfer->td_transfer_cache == NULL) {
3621                         goto done;
3622                 }
3623         }
3624         while (xfer->aframes != xfer->nframes) {
3625
3626                 err = dwc_otg_standard_done_sub(xfer);
3627                 xfer->aframes++;
3628
3629                 if (xfer->td_transfer_cache == NULL) {
3630                         goto done;
3631                 }
3632         }
3633
3634         if (xfer->flags_int.control_xfr &&
3635             !xfer->flags_int.control_act) {
3636
3637                 err = dwc_otg_standard_done_sub(xfer);
3638         }
3639 done:
3640         dwc_otg_device_done(xfer, err);
3641 }
3642
3643 /*------------------------------------------------------------------------*
3644  *      dwc_otg_device_done
3645  *
3646  * NOTE: this function can be called more than one time on the
3647  * same USB transfer!
3648  *------------------------------------------------------------------------*/
3649 static void
3650 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
3651 {
3652         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3653
3654         DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
3655             xfer, xfer->endpoint, error);
3656
3657         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3658
3659         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3660                 /* Interrupts are cleared by the interrupt handler */
3661         } else {
3662                 struct dwc_otg_td *td;
3663
3664                 td = xfer->td_transfer_cache;
3665                 if (td != NULL)
3666                         dwc_otg_host_channel_free(sc, td);
3667         }
3668         /* dequeue transfer and start next transfer */
3669         usbd_transfer_done(xfer, error);
3670
3671         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3672 }
3673
3674 static void
3675 dwc_otg_xfer_stall(struct usb_xfer *xfer)
3676 {
3677         dwc_otg_device_done(xfer, USB_ERR_STALLED);
3678 }
3679
3680 static void
3681 dwc_otg_set_stall(struct usb_device *udev,
3682     struct usb_endpoint *ep, uint8_t *did_stall)
3683 {
3684         struct dwc_otg_softc *sc;
3685         uint32_t temp;
3686         uint32_t reg;
3687         uint8_t ep_no;
3688
3689         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3690
3691         /* check mode */
3692         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3693                 /* not supported */
3694                 return;
3695         }
3696
3697         sc = DWC_OTG_BUS2SC(udev->bus);
3698
3699         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3700
3701         /* get endpoint address */
3702         ep_no = ep->edesc->bEndpointAddress;
3703
3704         DPRINTFN(5, "endpoint=0x%x\n", ep_no);
3705
3706         if (ep_no & UE_DIR_IN) {
3707                 reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
3708                 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3709         } else {
3710                 reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
3711                 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3712         }
3713
3714         /* disable and stall endpoint */
3715         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3716         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3717
3718         /* clear active OUT ep */
3719         if (!(ep_no & UE_DIR_IN)) {
3720
3721                 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3722
3723                 if (sc->sc_last_rx_status != 0 &&
3724                     (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
3725                     sc->sc_last_rx_status)) {
3726                         /* dump data */
3727                         dwc_otg_common_rx_ack(sc);
3728                         /* poll interrupt */
3729                         dwc_otg_interrupt_poll_locked(sc);
3730                         dwc_otg_interrupt_complete_locked(sc);
3731                 }
3732         }
3733         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3734 }
3735
3736 static void
3737 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
3738     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
3739 {
3740         uint32_t reg;
3741         uint32_t temp;
3742
3743         if (ep_type == UE_CONTROL) {
3744                 /* clearing stall is not needed */
3745                 return;
3746         }
3747
3748         if (ep_dir) {
3749                 reg = DOTG_DIEPCTL(ep_no);
3750         } else {
3751                 reg = DOTG_DOEPCTL(ep_no);
3752                 sc->sc_active_rx_ep |= (1U << ep_no);
3753         }
3754
3755         /* round up and mask away the multiplier count */
3756         mps = (mps + 3) & 0x7FC;
3757
3758         if (ep_type == UE_BULK) {
3759                 temp = DIEPCTL_EPTYPE_SET(
3760                     DIEPCTL_EPTYPE_BULK) |
3761                     DIEPCTL_USBACTEP;
3762         } else if (ep_type == UE_INTERRUPT) {
3763                 temp = DIEPCTL_EPTYPE_SET(
3764                     DIEPCTL_EPTYPE_INTERRUPT) |
3765                     DIEPCTL_USBACTEP;
3766         } else {
3767                 temp = DIEPCTL_EPTYPE_SET(
3768                     DIEPCTL_EPTYPE_ISOC) |
3769                     DIEPCTL_USBACTEP;
3770         }
3771
3772         temp |= DIEPCTL_MPS_SET(mps);
3773         temp |= DIEPCTL_TXFNUM_SET(ep_no);
3774
3775         if (ep_dir)
3776                 sc->sc_in_ctl[ep_no] = temp;
3777         else
3778                 sc->sc_out_ctl[ep_no] = temp;
3779
3780         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3781         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3782         DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3783
3784         /* we only reset the transmit FIFO */
3785         if (ep_dir) {
3786                 dwc_otg_tx_fifo_reset(sc,
3787                     GRSTCTL_TXFIFO(ep_no) |
3788                     GRSTCTL_TXFFLSH);
3789
3790                 DWC_OTG_WRITE_4(sc,
3791                     DOTG_DIEPTSIZ(ep_no), 0);
3792         }
3793
3794         /* poll interrupt */
3795         dwc_otg_interrupt_poll_locked(sc);
3796         dwc_otg_interrupt_complete_locked(sc);
3797 }
3798
3799 static void
3800 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3801 {
3802         struct dwc_otg_softc *sc;
3803         struct usb_endpoint_descriptor *ed;
3804
3805         DPRINTFN(5, "endpoint=%p\n", ep);
3806
3807         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3808
3809         /* check mode */
3810         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3811                 /* not supported */
3812                 return;
3813         }
3814         /* get softc */
3815         sc = DWC_OTG_BUS2SC(udev->bus);
3816
3817         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3818
3819         /* get endpoint descriptor */
3820         ed = ep->edesc;
3821
3822         /* reset endpoint */
3823         dwc_otg_clear_stall_sub_locked(sc,
3824             UGETW(ed->wMaxPacketSize),
3825             (ed->bEndpointAddress & UE_ADDR),
3826             (ed->bmAttributes & UE_XFERTYPE),
3827             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3828
3829         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3830 }
3831
3832 static void
3833 dwc_otg_device_state_change(struct usb_device *udev)
3834 {
3835         struct dwc_otg_softc *sc;
3836         uint8_t x;
3837
3838         /* check mode */
3839         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3840                 /* not supported */
3841                 return;
3842         }
3843
3844         /* get softc */
3845         sc = DWC_OTG_BUS2SC(udev->bus);
3846
3847         /* deactivate all other endpoint but the control endpoint */
3848         if (udev->state == USB_STATE_CONFIGURED ||
3849             udev->state == USB_STATE_ADDRESSED) {
3850
3851                 USB_BUS_LOCK(&sc->sc_bus);
3852
3853                 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3854
3855                         if (x < sc->sc_dev_in_ep_max) {
3856                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
3857                                     DIEPCTL_EPDIS);
3858                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
3859                         }
3860
3861                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
3862                             DOEPCTL_EPDIS);
3863                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
3864                 }
3865                 USB_BUS_UNLOCK(&sc->sc_bus);
3866         }
3867 }
3868
3869 int
3870 dwc_otg_init(struct dwc_otg_softc *sc)
3871 {
3872         uint32_t temp;
3873
3874         DPRINTF("start\n");
3875
3876         /* set up the bus structure */
3877         sc->sc_bus.usbrev = USB_REV_2_0;
3878         sc->sc_bus.methods = &dwc_otg_bus_methods;
3879
3880         usb_callout_init_mtx(&sc->sc_timer,
3881             &sc->sc_bus.bus_mtx, 0);
3882
3883         USB_BUS_LOCK(&sc->sc_bus);
3884
3885         /* turn on clocks */
3886         dwc_otg_clocks_on(sc);
3887
3888         temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3889         DPRINTF("Version = 0x%08x\n", temp);
3890
3891         /* disconnect */
3892         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3893             DCTL_SFTDISCON);
3894
3895         /* wait for host to detect disconnect */
3896         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3897
3898         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
3899             GRSTCTL_CSFTRST);
3900
3901         /* wait a little bit for block to reset */
3902         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3903
3904         switch (sc->sc_mode) {
3905         case DWC_MODE_DEVICE:
3906                 temp = GUSBCFG_FORCEDEVMODE;
3907                 break;
3908         case DWC_MODE_HOST:
3909                 temp = GUSBCFG_FORCEHOSTMODE;
3910                 break;
3911         default:
3912                 temp = 0;
3913                 break;
3914         }
3915
3916         /* select HSIC, ULPI or internal PHY mode */
3917         switch (dwc_otg_phy_type) {
3918         case DWC_OTG_PHY_HSIC:
3919                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3920                     GUSBCFG_PHYIF |
3921                     GUSBCFG_TRD_TIM_SET(5) | temp);
3922                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
3923                     0x000000EC);
3924
3925                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3926                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3927                     temp & ~GLPMCFG_HSIC_CONN);
3928                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3929                     temp | GLPMCFG_HSIC_CONN);
3930                 break;
3931         case DWC_OTG_PHY_ULPI:
3932                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3933                     GUSBCFG_ULPI_UTMI_SEL |
3934                     GUSBCFG_TRD_TIM_SET(5) | temp);
3935                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3936
3937                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3938                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3939                     temp & ~GLPMCFG_HSIC_CONN);
3940                 break;
3941         case DWC_OTG_PHY_INTERNAL:
3942                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3943                     GUSBCFG_PHYSEL |
3944                     GUSBCFG_TRD_TIM_SET(5) | temp);
3945                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3946
3947                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3948                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3949                     temp & ~GLPMCFG_HSIC_CONN);
3950
3951                 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3952                 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3953                 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3954                     DOTG_GGPIO_PWRDWN);
3955                 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3956                 break;
3957         default:
3958                 break;
3959         }
3960
3961         /* clear global nak */
3962         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3963             DCTL_CGOUTNAK |
3964             DCTL_CGNPINNAK);
3965
3966         /* disable USB port */
3967         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF);
3968
3969         /* wait 10ms */
3970         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3971
3972         /* enable USB port */
3973         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
3974
3975         /* wait 10ms */
3976         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3977
3978         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3979
3980         sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3981
3982         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3983
3984         sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3985
3986         if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
3987                 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
3988
3989         sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3990
3991         if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
3992                 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
3993
3994         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
3995
3996         sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
3997
3998         DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n",
3999             sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
4000             sc->sc_host_ch_max);
4001
4002         /* setup FIFO */
4003         if (dwc_otg_init_fifo(sc, DWC_MODE_OTG)) {
4004                 USB_BUS_UNLOCK(&sc->sc_bus);
4005                 return (EINVAL);
4006         }
4007
4008         /* enable interrupts */
4009         sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ;
4010         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
4011
4012         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
4013
4014                 /* enable all endpoint interrupts */
4015                 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4016                 if (temp & GHWCFG2_MPI) {
4017                         uint8_t x;
4018
4019                         DPRINTF("Disable Multi Process Interrupts\n");
4020
4021                         for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
4022                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0);
4023                                 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
4024                         }
4025                         DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0);
4026                 }
4027                 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
4028                     DIEPMSK_XFERCOMPLMSK);
4029                 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
4030                 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
4031         }
4032
4033         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
4034                 /* setup clocks */
4035                 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4036                 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4037                 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4038                 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4039         }
4040
4041         /* only enable global IRQ */
4042         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
4043             GAHBCFG_GLBLINTRMSK);
4044
4045         /* turn off clocks */
4046         dwc_otg_clocks_off(sc);
4047
4048         /* read initial VBUS state */
4049
4050         temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4051
4052         DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4053
4054         dwc_otg_vbus_interrupt(sc,
4055             (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4056
4057         USB_BUS_UNLOCK(&sc->sc_bus);
4058
4059         /* catch any lost interrupts */
4060
4061         dwc_otg_do_poll(&sc->sc_bus);
4062
4063         return (0);                     /* success */
4064 }
4065
4066 void
4067 dwc_otg_uninit(struct dwc_otg_softc *sc)
4068 {
4069         USB_BUS_LOCK(&sc->sc_bus);
4070
4071         /* stop host timer */
4072         dwc_otg_timer_stop(sc);
4073
4074         /* set disconnect */
4075         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
4076             DCTL_SFTDISCON);
4077
4078         /* turn off global IRQ */
4079         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
4080
4081         sc->sc_flags.port_enabled = 0;
4082         sc->sc_flags.port_powered = 0;
4083         sc->sc_flags.status_vbus = 0;
4084         sc->sc_flags.status_bus_reset = 0;
4085         sc->sc_flags.status_suspend = 0;
4086         sc->sc_flags.change_suspend = 0;
4087         sc->sc_flags.change_connect = 1;
4088
4089         dwc_otg_pull_down(sc);
4090         dwc_otg_clocks_off(sc);
4091
4092         USB_BUS_UNLOCK(&sc->sc_bus);
4093
4094         usb_callout_drain(&sc->sc_timer);
4095 }
4096
4097 static void
4098 dwc_otg_suspend(struct dwc_otg_softc *sc)
4099 {
4100         return;
4101 }
4102
4103 static void
4104 dwc_otg_resume(struct dwc_otg_softc *sc)
4105 {
4106         return;
4107 }
4108
4109 static void
4110 dwc_otg_do_poll(struct usb_bus *bus)
4111 {
4112         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4113
4114         USB_BUS_LOCK(&sc->sc_bus);
4115         USB_BUS_SPIN_LOCK(&sc->sc_bus);
4116         dwc_otg_interrupt_poll_locked(sc);
4117         dwc_otg_interrupt_complete_locked(sc);
4118         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
4119         USB_BUS_UNLOCK(&sc->sc_bus);
4120 }
4121
4122 /*------------------------------------------------------------------------*
4123  * DWC OTG bulk support
4124  * DWC OTG control support
4125  * DWC OTG interrupt support
4126  *------------------------------------------------------------------------*/
4127 static void
4128 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer)
4129 {
4130 }
4131
4132 static void
4133 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer)
4134 {
4135         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4136 }
4137
4138 static void
4139 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer)
4140 {
4141 }
4142
4143 static void
4144 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer)
4145 {
4146         /* setup TDs */
4147         dwc_otg_setup_standard_chain(xfer);
4148         dwc_otg_start_standard_chain(xfer);
4149 }
4150
4151 struct usb_pipe_methods dwc_otg_device_non_isoc_methods =
4152 {
4153         .open = dwc_otg_device_non_isoc_open,
4154         .close = dwc_otg_device_non_isoc_close,
4155         .enter = dwc_otg_device_non_isoc_enter,
4156         .start = dwc_otg_device_non_isoc_start,
4157 };
4158
4159 /*------------------------------------------------------------------------*
4160  * DWC OTG full speed isochronous support
4161  *------------------------------------------------------------------------*/
4162 static void
4163 dwc_otg_device_isoc_open(struct usb_xfer *xfer)
4164 {
4165 }
4166
4167 static void
4168 dwc_otg_device_isoc_close(struct usb_xfer *xfer)
4169 {
4170         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4171 }
4172
4173 static void
4174 dwc_otg_device_isoc_enter(struct usb_xfer *xfer)
4175 {
4176 }
4177
4178 static void
4179 dwc_otg_device_isoc_start(struct usb_xfer *xfer)
4180 {
4181         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4182         uint32_t temp;
4183         uint32_t msframes;
4184         uint32_t framenum;
4185         uint8_t shift = usbd_xfer_get_fps_shift(xfer);
4186
4187         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
4188             xfer, xfer->endpoint->isoc_next, xfer->nframes);
4189
4190         if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4191                 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4192
4193                 /* get the current frame index */
4194                 framenum = (temp & HFNUM_FRNUM_MASK);
4195         } else {
4196                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4197
4198                 /* get the current frame index */
4199                 framenum = DSTS_SOFFN_GET(temp);
4200         }
4201
4202         /*
4203          * Check if port is doing 8000 or 1000 frames per second:
4204          */
4205         if (sc->sc_flags.status_high_speed)
4206                 framenum /= 8;
4207
4208         framenum &= DWC_OTG_FRAME_MASK;
4209
4210         /*
4211          * Compute number of milliseconds worth of data traffic for
4212          * this USB transfer:
4213          */
4214         if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
4215                 msframes = ((xfer->nframes << shift) + 7) / 8;
4216         else
4217                 msframes = xfer->nframes;
4218
4219         /*
4220          * check if the frame index is within the window where the frames
4221          * will be inserted
4222          */
4223         temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4224
4225         if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4226                 /*
4227                  * If there is data underflow or the pipe queue is
4228                  * empty we schedule the transfer a few frames ahead
4229                  * of the current frame position. Else two isochronous
4230                  * transfers might overlap.
4231                  */
4232                 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK;
4233                 xfer->endpoint->is_synced = 1;
4234                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4235         }
4236         /*
4237          * compute how many milliseconds the insertion is ahead of the
4238          * current frame position:
4239          */
4240         temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4241
4242         /*
4243          * pre-compute when the isochronous transfer will be finished:
4244          */
4245         xfer->isoc_time_complete =
4246                 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;
4247
4248         /* setup TDs */
4249         dwc_otg_setup_standard_chain(xfer);
4250
4251         /* compute frame number for next insertion */
4252         xfer->endpoint->isoc_next += msframes;
4253
4254         /* start TD chain */
4255         dwc_otg_start_standard_chain(xfer);
4256 }
4257
4258 struct usb_pipe_methods dwc_otg_device_isoc_methods =
4259 {
4260         .open = dwc_otg_device_isoc_open,
4261         .close = dwc_otg_device_isoc_close,
4262         .enter = dwc_otg_device_isoc_enter,
4263         .start = dwc_otg_device_isoc_start,
4264 };
4265
4266 /*------------------------------------------------------------------------*
4267  * DWC OTG root control support
4268  *------------------------------------------------------------------------*
4269  * Simulate a hardware HUB by handling all the necessary requests.
4270  *------------------------------------------------------------------------*/
4271
4272 static const struct usb_device_descriptor dwc_otg_devd = {
4273         .bLength = sizeof(struct usb_device_descriptor),
4274         .bDescriptorType = UDESC_DEVICE,
4275         .bcdUSB = {0x00, 0x02},
4276         .bDeviceClass = UDCLASS_HUB,
4277         .bDeviceSubClass = UDSUBCLASS_HUB,
4278         .bDeviceProtocol = UDPROTO_HSHUBSTT,
4279         .bMaxPacketSize = 64,
4280         .bcdDevice = {0x00, 0x01},
4281         .iManufacturer = 1,
4282         .iProduct = 2,
4283         .bNumConfigurations = 1,
4284 };
4285
4286 static const struct dwc_otg_config_desc dwc_otg_confd = {
4287         .confd = {
4288                 .bLength = sizeof(struct usb_config_descriptor),
4289                 .bDescriptorType = UDESC_CONFIG,
4290                 .wTotalLength[0] = sizeof(dwc_otg_confd),
4291                 .bNumInterface = 1,
4292                 .bConfigurationValue = 1,
4293                 .iConfiguration = 0,
4294                 .bmAttributes = UC_SELF_POWERED,
4295                 .bMaxPower = 0,
4296         },
4297         .ifcd = {
4298                 .bLength = sizeof(struct usb_interface_descriptor),
4299                 .bDescriptorType = UDESC_INTERFACE,
4300                 .bNumEndpoints = 1,
4301                 .bInterfaceClass = UICLASS_HUB,
4302                 .bInterfaceSubClass = UISUBCLASS_HUB,
4303                 .bInterfaceProtocol = 0,
4304         },
4305         .endpd = {
4306                 .bLength = sizeof(struct usb_endpoint_descriptor),
4307                 .bDescriptorType = UDESC_ENDPOINT,
4308                 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT),
4309                 .bmAttributes = UE_INTERRUPT,
4310                 .wMaxPacketSize[0] = 8,
4311                 .bInterval = 255,
4312         },
4313 };
4314
4315 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
4316
4317 static const struct usb_hub_descriptor_min dwc_otg_hubd = {
4318         .bDescLength = sizeof(dwc_otg_hubd),
4319         .bDescriptorType = UDESC_HUB,
4320         .bNbrPorts = 1,
4321         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
4322         .bPwrOn2PwrGood = 50,
4323         .bHubContrCurrent = 0,
4324         .DeviceRemovable = {0},         /* port is removable */
4325 };
4326
4327 #define STRING_VENDOR \
4328   "D\0W\0C\0O\0T\0G"
4329
4330 #define STRING_PRODUCT \
4331   "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
4332
4333 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor);
4334 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product);
4335
4336 static usb_error_t
4337 dwc_otg_roothub_exec(struct usb_device *udev,
4338     struct usb_device_request *req, const void **pptr, uint16_t *plength)
4339 {
4340         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4341         const void *ptr;
4342         uint16_t len;
4343         uint16_t value;
4344         uint16_t index;
4345         usb_error_t err;
4346
4347         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4348
4349         /* buffer reset */
4350         ptr = (const void *)&sc->sc_hub_temp;
4351         len = 0;
4352         err = 0;
4353
4354         value = UGETW(req->wValue);
4355         index = UGETW(req->wIndex);
4356
4357         /* demultiplex the control request */
4358
4359         switch (req->bmRequestType) {
4360         case UT_READ_DEVICE:
4361                 switch (req->bRequest) {
4362                 case UR_GET_DESCRIPTOR:
4363                         goto tr_handle_get_descriptor;
4364                 case UR_GET_CONFIG:
4365                         goto tr_handle_get_config;
4366                 case UR_GET_STATUS:
4367                         goto tr_handle_get_status;
4368                 default:
4369                         goto tr_stalled;
4370                 }
4371                 break;
4372
4373         case UT_WRITE_DEVICE:
4374                 switch (req->bRequest) {
4375                 case UR_SET_ADDRESS:
4376                         goto tr_handle_set_address;
4377                 case UR_SET_CONFIG:
4378                         goto tr_handle_set_config;
4379                 case UR_CLEAR_FEATURE:
4380                         goto tr_valid;  /* nop */
4381                 case UR_SET_DESCRIPTOR:
4382                         goto tr_valid;  /* nop */
4383                 case UR_SET_FEATURE:
4384                 default:
4385                         goto tr_stalled;
4386                 }
4387                 break;
4388
4389         case UT_WRITE_ENDPOINT:
4390                 switch (req->bRequest) {
4391                 case UR_CLEAR_FEATURE:
4392                         switch (UGETW(req->wValue)) {
4393                         case UF_ENDPOINT_HALT:
4394                                 goto tr_handle_clear_halt;
4395                         case UF_DEVICE_REMOTE_WAKEUP:
4396                                 goto tr_handle_clear_wakeup;
4397                         default:
4398                                 goto tr_stalled;
4399                         }
4400                         break;
4401                 case UR_SET_FEATURE:
4402                         switch (UGETW(req->wValue)) {
4403                         case UF_ENDPOINT_HALT:
4404                                 goto tr_handle_set_halt;
4405                         case UF_DEVICE_REMOTE_WAKEUP:
4406                                 goto tr_handle_set_wakeup;
4407                         default:
4408                                 goto tr_stalled;
4409                         }
4410                         break;
4411                 case UR_SYNCH_FRAME:
4412                         goto tr_valid;  /* nop */
4413                 default:
4414                         goto tr_stalled;
4415                 }
4416                 break;
4417
4418         case UT_READ_ENDPOINT:
4419                 switch (req->bRequest) {
4420                 case UR_GET_STATUS:
4421                         goto tr_handle_get_ep_status;
4422                 default:
4423                         goto tr_stalled;
4424                 }
4425                 break;
4426
4427         case UT_WRITE_INTERFACE:
4428                 switch (req->bRequest) {
4429                 case UR_SET_INTERFACE:
4430                         goto tr_handle_set_interface;
4431                 case UR_CLEAR_FEATURE:
4432                         goto tr_valid;  /* nop */
4433                 case UR_SET_FEATURE:
4434                 default:
4435                         goto tr_stalled;
4436                 }
4437                 break;
4438
4439         case UT_READ_INTERFACE:
4440                 switch (req->bRequest) {
4441                 case UR_GET_INTERFACE:
4442                         goto tr_handle_get_interface;
4443                 case UR_GET_STATUS:
4444                         goto tr_handle_get_iface_status;
4445                 default:
4446                         goto tr_stalled;
4447                 }
4448                 break;
4449
4450         case UT_WRITE_CLASS_INTERFACE:
4451         case UT_WRITE_VENDOR_INTERFACE:
4452                 /* XXX forward */
4453                 break;
4454
4455         case UT_READ_CLASS_INTERFACE:
4456         case UT_READ_VENDOR_INTERFACE:
4457                 /* XXX forward */
4458                 break;
4459
4460         case UT_WRITE_CLASS_DEVICE:
4461                 switch (req->bRequest) {
4462                 case UR_CLEAR_FEATURE:
4463                         goto tr_valid;
4464                 case UR_SET_DESCRIPTOR:
4465                 case UR_SET_FEATURE:
4466                         break;
4467                 default:
4468                         goto tr_stalled;
4469                 }
4470                 break;
4471
4472         case UT_WRITE_CLASS_OTHER:
4473                 switch (req->bRequest) {
4474                 case UR_CLEAR_FEATURE:
4475                         goto tr_handle_clear_port_feature;
4476                 case UR_SET_FEATURE:
4477                         goto tr_handle_set_port_feature;
4478                 case UR_CLEAR_TT_BUFFER:
4479                 case UR_RESET_TT:
4480                 case UR_STOP_TT:
4481                         goto tr_valid;
4482
4483                 default:
4484                         goto tr_stalled;
4485                 }
4486                 break;
4487
4488         case UT_READ_CLASS_OTHER:
4489                 switch (req->bRequest) {
4490                 case UR_GET_TT_STATE:
4491                         goto tr_handle_get_tt_state;
4492                 case UR_GET_STATUS:
4493                         goto tr_handle_get_port_status;
4494                 default:
4495                         goto tr_stalled;
4496                 }
4497                 break;
4498
4499         case UT_READ_CLASS_DEVICE:
4500                 switch (req->bRequest) {
4501                 case UR_GET_DESCRIPTOR:
4502                         goto tr_handle_get_class_descriptor;
4503                 case UR_GET_STATUS:
4504                         goto tr_handle_get_class_status;
4505
4506                 default:
4507                         goto tr_stalled;
4508                 }
4509                 break;
4510         default:
4511                 goto tr_stalled;
4512         }
4513         goto tr_valid;
4514
4515 tr_handle_get_descriptor:
4516         switch (value >> 8) {
4517         case UDESC_DEVICE:
4518                 if (value & 0xff) {
4519                         goto tr_stalled;
4520                 }
4521                 len = sizeof(dwc_otg_devd);
4522                 ptr = (const void *)&dwc_otg_devd;
4523                 goto tr_valid;
4524         case UDESC_CONFIG:
4525                 if (value & 0xff) {
4526                         goto tr_stalled;
4527                 }
4528                 len = sizeof(dwc_otg_confd);
4529                 ptr = (const void *)&dwc_otg_confd;
4530                 goto tr_valid;
4531         case UDESC_STRING:
4532                 switch (value & 0xff) {
4533                 case 0:         /* Language table */
4534                         len = sizeof(usb_string_lang_en);
4535                         ptr = (const void *)&usb_string_lang_en;
4536                         goto tr_valid;
4537
4538                 case 1:         /* Vendor */
4539                         len = sizeof(dwc_otg_vendor);
4540                         ptr = (const void *)&dwc_otg_vendor;
4541                         goto tr_valid;
4542
4543                 case 2:         /* Product */
4544                         len = sizeof(dwc_otg_product);
4545                         ptr = (const void *)&dwc_otg_product;
4546                         goto tr_valid;
4547                 default:
4548                         break;
4549                 }
4550                 break;
4551         default:
4552                 goto tr_stalled;
4553         }
4554         goto tr_stalled;
4555
4556 tr_handle_get_config:
4557         len = 1;
4558         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4559         goto tr_valid;
4560
4561 tr_handle_get_status:
4562         len = 2;
4563         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4564         goto tr_valid;
4565
4566 tr_handle_set_address:
4567         if (value & 0xFF00) {
4568                 goto tr_stalled;
4569         }
4570         sc->sc_rt_addr = value;
4571         goto tr_valid;
4572
4573 tr_handle_set_config:
4574         if (value >= 2) {
4575                 goto tr_stalled;
4576         }
4577         sc->sc_conf = value;
4578         goto tr_valid;
4579
4580 tr_handle_get_interface:
4581         len = 1;
4582         sc->sc_hub_temp.wValue[0] = 0;
4583         goto tr_valid;
4584
4585 tr_handle_get_tt_state:
4586 tr_handle_get_class_status:
4587 tr_handle_get_iface_status:
4588 tr_handle_get_ep_status:
4589         len = 2;
4590         USETW(sc->sc_hub_temp.wValue, 0);
4591         goto tr_valid;
4592
4593 tr_handle_set_halt:
4594 tr_handle_set_interface:
4595 tr_handle_set_wakeup:
4596 tr_handle_clear_wakeup:
4597 tr_handle_clear_halt:
4598         goto tr_valid;
4599
4600 tr_handle_clear_port_feature:
4601         if (index != 1)
4602                 goto tr_stalled;
4603
4604         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
4605
4606         switch (value) {
4607         case UHF_PORT_SUSPEND:
4608                 dwc_otg_wakeup_peer(sc);
4609                 break;
4610
4611         case UHF_PORT_ENABLE:
4612                 if (sc->sc_flags.status_device_mode == 0) {
4613                         DWC_OTG_WRITE_4(sc, DOTG_HPRT,
4614                             sc->sc_hprt_val | HPRT_PRTENA);
4615                 }
4616                 sc->sc_flags.port_enabled = 0;
4617                 break;
4618
4619         case UHF_C_PORT_RESET:
4620                 sc->sc_flags.change_reset = 0;
4621                 break;
4622
4623         case UHF_C_PORT_ENABLE:
4624                 sc->sc_flags.change_enabled = 0;
4625                 break;
4626
4627         case UHF_C_PORT_OVER_CURRENT:
4628                 sc->sc_flags.change_over_current = 0;
4629                 break;
4630
4631         case UHF_PORT_TEST:
4632         case UHF_PORT_INDICATOR:
4633                 /* nops */
4634                 break;
4635
4636         case UHF_PORT_POWER:
4637                 sc->sc_flags.port_powered = 0;
4638                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4639                         sc->sc_hprt_val = 0;
4640                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA);
4641                 }
4642                 dwc_otg_pull_down(sc);
4643                 dwc_otg_clocks_off(sc);
4644                 break;
4645
4646         case UHF_C_PORT_CONNECTION:
4647                 /* clear connect change flag */
4648                 sc->sc_flags.change_connect = 0;
4649                 break;
4650
4651         case UHF_C_PORT_SUSPEND:
4652                 sc->sc_flags.change_suspend = 0;
4653                 break;
4654
4655         default:
4656                 err = USB_ERR_IOERROR;
4657                 goto done;
4658         }
4659         goto tr_valid;
4660
4661 tr_handle_set_port_feature:
4662         if (index != 1) {
4663                 goto tr_stalled;
4664         }
4665         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
4666
4667         switch (value) {
4668         case UHF_PORT_ENABLE:
4669                 break;
4670
4671         case UHF_PORT_SUSPEND:
4672                 if (sc->sc_flags.status_device_mode == 0) {
4673                         /* set suspend BIT */
4674                         sc->sc_hprt_val |= HPRT_PRTSUSP;
4675                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4676
4677                         /* generate HUB suspend event */
4678                         dwc_otg_suspend_irq(sc);
4679                 }
4680                 break;
4681
4682         case UHF_PORT_RESET:
4683                 if (sc->sc_flags.status_device_mode == 0) {
4684
4685                         DPRINTF("PORT RESET\n");
4686
4687                         /* enable PORT reset */
4688                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4689
4690                         /* Wait 62.5ms for reset to complete */
4691                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4692
4693                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4694
4695                         /* Wait 62.5ms for reset to complete */
4696                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4697
4698                         /* reset FIFOs */
4699                         (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST);
4700
4701                         sc->sc_flags.change_reset = 1;
4702                 } else {
4703                         err = USB_ERR_IOERROR;
4704                 }
4705                 break;
4706
4707         case UHF_PORT_TEST:
4708         case UHF_PORT_INDICATOR:
4709                 /* nops */
4710                 break;
4711         case UHF_PORT_POWER:
4712                 sc->sc_flags.port_powered = 1;
4713                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4714                         sc->sc_hprt_val |= HPRT_PRTPWR;
4715                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4716                 }
4717                 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4718                         /* pull up D+, if any */
4719                         dwc_otg_pull_up(sc);
4720                 }
4721                 break;
4722         default:
4723                 err = USB_ERR_IOERROR;
4724                 goto done;
4725         }
4726         goto tr_valid;
4727
4728 tr_handle_get_port_status:
4729
4730         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
4731
4732         if (index != 1)
4733                 goto tr_stalled;
4734
4735         if (sc->sc_flags.status_vbus)
4736                 dwc_otg_clocks_on(sc);
4737         else
4738                 dwc_otg_clocks_off(sc);
4739
4740         /* Select Device Side Mode */
4741
4742         if (sc->sc_flags.status_device_mode) {
4743                 value = UPS_PORT_MODE_DEVICE;
4744                 dwc_otg_timer_stop(sc);
4745         } else {
4746                 value = 0;
4747                 dwc_otg_timer_start(sc);
4748         }
4749
4750         if (sc->sc_flags.status_high_speed)
4751                 value |= UPS_HIGH_SPEED;
4752         else if (sc->sc_flags.status_low_speed)
4753                 value |= UPS_LOW_SPEED;
4754
4755         if (sc->sc_flags.port_powered)
4756                 value |= UPS_PORT_POWER;
4757
4758         if (sc->sc_flags.port_enabled)
4759                 value |= UPS_PORT_ENABLED;
4760
4761         if (sc->sc_flags.port_over_current)
4762                 value |= UPS_OVERCURRENT_INDICATOR;
4763
4764         if (sc->sc_flags.status_vbus &&
4765             sc->sc_flags.status_bus_reset)
4766                 value |= UPS_CURRENT_CONNECT_STATUS;
4767
4768         if (sc->sc_flags.status_suspend)
4769                 value |= UPS_SUSPEND;
4770
4771         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4772
4773         value = 0;
4774
4775         if (sc->sc_flags.change_enabled)
4776                 value |= UPS_C_PORT_ENABLED;
4777         if (sc->sc_flags.change_connect)
4778                 value |= UPS_C_CONNECT_STATUS;
4779         if (sc->sc_flags.change_suspend)
4780                 value |= UPS_C_SUSPEND;
4781         if (sc->sc_flags.change_reset)
4782                 value |= UPS_C_PORT_RESET;
4783         if (sc->sc_flags.change_over_current)
4784                 value |= UPS_C_OVERCURRENT_INDICATOR;
4785
4786         USETW(sc->sc_hub_temp.ps.wPortChange, value);
4787         len = sizeof(sc->sc_hub_temp.ps);
4788         goto tr_valid;
4789
4790 tr_handle_get_class_descriptor:
4791         if (value & 0xFF) {
4792                 goto tr_stalled;
4793         }
4794         ptr = (const void *)&dwc_otg_hubd;
4795         len = sizeof(dwc_otg_hubd);
4796         goto tr_valid;
4797
4798 tr_stalled:
4799         err = USB_ERR_STALLED;
4800 tr_valid:
4801 done:
4802         *plength = len;
4803         *pptr = ptr;
4804         return (err);
4805 }
4806
4807 static void
4808 dwc_otg_xfer_setup(struct usb_setup_params *parm)
4809 {
4810         struct usb_xfer *xfer;
4811         void *last_obj;
4812         uint32_t ntd;
4813         uint32_t n;
4814         uint8_t ep_no;
4815         uint8_t ep_type;
4816
4817         xfer = parm->curr_xfer;
4818
4819         /*
4820          * NOTE: This driver does not use any of the parameters that
4821          * are computed from the following values. Just set some
4822          * reasonable dummies:
4823          */
4824         parm->hc_max_packet_size = 0x500;
4825         parm->hc_max_packet_count = 3;
4826         parm->hc_max_frame_size = 3 * 0x500;
4827
4828         usbd_transfer_setup_sub(parm);
4829
4830         /*
4831          * compute maximum number of TDs
4832          */
4833         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4834
4835         if (ep_type == UE_CONTROL) {
4836
4837                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4838                     + 1 /* SYNC 2 */ + 1 /* SYNC 3 */;
4839         } else {
4840
4841                 ntd = xfer->nframes + 1 /* SYNC */ ;
4842         }
4843
4844         /*
4845          * check if "usbd_transfer_setup_sub" set an error
4846          */
4847         if (parm->err)
4848                 return;
4849
4850         /*
4851          * allocate transfer descriptors
4852          */
4853         last_obj = NULL;
4854
4855         ep_no = xfer->endpointno & UE_ADDR;
4856
4857         /*
4858          * Check for a valid endpoint profile in USB device mode:
4859          */
4860         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4861                 const struct usb_hw_ep_profile *pf;
4862
4863                 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4864
4865                 if (pf == NULL) {
4866                         /* should not happen */
4867                         parm->err = USB_ERR_INVAL;
4868                         return;
4869                 }
4870         }
4871
4872         /* align data */
4873         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4874
4875         for (n = 0; n != ntd; n++) {
4876
4877                 struct dwc_otg_td *td;
4878
4879                 if (parm->buf) {
4880
4881                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4882
4883                         /* compute shared bandwidth resource index for TT */
4884                         if (dwc_otg_uses_split(parm->udev)) {
4885                                 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4886                                         td->tt_index = parm->udev->device_index;
4887                                 else
4888                                         td->tt_index = parm->udev->parent_hs_hub->device_index;
4889                         } else {
4890                                 td->tt_index = parm->udev->device_index;
4891                         }
4892
4893                         /* init TD */
4894                         td->max_packet_size = xfer->max_packet_size;
4895                         td->max_packet_count = xfer->max_packet_count;
4896                         /* range check */
4897                         if (td->max_packet_count == 0 || td->max_packet_count > 3)
4898                                 td->max_packet_count = 1;
4899                         td->ep_no = ep_no;
4900                         td->ep_type = ep_type;
4901                         td->obj_next = last_obj;
4902
4903                         last_obj = td;
4904                 }
4905                 parm->size[0] += sizeof(*td);
4906         }
4907
4908         xfer->td_start[0] = last_obj;
4909 }
4910
4911 static void
4912 dwc_otg_xfer_unsetup(struct usb_xfer *xfer)
4913 {
4914         return;
4915 }
4916
4917 static void
4918 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4919     struct usb_endpoint *ep)
4920 {
4921         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4922
4923         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
4924             ep, udev->address,
4925             edesc->bEndpointAddress, udev->flags.usb_mode,
4926             sc->sc_rt_addr, udev->device_index);
4927
4928         if (udev->device_index != sc->sc_rt_addr) {
4929
4930                 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4931                         if (udev->speed != USB_SPEED_FULL &&
4932                             udev->speed != USB_SPEED_HIGH) {
4933                                 /* not supported */
4934                                 return;
4935                         }
4936                 } else {
4937                         if (udev->speed == USB_SPEED_HIGH &&
4938                             (edesc->wMaxPacketSize[1] & 0x18) != 0 &&
4939                             (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
4940                                 /* not supported */
4941                                 DPRINTFN(-1, "Non-isochronous high bandwidth "
4942                                     "endpoint not supported\n");
4943                                 return;
4944                         }
4945                 }
4946                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4947                         ep->methods = &dwc_otg_device_isoc_methods;
4948                 else
4949                         ep->methods = &dwc_otg_device_non_isoc_methods;
4950         }
4951 }
4952
4953 static void
4954 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4955 {
4956         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4957
4958         switch (state) {
4959         case USB_HW_POWER_SUSPEND:
4960                 dwc_otg_suspend(sc);
4961                 break;
4962         case USB_HW_POWER_SHUTDOWN:
4963                 dwc_otg_uninit(sc);
4964                 break;
4965         case USB_HW_POWER_RESUME:
4966                 dwc_otg_resume(sc);
4967                 break;
4968         default:
4969                 break;
4970         }
4971 }
4972
4973 static void
4974 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4975 {
4976         /* DMA delay - wait until any use of memory is finished */
4977         *pus = (2125);                  /* microseconds */
4978 }
4979
4980 static void
4981 dwc_otg_device_resume(struct usb_device *udev)
4982 {
4983         DPRINTF("\n");
4984
4985         /* poll all transfers again to restart resumed ones */
4986         dwc_otg_do_poll(udev->bus);
4987 }
4988
4989 static void
4990 dwc_otg_device_suspend(struct usb_device *udev)
4991 {
4992         DPRINTF("\n");
4993 }
4994
4995 struct usb_bus_methods dwc_otg_bus_methods =
4996 {
4997         .endpoint_init = &dwc_otg_ep_init,
4998         .xfer_setup = &dwc_otg_xfer_setup,
4999         .xfer_unsetup = &dwc_otg_xfer_unsetup,
5000         .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile,
5001         .xfer_stall = &dwc_otg_xfer_stall,
5002         .set_stall = &dwc_otg_set_stall,
5003         .clear_stall = &dwc_otg_clear_stall,
5004         .roothub_exec = &dwc_otg_roothub_exec,
5005         .xfer_poll = &dwc_otg_do_poll,
5006         .device_state_change = &dwc_otg_device_state_change,
5007         .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep,
5008         .get_dma_delay = &dwc_otg_get_dma_delay,
5009         .device_resume = &dwc_otg_device_resume,
5010         .device_suspend = &dwc_otg_device_suspend,
5011 };