3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32)
31 #define DWC_OTG_FRAME_MASK 0x7FF
32 #define DWC_OTG_MAX_TXP 4
33 #define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP)
34 #define DWC_OTG_MAX_CHANNELS 16
35 #define DWC_OTG_MAX_ENDPOINTS 16
36 #define DWC_OTG_HOST_TIMER_RATE 10 /* ms */
37 #define DWC_OTG_TT_SLOT_MAX 8
38 #define DWC_OTG_SLOT_IDLE_MAX 4
39 #define DWC_OTG_SLOT_IDLE_MIN 2
40 #define DWC_OTG_NAK_MAX 8 /* 1 ms */
42 #define DWC_OTG_READ_4(sc, reg) \
43 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
45 #define DWC_OTG_WRITE_4(sc, reg, data) \
46 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
51 typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_softc *sc, struct dwc_otg_td *td);
54 struct dwc_otg_td *obj_next;
56 struct usb_page_cache *pc;
60 uint32_t hcchar; /* HOST CFG */
61 uint32_t hcsplt; /* HOST CFG */
62 uint16_t max_packet_size; /* packet_size */
64 uint8_t max_packet_count; /* packet_count */
68 uint8_t did_nak; /* NAK counter */
72 uint8_t tt_start_slot; /* TT data */
73 uint8_t tt_complete_slot; /* TT data */
74 uint8_t tt_xactpos; /* TT data */
76 #define DWC_CHAN_ST_START 0
77 #define DWC_CHAN_ST_WAIT_ANE 1
78 #define DWC_CHAN_ST_WAIT_S_ANE 2
79 #define DWC_CHAN_ST_WAIT_C_ANE 3
80 #define DWC_CHAN_ST_WAIT_C_PKT 4
81 #define DWC_CHAN_ST_TX_PKT_ISOC 5
82 #define DWC_CHAN_ST_TX_WAIT_ISOC 6
85 uint8_t error_stall:1;
92 uint8_t tt_scheduled:1;
93 uint8_t tt_channel_tog:1;
96 struct dwc_otg_std_temp {
98 struct usb_page_cache *pc;
99 struct dwc_otg_td *td;
100 struct dwc_otg_td *td_next;
103 uint16_t max_frame_size;
107 * short_pkt = 0: transfer should be short terminated
108 * short_pkt = 1: transfer should not be short terminated
110 uint8_t setup_alt_next;
112 uint8_t bulk_or_control;
115 struct dwc_otg_config_desc {
116 struct usb_config_descriptor confd;
117 struct usb_interface_descriptor ifcd;
118 struct usb_endpoint_descriptor endpd;
121 union dwc_otg_hub_temp {
123 struct usb_port_status ps;
126 struct dwc_otg_flags {
127 uint8_t change_connect:1;
128 uint8_t change_suspend:1;
129 uint8_t change_reset:1;
130 uint8_t change_enabled:1;
131 uint8_t change_over_current:1;
132 uint8_t status_suspend:1; /* set if suspended */
133 uint8_t status_vbus:1; /* set if present */
134 uint8_t status_bus_reset:1; /* set if reset complete */
135 uint8_t status_high_speed:1; /* set if High Speed is selected */
136 uint8_t status_low_speed:1; /* set if Low Speed is selected */
137 uint8_t status_device_mode:1; /* set if device mode */
138 uint8_t self_powered:1;
139 uint8_t clocks_off:1;
140 uint8_t port_powered:1;
141 uint8_t port_enabled:1;
142 uint8_t port_over_current:1;
143 uint8_t d_pulled_up:1;
146 struct dwc_otg_profile {
147 struct usb_hw_ep_profile usb;
151 struct dwc_otg_chan_state {
155 uint16_t tx_p_size; /* periodic */
156 uint16_t tx_np_size; /* non-periodic */
159 struct dwc_otg_softc {
160 struct usb_bus sc_bus;
161 union dwc_otg_hub_temp sc_hub_temp;
162 struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS];
163 struct usb_callout sc_timer;
165 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES];
166 struct resource *sc_io_res;
167 struct resource *sc_irq_res;
169 bus_size_t sc_io_size;
170 bus_space_tag_t sc_io_tag;
171 bus_space_handle_t sc_io_hdl;
173 uint32_t sc_rx_bounce_buffer[1024 / 4];
174 uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4];
176 uint32_t sc_fifo_size;
177 uint32_t sc_tx_max_size;
178 uint32_t sc_tx_cur_p_level; /* periodic */
179 uint32_t sc_tx_cur_np_level; /* non-periodic */
180 uint32_t sc_irq_mask;
181 uint32_t sc_last_rx_status;
182 uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS];
183 uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS];
184 struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS];
186 uint32_t sc_hprt_val;
187 uint32_t sc_xfer_complete;
189 uint16_t sc_active_rx_ep;
190 uint16_t sc_last_frame_num;
192 uint8_t sc_timer_active;
193 uint8_t sc_dev_ep_max;
194 uint8_t sc_dev_in_ep_max;
195 uint8_t sc_host_ch_max;
197 uint8_t sc_rt_addr; /* root HUB address */
198 uint8_t sc_conf; /* root HUB config */
199 uint8_t sc_mode; /* mode of operation */
200 #define DWC_MODE_OTG 0 /* both modes */
201 #define DWC_MODE_DEVICE 1 /* device only */
202 #define DWC_MODE_HOST 2 /* host only */
204 uint8_t sc_hub_idata[1];
206 struct dwc_otg_flags sc_flags;
211 driver_filter_t dwc_otg_filter_interrupt;
212 driver_intr_t dwc_otg_interrupt;
213 int dwc_otg_init(struct dwc_otg_softc *);
214 void dwc_otg_uninit(struct dwc_otg_softc *);
216 #endif /* _DWC_OTG_H_ */