2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
43 * 1) command failures are not recovered correctly
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD$");
49 #include <sys/stdint.h>
50 #include <sys/stddef.h>
51 #include <sys/param.h>
52 #include <sys/queue.h>
53 #include <sys/types.h>
54 #include <sys/systm.h>
55 #include <sys/kernel.h>
57 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/condvar.h>
61 #include <sys/sysctl.h>
63 #include <sys/unistd.h>
64 #include <sys/callout.h>
65 #include <sys/malloc.h>
68 #include <dev/usb/usb.h>
69 #include <dev/usb/usbdi.h>
71 #define USB_DEBUG_VAR ehcidebug
73 #include <dev/usb/usb_core.h>
74 #include <dev/usb/usb_debug.h>
75 #include <dev/usb/usb_busdma.h>
76 #include <dev/usb/usb_process.h>
77 #include <dev/usb/usb_transfer.h>
78 #include <dev/usb/usb_device.h>
79 #include <dev/usb/usb_hub.h>
80 #include <dev/usb/usb_util.h>
82 #include <dev/usb/usb_controller.h>
83 #include <dev/usb/usb_bus.h>
84 #include <dev/usb/controller/ehci.h>
85 #include <dev/usb/controller/ehcireg.h>
87 #define EHCI_BUS2SC(bus) \
88 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
89 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
92 static int ehcidebug = 0;
93 static int ehcinohighspeed = 0;
94 static int ehciiaadbug = 0;
95 static int ehcilostintrbug = 0;
97 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
99 &ehcidebug, 0, "Debug level");
100 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW | CTLFLAG_TUN,
102 &ehcinohighspeed, 0, "Disable High Speed USB");
103 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW | CTLFLAG_TUN,
105 &ehciiaadbug, 0, "Enable doorbell bug workaround");
106 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW | CTLFLAG_TUN,
108 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
109 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
112 static void ehci_dump_regs(ehci_softc_t *sc);
113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
117 #define EHCI_INTR_ENDPT 1
119 extern struct usb_bus_methods ehci_bus_methods;
120 extern struct usb_pipe_methods ehci_device_bulk_methods;
121 extern struct usb_pipe_methods ehci_device_ctrl_methods;
122 extern struct usb_pipe_methods ehci_device_intr_methods;
123 extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
124 extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
126 static void ehci_do_poll(struct usb_bus *);
127 static void ehci_device_done(struct usb_xfer *, usb_error_t);
128 static uint8_t ehci_check_transfer(struct usb_xfer *);
129 static void ehci_timeout(void *);
130 static void ehci_poll_timeout(void *);
132 static void ehci_root_intr(ehci_softc_t *sc);
134 struct ehci_std_temp {
136 struct usb_page_cache *pc;
142 uint16_t max_frame_size;
144 uint8_t auto_data_toggle;
145 uint8_t setup_alt_next;
150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
152 ehci_softc_t *sc = EHCI_BUS2SC(bus);
155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
162 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165 cb(bus, sc->sc_hw.intr_start_pc + i,
166 sc->sc_hw.intr_start_pg + i,
167 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
172 sc->sc_hw.isoc_hs_start_pg + i,
173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
178 sc->sc_hw.isoc_fs_start_pg + i,
179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
184 ehci_reset(ehci_softc_t *sc)
189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
190 for (i = 0; i < 100; i++) {
191 usb_pause_mtx(NULL, hz / 128);
192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
194 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
196 * Force USBMODE as requested. Controllers
197 * may have multiple operating modes.
199 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
200 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
201 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
202 device_printf(sc->sc_bus.bdev,
203 "set host controller mode\n");
205 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
206 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
207 device_printf(sc->sc_bus.bdev,
208 "set big-endian mode\n");
210 EOWRITE4(sc, EHCI_USBMODE, usbmode);
215 device_printf(sc->sc_bus.bdev, "Reset timeout\n");
216 return (USB_ERR_IOERROR);
220 ehci_hcreset(ehci_softc_t *sc)
225 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
226 for (i = 0; i < 100; i++) {
227 usb_pause_mtx(NULL, hz / 128);
228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
234 * Fall through and try reset anyway even though
235 * Table 2-9 in the EHCI spec says this will result
236 * in undefined behavior.
238 device_printf(sc->sc_bus.bdev, "stop timeout\n");
240 return (ehci_reset(sc));
244 ehci_init_sub(struct ehci_softc *sc)
246 struct usb_page_search buf_res;
251 cparams = EREAD4(sc, EHCI_HCCPARAMS);
253 DPRINTF("cparams=0x%x\n", cparams);
255 if (EHCI_HCC_64BIT(cparams)) {
256 DPRINTF("HCC uses 64-bit structures\n");
258 /* MUST clear segment register if 64 bit capable */
259 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
262 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
263 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
265 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
266 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
268 /* enable interrupts */
269 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
271 /* turn on controller */
272 EOWRITE4(sc, EHCI_USBCMD,
273 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
274 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
279 /* Take over port ownership */
280 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
282 for (i = 0; i < 100; i++) {
283 usb_pause_mtx(NULL, hz / 128);
284 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
290 device_printf(sc->sc_bus.bdev, "Run timeout\n");
291 return (USB_ERR_IOERROR);
293 return (USB_ERR_NORMAL_COMPLETION);
297 ehci_init(ehci_softc_t *sc)
299 struct usb_page_search buf_res;
310 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
311 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
313 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
317 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
319 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
325 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
326 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
327 version >> 8, version & 0xff);
329 sparams = EREAD4(sc, EHCI_HCSPARAMS);
330 DPRINTF("sparams=0x%x\n", sparams);
332 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
333 sc->sc_bus.usbrev = USB_REV_2_0;
335 /* Reset the controller */
336 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
338 err = ehci_hcreset(sc);
340 device_printf(sc->sc_bus.bdev, "reset timeout\n");
344 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
345 * bytes 2: 256*4 bytes 3: unknown
347 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
348 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
349 return (USB_ERR_IOERROR);
351 /* set up the bus struct */
352 sc->sc_bus.methods = &ehci_bus_methods;
354 sc->sc_eintrs = EHCI_NORMAL_INTRS;
357 struct ehci_qh_sub *qh;
359 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
363 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
365 /* init terminate TD */
367 htohc32(sc, EHCI_LINK_TERMINATE);
369 htohc32(sc, EHCI_LINK_TERMINATE);
371 htohc32(sc, EHCI_QTD_HALTED);
374 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
377 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
381 /* initialize page cache pointer */
383 qh->page_cache = sc->sc_hw.intr_start_pc + i;
385 /* store a pointer to queue head */
387 sc->sc_intr_p_last[i] = qh;
390 htohc32(sc, buf_res.physaddr) |
391 htohc32(sc, EHCI_LINK_QH);
394 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
396 htohc32(sc, EHCI_QH_SET_MULT(1));
399 qh->qh_qtd.qtd_next =
400 htohc32(sc, EHCI_LINK_TERMINATE);
401 qh->qh_qtd.qtd_altnext =
402 htohc32(sc, EHCI_LINK_TERMINATE);
403 qh->qh_qtd.qtd_status =
404 htohc32(sc, EHCI_QTD_HALTED);
408 * the QHs are arranged to give poll intervals that are
409 * powers of 2 times 1ms
411 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
418 y = (x ^ bit) | (bit / 2);
420 qh_x = sc->sc_intr_p_last[x];
421 qh_y = sc->sc_intr_p_last[y];
424 * the next QH has half the poll interval
426 qh_x->qh_link = qh_y->qh_self;
436 qh = sc->sc_intr_p_last[0];
438 /* the last (1ms) QH terminates */
439 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
441 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
445 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
447 sitd = buf_res.buffer;
449 /* initialize page cache pointer */
451 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
453 /* store a pointer to the transfer descriptor */
455 sc->sc_isoc_fs_p_last[i] = sitd;
457 /* initialize full speed isochronous */
460 htohc32(sc, buf_res.physaddr) |
461 htohc32(sc, EHCI_LINK_SITD);
464 htohc32(sc, EHCI_LINK_TERMINATE);
467 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
470 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
472 itd = buf_res.buffer;
474 /* initialize page cache pointer */
476 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
478 /* store a pointer to the transfer descriptor */
480 sc->sc_isoc_hs_p_last[i] = itd;
482 /* initialize high speed isochronous */
485 htohc32(sc, buf_res.physaddr) |
486 htohc32(sc, EHCI_LINK_ITD);
492 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
497 pframes = buf_res.buffer;
501 * pframes -> high speed isochronous ->
502 * full speed isochronous -> interrupt QH's
504 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
505 pframes[i] = sc->sc_isoc_hs_p_last
506 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
509 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
517 /* initialize page cache pointer */
519 qh->page_cache = &sc->sc_hw.async_start_pc;
521 /* store a pointer to the queue head */
523 sc->sc_async_p_last = qh;
525 /* init dummy QH that starts the async list */
528 htohc32(sc, buf_res.physaddr) |
529 htohc32(sc, EHCI_LINK_QH);
533 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
534 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
535 qh->qh_link = qh->qh_self;
538 /* fill the overlay qTD */
539 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
540 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
541 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
543 /* flush all cache into memory */
545 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
549 ehci_dump_sqh(sc, sc->sc_async_p_last);
554 err = ehci_init_sub(sc);
557 /* catch any lost interrupts */
558 ehci_do_poll(&sc->sc_bus);
564 * shut down the controller when the system is going down
567 ehci_detach(ehci_softc_t *sc)
569 USB_BUS_LOCK(&sc->sc_bus);
571 usb_callout_stop(&sc->sc_tmo_pcd);
572 usb_callout_stop(&sc->sc_tmo_poll);
574 EOWRITE4(sc, EHCI_USBINTR, 0);
575 USB_BUS_UNLOCK(&sc->sc_bus);
577 if (ehci_hcreset(sc)) {
578 DPRINTF("reset failed!\n");
581 /* XXX let stray task complete */
582 usb_pause_mtx(NULL, hz / 20);
584 usb_callout_drain(&sc->sc_tmo_pcd);
585 usb_callout_drain(&sc->sc_tmo_poll);
589 ehci_suspend(ehci_softc_t *sc)
591 DPRINTF("stopping the HC\n");
598 ehci_resume(ehci_softc_t *sc)
606 /* catch any lost interrupts */
607 ehci_do_poll(&sc->sc_bus);
612 ehci_dump_regs(ehci_softc_t *sc)
616 i = EOREAD4(sc, EHCI_USBCMD);
617 printf("cmd=0x%08x\n", i);
619 if (i & EHCI_CMD_ITC_1)
620 printf(" EHCI_CMD_ITC_1\n");
621 if (i & EHCI_CMD_ITC_2)
622 printf(" EHCI_CMD_ITC_2\n");
623 if (i & EHCI_CMD_ITC_4)
624 printf(" EHCI_CMD_ITC_4\n");
625 if (i & EHCI_CMD_ITC_8)
626 printf(" EHCI_CMD_ITC_8\n");
627 if (i & EHCI_CMD_ITC_16)
628 printf(" EHCI_CMD_ITC_16\n");
629 if (i & EHCI_CMD_ITC_32)
630 printf(" EHCI_CMD_ITC_32\n");
631 if (i & EHCI_CMD_ITC_64)
632 printf(" EHCI_CMD_ITC_64\n");
633 if (i & EHCI_CMD_ASPME)
634 printf(" EHCI_CMD_ASPME\n");
635 if (i & EHCI_CMD_ASPMC)
636 printf(" EHCI_CMD_ASPMC\n");
637 if (i & EHCI_CMD_LHCR)
638 printf(" EHCI_CMD_LHCR\n");
639 if (i & EHCI_CMD_IAAD)
640 printf(" EHCI_CMD_IAAD\n");
641 if (i & EHCI_CMD_ASE)
642 printf(" EHCI_CMD_ASE\n");
643 if (i & EHCI_CMD_PSE)
644 printf(" EHCI_CMD_PSE\n");
645 if (i & EHCI_CMD_FLS_M)
646 printf(" EHCI_CMD_FLS_M\n");
647 if (i & EHCI_CMD_HCRESET)
648 printf(" EHCI_CMD_HCRESET\n");
650 printf(" EHCI_CMD_RS\n");
652 i = EOREAD4(sc, EHCI_USBSTS);
654 printf("sts=0x%08x\n", i);
656 if (i & EHCI_STS_ASS)
657 printf(" EHCI_STS_ASS\n");
658 if (i & EHCI_STS_PSS)
659 printf(" EHCI_STS_PSS\n");
660 if (i & EHCI_STS_REC)
661 printf(" EHCI_STS_REC\n");
662 if (i & EHCI_STS_HCH)
663 printf(" EHCI_STS_HCH\n");
664 if (i & EHCI_STS_IAA)
665 printf(" EHCI_STS_IAA\n");
666 if (i & EHCI_STS_HSE)
667 printf(" EHCI_STS_HSE\n");
668 if (i & EHCI_STS_FLR)
669 printf(" EHCI_STS_FLR\n");
670 if (i & EHCI_STS_PCD)
671 printf(" EHCI_STS_PCD\n");
672 if (i & EHCI_STS_ERRINT)
673 printf(" EHCI_STS_ERRINT\n");
674 if (i & EHCI_STS_INT)
675 printf(" EHCI_STS_INT\n");
677 printf("ien=0x%08x\n",
678 EOREAD4(sc, EHCI_USBINTR));
679 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
680 EOREAD4(sc, EHCI_FRINDEX),
681 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
682 EOREAD4(sc, EHCI_PERIODICLISTBASE),
683 EOREAD4(sc, EHCI_ASYNCLISTADDR));
684 for (i = 1; i <= sc->sc_noport; i++) {
685 printf("port %d status=0x%08x\n", i,
686 EOREAD4(sc, EHCI_PORTSC(i)));
691 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
693 link = hc32toh(sc, link);
694 printf("0x%08x", link);
695 if (link & EHCI_LINK_TERMINATE)
700 switch (EHCI_LINK_TYPE(link)) {
720 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
725 ehci_dump_link(sc, qtd->qtd_next, 0);
727 ehci_dump_link(sc, qtd->qtd_altnext, 0);
729 s = hc32toh(sc, qtd->qtd_status);
730 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
731 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
732 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
733 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
734 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
735 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
736 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
737 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
738 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
739 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
740 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
741 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
742 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
744 for (s = 0; s < 5; s++) {
745 printf(" buffer[%d]=0x%08x\n", s,
746 hc32toh(sc, qtd->qtd_buffer[s]));
748 for (s = 0; s < 5; s++) {
749 printf(" buffer_hi[%d]=0x%08x\n", s,
750 hc32toh(sc, qtd->qtd_buffer_hi[s]));
755 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
759 usb_pc_cpu_invalidate(sqtd->page_cache);
760 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
761 ehci_dump_qtd(sc, sqtd);
762 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
767 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
773 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
774 stop = ehci_dump_sqtd(sc, sqtd);
777 printf("dump aborted, too many TDs\n");
782 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
787 usb_pc_cpu_invalidate(qh->page_cache);
788 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
790 ehci_dump_link(sc, qh->qh_link, 1);
792 endp = hc32toh(sc, qh->qh_endp);
793 printf(" endp=0x%08x\n", endp);
794 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
795 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
796 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
797 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
798 printf(" mpl=0x%x ctl=%d nrl=%d\n",
799 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
800 EHCI_QH_GET_NRL(endp));
801 endphub = hc32toh(sc, qh->qh_endphub);
802 printf(" endphub=0x%08x\n", endphub);
803 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
804 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
805 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
806 EHCI_QH_GET_MULT(endphub));
808 ehci_dump_link(sc, qh->qh_curqtd, 0);
810 printf("Overlay qTD:\n");
811 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
815 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
817 usb_pc_cpu_invalidate(sitd->page_cache);
818 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
819 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
820 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
821 hc32toh(sc, sitd->sitd_portaddr),
822 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
824 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
825 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
826 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
827 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
828 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
829 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
830 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
831 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
832 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
833 hc32toh(sc, sitd->sitd_back),
834 hc32toh(sc, sitd->sitd_bp[0]),
835 hc32toh(sc, sitd->sitd_bp[1]),
836 hc32toh(sc, sitd->sitd_bp_hi[0]),
837 hc32toh(sc, sitd->sitd_bp_hi[1]));
841 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
843 usb_pc_cpu_invalidate(itd->page_cache);
844 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
845 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
846 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
847 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
848 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
849 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
850 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
851 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
852 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
853 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
854 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
855 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
856 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
857 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
858 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
859 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
860 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
861 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
862 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
863 printf(" addr=0x%02x; endpt=0x%01x\n",
864 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
865 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
866 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
867 printf(" dir=%s; mpl=0x%02x\n",
868 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
869 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
870 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
871 hc32toh(sc, itd->itd_bp[2]),
872 hc32toh(sc, itd->itd_bp[3]),
873 hc32toh(sc, itd->itd_bp[4]),
874 hc32toh(sc, itd->itd_bp[5]),
875 hc32toh(sc, itd->itd_bp[6]));
876 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
877 " 0x%08x,0x%08x,0x%08x\n",
878 hc32toh(sc, itd->itd_bp_hi[0]),
879 hc32toh(sc, itd->itd_bp_hi[1]),
880 hc32toh(sc, itd->itd_bp_hi[2]),
881 hc32toh(sc, itd->itd_bp_hi[3]),
882 hc32toh(sc, itd->itd_bp_hi[4]),
883 hc32toh(sc, itd->itd_bp_hi[5]),
884 hc32toh(sc, itd->itd_bp_hi[6]));
888 ehci_dump_isoc(ehci_softc_t *sc)
895 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
896 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
898 printf("%s: isochronous dump from frame 0x%03x:\n",
901 itd = sc->sc_isoc_hs_p_last[pos];
902 sitd = sc->sc_isoc_fs_p_last[pos];
904 while (itd && max && max--) {
905 ehci_dump_itd(sc, itd);
909 while (sitd && max && max--) {
910 ehci_dump_sitd(sc, sitd);
918 ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
920 /* check for early completion */
921 if (ehci_check_transfer(xfer)) {
924 /* put transfer on interrupt queue */
925 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
927 /* start timeout, if any */
928 if (xfer->timeout != 0) {
929 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
933 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
935 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
937 DPRINTFN(11, "%p to %p\n", std, last);
939 /* (sc->sc_bus.mtx) must be locked */
941 std->next = last->next;
942 std->sitd_next = last->sitd_next;
946 usb_pc_cpu_flush(std->page_cache);
949 * the last->next->prev is never followed: std->next->prev = std;
952 last->sitd_next = std->sitd_self;
954 usb_pc_cpu_flush(last->page_cache);
959 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
961 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
963 DPRINTFN(11, "%p to %p\n", std, last);
965 /* (sc->sc_bus.mtx) must be locked */
967 std->next = last->next;
968 std->itd_next = last->itd_next;
972 usb_pc_cpu_flush(std->page_cache);
975 * the last->next->prev is never followed: std->next->prev = std;
978 last->itd_next = std->itd_self;
980 usb_pc_cpu_flush(last->page_cache);
985 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
987 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
989 DPRINTFN(11, "%p to %p\n", sqh, last);
991 if (sqh->prev != NULL) {
992 /* should not happen */
993 DPRINTFN(0, "QH already linked!\n");
996 /* (sc->sc_bus.mtx) must be locked */
998 sqh->next = last->next;
999 sqh->qh_link = last->qh_link;
1003 usb_pc_cpu_flush(sqh->page_cache);
1006 * the last->next->prev is never followed: sqh->next->prev = sqh;
1010 last->qh_link = sqh->qh_self;
1012 usb_pc_cpu_flush(last->page_cache);
1017 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1018 static ehci_sitd_t *
1019 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1021 DPRINTFN(11, "%p from %p\n", std, last);
1023 /* (sc->sc_bus.mtx) must be locked */
1025 std->prev->next = std->next;
1026 std->prev->sitd_next = std->sitd_next;
1028 usb_pc_cpu_flush(std->prev->page_cache);
1031 std->next->prev = std->prev;
1032 usb_pc_cpu_flush(std->next->page_cache);
1034 return ((last == std) ? std->prev : last);
1037 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1039 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1041 DPRINTFN(11, "%p from %p\n", std, last);
1043 /* (sc->sc_bus.mtx) must be locked */
1045 std->prev->next = std->next;
1046 std->prev->itd_next = std->itd_next;
1048 usb_pc_cpu_flush(std->prev->page_cache);
1051 std->next->prev = std->prev;
1052 usb_pc_cpu_flush(std->next->page_cache);
1054 return ((last == std) ? std->prev : last);
1057 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1059 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1061 DPRINTFN(11, "%p from %p\n", sqh, last);
1063 /* (sc->sc_bus.mtx) must be locked */
1065 /* only remove if not removed from a queue */
1068 sqh->prev->next = sqh->next;
1069 sqh->prev->qh_link = sqh->qh_link;
1071 usb_pc_cpu_flush(sqh->prev->page_cache);
1074 sqh->next->prev = sqh->prev;
1075 usb_pc_cpu_flush(sqh->next->page_cache);
1077 last = ((last == sqh) ? sqh->prev : last);
1081 usb_pc_cpu_flush(sqh->page_cache);
1087 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1092 /* count number of full packets */
1093 dt = (actlen / xfer->max_packet_size) & 1;
1095 /* compute remainder */
1096 rem = actlen % xfer->max_packet_size;
1099 dt ^= 1; /* short packet at the end */
1100 else if (actlen != xlen)
1101 dt ^= 1; /* zero length packet at the end */
1103 dt ^= 1; /* zero length transfer */
1105 xfer->endpoint->toggle_next ^= dt;
1109 ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1111 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1113 ehci_qtd_t *td_alt_next;
1117 td = xfer->td_transfer_cache;
1118 td_alt_next = td->alt_next;
1120 if (xfer->aframes != xfer->nframes) {
1121 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1125 usb_pc_cpu_invalidate(td->page_cache);
1126 status = hc32toh(sc, td->qtd_status);
1128 len = EHCI_QTD_GET_BYTES(status);
1131 * Verify the status length and
1132 * add the length to "frlengths[]":
1134 if (len > td->len) {
1135 /* should not happen */
1136 DPRINTF("Invalid status length, "
1137 "0x%04x/0x%04x bytes\n", len, td->len);
1138 status |= EHCI_QTD_HALTED;
1139 } else if (xfer->aframes != xfer->nframes) {
1140 xfer->frlengths[xfer->aframes] += td->len - len;
1141 /* manually update data toggle */
1142 ehci_data_toggle_update(xfer, td->len - len, td->len);
1145 /* Check for last transfer */
1146 if (((void *)td) == xfer->td_transfer_last) {
1150 /* Check for transfer error */
1151 if (status & EHCI_QTD_HALTED) {
1152 /* the transfer is finished */
1156 /* Check for short transfer */
1158 if (xfer->flags_int.short_frames_ok) {
1159 /* follow alt next */
1162 /* the transfer is finished */
1169 if (td->alt_next != td_alt_next) {
1170 /* this USB frame is complete */
1175 /* update transfer cache */
1177 xfer->td_transfer_cache = td;
1180 if (status & EHCI_QTD_STATERRS) {
1181 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1182 "status=%s%s%s%s%s%s%s%s\n",
1183 xfer->address, xfer->endpointno, xfer->aframes,
1184 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1185 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1186 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1187 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1188 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1189 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1190 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1191 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1194 if (status & EHCI_QTD_HALTED) {
1195 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1196 (xfer->xroot->udev->address != 0)) {
1197 /* try to separate I/O errors from STALL */
1198 if (EHCI_QTD_GET_CERR(status) == 0)
1199 return (USB_ERR_IOERROR);
1201 return (USB_ERR_STALLED);
1203 return (USB_ERR_NORMAL_COMPLETION);
1207 ehci_non_isoc_done(struct usb_xfer *xfer)
1209 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1212 usb_error_t err = 0;
1214 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1215 xfer, xfer->endpoint);
1218 if (ehcidebug > 10) {
1219 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1221 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1225 /* extract data toggle directly from the QH's overlay area */
1227 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1229 usb_pc_cpu_invalidate(qh->page_cache);
1231 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1235 xfer->td_transfer_cache = xfer->td_transfer_first;
1237 if (xfer->flags_int.control_xfr) {
1239 if (xfer->flags_int.control_hdr) {
1241 err = ehci_non_isoc_done_sub(xfer);
1245 if (xfer->td_transfer_cache == NULL) {
1249 while (xfer->aframes != xfer->nframes) {
1251 err = ehci_non_isoc_done_sub(xfer);
1254 if (xfer->td_transfer_cache == NULL) {
1259 if (xfer->flags_int.control_xfr &&
1260 !xfer->flags_int.control_act) {
1262 err = ehci_non_isoc_done_sub(xfer);
1265 ehci_device_done(xfer, err);
1268 /*------------------------------------------------------------------------*
1269 * ehci_check_transfer
1272 * 0: USB transfer is not finished
1273 * Else: USB transfer is finished
1274 *------------------------------------------------------------------------*/
1276 ehci_check_transfer(struct usb_xfer *xfer)
1278 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1279 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1283 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1285 if (methods == &ehci_device_isoc_fs_methods) {
1288 /* isochronous full speed transfer */
1290 td = xfer->td_transfer_last;
1291 usb_pc_cpu_invalidate(td->page_cache);
1292 status = hc32toh(sc, td->sitd_status);
1294 /* also check if first is complete */
1296 td = xfer->td_transfer_first;
1297 usb_pc_cpu_invalidate(td->page_cache);
1298 status |= hc32toh(sc, td->sitd_status);
1300 if (!(status & EHCI_SITD_ACTIVE)) {
1301 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1304 } else if (methods == &ehci_device_isoc_hs_methods) {
1307 /* isochronous high speed transfer */
1309 /* check last transfer */
1310 td = xfer->td_transfer_last;
1311 usb_pc_cpu_invalidate(td->page_cache);
1312 status = td->itd_status[0];
1313 status |= td->itd_status[1];
1314 status |= td->itd_status[2];
1315 status |= td->itd_status[3];
1316 status |= td->itd_status[4];
1317 status |= td->itd_status[5];
1318 status |= td->itd_status[6];
1319 status |= td->itd_status[7];
1321 /* also check first transfer */
1322 td = xfer->td_transfer_first;
1323 usb_pc_cpu_invalidate(td->page_cache);
1324 status |= td->itd_status[0];
1325 status |= td->itd_status[1];
1326 status |= td->itd_status[2];
1327 status |= td->itd_status[3];
1328 status |= td->itd_status[4];
1329 status |= td->itd_status[5];
1330 status |= td->itd_status[6];
1331 status |= td->itd_status[7];
1333 /* if no transactions are active we continue */
1334 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1335 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1342 /* non-isochronous transfer */
1345 * check whether there is an error somewhere in the middle,
1346 * or whether there was a short packet (SPD and not ACTIVE)
1348 td = xfer->td_transfer_cache;
1350 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1352 usb_pc_cpu_invalidate(qh->page_cache);
1354 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1355 if (status & EHCI_QTD_ACTIVE) {
1356 /* transfer is pending */
1361 usb_pc_cpu_invalidate(td->page_cache);
1362 status = hc32toh(sc, td->qtd_status);
1365 * Check if there is an active TD which
1366 * indicates that the transfer isn't done.
1368 if (status & EHCI_QTD_ACTIVE) {
1370 xfer->td_transfer_cache = td;
1374 * last transfer descriptor makes the transfer done
1376 if (((void *)td) == xfer->td_transfer_last) {
1380 * any kind of error makes the transfer done
1382 if (status & EHCI_QTD_HALTED) {
1386 * if there is no alternate next transfer, a short
1387 * packet also makes the transfer done
1389 if (EHCI_QTD_GET_BYTES(status)) {
1390 if (xfer->flags_int.short_frames_ok) {
1391 /* follow alt next */
1397 /* transfer is done */
1402 ehci_non_isoc_done(xfer);
1407 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1415 ehci_pcd_enable(ehci_softc_t *sc)
1417 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1419 sc->sc_eintrs |= EHCI_STS_PCD;
1420 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1422 /* acknowledge any PCD interrupt */
1423 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1429 ehci_interrupt_poll(ehci_softc_t *sc)
1431 struct usb_xfer *xfer;
1434 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1436 * check if transfer is transferred
1438 if (ehci_check_transfer(xfer)) {
1439 /* queue has been modified */
1446 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1447 * writing back the qTD status, or miss signalling occasionally under
1448 * heavy load. If the host machine is too fast, we can miss
1449 * transaction completion - when we scan the active list the
1450 * transaction still seems to be active. This generally exhibits
1451 * itself as a umass stall that never recovers.
1453 * We work around this behaviour by setting up this callback after any
1454 * softintr that completes with transactions still pending, giving us
1455 * another chance to check for completion after the writeback has
1459 ehci_poll_timeout(void *arg)
1461 ehci_softc_t *sc = arg;
1464 ehci_interrupt_poll(sc);
1467 /*------------------------------------------------------------------------*
1468 * ehci_interrupt - EHCI interrupt handler
1470 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1471 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1473 *------------------------------------------------------------------------*/
1475 ehci_interrupt(ehci_softc_t *sc)
1479 USB_BUS_LOCK(&sc->sc_bus);
1481 DPRINTFN(16, "real interrupt\n");
1484 if (ehcidebug > 15) {
1489 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1491 /* the interrupt was not for us */
1494 if (!(status & sc->sc_eintrs)) {
1497 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1499 status &= sc->sc_eintrs;
1501 if (status & EHCI_STS_HSE) {
1502 printf("%s: unrecoverable error, "
1503 "controller halted\n", __FUNCTION__);
1509 if (status & EHCI_STS_PCD) {
1511 * Disable PCD interrupt for now, because it will be
1512 * on until the port has been reset.
1514 sc->sc_eintrs &= ~EHCI_STS_PCD;
1515 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1519 /* do not allow RHSC interrupts > 1 per second */
1520 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1521 (void *)&ehci_pcd_enable, sc);
1523 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1526 /* block unprocessed interrupts */
1527 sc->sc_eintrs &= ~status;
1528 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1529 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1531 /* poll all the USB transfers */
1532 ehci_interrupt_poll(sc);
1534 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1535 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1536 (void *)&ehci_poll_timeout, sc);
1540 USB_BUS_UNLOCK(&sc->sc_bus);
1544 * called when a request does not complete
1547 ehci_timeout(void *arg)
1549 struct usb_xfer *xfer = arg;
1551 DPRINTF("xfer=%p\n", xfer);
1553 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1555 /* transfer is transferred */
1556 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1560 ehci_do_poll(struct usb_bus *bus)
1562 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1564 USB_BUS_LOCK(&sc->sc_bus);
1565 ehci_interrupt_poll(sc);
1566 USB_BUS_UNLOCK(&sc->sc_bus);
1570 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1572 struct usb_page_search buf_res;
1574 ehci_qtd_t *td_next;
1575 ehci_qtd_t *td_alt_next;
1576 uint32_t buf_offset;
1580 uint32_t qtd_altnext;
1581 uint8_t shortpkt_old;
1584 terminate = temp->sc->sc_terminate_self;
1585 qtd_altnext = temp->sc->sc_terminate_self;
1588 shortpkt_old = temp->shortpkt;
1589 len_old = temp->len;
1595 td_next = temp->td_next;
1599 if (temp->len == 0) {
1601 if (temp->shortpkt) {
1604 /* send a Zero Length Packet, ZLP, last */
1611 average = temp->average;
1613 if (temp->len < average) {
1614 if (temp->len % temp->max_frame_size) {
1617 average = temp->len;
1621 if (td_next == NULL) {
1622 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1627 td_next = td->obj_next;
1629 /* check if we are pre-computing */
1633 /* update remaining length */
1635 temp->len -= average;
1639 /* fill out current TD */
1643 htohc32(temp->sc, EHCI_QTD_IOC |
1644 EHCI_QTD_SET_BYTES(average));
1648 if (temp->auto_data_toggle == 0) {
1650 /* update data toggle, ZLP case */
1653 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1657 /* properly reset reserved fields */
1658 td->qtd_buffer[0] = 0;
1659 td->qtd_buffer[1] = 0;
1660 td->qtd_buffer[2] = 0;
1661 td->qtd_buffer[3] = 0;
1662 td->qtd_buffer[4] = 0;
1663 td->qtd_buffer_hi[0] = 0;
1664 td->qtd_buffer_hi[1] = 0;
1665 td->qtd_buffer_hi[2] = 0;
1666 td->qtd_buffer_hi[3] = 0;
1667 td->qtd_buffer_hi[4] = 0;
1672 if (temp->auto_data_toggle == 0) {
1674 /* update data toggle */
1676 if (((average + temp->max_frame_size - 1) /
1677 temp->max_frame_size) & 1) {
1679 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1684 /* update remaining length */
1686 temp->len -= average;
1688 /* fill out buffer pointers */
1690 usbd_get_page(temp->pc, buf_offset, &buf_res);
1692 htohc32(temp->sc, buf_res.physaddr);
1693 td->qtd_buffer_hi[0] = 0;
1697 while (average > EHCI_PAGE_SIZE) {
1698 average -= EHCI_PAGE_SIZE;
1699 buf_offset += EHCI_PAGE_SIZE;
1700 usbd_get_page(temp->pc, buf_offset, &buf_res);
1703 buf_res.physaddr & (~0xFFF));
1704 td->qtd_buffer_hi[x] = 0;
1709 * NOTE: The "average" variable is never zero after
1710 * exiting the loop above !
1712 * NOTE: We have to subtract one from the offset to
1713 * ensure that we are computing the physical address
1716 buf_offset += average;
1717 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1720 buf_res.physaddr & (~0xFFF));
1721 td->qtd_buffer_hi[x] = 0;
1723 /* properly reset reserved fields */
1724 while (++x < EHCI_QTD_NBUFFERS) {
1725 td->qtd_buffer[x] = 0;
1726 td->qtd_buffer_hi[x] = 0;
1731 /* link the current TD with the next one */
1732 td->qtd_next = td_next->qtd_self;
1734 td->qtd_altnext = qtd_altnext;
1735 td->alt_next = td_alt_next;
1737 usb_pc_cpu_flush(td->page_cache);
1743 /* setup alt next pointer, if any */
1744 if (temp->last_frame) {
1746 qtd_altnext = terminate;
1748 /* we use this field internally */
1749 td_alt_next = td_next;
1750 if (temp->setup_alt_next) {
1751 qtd_altnext = td_next->qtd_self;
1753 qtd_altnext = terminate;
1758 temp->shortpkt = shortpkt_old;
1759 temp->len = len_old;
1763 temp->td_next = td_next;
1767 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1769 struct ehci_std_temp temp;
1770 struct usb_pipe_methods *methods;
1774 uint32_t qh_endphub;
1777 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1778 xfer->address, UE_GET_ADDR(xfer->endpointno),
1779 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1781 temp.average = xfer->max_hc_frame_size;
1782 temp.max_frame_size = xfer->max_frame_size;
1783 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1785 /* toggle the DMA set we are using */
1786 xfer->flags_int.curr_dma_set ^= 1;
1788 /* get next DMA set */
1789 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1791 xfer->td_transfer_first = td;
1792 xfer->td_transfer_cache = td;
1796 temp.qtd_status = 0;
1797 temp.last_frame = 0;
1798 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1800 if (xfer->flags_int.control_xfr) {
1801 if (xfer->endpoint->toggle_next) {
1804 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1806 temp.auto_data_toggle = 0;
1808 temp.auto_data_toggle = 1;
1811 if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1812 (xfer->xroot->udev->address != 0)) {
1815 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1817 /* check if we should prepend a setup message */
1819 if (xfer->flags_int.control_xfr) {
1820 if (xfer->flags_int.control_hdr) {
1822 xfer->endpoint->toggle_next = 0;
1825 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1826 temp.qtd_status |= htohc32(temp.sc,
1828 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1829 EHCI_QTD_SET_TOGGLE(0));
1831 temp.len = xfer->frlengths[0];
1832 temp.pc = xfer->frbuffers + 0;
1833 temp.shortpkt = temp.len ? 1 : 0;
1834 /* check for last frame */
1835 if (xfer->nframes == 1) {
1836 /* no STATUS stage yet, SETUP is last */
1837 if (xfer->flags_int.control_act) {
1838 temp.last_frame = 1;
1839 temp.setup_alt_next = 0;
1842 ehci_setup_standard_chain_sub(&temp);
1849 while (x != xfer->nframes) {
1851 /* DATA0 / DATA1 message */
1853 temp.len = xfer->frlengths[x];
1854 temp.pc = xfer->frbuffers + x;
1858 if (x == xfer->nframes) {
1859 if (xfer->flags_int.control_xfr) {
1860 /* no STATUS stage yet, DATA is last */
1861 if (xfer->flags_int.control_act) {
1862 temp.last_frame = 1;
1863 temp.setup_alt_next = 0;
1866 temp.last_frame = 1;
1867 temp.setup_alt_next = 0;
1870 /* keep previous data toggle and error count */
1873 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1874 EHCI_QTD_SET_TOGGLE(1));
1876 if (temp.len == 0) {
1878 /* make sure that we send an USB packet */
1884 /* regular data transfer */
1886 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1889 /* set endpoint direction */
1892 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1893 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1894 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1895 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1896 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1898 ehci_setup_standard_chain_sub(&temp);
1901 /* check if we should append a status stage */
1903 if (xfer->flags_int.control_xfr &&
1904 !xfer->flags_int.control_act) {
1907 * Send a DATA1 message and invert the current endpoint
1911 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1912 EHCI_QTD_SET_TOGGLE(1));
1914 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1915 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1916 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1917 EHCI_QTD_SET_TOGGLE(1)) :
1918 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1919 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1920 EHCI_QTD_SET_TOGGLE(1));
1925 temp.last_frame = 1;
1926 temp.setup_alt_next = 0;
1928 ehci_setup_standard_chain_sub(&temp);
1932 /* the last TD terminates the transfer: */
1933 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1934 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1936 usb_pc_cpu_flush(td->page_cache);
1938 /* must have at least one frame! */
1940 xfer->td_transfer_last = td;
1943 if (ehcidebug > 8) {
1944 DPRINTF("nexttog=%d; data before transfer:\n",
1945 xfer->endpoint->toggle_next);
1946 ehci_dump_sqtds(temp.sc,
1947 xfer->td_transfer_first);
1951 methods = xfer->endpoint->methods;
1953 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1955 /* the "qh_link" field is filled when the QH is added */
1958 (EHCI_QH_SET_ADDR(xfer->address) |
1959 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1960 EHCI_QH_SET_MPL(xfer->max_packet_size));
1962 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1963 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1964 if (methods != &ehci_device_intr_methods)
1965 qh_endp |= EHCI_QH_SET_NRL(8);
1968 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1969 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1971 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1974 if (methods == &ehci_device_ctrl_methods) {
1975 qh_endp |= EHCI_QH_CTL;
1977 if (methods != &ehci_device_intr_methods) {
1978 /* Only try one time per microframe! */
1979 qh_endp |= EHCI_QH_SET_NRL(1);
1983 if (temp.auto_data_toggle == 0) {
1984 /* software computes the data toggle */
1985 qh_endp |= EHCI_QH_DTC;
1988 qh->qh_endp = htohc32(temp.sc, qh_endp);
1991 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1992 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1993 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1994 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1995 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1997 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2000 /* fill the overlay qTD */
2002 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2004 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2006 qh->qh_qtd.qtd_status = 0;
2009 td = xfer->td_transfer_first;
2011 qh->qh_qtd.qtd_next = td->qtd_self;
2012 qh->qh_qtd.qtd_altnext =
2013 htohc32(temp.sc, EHCI_LINK_TERMINATE);
2015 /* properly reset reserved fields */
2016 qh->qh_qtd.qtd_buffer[0] = 0;
2017 qh->qh_qtd.qtd_buffer[1] = 0;
2018 qh->qh_qtd.qtd_buffer[2] = 0;
2019 qh->qh_qtd.qtd_buffer[3] = 0;
2020 qh->qh_qtd.qtd_buffer[4] = 0;
2021 qh->qh_qtd.qtd_buffer_hi[0] = 0;
2022 qh->qh_qtd.qtd_buffer_hi[1] = 0;
2023 qh->qh_qtd.qtd_buffer_hi[2] = 0;
2024 qh->qh_qtd.qtd_buffer_hi[3] = 0;
2025 qh->qh_qtd.qtd_buffer_hi[4] = 0;
2027 usb_pc_cpu_flush(qh->page_cache);
2029 if (xfer->xroot->udev->flags.self_suspended == 0) {
2030 EHCI_APPEND_QH(qh, *qh_last);
2035 ehci_root_intr(ehci_softc_t *sc)
2040 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2042 /* clear any old interrupt data */
2043 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2046 m = (sc->sc_noport + 1);
2047 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2048 m = (8 * sizeof(sc->sc_hub_idata));
2050 for (i = 1; i < m; i++) {
2051 /* pick out CHANGE bits from the status register */
2052 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2053 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2054 DPRINTF("port %d changed\n", i);
2057 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2058 sizeof(sc->sc_hub_idata));
2062 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2064 uint32_t nframes = xfer->nframes;
2066 uint32_t *plen = xfer->frlengths;
2068 ehci_sitd_t *td = xfer->td_transfer_first;
2069 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2071 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2072 xfer, xfer->endpoint);
2076 panic("%s:%d: out of TD's\n",
2077 __FUNCTION__, __LINE__);
2079 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2080 pp_last = &sc->sc_isoc_fs_p_last[0];
2083 if (ehcidebug > 15) {
2084 DPRINTF("isoc FS-TD\n");
2085 ehci_dump_sitd(sc, td);
2088 usb_pc_cpu_invalidate(td->page_cache);
2089 status = hc32toh(sc, td->sitd_status);
2091 len = EHCI_SITD_GET_LEN(status);
2093 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2103 /* remove FS-TD from schedule */
2104 EHCI_REMOVE_FS_TD(td, *pp_last);
2111 xfer->aframes = xfer->nframes;
2115 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2117 uint32_t nframes = xfer->nframes;
2119 uint32_t *plen = xfer->frlengths;
2122 ehci_itd_t *td = xfer->td_transfer_first;
2123 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2125 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2126 xfer, xfer->endpoint);
2130 panic("%s:%d: out of TD's\n",
2131 __FUNCTION__, __LINE__);
2133 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2134 pp_last = &sc->sc_isoc_hs_p_last[0];
2137 if (ehcidebug > 15) {
2138 DPRINTF("isoc HS-TD\n");
2139 ehci_dump_itd(sc, td);
2143 usb_pc_cpu_invalidate(td->page_cache);
2144 status = hc32toh(sc, td->itd_status[td_no]);
2146 len = EHCI_ITD_GET_LEN(status);
2148 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2150 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2154 * The length is valid. NOTE: The
2155 * complete length is written back
2156 * into the status field, and not the
2157 * remainder like with other transfer
2161 /* Invalid length - truncate */
2172 if ((td_no == 8) || (nframes == 0)) {
2173 /* remove HS-TD from schedule */
2174 EHCI_REMOVE_HS_TD(td, *pp_last);
2181 xfer->aframes = xfer->nframes;
2184 /* NOTE: "done" can be run two times in a row,
2185 * from close and from interrupt
2188 ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2190 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2191 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2193 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2195 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2196 xfer, xfer->endpoint, error);
2198 if ((methods == &ehci_device_bulk_methods) ||
2199 (methods == &ehci_device_ctrl_methods)) {
2201 if (ehcidebug > 8) {
2202 DPRINTF("nexttog=%d; data after transfer:\n",
2203 xfer->endpoint->toggle_next);
2205 xfer->td_transfer_first);
2209 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2210 sc->sc_async_p_last);
2212 if (methods == &ehci_device_intr_methods) {
2213 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2214 sc->sc_intr_p_last[xfer->qh_pos]);
2217 * Only finish isochronous transfers once which will update
2218 * "xfer->frlengths".
2220 if (xfer->td_transfer_first &&
2221 xfer->td_transfer_last) {
2222 if (methods == &ehci_device_isoc_fs_methods) {
2223 ehci_isoc_fs_done(sc, xfer);
2225 if (methods == &ehci_device_isoc_hs_methods) {
2226 ehci_isoc_hs_done(sc, xfer);
2228 xfer->td_transfer_first = NULL;
2229 xfer->td_transfer_last = NULL;
2231 /* dequeue transfer and start next transfer */
2232 usbd_transfer_done(xfer, error);
2235 /*------------------------------------------------------------------------*
2237 *------------------------------------------------------------------------*/
2239 ehci_device_bulk_open(struct usb_xfer *xfer)
2245 ehci_device_bulk_close(struct usb_xfer *xfer)
2247 ehci_device_done(xfer, USB_ERR_CANCELLED);
2251 ehci_device_bulk_enter(struct usb_xfer *xfer)
2257 ehci_doorbell_async(struct ehci_softc *sc)
2262 * XXX Performance quirk: Some Host Controllers have a too low
2263 * interrupt rate. Issue an IAAD to stimulate the Host
2264 * Controller after queueing the BULK transfer.
2266 * XXX Force the host controller to refresh any QH caches.
2268 temp = EOREAD4(sc, EHCI_USBCMD);
2269 if (!(temp & EHCI_CMD_IAAD))
2270 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2274 ehci_device_bulk_start(struct usb_xfer *xfer)
2276 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2278 /* setup TD's and QH */
2279 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2281 /* put transfer on interrupt queue */
2282 ehci_transfer_intr_enqueue(xfer);
2285 * XXX Certain nVidia chipsets choke when using the IAAD
2286 * feature too frequently.
2288 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2291 ehci_doorbell_async(sc);
2294 struct usb_pipe_methods ehci_device_bulk_methods =
2296 .open = ehci_device_bulk_open,
2297 .close = ehci_device_bulk_close,
2298 .enter = ehci_device_bulk_enter,
2299 .start = ehci_device_bulk_start,
2302 /*------------------------------------------------------------------------*
2303 * ehci control support
2304 *------------------------------------------------------------------------*/
2306 ehci_device_ctrl_open(struct usb_xfer *xfer)
2312 ehci_device_ctrl_close(struct usb_xfer *xfer)
2314 ehci_device_done(xfer, USB_ERR_CANCELLED);
2318 ehci_device_ctrl_enter(struct usb_xfer *xfer)
2324 ehci_device_ctrl_start(struct usb_xfer *xfer)
2326 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2328 /* setup TD's and QH */
2329 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2331 /* put transfer on interrupt queue */
2332 ehci_transfer_intr_enqueue(xfer);
2335 struct usb_pipe_methods ehci_device_ctrl_methods =
2337 .open = ehci_device_ctrl_open,
2338 .close = ehci_device_ctrl_close,
2339 .enter = ehci_device_ctrl_enter,
2340 .start = ehci_device_ctrl_start,
2343 /*------------------------------------------------------------------------*
2344 * ehci interrupt support
2345 *------------------------------------------------------------------------*/
2347 ehci_device_intr_open(struct usb_xfer *xfer)
2349 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2354 usb_hs_bandwidth_alloc(xfer);
2357 * Find the best QH position corresponding to the given interval:
2361 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2363 if (xfer->interval >= bit) {
2367 if (sc->sc_intr_stat[x] <
2368 sc->sc_intr_stat[best]) {
2378 sc->sc_intr_stat[best]++;
2379 xfer->qh_pos = best;
2381 DPRINTFN(3, "best=%d interval=%d\n",
2382 best, xfer->interval);
2386 ehci_device_intr_close(struct usb_xfer *xfer)
2388 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2390 sc->sc_intr_stat[xfer->qh_pos]--;
2392 ehci_device_done(xfer, USB_ERR_CANCELLED);
2394 /* bandwidth must be freed after device done */
2395 usb_hs_bandwidth_free(xfer);
2399 ehci_device_intr_enter(struct usb_xfer *xfer)
2405 ehci_device_intr_start(struct usb_xfer *xfer)
2407 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2409 /* setup TD's and QH */
2410 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2412 /* put transfer on interrupt queue */
2413 ehci_transfer_intr_enqueue(xfer);
2416 struct usb_pipe_methods ehci_device_intr_methods =
2418 .open = ehci_device_intr_open,
2419 .close = ehci_device_intr_close,
2420 .enter = ehci_device_intr_enter,
2421 .start = ehci_device_intr_start,
2424 /*------------------------------------------------------------------------*
2425 * ehci full speed isochronous support
2426 *------------------------------------------------------------------------*/
2428 ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2430 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2432 uint32_t sitd_portaddr;
2436 EHCI_SITD_SET_ADDR(xfer->address) |
2437 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2438 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2439 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2441 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2442 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2444 sitd_portaddr = htohc32(sc, sitd_portaddr);
2446 /* initialize all TD's */
2448 for (ds = 0; ds != 2; ds++) {
2450 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2452 td->sitd_portaddr = sitd_portaddr;
2455 * TODO: make some kind of automatic
2456 * SMASK/CMASK selection based on micro-frame
2459 * micro-frame usage (8 microframes per 1ms)
2461 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2463 usb_pc_cpu_flush(td->page_cache);
2469 ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2471 ehci_device_done(xfer, USB_ERR_CANCELLED);
2475 ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2477 struct usb_page_search buf_res;
2478 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2480 ehci_sitd_t *td_last = NULL;
2481 ehci_sitd_t **pp_last;
2483 uint32_t buf_offset;
2496 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2497 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2499 /* get the current frame index */
2501 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2504 * check if the frame index is within the window where the frames
2507 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2508 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2510 if ((xfer->endpoint->is_synced == 0) ||
2511 (buf_offset < xfer->nframes)) {
2513 * If there is data underflow or the pipe queue is empty we
2514 * schedule the transfer a few frames ahead of the current
2515 * frame position. Else two isochronous transfers might
2518 xfer->endpoint->isoc_next = (nframes + 3) &
2519 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2520 xfer->endpoint->is_synced = 1;
2521 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2524 * compute how many milliseconds the insertion is ahead of the
2525 * current frame position:
2527 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2528 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2531 * pre-compute when the isochronous transfer will be finished:
2533 xfer->isoc_time_complete =
2534 usb_isoc_time_expand(&sc->sc_bus, nframes) +
2535 buf_offset + xfer->nframes;
2537 /* get the real number of frames */
2539 nframes = xfer->nframes;
2543 plen = xfer->frlengths;
2545 /* toggle the DMA set we are using */
2546 xfer->flags_int.curr_dma_set ^= 1;
2548 /* get next DMA set */
2549 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2550 xfer->td_transfer_first = td;
2552 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2554 /* store starting position */
2556 xfer->qh_pos = xfer->endpoint->isoc_next;
2560 panic("%s:%d: out of TD's\n",
2561 __FUNCTION__, __LINE__);
2563 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2564 pp_last = &sc->sc_isoc_fs_p_last[0];
2566 /* reuse sitd_portaddr and sitd_back from last transfer */
2568 if (*plen > xfer->max_frame_size) {
2572 printf("%s: frame length(%d) exceeds %d "
2573 "bytes (frame truncated)\n",
2574 __FUNCTION__, *plen,
2575 xfer->max_frame_size);
2578 *plen = xfer->max_frame_size;
2581 /* allocate a slot */
2583 sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2584 xfer->isoc_time_complete - nframes - 1);
2588 * Schedule is FULL, set length to zero:
2592 sa = USB_FS_ISOC_UFRAME_MAX - 1;
2596 * only call "usbd_get_page()" when we have a
2599 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2600 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2601 buf_offset += *plen;
2603 * NOTE: We need to subtract one from the offset so
2604 * that we are on a valid page!
2606 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2608 temp = buf_res.physaddr & ~0xFFF;
2614 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2617 temp |= 1; /* T-count = 1, TP = ALL */
2622 temp |= tlen; /* T-count = [1..6] */
2623 temp |= 8; /* TP = Begin */
2635 sa = (sb - sa) & 0x3F;
2638 sb = (-(4 << sa)) & 0xFE;
2639 sa = (1 << sa) & 0x3F;
2642 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2643 EHCI_SITD_SET_CMASK(sb));
2645 td->sitd_bp[1] = htohc32(sc, temp);
2647 td->sitd_mask = htohc32(sc, sitd_mask);
2650 td->sitd_status = htohc32(sc,
2653 EHCI_SITD_SET_LEN(*plen));
2655 td->sitd_status = htohc32(sc,
2657 EHCI_SITD_SET_LEN(*plen));
2659 usb_pc_cpu_flush(td->page_cache);
2662 if (ehcidebug > 15) {
2663 DPRINTF("FS-TD %d\n", nframes);
2664 ehci_dump_sitd(sc, td);
2667 /* insert TD into schedule */
2668 EHCI_APPEND_FS_TD(td, *pp_last);
2676 xfer->td_transfer_last = td_last;
2678 /* update isoc_next */
2679 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2680 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2683 * We don't allow cancelling of the SPLIT transaction USB FULL
2684 * speed transfer, because it disturbs the bandwidth
2685 * computation algorithm.
2687 xfer->flags_int.can_cancel_immed = 0;
2691 ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2694 * We don't allow cancelling of the SPLIT transaction USB FULL
2695 * speed transfer, because it disturbs the bandwidth
2696 * computation algorithm.
2698 xfer->flags_int.can_cancel_immed = 0;
2700 /* set a default timeout */
2701 if (xfer->timeout == 0)
2702 xfer->timeout = 500; /* ms */
2704 /* put transfer on interrupt queue */
2705 ehci_transfer_intr_enqueue(xfer);
2708 struct usb_pipe_methods ehci_device_isoc_fs_methods =
2710 .open = ehci_device_isoc_fs_open,
2711 .close = ehci_device_isoc_fs_close,
2712 .enter = ehci_device_isoc_fs_enter,
2713 .start = ehci_device_isoc_fs_start,
2716 /*------------------------------------------------------------------------*
2717 * ehci high speed isochronous support
2718 *------------------------------------------------------------------------*/
2720 ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2722 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2727 usb_hs_bandwidth_alloc(xfer);
2729 /* initialize all TD's */
2731 for (ds = 0; ds != 2; ds++) {
2733 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2735 /* set TD inactive */
2736 td->itd_status[0] = 0;
2737 td->itd_status[1] = 0;
2738 td->itd_status[2] = 0;
2739 td->itd_status[3] = 0;
2740 td->itd_status[4] = 0;
2741 td->itd_status[5] = 0;
2742 td->itd_status[6] = 0;
2743 td->itd_status[7] = 0;
2745 /* set endpoint and address */
2746 td->itd_bp[0] = htohc32(sc,
2747 EHCI_ITD_SET_ADDR(xfer->address) |
2748 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2751 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2754 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2755 temp |= EHCI_ITD_SET_DIR_IN;
2757 /* set maximum packet size */
2758 td->itd_bp[1] = htohc32(sc, temp);
2760 /* set transfer multiplier */
2761 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2763 usb_pc_cpu_flush(td->page_cache);
2769 ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2771 ehci_device_done(xfer, USB_ERR_CANCELLED);
2773 /* bandwidth must be freed after device done */
2774 usb_hs_bandwidth_free(xfer);
2778 ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2780 struct usb_page_search buf_res;
2781 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2783 ehci_itd_t *td_last = NULL;
2784 ehci_itd_t **pp_last;
2785 bus_size_t page_addr;
2788 uint32_t buf_offset;
2790 uint32_t itd_offset[8 + 1];
2794 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2801 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2802 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2804 /* get the current frame index */
2806 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2809 * check if the frame index is within the window where the frames
2812 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2813 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2815 if ((xfer->endpoint->is_synced == 0) ||
2816 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2818 * If there is data underflow or the pipe queue is empty we
2819 * schedule the transfer a few frames ahead of the current
2820 * frame position. Else two isochronous transfers might
2823 xfer->endpoint->isoc_next = (nframes + 3) &
2824 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2825 xfer->endpoint->is_synced = 1;
2826 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2829 * compute how many milliseconds the insertion is ahead of the
2830 * current frame position:
2832 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2833 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2836 * pre-compute when the isochronous transfer will be finished:
2838 xfer->isoc_time_complete =
2839 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2840 (((xfer->nframes << shift) + 7) / 8);
2842 /* get the real number of frames */
2844 nframes = xfer->nframes;
2849 plen = xfer->frlengths;
2851 /* toggle the DMA set we are using */
2852 xfer->flags_int.curr_dma_set ^= 1;
2854 /* get next DMA set */
2855 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2856 xfer->td_transfer_first = td;
2858 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2860 /* store starting position */
2862 xfer->qh_pos = xfer->endpoint->isoc_next;
2866 panic("%s:%d: out of TD's\n",
2867 __FUNCTION__, __LINE__);
2869 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2870 pp_last = &sc->sc_isoc_hs_p_last[0];
2873 if (*plen > xfer->max_frame_size) {
2877 printf("%s: frame length(%d) exceeds %d bytes "
2878 "(frame truncated)\n",
2879 __FUNCTION__, *plen, xfer->max_frame_size);
2882 *plen = xfer->max_frame_size;
2885 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2886 status = (EHCI_ITD_SET_LEN(*plen) |
2888 EHCI_ITD_SET_PG(0));
2889 td->itd_status[td_no] = htohc32(sc, status);
2890 itd_offset[td_no] = buf_offset;
2891 buf_offset += *plen;
2895 td->itd_status[td_no] = 0; /* not active */
2896 itd_offset[td_no] = buf_offset;
2901 if ((td_no == 8) || (nframes == 0)) {
2903 /* the rest of the transfers are not active, if any */
2904 for (x = td_no; x != 8; x++) {
2905 td->itd_status[x] = 0; /* not active */
2908 /* check if there is any data to be transferred */
2909 if (itd_offset[0] != buf_offset) {
2911 itd_offset[td_no] = buf_offset;
2913 /* get first page offset */
2914 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2915 /* get page address */
2916 page_addr = buf_res.physaddr & ~0xFFF;
2917 /* update page address */
2918 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2919 td->itd_bp[0] |= htohc32(sc, page_addr);
2921 for (x = 0; x != td_no; x++) {
2922 /* set page number and page offset */
2923 status = (EHCI_ITD_SET_PG(page_no) |
2924 (buf_res.physaddr & 0xFFF));
2925 td->itd_status[x] |= htohc32(sc, status);
2927 /* get next page offset */
2928 if (itd_offset[x + 1] == buf_offset) {
2930 * We subtract one so that
2931 * we don't go off the last
2934 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2936 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2939 /* check if we need a new page */
2940 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2941 /* new page needed */
2942 page_addr = buf_res.physaddr & ~0xFFF;
2944 panic("%s: too many pages\n", __FUNCTION__);
2947 /* update page address */
2948 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2949 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2953 /* set IOC bit if we are complete */
2955 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2957 usb_pc_cpu_flush(td->page_cache);
2959 if (ehcidebug > 15) {
2960 DPRINTF("HS-TD %d\n", nframes);
2961 ehci_dump_itd(sc, td);
2964 /* insert TD into schedule */
2965 EHCI_APPEND_HS_TD(td, *pp_last);
2974 xfer->td_transfer_last = td_last;
2976 /* update isoc_next */
2977 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2978 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2982 ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2984 /* put transfer on interrupt queue */
2985 ehci_transfer_intr_enqueue(xfer);
2988 struct usb_pipe_methods ehci_device_isoc_hs_methods =
2990 .open = ehci_device_isoc_hs_open,
2991 .close = ehci_device_isoc_hs_close,
2992 .enter = ehci_device_isoc_hs_enter,
2993 .start = ehci_device_isoc_hs_start,
2996 /*------------------------------------------------------------------------*
2997 * ehci root control support
2998 *------------------------------------------------------------------------*
2999 * Simulate a hardware hub by handling all the necessary requests.
3000 *------------------------------------------------------------------------*/
3003 struct usb_device_descriptor ehci_devd =
3005 sizeof(struct usb_device_descriptor),
3006 UDESC_DEVICE, /* type */
3007 {0x00, 0x02}, /* USB version */
3008 UDCLASS_HUB, /* class */
3009 UDSUBCLASS_HUB, /* subclass */
3010 UDPROTO_HSHUBSTT, /* protocol */
3011 64, /* max packet */
3012 {0}, {0}, {0x00, 0x01}, /* device id */
3013 1, 2, 0, /* string indicies */
3014 1 /* # of configurations */
3018 struct usb_device_qualifier ehci_odevd =
3020 sizeof(struct usb_device_qualifier),
3021 UDESC_DEVICE_QUALIFIER, /* type */
3022 {0x00, 0x02}, /* USB version */
3023 UDCLASS_HUB, /* class */
3024 UDSUBCLASS_HUB, /* subclass */
3025 UDPROTO_FSHUB, /* protocol */
3027 0, /* # of configurations */
3031 static const struct ehci_config_desc ehci_confd = {
3033 .bLength = sizeof(struct usb_config_descriptor),
3034 .bDescriptorType = UDESC_CONFIG,
3035 .wTotalLength[0] = sizeof(ehci_confd),
3037 .bConfigurationValue = 1,
3038 .iConfiguration = 0,
3039 .bmAttributes = UC_SELF_POWERED,
3040 .bMaxPower = 0 /* max power */
3043 .bLength = sizeof(struct usb_interface_descriptor),
3044 .bDescriptorType = UDESC_INTERFACE,
3046 .bInterfaceClass = UICLASS_HUB,
3047 .bInterfaceSubClass = UISUBCLASS_HUB,
3048 .bInterfaceProtocol = 0,
3051 .bLength = sizeof(struct usb_endpoint_descriptor),
3052 .bDescriptorType = UDESC_ENDPOINT,
3053 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3054 .bmAttributes = UE_INTERRUPT,
3055 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3061 struct usb_hub_descriptor ehci_hubd =
3063 .bDescLength = 0, /* dynamic length */
3064 .bDescriptorType = UDESC_HUB,
3068 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3073 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3075 port = EHCI_PORTSC(index);
3076 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3077 EOWRITE4(sc, port, v | EHCI_PS_PO);
3081 ehci_roothub_exec(struct usb_device *udev,
3082 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3084 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3085 const char *str_ptr;
3095 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3098 ptr = (const void *)&sc->sc_hub_desc;
3102 value = UGETW(req->wValue);
3103 index = UGETW(req->wIndex);
3105 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3106 "wValue=0x%04x wIndex=0x%04x\n",
3107 req->bmRequestType, req->bRequest,
3108 UGETW(req->wLength), value, index);
3110 #define C(x,y) ((x) | ((y) << 8))
3111 switch (C(req->bRequest, req->bmRequestType)) {
3112 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3113 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3114 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3116 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3117 * for the integrated root hub.
3120 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3122 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3124 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3125 switch (value >> 8) {
3127 if ((value & 0xff) != 0) {
3128 err = USB_ERR_IOERROR;
3131 len = sizeof(ehci_devd);
3132 ptr = (const void *)&ehci_devd;
3135 * We can't really operate at another speed,
3136 * but the specification says we need this
3139 case UDESC_DEVICE_QUALIFIER:
3140 if ((value & 0xff) != 0) {
3141 err = USB_ERR_IOERROR;
3144 len = sizeof(ehci_odevd);
3145 ptr = (const void *)&ehci_odevd;
3149 if ((value & 0xff) != 0) {
3150 err = USB_ERR_IOERROR;
3153 len = sizeof(ehci_confd);
3154 ptr = (const void *)&ehci_confd;
3158 switch (value & 0xff) {
3159 case 0: /* Language table */
3163 case 1: /* Vendor */
3164 str_ptr = sc->sc_vendor;
3167 case 2: /* Product */
3168 str_ptr = "EHCI root HUB";
3176 len = usb_make_str_desc(
3177 sc->sc_hub_desc.temp,
3178 sizeof(sc->sc_hub_desc.temp),
3182 err = USB_ERR_IOERROR;
3186 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3188 sc->sc_hub_desc.temp[0] = 0;
3190 case C(UR_GET_STATUS, UT_READ_DEVICE):
3192 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3194 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3195 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3197 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3199 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3200 if (value >= EHCI_MAX_DEVICES) {
3201 err = USB_ERR_IOERROR;
3204 sc->sc_addr = value;
3206 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3207 if ((value != 0) && (value != 1)) {
3208 err = USB_ERR_IOERROR;
3211 sc->sc_conf = value;
3213 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3215 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3216 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3217 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3218 err = USB_ERR_IOERROR;
3220 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3222 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3225 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3227 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3228 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3231 (index > sc->sc_noport)) {
3232 err = USB_ERR_IOERROR;
3235 port = EHCI_PORTSC(index);
3236 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3238 case UHF_PORT_ENABLE:
3239 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3241 case UHF_PORT_SUSPEND:
3242 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3245 * waking up a High Speed device is rather
3248 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3250 /* wait 20ms for resume sequence to complete */
3251 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3253 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3254 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3256 /* 4ms settle time */
3257 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3259 case UHF_PORT_POWER:
3260 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3263 DPRINTFN(3, "clear port test "
3266 case UHF_PORT_INDICATOR:
3267 DPRINTFN(3, "clear port ind "
3269 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3271 case UHF_C_PORT_CONNECTION:
3272 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3274 case UHF_C_PORT_ENABLE:
3275 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3277 case UHF_C_PORT_SUSPEND:
3278 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3280 case UHF_C_PORT_OVER_CURRENT:
3281 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3283 case UHF_C_PORT_RESET:
3287 err = USB_ERR_IOERROR;
3291 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3292 if ((value & 0xff) != 0) {
3293 err = USB_ERR_IOERROR;
3296 v = EREAD4(sc, EHCI_HCSPARAMS);
3298 sc->sc_hub_desc.hubd = ehci_hubd;
3299 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3301 if (EHCI_HCS_PPC(v))
3302 i = UHD_PWR_INDIVIDUAL;
3304 i = UHD_PWR_NO_SWITCH;
3306 if (EHCI_HCS_P_INDICATOR(v))
3309 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3310 /* XXX can't find out? */
3311 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3312 /* XXX don't know if ports are removable or not */
3313 sc->sc_hub_desc.hubd.bDescLength =
3314 8 + ((sc->sc_noport + 7) / 8);
3315 len = sc->sc_hub_desc.hubd.bDescLength;
3317 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3319 memset(sc->sc_hub_desc.temp, 0, 16);
3321 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3322 DPRINTFN(9, "get port status i=%d\n",
3325 (index > sc->sc_noport)) {
3326 err = USB_ERR_IOERROR;
3329 v = EOREAD4(sc, EHCI_PORTSC(index));
3330 DPRINTFN(9, "port status=0x%04x\n", v);
3331 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3332 if ((v & 0xc000000) == 0x8000000)
3334 else if ((v & 0xc000000) == 0x4000000)
3342 i |= UPS_CURRENT_CONNECT_STATUS;
3344 i |= UPS_PORT_ENABLED;
3345 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3347 if (v & EHCI_PS_OCA)
3348 i |= UPS_OVERCURRENT_INDICATOR;
3352 i |= UPS_PORT_POWER;
3353 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3355 if (v & EHCI_PS_CSC)
3356 i |= UPS_C_CONNECT_STATUS;
3357 if (v & EHCI_PS_PEC)
3358 i |= UPS_C_PORT_ENABLED;
3359 if (v & EHCI_PS_OCC)
3360 i |= UPS_C_OVERCURRENT_INDICATOR;
3361 if (v & EHCI_PS_FPR)
3364 i |= UPS_C_PORT_RESET;
3365 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3366 len = sizeof(sc->sc_hub_desc.ps);
3368 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3369 err = USB_ERR_IOERROR;
3371 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3373 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3375 (index > sc->sc_noport)) {
3376 err = USB_ERR_IOERROR;
3379 port = EHCI_PORTSC(index);
3380 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3382 case UHF_PORT_ENABLE:
3383 EOWRITE4(sc, port, v | EHCI_PS_PE);
3385 case UHF_PORT_SUSPEND:
3386 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3388 case UHF_PORT_RESET:
3389 DPRINTFN(6, "reset port %d\n", index);
3391 if (ehcinohighspeed) {
3393 * Connect USB device to companion
3396 ehci_disown(sc, index, 1);
3400 if (EHCI_PS_IS_LOWSPEED(v) &&
3401 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3402 /* Low speed device, give up ownership. */
3403 ehci_disown(sc, index, 1);
3406 /* Start reset sequence. */
3407 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3408 EOWRITE4(sc, port, v | EHCI_PS_PR);
3410 /* Wait for reset to complete. */
3411 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3412 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3414 /* Terminate reset sequence. */
3415 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3416 EOWRITE4(sc, port, v);
3418 /* Wait for HC to complete reset. */
3419 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3420 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3422 v = EOREAD4(sc, port);
3423 DPRINTF("ehci after reset, status=0x%08x\n", v);
3424 if (v & EHCI_PS_PR) {
3425 device_printf(sc->sc_bus.bdev,
3426 "port reset timeout\n");
3427 err = USB_ERR_TIMEOUT;
3430 if (!(v & EHCI_PS_PE) &&
3431 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3432 /* Not a high speed device, give up ownership.*/
3433 ehci_disown(sc, index, 0);
3437 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3441 case UHF_PORT_POWER:
3442 DPRINTFN(3, "set port power %d\n", index);
3443 EOWRITE4(sc, port, v | EHCI_PS_PP);
3447 DPRINTFN(3, "set port test %d\n", index);
3450 case UHF_PORT_INDICATOR:
3451 DPRINTFN(3, "set port ind %d\n", index);
3452 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3456 err = USB_ERR_IOERROR;
3460 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3461 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3462 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3463 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3466 err = USB_ERR_IOERROR;
3476 ehci_xfer_setup(struct usb_setup_params *parm)
3478 struct usb_page_search page_info;
3479 struct usb_page_cache *pc;
3481 struct usb_xfer *xfer;
3489 sc = EHCI_BUS2SC(parm->udev->bus);
3490 xfer = parm->curr_xfer;
3498 * compute maximum number of some structures
3500 if (parm->methods == &ehci_device_ctrl_methods) {
3503 * The proof for the "nqtd" formula is illustrated like
3506 * +------------------------------------+
3510 * | | xxx | x | frm 0 |
3512 * | | xxx | xx | frm 1 |
3515 * +------------------------------------+
3517 * "xxx" means a completely full USB transfer descriptor
3519 * "x" and "xx" means a short USB packet
3521 * For the remainder of an USB transfer modulo
3522 * "max_data_length" we need two USB transfer descriptors.
3523 * One to transfer the remaining data and one to finalise
3524 * with a zero length packet in case the "force_short_xfer"
3525 * flag is set. We only need two USB transfer descriptors in
3526 * the case where the transfer length of the first one is a
3527 * factor of "max_frame_size". The rest of the needed USB
3528 * transfer descriptors is given by the buffer size divided
3529 * by the maximum data payload.
3531 parm->hc_max_packet_size = 0x400;
3532 parm->hc_max_packet_count = 1;
3533 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3534 xfer->flags_int.bdma_enable = 1;
3536 usbd_transfer_setup_sub(parm);
3539 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3540 + (xfer->max_data_length / xfer->max_hc_frame_size));
3542 } else if (parm->methods == &ehci_device_bulk_methods) {
3544 parm->hc_max_packet_size = 0x400;
3545 parm->hc_max_packet_count = 1;
3546 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3547 xfer->flags_int.bdma_enable = 1;
3549 usbd_transfer_setup_sub(parm);
3552 nqtd = ((2 * xfer->nframes)
3553 + (xfer->max_data_length / xfer->max_hc_frame_size));
3555 } else if (parm->methods == &ehci_device_intr_methods) {
3557 if (parm->speed == USB_SPEED_HIGH) {
3558 parm->hc_max_packet_size = 0x400;
3559 parm->hc_max_packet_count = 3;
3560 } else if (parm->speed == USB_SPEED_FULL) {
3561 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3562 parm->hc_max_packet_count = 1;
3564 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3565 parm->hc_max_packet_count = 1;
3568 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3569 xfer->flags_int.bdma_enable = 1;
3571 usbd_transfer_setup_sub(parm);
3574 nqtd = ((2 * xfer->nframes)
3575 + (xfer->max_data_length / xfer->max_hc_frame_size));
3577 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3579 parm->hc_max_packet_size = 0x3FF;
3580 parm->hc_max_packet_count = 1;
3581 parm->hc_max_frame_size = 0x3FF;
3582 xfer->flags_int.bdma_enable = 1;
3584 usbd_transfer_setup_sub(parm);
3586 nsitd = xfer->nframes;
3588 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3590 parm->hc_max_packet_size = 0x400;
3591 parm->hc_max_packet_count = 3;
3592 parm->hc_max_frame_size = 0xC00;
3593 xfer->flags_int.bdma_enable = 1;
3595 usbd_transfer_setup_sub(parm);
3597 nitd = ((xfer->nframes + 7) / 8) <<
3598 usbd_xfer_get_fps_shift(xfer);
3602 parm->hc_max_packet_size = 0x400;
3603 parm->hc_max_packet_count = 1;
3604 parm->hc_max_frame_size = 0x400;
3606 usbd_transfer_setup_sub(parm);
3615 * Allocate queue heads and transfer descriptors
3619 if (usbd_transfer_setup_sub_malloc(
3620 parm, &pc, sizeof(ehci_itd_t),
3621 EHCI_ITD_ALIGN, nitd)) {
3622 parm->err = USB_ERR_NOMEM;
3626 for (n = 0; n != nitd; n++) {
3629 usbd_get_page(pc + n, 0, &page_info);
3631 td = page_info.buffer;
3634 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3635 td->obj_next = last_obj;
3636 td->page_cache = pc + n;
3640 usb_pc_cpu_flush(pc + n);
3643 if (usbd_transfer_setup_sub_malloc(
3644 parm, &pc, sizeof(ehci_sitd_t),
3645 EHCI_SITD_ALIGN, nsitd)) {
3646 parm->err = USB_ERR_NOMEM;
3650 for (n = 0; n != nsitd; n++) {
3653 usbd_get_page(pc + n, 0, &page_info);
3655 td = page_info.buffer;
3658 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3659 td->obj_next = last_obj;
3660 td->page_cache = pc + n;
3664 usb_pc_cpu_flush(pc + n);
3667 if (usbd_transfer_setup_sub_malloc(
3668 parm, &pc, sizeof(ehci_qtd_t),
3669 EHCI_QTD_ALIGN, nqtd)) {
3670 parm->err = USB_ERR_NOMEM;
3674 for (n = 0; n != nqtd; n++) {
3677 usbd_get_page(pc + n, 0, &page_info);
3679 qtd = page_info.buffer;
3682 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3683 qtd->obj_next = last_obj;
3684 qtd->page_cache = pc + n;
3688 usb_pc_cpu_flush(pc + n);
3691 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3695 if (usbd_transfer_setup_sub_malloc(
3696 parm, &pc, sizeof(ehci_qh_t),
3697 EHCI_QH_ALIGN, nqh)) {
3698 parm->err = USB_ERR_NOMEM;
3702 for (n = 0; n != nqh; n++) {
3705 usbd_get_page(pc + n, 0, &page_info);
3707 qh = page_info.buffer;
3710 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3711 qh->obj_next = last_obj;
3712 qh->page_cache = pc + n;
3716 usb_pc_cpu_flush(pc + n);
3719 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3721 if (!xfer->flags_int.curr_dma_set) {
3722 xfer->flags_int.curr_dma_set = 1;
3728 ehci_xfer_unsetup(struct usb_xfer *xfer)
3734 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3735 struct usb_endpoint *ep)
3737 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3739 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3741 edesc->bEndpointAddress, udev->flags.usb_mode,
3744 if (udev->flags.usb_mode != USB_MODE_HOST) {
3748 if (udev->device_index != sc->sc_addr) {
3750 if ((udev->speed != USB_SPEED_HIGH) &&
3751 ((udev->hs_hub_addr == 0) ||
3752 (udev->hs_port_no == 0) ||
3753 (udev->parent_hs_hub == NULL) ||
3754 (udev->parent_hs_hub->hub == NULL))) {
3755 /* We need a transaction translator */
3758 switch (edesc->bmAttributes & UE_XFERTYPE) {
3760 ep->methods = &ehci_device_ctrl_methods;
3763 ep->methods = &ehci_device_intr_methods;
3765 case UE_ISOCHRONOUS:
3766 if (udev->speed == USB_SPEED_HIGH) {
3767 ep->methods = &ehci_device_isoc_hs_methods;
3768 } else if (udev->speed == USB_SPEED_FULL) {
3769 ep->methods = &ehci_device_isoc_fs_methods;
3773 ep->methods = &ehci_device_bulk_methods;
3785 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3788 * Wait until the hardware has finished any possible use of
3789 * the transfer descriptor(s) and QH
3791 *pus = (1125); /* microseconds */
3795 ehci_device_resume(struct usb_device *udev)
3797 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3798 struct usb_xfer *xfer;
3799 struct usb_pipe_methods *methods;
3803 USB_BUS_LOCK(udev->bus);
3805 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3807 if (xfer->xroot->udev == udev) {
3809 methods = xfer->endpoint->methods;
3811 if ((methods == &ehci_device_bulk_methods) ||
3812 (methods == &ehci_device_ctrl_methods)) {
3813 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3814 sc->sc_async_p_last);
3816 if (methods == &ehci_device_intr_methods) {
3817 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3818 sc->sc_intr_p_last[xfer->qh_pos]);
3823 USB_BUS_UNLOCK(udev->bus);
3829 ehci_device_suspend(struct usb_device *udev)
3831 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3832 struct usb_xfer *xfer;
3833 struct usb_pipe_methods *methods;
3837 USB_BUS_LOCK(udev->bus);
3839 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3841 if (xfer->xroot->udev == udev) {
3843 methods = xfer->endpoint->methods;
3845 if ((methods == &ehci_device_bulk_methods) ||
3846 (methods == &ehci_device_ctrl_methods)) {
3847 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3848 sc->sc_async_p_last);
3850 if (methods == &ehci_device_intr_methods) {
3851 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3852 sc->sc_intr_p_last[xfer->qh_pos]);
3857 USB_BUS_UNLOCK(udev->bus);
3861 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3863 struct ehci_softc *sc = EHCI_BUS2SC(bus);
3866 case USB_HW_POWER_SUSPEND:
3867 case USB_HW_POWER_SHUTDOWN:
3870 case USB_HW_POWER_RESUME:
3879 ehci_set_hw_power(struct usb_bus *bus)
3881 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3889 flags = bus->hw_power_state;
3891 temp = EOREAD4(sc, EHCI_USBCMD);
3893 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3895 if (flags & (USB_HW_POWER_CONTROL |
3896 USB_HW_POWER_BULK)) {
3897 DPRINTF("Async is active\n");
3898 temp |= EHCI_CMD_ASE;
3900 if (flags & (USB_HW_POWER_INTERRUPT |
3901 USB_HW_POWER_ISOC)) {
3902 DPRINTF("Periodic is active\n");
3903 temp |= EHCI_CMD_PSE;
3905 EOWRITE4(sc, EHCI_USBCMD, temp);
3907 USB_BUS_UNLOCK(bus);
3913 ehci_start_dma_delay_second(struct usb_xfer *xfer)
3915 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3919 /* trigger doorbell */
3920 ehci_doorbell_async(sc);
3922 /* give the doorbell 4ms */
3923 usbd_transfer_timeout_ms(xfer,
3924 (void (*)(void *))&usb_dma_delay_done_cb, 4);
3928 * Ring the doorbell twice before freeing any DMA descriptors. Some host
3929 * controllers apparently cache the QH descriptors and need a message
3930 * that the cache needs to be discarded.
3933 ehci_start_dma_delay(struct usb_xfer *xfer)
3935 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3939 /* trigger doorbell */
3940 ehci_doorbell_async(sc);
3942 /* give the doorbell 4ms */
3943 usbd_transfer_timeout_ms(xfer,
3944 (void (*)(void *))&ehci_start_dma_delay_second, 4);
3947 struct usb_bus_methods ehci_bus_methods =
3949 .endpoint_init = ehci_ep_init,
3950 .xfer_setup = ehci_xfer_setup,
3951 .xfer_unsetup = ehci_xfer_unsetup,
3952 .get_dma_delay = ehci_get_dma_delay,
3953 .device_resume = ehci_device_resume,
3954 .device_suspend = ehci_device_suspend,
3955 .set_hw_power = ehci_set_hw_power,
3956 .set_hw_power_sleep = ehci_set_hw_power_sleep,
3957 .roothub_exec = ehci_roothub_exec,
3958 .xfer_poll = ehci_do_poll,
3959 .start_dma_delay = ehci_start_dma_delay,