2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
43 * 1) command failures are not recovered correctly
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD$");
49 #include <sys/stdint.h>
50 #include <sys/stddef.h>
51 #include <sys/param.h>
52 #include <sys/queue.h>
53 #include <sys/types.h>
54 #include <sys/systm.h>
55 #include <sys/kernel.h>
57 #include <sys/linker_set.h>
58 #include <sys/module.h>
60 #include <sys/mutex.h>
61 #include <sys/condvar.h>
62 #include <sys/sysctl.h>
64 #include <sys/unistd.h>
65 #include <sys/callout.h>
66 #include <sys/malloc.h>
69 #include <dev/usb/usb.h>
70 #include <dev/usb/usbdi.h>
72 #define USB_DEBUG_VAR ehcidebug
74 #include <dev/usb/usb_core.h>
75 #include <dev/usb/usb_debug.h>
76 #include <dev/usb/usb_busdma.h>
77 #include <dev/usb/usb_process.h>
78 #include <dev/usb/usb_transfer.h>
79 #include <dev/usb/usb_device.h>
80 #include <dev/usb/usb_hub.h>
81 #include <dev/usb/usb_util.h>
83 #include <dev/usb/usb_controller.h>
84 #include <dev/usb/usb_bus.h>
85 #include <dev/usb/controller/ehci.h>
86 #include <dev/usb/controller/ehcireg.h>
88 #define EHCI_BUS2SC(bus) \
89 ((ehci_softc_t *)(((uint8_t *)(bus)) - \
90 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
93 static int ehcidebug = 0;
94 static int ehcinohighspeed = 0;
95 static int ehciiaadbug = 0;
96 static int ehcilostintrbug = 0;
98 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
99 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
100 &ehcidebug, 0, "Debug level");
101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
102 &ehcinohighspeed, 0, "Disable High Speed USB");
103 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW,
104 &ehciiaadbug, 0, "Enable doorbell bug workaround");
105 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW,
106 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
108 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
109 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
110 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
111 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
113 static void ehci_dump_regs(ehci_softc_t *sc);
114 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
118 #define EHCI_INTR_ENDPT 1
120 extern struct usb_bus_methods ehci_bus_methods;
121 extern struct usb_pipe_methods ehci_device_bulk_methods;
122 extern struct usb_pipe_methods ehci_device_ctrl_methods;
123 extern struct usb_pipe_methods ehci_device_intr_methods;
124 extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
125 extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
127 static void ehci_do_poll(struct usb_bus *);
128 static void ehci_device_done(struct usb_xfer *, usb_error_t);
129 static uint8_t ehci_check_transfer(struct usb_xfer *);
130 static void ehci_timeout(void *);
131 static void ehci_poll_timeout(void *);
133 static void ehci_root_intr(ehci_softc_t *sc);
135 struct ehci_std_temp {
137 struct usb_page_cache *pc;
143 uint16_t max_frame_size;
145 uint8_t auto_data_toggle;
146 uint8_t setup_alt_next;
148 uint8_t can_use_next;
152 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
154 ehci_softc_t *sc = EHCI_BUS2SC(bus);
157 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
158 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
160 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
161 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
163 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
164 cb(bus, sc->sc_hw.intr_start_pc + i,
165 sc->sc_hw.intr_start_pg + i,
166 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
169 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
170 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
171 sc->sc_hw.isoc_hs_start_pg + i,
172 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
175 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
176 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
177 sc->sc_hw.isoc_fs_start_pg + i,
178 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
183 ehci_reset(ehci_softc_t *sc)
188 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
189 for (i = 0; i < 100; i++) {
190 usb_pause_mtx(NULL, hz / 1000);
191 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
193 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
195 * Force USBMODE as requested. Controllers
196 * may have multiple operating modes.
198 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
199 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
200 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
201 device_printf(sc->sc_bus.bdev,
202 "set host controller mode\n");
204 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
205 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
206 device_printf(sc->sc_bus.bdev,
207 "set big-endian mode\n");
209 EOWRITE4(sc, EHCI_USBMODE, usbmode);
214 device_printf(sc->sc_bus.bdev, "reset timeout\n");
215 return (USB_ERR_IOERROR);
219 ehci_hcreset(ehci_softc_t *sc)
224 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
225 for (i = 0; i < 100; i++) {
226 usb_pause_mtx(NULL, hz / 1000);
227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
233 * Fall through and try reset anyway even though
234 * Table 2-9 in the EHCI spec says this will result
235 * in undefined behavior.
237 device_printf(sc->sc_bus.bdev, "stop timeout\n");
239 return ehci_reset(sc);
243 ehci_init(ehci_softc_t *sc)
245 struct usb_page_search buf_res;
258 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
259 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
263 sc->sc_flags |= EHCI_SCFLG_IAADBUG;
265 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
271 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
273 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
274 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
275 version >> 8, version & 0xff);
277 sparams = EREAD4(sc, EHCI_HCSPARAMS);
278 DPRINTF("sparams=0x%x\n", sparams);
280 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
281 cparams = EREAD4(sc, EHCI_HCCPARAMS);
282 DPRINTF("cparams=0x%x\n", cparams);
284 if (EHCI_HCC_64BIT(cparams)) {
285 DPRINTF("HCC uses 64-bit structures\n");
287 /* MUST clear segment register if 64 bit capable */
288 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
290 sc->sc_bus.usbrev = USB_REV_2_0;
292 /* Reset the controller */
293 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
295 err = ehci_hcreset(sc);
297 device_printf(sc->sc_bus.bdev, "reset timeout\n");
301 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
302 * bytes 2: 256*4 bytes 3: unknown
304 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
305 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
306 return (USB_ERR_IOERROR);
308 /* set up the bus struct */
309 sc->sc_bus.methods = &ehci_bus_methods;
311 sc->sc_eintrs = EHCI_NORMAL_INTRS;
313 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
316 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
320 /* initialize page cache pointer */
322 qh->page_cache = sc->sc_hw.intr_start_pc + i;
324 /* store a pointer to queue head */
326 sc->sc_intr_p_last[i] = qh;
329 htohc32(sc, buf_res.physaddr) |
330 htohc32(sc, EHCI_LINK_QH);
333 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
335 htohc32(sc, EHCI_QH_SET_MULT(1));
338 qh->qh_qtd.qtd_next =
339 htohc32(sc, EHCI_LINK_TERMINATE);
340 qh->qh_qtd.qtd_altnext =
341 htohc32(sc, EHCI_LINK_TERMINATE);
342 qh->qh_qtd.qtd_status =
343 htohc32(sc, EHCI_QTD_HALTED);
347 * the QHs are arranged to give poll intervals that are
348 * powers of 2 times 1ms
350 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
357 y = (x ^ bit) | (bit / 2);
359 qh_x = sc->sc_intr_p_last[x];
360 qh_y = sc->sc_intr_p_last[y];
363 * the next QH has half the poll interval
365 qh_x->qh_link = qh_y->qh_self;
375 qh = sc->sc_intr_p_last[0];
377 /* the last (1ms) QH terminates */
378 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
380 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
384 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
386 sitd = buf_res.buffer;
388 /* initialize page cache pointer */
390 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
392 /* store a pointer to the transfer descriptor */
394 sc->sc_isoc_fs_p_last[i] = sitd;
396 /* initialize full speed isochronous */
399 htohc32(sc, buf_res.physaddr) |
400 htohc32(sc, EHCI_LINK_SITD);
403 htohc32(sc, EHCI_LINK_TERMINATE);
406 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
409 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
411 itd = buf_res.buffer;
413 /* initialize page cache pointer */
415 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
417 /* store a pointer to the transfer descriptor */
419 sc->sc_isoc_hs_p_last[i] = itd;
421 /* initialize high speed isochronous */
424 htohc32(sc, buf_res.physaddr) |
425 htohc32(sc, EHCI_LINK_ITD);
431 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
436 pframes = buf_res.buffer;
440 * pframes -> high speed isochronous ->
441 * full speed isochronous -> interrupt QH's
443 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
444 pframes[i] = sc->sc_isoc_hs_p_last
445 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
448 /* setup sync list pointer */
449 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
451 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
459 /* initialize page cache pointer */
461 qh->page_cache = &sc->sc_hw.async_start_pc;
463 /* store a pointer to the queue head */
465 sc->sc_async_p_last = qh;
467 /* init dummy QH that starts the async list */
470 htohc32(sc, buf_res.physaddr) |
471 htohc32(sc, EHCI_LINK_QH);
475 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
476 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
477 qh->qh_link = qh->qh_self;
480 /* fill the overlay qTD */
481 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
482 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
483 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
485 /* flush all cache into memory */
487 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
491 ehci_dump_sqh(sc, sc->sc_async_p_last);
495 /* setup async list pointer */
496 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
499 /* enable interrupts */
500 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
502 /* turn on controller */
503 EOWRITE4(sc, EHCI_USBCMD,
504 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
505 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
510 /* Take over port ownership */
511 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
513 for (i = 0; i < 100; i++) {
514 usb_pause_mtx(NULL, hz / 1000);
515 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
521 device_printf(sc->sc_bus.bdev, "run timeout\n");
522 return (USB_ERR_IOERROR);
526 /* catch any lost interrupts */
527 ehci_do_poll(&sc->sc_bus);
533 * shut down the controller when the system is going down
536 ehci_detach(ehci_softc_t *sc)
538 USB_BUS_LOCK(&sc->sc_bus);
540 usb_callout_stop(&sc->sc_tmo_pcd);
541 usb_callout_stop(&sc->sc_tmo_poll);
543 EOWRITE4(sc, EHCI_USBINTR, 0);
544 USB_BUS_UNLOCK(&sc->sc_bus);
546 if (ehci_hcreset(sc)) {
547 DPRINTF("reset failed!\n");
550 /* XXX let stray task complete */
551 usb_pause_mtx(NULL, hz / 20);
553 usb_callout_drain(&sc->sc_tmo_pcd);
554 usb_callout_drain(&sc->sc_tmo_poll);
558 ehci_suspend(ehci_softc_t *sc)
564 USB_BUS_LOCK(&sc->sc_bus);
566 for (i = 1; i <= sc->sc_noport; i++) {
567 cmd = EOREAD4(sc, EHCI_PORTSC(i));
568 if (((cmd & EHCI_PS_PO) == 0) &&
569 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
570 EOWRITE4(sc, EHCI_PORTSC(i),
575 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
577 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
578 EOWRITE4(sc, EHCI_USBCMD, cmd);
580 for (i = 0; i < 100; i++) {
581 hcr = EOREAD4(sc, EHCI_USBSTS) &
582 (EHCI_STS_ASS | EHCI_STS_PSS);
587 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
591 device_printf(sc->sc_bus.bdev, "reset timeout\n");
594 EOWRITE4(sc, EHCI_USBCMD, cmd);
596 for (i = 0; i < 100; i++) {
597 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
598 if (hcr == EHCI_STS_HCH) {
601 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
604 if (hcr != EHCI_STS_HCH) {
605 device_printf(sc->sc_bus.bdev,
608 USB_BUS_UNLOCK(&sc->sc_bus);
612 ehci_resume(ehci_softc_t *sc)
614 struct usb_page_search buf_res;
619 USB_BUS_LOCK(&sc->sc_bus);
621 /* restore things in case the bios doesn't */
622 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
624 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
625 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
627 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
628 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
630 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
633 for (i = 1; i <= sc->sc_noport; i++) {
634 cmd = EOREAD4(sc, EHCI_PORTSC(i));
635 if (((cmd & EHCI_PS_PO) == 0) &&
636 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
637 EOWRITE4(sc, EHCI_PORTSC(i),
644 usb_pause_mtx(&sc->sc_bus.bus_mtx,
645 USB_MS_TO_TICKS(USB_RESUME_WAIT));
647 for (i = 1; i <= sc->sc_noport; i++) {
648 cmd = EOREAD4(sc, EHCI_PORTSC(i));
649 if (((cmd & EHCI_PS_PO) == 0) &&
650 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
651 EOWRITE4(sc, EHCI_PORTSC(i),
656 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
658 for (i = 0; i < 100; i++) {
659 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
660 if (hcr != EHCI_STS_HCH) {
663 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
665 if (hcr == EHCI_STS_HCH) {
666 device_printf(sc->sc_bus.bdev, "config timeout\n");
669 USB_BUS_UNLOCK(&sc->sc_bus);
672 USB_MS_TO_TICKS(USB_RESUME_WAIT));
674 /* catch any lost interrupts */
675 ehci_do_poll(&sc->sc_bus);
679 ehci_shutdown(ehci_softc_t *sc)
681 DPRINTF("stopping the HC\n");
683 if (ehci_hcreset(sc)) {
684 DPRINTF("reset failed!\n");
690 ehci_dump_regs(ehci_softc_t *sc)
694 i = EOREAD4(sc, EHCI_USBCMD);
695 printf("cmd=0x%08x\n", i);
697 if (i & EHCI_CMD_ITC_1)
698 printf(" EHCI_CMD_ITC_1\n");
699 if (i & EHCI_CMD_ITC_2)
700 printf(" EHCI_CMD_ITC_2\n");
701 if (i & EHCI_CMD_ITC_4)
702 printf(" EHCI_CMD_ITC_4\n");
703 if (i & EHCI_CMD_ITC_8)
704 printf(" EHCI_CMD_ITC_8\n");
705 if (i & EHCI_CMD_ITC_16)
706 printf(" EHCI_CMD_ITC_16\n");
707 if (i & EHCI_CMD_ITC_32)
708 printf(" EHCI_CMD_ITC_32\n");
709 if (i & EHCI_CMD_ITC_64)
710 printf(" EHCI_CMD_ITC_64\n");
711 if (i & EHCI_CMD_ASPME)
712 printf(" EHCI_CMD_ASPME\n");
713 if (i & EHCI_CMD_ASPMC)
714 printf(" EHCI_CMD_ASPMC\n");
715 if (i & EHCI_CMD_LHCR)
716 printf(" EHCI_CMD_LHCR\n");
717 if (i & EHCI_CMD_IAAD)
718 printf(" EHCI_CMD_IAAD\n");
719 if (i & EHCI_CMD_ASE)
720 printf(" EHCI_CMD_ASE\n");
721 if (i & EHCI_CMD_PSE)
722 printf(" EHCI_CMD_PSE\n");
723 if (i & EHCI_CMD_FLS_M)
724 printf(" EHCI_CMD_FLS_M\n");
725 if (i & EHCI_CMD_HCRESET)
726 printf(" EHCI_CMD_HCRESET\n");
728 printf(" EHCI_CMD_RS\n");
730 i = EOREAD4(sc, EHCI_USBSTS);
732 printf("sts=0x%08x\n", i);
734 if (i & EHCI_STS_ASS)
735 printf(" EHCI_STS_ASS\n");
736 if (i & EHCI_STS_PSS)
737 printf(" EHCI_STS_PSS\n");
738 if (i & EHCI_STS_REC)
739 printf(" EHCI_STS_REC\n");
740 if (i & EHCI_STS_HCH)
741 printf(" EHCI_STS_HCH\n");
742 if (i & EHCI_STS_IAA)
743 printf(" EHCI_STS_IAA\n");
744 if (i & EHCI_STS_HSE)
745 printf(" EHCI_STS_HSE\n");
746 if (i & EHCI_STS_FLR)
747 printf(" EHCI_STS_FLR\n");
748 if (i & EHCI_STS_PCD)
749 printf(" EHCI_STS_PCD\n");
750 if (i & EHCI_STS_ERRINT)
751 printf(" EHCI_STS_ERRINT\n");
752 if (i & EHCI_STS_INT)
753 printf(" EHCI_STS_INT\n");
755 printf("ien=0x%08x\n",
756 EOREAD4(sc, EHCI_USBINTR));
757 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
758 EOREAD4(sc, EHCI_FRINDEX),
759 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
760 EOREAD4(sc, EHCI_PERIODICLISTBASE),
761 EOREAD4(sc, EHCI_ASYNCLISTADDR));
762 for (i = 1; i <= sc->sc_noport; i++) {
763 printf("port %d status=0x%08x\n", i,
764 EOREAD4(sc, EHCI_PORTSC(i)));
769 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
771 link = hc32toh(sc, link);
772 printf("0x%08x", link);
773 if (link & EHCI_LINK_TERMINATE)
778 switch (EHCI_LINK_TYPE(link)) {
798 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
803 ehci_dump_link(sc, qtd->qtd_next, 0);
805 ehci_dump_link(sc, qtd->qtd_altnext, 0);
807 s = hc32toh(sc, qtd->qtd_status);
808 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
809 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
810 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
811 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
812 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
813 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
814 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
815 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
816 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
817 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
818 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
819 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
820 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
822 for (s = 0; s < 5; s++) {
823 printf(" buffer[%d]=0x%08x\n", s,
824 hc32toh(sc, qtd->qtd_buffer[s]));
826 for (s = 0; s < 5; s++) {
827 printf(" buffer_hi[%d]=0x%08x\n", s,
828 hc32toh(sc, qtd->qtd_buffer_hi[s]));
833 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
837 usb_pc_cpu_invalidate(sqtd->page_cache);
838 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
839 ehci_dump_qtd(sc, sqtd);
840 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
845 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
851 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
852 stop = ehci_dump_sqtd(sc, sqtd);
855 printf("dump aborted, too many TDs\n");
860 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
865 usb_pc_cpu_invalidate(qh->page_cache);
866 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
868 ehci_dump_link(sc, qh->qh_link, 1);
870 endp = hc32toh(sc, qh->qh_endp);
871 printf(" endp=0x%08x\n", endp);
872 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
873 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
874 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
875 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
876 printf(" mpl=0x%x ctl=%d nrl=%d\n",
877 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
878 EHCI_QH_GET_NRL(endp));
879 endphub = hc32toh(sc, qh->qh_endphub);
880 printf(" endphub=0x%08x\n", endphub);
881 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
882 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
883 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
884 EHCI_QH_GET_MULT(endphub));
886 ehci_dump_link(sc, qh->qh_curqtd, 0);
888 printf("Overlay qTD:\n");
889 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
893 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
895 usb_pc_cpu_invalidate(sitd->page_cache);
896 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
897 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
898 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
899 hc32toh(sc, sitd->sitd_portaddr),
900 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
902 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
903 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
904 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
905 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
906 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
907 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
908 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
909 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
910 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
911 hc32toh(sc, sitd->sitd_back),
912 hc32toh(sc, sitd->sitd_bp[0]),
913 hc32toh(sc, sitd->sitd_bp[1]),
914 hc32toh(sc, sitd->sitd_bp_hi[0]),
915 hc32toh(sc, sitd->sitd_bp_hi[1]));
919 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
921 usb_pc_cpu_invalidate(itd->page_cache);
922 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
923 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
924 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
925 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
926 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
927 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
928 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
929 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
930 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
931 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
932 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
933 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
934 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
935 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
936 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
937 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
938 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
939 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
940 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
941 printf(" addr=0x%02x; endpt=0x%01x\n",
942 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
943 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
944 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
945 printf(" dir=%s; mpl=0x%02x\n",
946 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
947 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
948 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
949 hc32toh(sc, itd->itd_bp[2]),
950 hc32toh(sc, itd->itd_bp[3]),
951 hc32toh(sc, itd->itd_bp[4]),
952 hc32toh(sc, itd->itd_bp[5]),
953 hc32toh(sc, itd->itd_bp[6]));
954 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
955 " 0x%08x,0x%08x,0x%08x\n",
956 hc32toh(sc, itd->itd_bp_hi[0]),
957 hc32toh(sc, itd->itd_bp_hi[1]),
958 hc32toh(sc, itd->itd_bp_hi[2]),
959 hc32toh(sc, itd->itd_bp_hi[3]),
960 hc32toh(sc, itd->itd_bp_hi[4]),
961 hc32toh(sc, itd->itd_bp_hi[5]),
962 hc32toh(sc, itd->itd_bp_hi[6]));
966 ehci_dump_isoc(ehci_softc_t *sc)
973 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
974 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
976 printf("%s: isochronous dump from frame 0x%03x:\n",
979 itd = sc->sc_isoc_hs_p_last[pos];
980 sitd = sc->sc_isoc_fs_p_last[pos];
982 while (itd && max && max--) {
983 ehci_dump_itd(sc, itd);
987 while (sitd && max && max--) {
988 ehci_dump_sitd(sc, sitd);
996 ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
998 /* check for early completion */
999 if (ehci_check_transfer(xfer)) {
1002 /* put transfer on interrupt queue */
1003 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1005 /* start timeout, if any */
1006 if (xfer->timeout != 0) {
1007 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
1011 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
1012 static ehci_sitd_t *
1013 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1015 DPRINTFN(11, "%p to %p\n", std, last);
1017 /* (sc->sc_bus.mtx) must be locked */
1019 std->next = last->next;
1020 std->sitd_next = last->sitd_next;
1024 usb_pc_cpu_flush(std->page_cache);
1027 * the last->next->prev is never followed: std->next->prev = std;
1030 last->sitd_next = std->sitd_self;
1032 usb_pc_cpu_flush(last->page_cache);
1037 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
1039 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1041 DPRINTFN(11, "%p to %p\n", std, last);
1043 /* (sc->sc_bus.mtx) must be locked */
1045 std->next = last->next;
1046 std->itd_next = last->itd_next;
1050 usb_pc_cpu_flush(std->page_cache);
1053 * the last->next->prev is never followed: std->next->prev = std;
1056 last->itd_next = std->itd_self;
1058 usb_pc_cpu_flush(last->page_cache);
1063 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1065 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1067 DPRINTFN(11, "%p to %p\n", sqh, last);
1069 if (sqh->prev != NULL) {
1070 /* should not happen */
1071 DPRINTFN(0, "QH already linked!\n");
1074 /* (sc->sc_bus.mtx) must be locked */
1076 sqh->next = last->next;
1077 sqh->qh_link = last->qh_link;
1081 usb_pc_cpu_flush(sqh->page_cache);
1084 * the last->next->prev is never followed: sqh->next->prev = sqh;
1088 last->qh_link = sqh->qh_self;
1090 usb_pc_cpu_flush(last->page_cache);
1095 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1096 static ehci_sitd_t *
1097 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1099 DPRINTFN(11, "%p from %p\n", std, last);
1101 /* (sc->sc_bus.mtx) must be locked */
1103 std->prev->next = std->next;
1104 std->prev->sitd_next = std->sitd_next;
1106 usb_pc_cpu_flush(std->prev->page_cache);
1109 std->next->prev = std->prev;
1110 usb_pc_cpu_flush(std->next->page_cache);
1112 return ((last == std) ? std->prev : last);
1115 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1117 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1119 DPRINTFN(11, "%p from %p\n", std, last);
1121 /* (sc->sc_bus.mtx) must be locked */
1123 std->prev->next = std->next;
1124 std->prev->itd_next = std->itd_next;
1126 usb_pc_cpu_flush(std->prev->page_cache);
1129 std->next->prev = std->prev;
1130 usb_pc_cpu_flush(std->next->page_cache);
1132 return ((last == std) ? std->prev : last);
1135 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1137 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1139 DPRINTFN(11, "%p from %p\n", sqh, last);
1141 /* (sc->sc_bus.mtx) must be locked */
1143 /* only remove if not removed from a queue */
1146 sqh->prev->next = sqh->next;
1147 sqh->prev->qh_link = sqh->qh_link;
1149 usb_pc_cpu_flush(sqh->prev->page_cache);
1152 sqh->next->prev = sqh->prev;
1153 usb_pc_cpu_flush(sqh->next->page_cache);
1155 last = ((last == sqh) ? sqh->prev : last);
1159 usb_pc_cpu_flush(sqh->page_cache);
1165 ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1167 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1169 ehci_qtd_t *td_alt_next;
1173 td = xfer->td_transfer_cache;
1174 td_alt_next = td->alt_next;
1176 if (xfer->aframes != xfer->nframes) {
1177 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1181 usb_pc_cpu_invalidate(td->page_cache);
1182 status = hc32toh(sc, td->qtd_status);
1184 len = EHCI_QTD_GET_BYTES(status);
1187 * Verify the status length and
1188 * add the length to "frlengths[]":
1190 if (len > td->len) {
1191 /* should not happen */
1192 DPRINTF("Invalid status length, "
1193 "0x%04x/0x%04x bytes\n", len, td->len);
1194 status |= EHCI_QTD_HALTED;
1195 } else if (xfer->aframes != xfer->nframes) {
1196 xfer->frlengths[xfer->aframes] += td->len - len;
1198 /* Check for last transfer */
1199 if (((void *)td) == xfer->td_transfer_last) {
1203 /* Check for transfer error */
1204 if (status & EHCI_QTD_HALTED) {
1205 /* the transfer is finished */
1209 /* Check for short transfer */
1211 if (xfer->flags_int.short_frames_ok) {
1212 /* follow alt next */
1215 /* the transfer is finished */
1222 if (td->alt_next != td_alt_next) {
1223 /* this USB frame is complete */
1228 /* update transfer cache */
1230 xfer->td_transfer_cache = td;
1233 if (status & EHCI_QTD_STATERRS) {
1234 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1235 "status=%s%s%s%s%s%s%s%s\n",
1236 xfer->address, xfer->endpointno, xfer->aframes,
1237 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1238 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1239 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1240 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1241 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1242 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1243 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1244 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1248 return ((status & EHCI_QTD_HALTED) ?
1249 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1253 ehci_non_isoc_done(struct usb_xfer *xfer)
1255 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1258 usb_error_t err = 0;
1260 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1261 xfer, xfer->endpoint);
1264 if (ehcidebug > 10) {
1265 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1267 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1271 /* extract data toggle directly from the QH's overlay area */
1273 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1275 usb_pc_cpu_invalidate(qh->page_cache);
1277 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1279 xfer->endpoint->toggle_next =
1280 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0;
1284 xfer->td_transfer_cache = xfer->td_transfer_first;
1286 if (xfer->flags_int.control_xfr) {
1288 if (xfer->flags_int.control_hdr) {
1290 err = ehci_non_isoc_done_sub(xfer);
1294 if (xfer->td_transfer_cache == NULL) {
1298 while (xfer->aframes != xfer->nframes) {
1300 err = ehci_non_isoc_done_sub(xfer);
1303 if (xfer->td_transfer_cache == NULL) {
1308 if (xfer->flags_int.control_xfr &&
1309 !xfer->flags_int.control_act) {
1311 err = ehci_non_isoc_done_sub(xfer);
1314 ehci_device_done(xfer, err);
1317 /*------------------------------------------------------------------------*
1318 * ehci_check_transfer
1321 * 0: USB transfer is not finished
1322 * Else: USB transfer is finished
1323 *------------------------------------------------------------------------*/
1325 ehci_check_transfer(struct usb_xfer *xfer)
1327 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1328 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1332 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1334 if (methods == &ehci_device_isoc_fs_methods) {
1337 /* isochronous full speed transfer */
1339 td = xfer->td_transfer_last;
1340 usb_pc_cpu_invalidate(td->page_cache);
1341 status = hc32toh(sc, td->sitd_status);
1343 /* also check if first is complete */
1345 td = xfer->td_transfer_first;
1346 usb_pc_cpu_invalidate(td->page_cache);
1347 status |= hc32toh(sc, td->sitd_status);
1349 if (!(status & EHCI_SITD_ACTIVE)) {
1350 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1353 } else if (methods == &ehci_device_isoc_hs_methods) {
1356 /* isochronous high speed transfer */
1358 /* check last transfer */
1359 td = xfer->td_transfer_last;
1360 usb_pc_cpu_invalidate(td->page_cache);
1361 status = td->itd_status[0];
1362 status |= td->itd_status[1];
1363 status |= td->itd_status[2];
1364 status |= td->itd_status[3];
1365 status |= td->itd_status[4];
1366 status |= td->itd_status[5];
1367 status |= td->itd_status[6];
1368 status |= td->itd_status[7];
1370 /* also check first transfer */
1371 td = xfer->td_transfer_first;
1372 usb_pc_cpu_invalidate(td->page_cache);
1373 status |= td->itd_status[0];
1374 status |= td->itd_status[1];
1375 status |= td->itd_status[2];
1376 status |= td->itd_status[3];
1377 status |= td->itd_status[4];
1378 status |= td->itd_status[5];
1379 status |= td->itd_status[6];
1380 status |= td->itd_status[7];
1382 /* if no transactions are active we continue */
1383 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1384 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1391 /* non-isochronous transfer */
1394 * check whether there is an error somewhere in the middle,
1395 * or whether there was a short packet (SPD and not ACTIVE)
1397 td = xfer->td_transfer_cache;
1399 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1401 usb_pc_cpu_invalidate(qh->page_cache);
1403 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1404 if (status & EHCI_QTD_ACTIVE) {
1405 /* transfer is pending */
1410 usb_pc_cpu_invalidate(td->page_cache);
1411 status = hc32toh(sc, td->qtd_status);
1414 * Check if there is an active TD which
1415 * indicates that the transfer isn't done.
1417 if (status & EHCI_QTD_ACTIVE) {
1419 if (xfer->td_transfer_cache != td) {
1420 xfer->td_transfer_cache = td;
1421 if (qh->qh_qtd.qtd_next &
1422 htohc32(sc, EHCI_LINK_TERMINATE)) {
1423 /* XXX - manually advance to next frame */
1424 qh->qh_qtd.qtd_next = td->qtd_self;
1425 usb_pc_cpu_flush(td->page_cache);
1431 * last transfer descriptor makes the transfer done
1433 if (((void *)td) == xfer->td_transfer_last) {
1437 * any kind of error makes the transfer done
1439 if (status & EHCI_QTD_HALTED) {
1443 * if there is no alternate next transfer, a short
1444 * packet also makes the transfer done
1446 if (EHCI_QTD_GET_BYTES(status)) {
1447 if (xfer->flags_int.short_frames_ok) {
1448 /* follow alt next */
1454 /* transfer is done */
1459 ehci_non_isoc_done(xfer);
1464 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1472 ehci_pcd_enable(ehci_softc_t *sc)
1474 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1476 sc->sc_eintrs |= EHCI_STS_PCD;
1477 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1479 /* acknowledge any PCD interrupt */
1480 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1486 ehci_interrupt_poll(ehci_softc_t *sc)
1488 struct usb_xfer *xfer;
1491 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1493 * check if transfer is transferred
1495 if (ehci_check_transfer(xfer)) {
1496 /* queue has been modified */
1503 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1504 * writing back the qTD status, or miss signalling occasionally under
1505 * heavy load. If the host machine is too fast, we can miss
1506 * transaction completion - when we scan the active list the
1507 * transaction still seems to be active. This generally exhibits
1508 * itself as a umass stall that never recovers.
1510 * We work around this behaviour by setting up this callback after any
1511 * softintr that completes with transactions still pending, giving us
1512 * another chance to check for completion after the writeback has
1516 ehci_poll_timeout(void *arg)
1518 ehci_softc_t *sc = arg;
1521 ehci_interrupt_poll(sc);
1524 /*------------------------------------------------------------------------*
1525 * ehci_interrupt - EHCI interrupt handler
1527 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1528 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1530 *------------------------------------------------------------------------*/
1532 ehci_interrupt(ehci_softc_t *sc)
1536 USB_BUS_LOCK(&sc->sc_bus);
1538 DPRINTFN(16, "real interrupt\n");
1541 if (ehcidebug > 15) {
1546 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1548 /* the interrupt was not for us */
1551 if (!(status & sc->sc_eintrs)) {
1554 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1556 status &= sc->sc_eintrs;
1558 if (status & EHCI_STS_HSE) {
1559 printf("%s: unrecoverable error, "
1560 "controller halted\n", __FUNCTION__);
1566 if (status & EHCI_STS_PCD) {
1568 * Disable PCD interrupt for now, because it will be
1569 * on until the port has been reset.
1571 sc->sc_eintrs &= ~EHCI_STS_PCD;
1572 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1576 /* do not allow RHSC interrupts > 1 per second */
1577 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1578 (void *)&ehci_pcd_enable, sc);
1580 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1583 /* block unprocessed interrupts */
1584 sc->sc_eintrs &= ~status;
1585 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1586 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1588 /* poll all the USB transfers */
1589 ehci_interrupt_poll(sc);
1591 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1592 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1593 (void *)&ehci_poll_timeout, sc);
1597 USB_BUS_UNLOCK(&sc->sc_bus);
1601 * called when a request does not complete
1604 ehci_timeout(void *arg)
1606 struct usb_xfer *xfer = arg;
1608 DPRINTF("xfer=%p\n", xfer);
1610 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1612 /* transfer is transferred */
1613 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1617 ehci_do_poll(struct usb_bus *bus)
1619 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1621 USB_BUS_LOCK(&sc->sc_bus);
1622 ehci_interrupt_poll(sc);
1623 USB_BUS_UNLOCK(&sc->sc_bus);
1627 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1629 struct usb_page_search buf_res;
1631 ehci_qtd_t *td_next;
1632 ehci_qtd_t *td_alt_next;
1633 uint32_t buf_offset;
1637 uint8_t shortpkt_old;
1640 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE);
1643 shortpkt_old = temp->shortpkt;
1644 len_old = temp->len;
1650 td_next = temp->td_next;
1654 if (temp->len == 0) {
1656 if (temp->shortpkt) {
1659 /* send a Zero Length Packet, ZLP, last */
1666 average = temp->average;
1668 if (temp->len < average) {
1669 if (temp->len % temp->max_frame_size) {
1672 average = temp->len;
1676 if (td_next == NULL) {
1677 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1682 td_next = td->obj_next;
1684 /* check if we are pre-computing */
1688 /* update remaining length */
1690 temp->len -= average;
1694 /* fill out current TD */
1698 htohc32(temp->sc, EHCI_QTD_IOC |
1699 EHCI_QTD_SET_BYTES(average));
1703 if (temp->auto_data_toggle == 0) {
1705 /* update data toggle, ZLP case */
1708 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1712 td->qtd_buffer[0] = 0;
1713 td->qtd_buffer_hi[0] = 0;
1715 td->qtd_buffer[1] = 0;
1716 td->qtd_buffer_hi[1] = 0;
1722 if (temp->auto_data_toggle == 0) {
1724 /* update data toggle */
1726 if (((average + temp->max_frame_size - 1) /
1727 temp->max_frame_size) & 1) {
1729 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1734 /* update remaining length */
1736 temp->len -= average;
1738 /* fill out buffer pointers */
1740 usbd_get_page(temp->pc, buf_offset, &buf_res);
1742 htohc32(temp->sc, buf_res.physaddr);
1743 td->qtd_buffer_hi[0] = 0;
1747 while (average > EHCI_PAGE_SIZE) {
1748 average -= EHCI_PAGE_SIZE;
1749 buf_offset += EHCI_PAGE_SIZE;
1750 usbd_get_page(temp->pc, buf_offset, &buf_res);
1753 buf_res.physaddr & (~0xFFF));
1754 td->qtd_buffer_hi[x] = 0;
1759 * NOTE: The "average" variable is never zero after
1760 * exiting the loop above !
1762 * NOTE: We have to subtract one from the offset to
1763 * ensure that we are computing the physical address
1766 buf_offset += average;
1767 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1770 buf_res.physaddr & (~0xFFF));
1771 td->qtd_buffer_hi[x] = 0;
1774 if (temp->can_use_next) {
1776 /* link the current TD with the next one */
1777 td->qtd_next = td_next->qtd_self;
1781 * BUG WARNING: The EHCI HW can use the
1782 * qtd_next field instead of qtd_altnext when
1783 * a short packet is received! We work this
1784 * around in software by not queueing more
1785 * than one job/TD at a time!
1787 td->qtd_next = terminate;
1790 td->qtd_altnext = terminate;
1791 td->alt_next = td_alt_next;
1793 usb_pc_cpu_flush(td->page_cache);
1799 /* setup alt next pointer, if any */
1800 if (temp->last_frame) {
1803 /* we use this field internally */
1804 td_alt_next = td_next;
1808 temp->shortpkt = shortpkt_old;
1809 temp->len = len_old;
1813 temp->td_next = td_next;
1817 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1819 struct ehci_std_temp temp;
1820 struct usb_pipe_methods *methods;
1824 uint32_t qh_endphub;
1827 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1828 xfer->address, UE_GET_ADDR(xfer->endpointno),
1829 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1831 temp.average = xfer->max_hc_frame_size;
1832 temp.max_frame_size = xfer->max_frame_size;
1833 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1835 /* toggle the DMA set we are using */
1836 xfer->flags_int.curr_dma_set ^= 1;
1838 /* get next DMA set */
1839 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1841 xfer->td_transfer_first = td;
1842 xfer->td_transfer_cache = td;
1846 temp.qtd_status = 0;
1847 temp.last_frame = 0;
1848 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1849 temp.can_use_next = (xfer->flags_int.control_xfr ||
1850 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT));
1852 if (xfer->flags_int.control_xfr) {
1853 if (xfer->endpoint->toggle_next) {
1856 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1858 temp.auto_data_toggle = 0;
1860 temp.auto_data_toggle = 1;
1863 if (usbd_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) {
1866 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1868 /* check if we should prepend a setup message */
1870 if (xfer->flags_int.control_xfr) {
1871 if (xfer->flags_int.control_hdr) {
1874 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1875 temp.qtd_status |= htohc32(temp.sc,
1877 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1878 EHCI_QTD_SET_TOGGLE(0));
1880 temp.len = xfer->frlengths[0];
1881 temp.pc = xfer->frbuffers + 0;
1882 temp.shortpkt = temp.len ? 1 : 0;
1883 /* check for last frame */
1884 if (xfer->nframes == 1) {
1885 /* no STATUS stage yet, SETUP is last */
1886 if (xfer->flags_int.control_act) {
1887 temp.last_frame = 1;
1888 temp.setup_alt_next = 0;
1891 ehci_setup_standard_chain_sub(&temp);
1898 while (x != xfer->nframes) {
1900 /* DATA0 / DATA1 message */
1902 temp.len = xfer->frlengths[x];
1903 temp.pc = xfer->frbuffers + x;
1907 if (x == xfer->nframes) {
1908 if (xfer->flags_int.control_xfr) {
1909 /* no STATUS stage yet, DATA is last */
1910 if (xfer->flags_int.control_act) {
1911 temp.last_frame = 1;
1912 temp.setup_alt_next = 0;
1915 temp.last_frame = 1;
1916 temp.setup_alt_next = 0;
1919 /* keep previous data toggle and error count */
1922 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1923 EHCI_QTD_SET_TOGGLE(1));
1925 if (temp.len == 0) {
1927 /* make sure that we send an USB packet */
1933 /* regular data transfer */
1935 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1938 /* set endpoint direction */
1941 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1942 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1943 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1944 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1945 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1947 ehci_setup_standard_chain_sub(&temp);
1950 /* check if we should append a status stage */
1952 if (xfer->flags_int.control_xfr &&
1953 !xfer->flags_int.control_act) {
1956 * Send a DATA1 message and invert the current endpoint
1960 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1961 EHCI_QTD_SET_TOGGLE(1));
1963 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1964 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1965 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1966 EHCI_QTD_SET_TOGGLE(1)) :
1967 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1968 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1969 EHCI_QTD_SET_TOGGLE(1));
1974 temp.last_frame = 1;
1975 temp.setup_alt_next = 0;
1977 ehci_setup_standard_chain_sub(&temp);
1981 /* the last TD terminates the transfer: */
1982 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1983 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1985 usb_pc_cpu_flush(td->page_cache);
1987 /* must have at least one frame! */
1989 xfer->td_transfer_last = td;
1992 if (ehcidebug > 8) {
1993 DPRINTF("nexttog=%d; data before transfer:\n",
1994 xfer->endpoint->toggle_next);
1995 ehci_dump_sqtds(temp.sc,
1996 xfer->td_transfer_first);
2000 methods = xfer->endpoint->methods;
2002 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2004 /* the "qh_link" field is filled when the QH is added */
2007 (EHCI_QH_SET_ADDR(xfer->address) |
2008 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2009 EHCI_QH_SET_MPL(xfer->max_packet_size));
2011 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2012 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
2013 if (methods != &ehci_device_intr_methods)
2014 qh_endp |= EHCI_QH_SET_NRL(8);
2017 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
2018 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
2020 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
2023 if (methods == &ehci_device_ctrl_methods) {
2024 qh_endp |= EHCI_QH_CTL;
2026 if (methods != &ehci_device_intr_methods) {
2027 /* Only try one time per microframe! */
2028 qh_endp |= EHCI_QH_SET_NRL(1);
2032 if (temp.auto_data_toggle == 0) {
2033 /* software computes the data toggle */
2034 qh_endp |= EHCI_QH_DTC;
2037 qh->qh_endp = htohc32(temp.sc, qh_endp);
2040 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
2041 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
2042 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
2043 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2044 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2046 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2049 /* fill the overlay qTD */
2051 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2053 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2055 qh->qh_qtd.qtd_status = 0;
2058 td = xfer->td_transfer_first;
2060 qh->qh_qtd.qtd_next = td->qtd_self;
2061 qh->qh_qtd.qtd_altnext =
2062 htohc32(temp.sc, EHCI_LINK_TERMINATE);
2064 usb_pc_cpu_flush(qh->page_cache);
2066 if (xfer->xroot->udev->flags.self_suspended == 0) {
2067 EHCI_APPEND_QH(qh, *qh_last);
2072 ehci_root_intr(ehci_softc_t *sc)
2077 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2079 /* clear any old interrupt data */
2080 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2083 m = (sc->sc_noport + 1);
2084 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2085 m = (8 * sizeof(sc->sc_hub_idata));
2087 for (i = 1; i < m; i++) {
2088 /* pick out CHANGE bits from the status register */
2089 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2090 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2091 DPRINTF("port %d changed\n", i);
2094 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2095 sizeof(sc->sc_hub_idata));
2099 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2101 uint32_t nframes = xfer->nframes;
2103 uint32_t *plen = xfer->frlengths;
2105 ehci_sitd_t *td = xfer->td_transfer_first;
2106 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2108 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2109 xfer, xfer->endpoint);
2113 panic("%s:%d: out of TD's\n",
2114 __FUNCTION__, __LINE__);
2116 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2117 pp_last = &sc->sc_isoc_fs_p_last[0];
2120 if (ehcidebug > 15) {
2121 DPRINTF("isoc FS-TD\n");
2122 ehci_dump_sitd(sc, td);
2125 usb_pc_cpu_invalidate(td->page_cache);
2126 status = hc32toh(sc, td->sitd_status);
2128 len = EHCI_SITD_GET_LEN(status);
2130 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2140 /* remove FS-TD from schedule */
2141 EHCI_REMOVE_FS_TD(td, *pp_last);
2148 xfer->aframes = xfer->nframes;
2152 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2154 uint32_t nframes = xfer->nframes;
2156 uint32_t *plen = xfer->frlengths;
2159 ehci_itd_t *td = xfer->td_transfer_first;
2160 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2162 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2163 xfer, xfer->endpoint);
2167 panic("%s:%d: out of TD's\n",
2168 __FUNCTION__, __LINE__);
2170 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2171 pp_last = &sc->sc_isoc_hs_p_last[0];
2174 if (ehcidebug > 15) {
2175 DPRINTF("isoc HS-TD\n");
2176 ehci_dump_itd(sc, td);
2180 usb_pc_cpu_invalidate(td->page_cache);
2181 status = hc32toh(sc, td->itd_status[td_no]);
2183 len = EHCI_ITD_GET_LEN(status);
2185 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2187 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2191 * The length is valid. NOTE: The
2192 * complete length is written back
2193 * into the status field, and not the
2194 * remainder like with other transfer
2198 /* Invalid length - truncate */
2209 if ((td_no == 8) || (nframes == 0)) {
2210 /* remove HS-TD from schedule */
2211 EHCI_REMOVE_HS_TD(td, *pp_last);
2218 xfer->aframes = xfer->nframes;
2221 /* NOTE: "done" can be run two times in a row,
2222 * from close and from interrupt
2225 ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2227 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2228 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2230 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2232 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2233 xfer, xfer->endpoint, error);
2235 if ((methods == &ehci_device_bulk_methods) ||
2236 (methods == &ehci_device_ctrl_methods)) {
2238 if (ehcidebug > 8) {
2239 DPRINTF("nexttog=%d; data after transfer:\n",
2240 xfer->endpoint->toggle_next);
2242 xfer->td_transfer_first);
2246 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2247 sc->sc_async_p_last);
2249 if (methods == &ehci_device_intr_methods) {
2250 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2251 sc->sc_intr_p_last[xfer->qh_pos]);
2254 * Only finish isochronous transfers once which will update
2255 * "xfer->frlengths".
2257 if (xfer->td_transfer_first &&
2258 xfer->td_transfer_last) {
2259 if (methods == &ehci_device_isoc_fs_methods) {
2260 ehci_isoc_fs_done(sc, xfer);
2262 if (methods == &ehci_device_isoc_hs_methods) {
2263 ehci_isoc_hs_done(sc, xfer);
2265 xfer->td_transfer_first = NULL;
2266 xfer->td_transfer_last = NULL;
2268 /* dequeue transfer and start next transfer */
2269 usbd_transfer_done(xfer, error);
2272 /*------------------------------------------------------------------------*
2274 *------------------------------------------------------------------------*/
2276 ehci_device_bulk_open(struct usb_xfer *xfer)
2282 ehci_device_bulk_close(struct usb_xfer *xfer)
2284 ehci_device_done(xfer, USB_ERR_CANCELLED);
2288 ehci_device_bulk_enter(struct usb_xfer *xfer)
2294 ehci_device_bulk_start(struct usb_xfer *xfer)
2296 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2299 /* setup TD's and QH */
2300 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2302 /* put transfer on interrupt queue */
2303 ehci_transfer_intr_enqueue(xfer);
2306 * XXX Certain nVidia chipsets choke when using the IAAD
2307 * feature too frequently.
2309 if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2312 /* XXX Performance quirk: Some Host Controllers have a too low
2313 * interrupt rate. Issue an IAAD to stimulate the Host
2314 * Controller after queueing the BULK transfer.
2316 temp = EOREAD4(sc, EHCI_USBCMD);
2317 if (!(temp & EHCI_CMD_IAAD))
2318 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2321 struct usb_pipe_methods ehci_device_bulk_methods =
2323 .open = ehci_device_bulk_open,
2324 .close = ehci_device_bulk_close,
2325 .enter = ehci_device_bulk_enter,
2326 .start = ehci_device_bulk_start,
2329 /*------------------------------------------------------------------------*
2330 * ehci control support
2331 *------------------------------------------------------------------------*/
2333 ehci_device_ctrl_open(struct usb_xfer *xfer)
2339 ehci_device_ctrl_close(struct usb_xfer *xfer)
2341 ehci_device_done(xfer, USB_ERR_CANCELLED);
2345 ehci_device_ctrl_enter(struct usb_xfer *xfer)
2351 ehci_device_ctrl_start(struct usb_xfer *xfer)
2353 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2355 /* setup TD's and QH */
2356 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2358 /* put transfer on interrupt queue */
2359 ehci_transfer_intr_enqueue(xfer);
2362 struct usb_pipe_methods ehci_device_ctrl_methods =
2364 .open = ehci_device_ctrl_open,
2365 .close = ehci_device_ctrl_close,
2366 .enter = ehci_device_ctrl_enter,
2367 .start = ehci_device_ctrl_start,
2370 /*------------------------------------------------------------------------*
2371 * ehci interrupt support
2372 *------------------------------------------------------------------------*/
2374 ehci_device_intr_open(struct usb_xfer *xfer)
2376 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2381 usb_hs_bandwidth_alloc(xfer);
2384 * Find the best QH position corresponding to the given interval:
2388 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2390 if (xfer->interval >= bit) {
2394 if (sc->sc_intr_stat[x] <
2395 sc->sc_intr_stat[best]) {
2405 sc->sc_intr_stat[best]++;
2406 xfer->qh_pos = best;
2408 DPRINTFN(3, "best=%d interval=%d\n",
2409 best, xfer->interval);
2413 ehci_device_intr_close(struct usb_xfer *xfer)
2415 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2417 sc->sc_intr_stat[xfer->qh_pos]--;
2419 ehci_device_done(xfer, USB_ERR_CANCELLED);
2421 /* bandwidth must be freed after device done */
2422 usb_hs_bandwidth_free(xfer);
2426 ehci_device_intr_enter(struct usb_xfer *xfer)
2432 ehci_device_intr_start(struct usb_xfer *xfer)
2434 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2436 /* setup TD's and QH */
2437 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2439 /* put transfer on interrupt queue */
2440 ehci_transfer_intr_enqueue(xfer);
2443 struct usb_pipe_methods ehci_device_intr_methods =
2445 .open = ehci_device_intr_open,
2446 .close = ehci_device_intr_close,
2447 .enter = ehci_device_intr_enter,
2448 .start = ehci_device_intr_start,
2451 /*------------------------------------------------------------------------*
2452 * ehci full speed isochronous support
2453 *------------------------------------------------------------------------*/
2455 ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2457 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2459 uint32_t sitd_portaddr;
2463 EHCI_SITD_SET_ADDR(xfer->address) |
2464 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2465 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2466 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2468 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2469 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2471 sitd_portaddr = htohc32(sc, sitd_portaddr);
2473 /* initialize all TD's */
2475 for (ds = 0; ds != 2; ds++) {
2477 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2479 td->sitd_portaddr = sitd_portaddr;
2482 * TODO: make some kind of automatic
2483 * SMASK/CMASK selection based on micro-frame
2486 * micro-frame usage (8 microframes per 1ms)
2488 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2490 usb_pc_cpu_flush(td->page_cache);
2496 ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2498 ehci_device_done(xfer, USB_ERR_CANCELLED);
2502 ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2504 struct usb_page_search buf_res;
2505 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2506 struct usb_fs_isoc_schedule *fss_start;
2507 struct usb_fs_isoc_schedule *fss_end;
2508 struct usb_fs_isoc_schedule *fss;
2510 ehci_sitd_t *td_last = NULL;
2511 ehci_sitd_t **pp_last;
2513 uint32_t buf_offset;
2527 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2528 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2530 /* get the current frame index */
2532 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2535 * check if the frame index is within the window where the frames
2538 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2539 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2541 if ((xfer->endpoint->is_synced == 0) ||
2542 (buf_offset < xfer->nframes)) {
2544 * If there is data underflow or the pipe queue is empty we
2545 * schedule the transfer a few frames ahead of the current
2546 * frame position. Else two isochronous transfers might
2549 xfer->endpoint->isoc_next = (nframes + 3) &
2550 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2551 xfer->endpoint->is_synced = 1;
2552 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2555 * compute how many milliseconds the insertion is ahead of the
2556 * current frame position:
2558 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2559 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2562 * pre-compute when the isochronous transfer will be finished:
2564 xfer->isoc_time_complete =
2565 usbd_fs_isoc_schedule_isoc_time_expand
2566 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2569 /* get the real number of frames */
2571 nframes = xfer->nframes;
2575 plen = xfer->frlengths;
2577 /* toggle the DMA set we are using */
2578 xfer->flags_int.curr_dma_set ^= 1;
2580 /* get next DMA set */
2581 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2582 xfer->td_transfer_first = td;
2584 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2586 /* store starting position */
2588 xfer->qh_pos = xfer->endpoint->isoc_next;
2590 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2594 panic("%s:%d: out of TD's\n",
2595 __FUNCTION__, __LINE__);
2597 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2598 pp_last = &sc->sc_isoc_fs_p_last[0];
2600 if (fss >= fss_end) {
2603 /* reuse sitd_portaddr and sitd_back from last transfer */
2605 if (*plen > xfer->max_frame_size) {
2609 printf("%s: frame length(%d) exceeds %d "
2610 "bytes (frame truncated)\n",
2611 __FUNCTION__, *plen,
2612 xfer->max_frame_size);
2615 *plen = xfer->max_frame_size;
2618 * We currently don't care if the ISOCHRONOUS schedule is
2621 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2624 * The FULL speed schedule is FULL! Set length
2631 * only call "usbd_get_page()" when we have a
2634 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2635 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2636 buf_offset += *plen;
2638 * NOTE: We need to subtract one from the offset so
2639 * that we are on a valid page!
2641 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2643 temp = buf_res.physaddr & ~0xFFF;
2649 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2652 temp |= 1; /* T-count = 1, TP = ALL */
2657 temp |= tlen; /* T-count = [1..6] */
2658 temp |= 8; /* TP = Begin */
2670 sa = (sb - sa) & 0x3F;
2673 sb = (-(4 << sa)) & 0xFE;
2674 sa = (1 << sa) & 0x3F;
2677 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2678 EHCI_SITD_SET_CMASK(sb));
2680 td->sitd_bp[1] = htohc32(sc, temp);
2682 td->sitd_mask = htohc32(sc, sitd_mask);
2685 td->sitd_status = htohc32(sc,
2688 EHCI_SITD_SET_LEN(*plen));
2690 td->sitd_status = htohc32(sc,
2692 EHCI_SITD_SET_LEN(*plen));
2694 usb_pc_cpu_flush(td->page_cache);
2697 if (ehcidebug > 15) {
2698 DPRINTF("FS-TD %d\n", nframes);
2699 ehci_dump_sitd(sc, td);
2702 /* insert TD into schedule */
2703 EHCI_APPEND_FS_TD(td, *pp_last);
2712 xfer->td_transfer_last = td_last;
2714 /* update isoc_next */
2715 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2716 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2720 ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2722 /* put transfer on interrupt queue */
2723 ehci_transfer_intr_enqueue(xfer);
2726 struct usb_pipe_methods ehci_device_isoc_fs_methods =
2728 .open = ehci_device_isoc_fs_open,
2729 .close = ehci_device_isoc_fs_close,
2730 .enter = ehci_device_isoc_fs_enter,
2731 .start = ehci_device_isoc_fs_start,
2734 /*------------------------------------------------------------------------*
2735 * ehci high speed isochronous support
2736 *------------------------------------------------------------------------*/
2738 ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2740 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2745 usb_hs_bandwidth_alloc(xfer);
2747 /* initialize all TD's */
2749 for (ds = 0; ds != 2; ds++) {
2751 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2753 /* set TD inactive */
2754 td->itd_status[0] = 0;
2755 td->itd_status[1] = 0;
2756 td->itd_status[2] = 0;
2757 td->itd_status[3] = 0;
2758 td->itd_status[4] = 0;
2759 td->itd_status[5] = 0;
2760 td->itd_status[6] = 0;
2761 td->itd_status[7] = 0;
2763 /* set endpoint and address */
2764 td->itd_bp[0] = htohc32(sc,
2765 EHCI_ITD_SET_ADDR(xfer->address) |
2766 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2769 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2772 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2773 temp |= EHCI_ITD_SET_DIR_IN;
2775 /* set maximum packet size */
2776 td->itd_bp[1] = htohc32(sc, temp);
2778 /* set transfer multiplier */
2779 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2781 usb_pc_cpu_flush(td->page_cache);
2787 ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2789 ehci_device_done(xfer, USB_ERR_CANCELLED);
2791 /* bandwidth must be freed after device done */
2792 usb_hs_bandwidth_free(xfer);
2796 ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2798 struct usb_page_search buf_res;
2799 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2801 ehci_itd_t *td_last = NULL;
2802 ehci_itd_t **pp_last;
2803 bus_size_t page_addr;
2806 uint32_t buf_offset;
2808 uint32_t itd_offset[8 + 1];
2812 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2819 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2820 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2822 /* get the current frame index */
2824 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2827 * check if the frame index is within the window where the frames
2830 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2831 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2833 if ((xfer->endpoint->is_synced == 0) ||
2834 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2836 * If there is data underflow or the pipe queue is empty we
2837 * schedule the transfer a few frames ahead of the current
2838 * frame position. Else two isochronous transfers might
2841 xfer->endpoint->isoc_next = (nframes + 3) &
2842 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2843 xfer->endpoint->is_synced = 1;
2844 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2847 * compute how many milliseconds the insertion is ahead of the
2848 * current frame position:
2850 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2851 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2854 * pre-compute when the isochronous transfer will be finished:
2856 xfer->isoc_time_complete =
2857 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2858 (((xfer->nframes << shift) + 7) / 8);
2860 /* get the real number of frames */
2862 nframes = xfer->nframes;
2867 plen = xfer->frlengths;
2869 /* toggle the DMA set we are using */
2870 xfer->flags_int.curr_dma_set ^= 1;
2872 /* get next DMA set */
2873 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2874 xfer->td_transfer_first = td;
2876 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2878 /* store starting position */
2880 xfer->qh_pos = xfer->endpoint->isoc_next;
2884 panic("%s:%d: out of TD's\n",
2885 __FUNCTION__, __LINE__);
2887 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2888 pp_last = &sc->sc_isoc_hs_p_last[0];
2891 if (*plen > xfer->max_frame_size) {
2895 printf("%s: frame length(%d) exceeds %d bytes "
2896 "(frame truncated)\n",
2897 __FUNCTION__, *plen, xfer->max_frame_size);
2900 *plen = xfer->max_frame_size;
2903 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2904 status = (EHCI_ITD_SET_LEN(*plen) |
2906 EHCI_ITD_SET_PG(0));
2907 td->itd_status[td_no] = htohc32(sc, status);
2908 itd_offset[td_no] = buf_offset;
2909 buf_offset += *plen;
2913 td->itd_status[td_no] = 0; /* not active */
2914 itd_offset[td_no] = buf_offset;
2919 if ((td_no == 8) || (nframes == 0)) {
2921 /* the rest of the transfers are not active, if any */
2922 for (x = td_no; x != 8; x++) {
2923 td->itd_status[x] = 0; /* not active */
2926 /* check if there is any data to be transferred */
2927 if (itd_offset[0] != buf_offset) {
2929 itd_offset[td_no] = buf_offset;
2931 /* get first page offset */
2932 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2933 /* get page address */
2934 page_addr = buf_res.physaddr & ~0xFFF;
2935 /* update page address */
2936 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2937 td->itd_bp[0] |= htohc32(sc, page_addr);
2939 for (x = 0; x != td_no; x++) {
2940 /* set page number and page offset */
2941 status = (EHCI_ITD_SET_PG(page_no) |
2942 (buf_res.physaddr & 0xFFF));
2943 td->itd_status[x] |= htohc32(sc, status);
2945 /* get next page offset */
2946 if (itd_offset[x + 1] == buf_offset) {
2948 * We subtract one so that
2949 * we don't go off the last
2952 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2954 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2957 /* check if we need a new page */
2958 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2959 /* new page needed */
2960 page_addr = buf_res.physaddr & ~0xFFF;
2962 panic("%s: too many pages\n", __FUNCTION__);
2965 /* update page address */
2966 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2967 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2971 /* set IOC bit if we are complete */
2973 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2975 usb_pc_cpu_flush(td->page_cache);
2977 if (ehcidebug > 15) {
2978 DPRINTF("HS-TD %d\n", nframes);
2979 ehci_dump_itd(sc, td);
2982 /* insert TD into schedule */
2983 EHCI_APPEND_HS_TD(td, *pp_last);
2992 xfer->td_transfer_last = td_last;
2994 /* update isoc_next */
2995 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2996 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
3000 ehci_device_isoc_hs_start(struct usb_xfer *xfer)
3002 /* put transfer on interrupt queue */
3003 ehci_transfer_intr_enqueue(xfer);
3006 struct usb_pipe_methods ehci_device_isoc_hs_methods =
3008 .open = ehci_device_isoc_hs_open,
3009 .close = ehci_device_isoc_hs_close,
3010 .enter = ehci_device_isoc_hs_enter,
3011 .start = ehci_device_isoc_hs_start,
3014 /*------------------------------------------------------------------------*
3015 * ehci root control support
3016 *------------------------------------------------------------------------*
3017 * Simulate a hardware hub by handling all the necessary requests.
3018 *------------------------------------------------------------------------*/
3021 struct usb_device_descriptor ehci_devd =
3023 sizeof(struct usb_device_descriptor),
3024 UDESC_DEVICE, /* type */
3025 {0x00, 0x02}, /* USB version */
3026 UDCLASS_HUB, /* class */
3027 UDSUBCLASS_HUB, /* subclass */
3028 UDPROTO_HSHUBSTT, /* protocol */
3029 64, /* max packet */
3030 {0}, {0}, {0x00, 0x01}, /* device id */
3031 1, 2, 0, /* string indicies */
3032 1 /* # of configurations */
3036 struct usb_device_qualifier ehci_odevd =
3038 sizeof(struct usb_device_qualifier),
3039 UDESC_DEVICE_QUALIFIER, /* type */
3040 {0x00, 0x02}, /* USB version */
3041 UDCLASS_HUB, /* class */
3042 UDSUBCLASS_HUB, /* subclass */
3043 UDPROTO_FSHUB, /* protocol */
3045 0, /* # of configurations */
3049 static const struct ehci_config_desc ehci_confd = {
3051 .bLength = sizeof(struct usb_config_descriptor),
3052 .bDescriptorType = UDESC_CONFIG,
3053 .wTotalLength[0] = sizeof(ehci_confd),
3055 .bConfigurationValue = 1,
3056 .iConfiguration = 0,
3057 .bmAttributes = UC_SELF_POWERED,
3058 .bMaxPower = 0 /* max power */
3061 .bLength = sizeof(struct usb_interface_descriptor),
3062 .bDescriptorType = UDESC_INTERFACE,
3064 .bInterfaceClass = UICLASS_HUB,
3065 .bInterfaceSubClass = UISUBCLASS_HUB,
3066 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
3070 .bLength = sizeof(struct usb_endpoint_descriptor),
3071 .bDescriptorType = UDESC_ENDPOINT,
3072 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3073 .bmAttributes = UE_INTERRUPT,
3074 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3080 struct usb_hub_descriptor ehci_hubd =
3082 0, /* dynamic length */
3092 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3097 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3099 port = EHCI_PORTSC(index);
3100 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3101 EOWRITE4(sc, port, v | EHCI_PS_PO);
3105 ehci_roothub_exec(struct usb_device *udev,
3106 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3108 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3109 const char *str_ptr;
3120 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3123 ptr = (const void *)&sc->sc_hub_desc;
3127 value = UGETW(req->wValue);
3128 index = UGETW(req->wIndex);
3130 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3131 "wValue=0x%04x wIndex=0x%04x\n",
3132 req->bmRequestType, req->bRequest,
3133 UGETW(req->wLength), value, index);
3135 #define C(x,y) ((x) | ((y) << 8))
3136 switch (C(req->bRequest, req->bmRequestType)) {
3137 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3138 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3139 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3141 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3142 * for the integrated root hub.
3145 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3147 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3149 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3150 switch (value >> 8) {
3152 if ((value & 0xff) != 0) {
3153 err = USB_ERR_IOERROR;
3156 len = sizeof(ehci_devd);
3157 ptr = (const void *)&ehci_devd;
3160 * We can't really operate at another speed,
3161 * but the specification says we need this
3164 case UDESC_DEVICE_QUALIFIER:
3165 if ((value & 0xff) != 0) {
3166 err = USB_ERR_IOERROR;
3169 len = sizeof(ehci_odevd);
3170 ptr = (const void *)&ehci_odevd;
3174 if ((value & 0xff) != 0) {
3175 err = USB_ERR_IOERROR;
3178 len = sizeof(ehci_confd);
3179 ptr = (const void *)&ehci_confd;
3183 switch (value & 0xff) {
3184 case 0: /* Language table */
3188 case 1: /* Vendor */
3189 str_ptr = sc->sc_vendor;
3192 case 2: /* Product */
3193 str_ptr = "EHCI root HUB";
3201 len = usb_make_str_desc(
3202 sc->sc_hub_desc.temp,
3203 sizeof(sc->sc_hub_desc.temp),
3207 err = USB_ERR_IOERROR;
3211 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3213 sc->sc_hub_desc.temp[0] = 0;
3215 case C(UR_GET_STATUS, UT_READ_DEVICE):
3217 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3219 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3220 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3222 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3224 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3225 if (value >= EHCI_MAX_DEVICES) {
3226 err = USB_ERR_IOERROR;
3229 sc->sc_addr = value;
3231 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3232 if ((value != 0) && (value != 1)) {
3233 err = USB_ERR_IOERROR;
3236 sc->sc_conf = value;
3238 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3240 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3241 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3242 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3243 err = USB_ERR_IOERROR;
3245 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3247 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3250 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3252 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3253 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3256 (index > sc->sc_noport)) {
3257 err = USB_ERR_IOERROR;
3260 port = EHCI_PORTSC(index);
3261 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3263 case UHF_PORT_ENABLE:
3264 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3266 case UHF_PORT_SUSPEND:
3267 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3270 * waking up a High Speed device is rather
3273 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3275 /* wait 20ms for resume sequence to complete */
3276 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3278 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3279 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3281 /* 4ms settle time */
3282 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3284 case UHF_PORT_POWER:
3285 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3288 DPRINTFN(3, "clear port test "
3291 case UHF_PORT_INDICATOR:
3292 DPRINTFN(3, "clear port ind "
3294 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3296 case UHF_C_PORT_CONNECTION:
3297 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3299 case UHF_C_PORT_ENABLE:
3300 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3302 case UHF_C_PORT_SUSPEND:
3303 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3305 case UHF_C_PORT_OVER_CURRENT:
3306 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3308 case UHF_C_PORT_RESET:
3312 err = USB_ERR_IOERROR;
3316 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3317 if ((value & 0xff) != 0) {
3318 err = USB_ERR_IOERROR;
3321 v = EOREAD4(sc, EHCI_HCSPARAMS);
3323 sc->sc_hub_desc.hubd = ehci_hubd;
3324 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3325 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
3326 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
3327 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ?
3329 /* XXX can't find out? */
3330 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3331 for (l = 0; l < sc->sc_noport; l++) {
3332 /* XXX can't find out? */
3333 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8));
3335 sc->sc_hub_desc.hubd.bDescLength =
3336 8 + ((sc->sc_noport + 7) / 8);
3337 len = sc->sc_hub_desc.hubd.bDescLength;
3339 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3341 bzero(sc->sc_hub_desc.temp, 16);
3343 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3344 DPRINTFN(9, "get port status i=%d\n",
3347 (index > sc->sc_noport)) {
3348 err = USB_ERR_IOERROR;
3351 v = EOREAD4(sc, EHCI_PORTSC(index));
3352 DPRINTFN(9, "port status=0x%04x\n", v);
3353 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3354 if ((v & 0xc000000) == 0x8000000)
3356 else if ((v & 0xc000000) == 0x4000000)
3364 i |= UPS_CURRENT_CONNECT_STATUS;
3366 i |= UPS_PORT_ENABLED;
3367 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3369 if (v & EHCI_PS_OCA)
3370 i |= UPS_OVERCURRENT_INDICATOR;
3374 i |= UPS_PORT_POWER;
3375 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3377 if (v & EHCI_PS_CSC)
3378 i |= UPS_C_CONNECT_STATUS;
3379 if (v & EHCI_PS_PEC)
3380 i |= UPS_C_PORT_ENABLED;
3381 if (v & EHCI_PS_OCC)
3382 i |= UPS_C_OVERCURRENT_INDICATOR;
3383 if (v & EHCI_PS_FPR)
3386 i |= UPS_C_PORT_RESET;
3387 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3388 len = sizeof(sc->sc_hub_desc.ps);
3390 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3391 err = USB_ERR_IOERROR;
3393 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3395 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3397 (index > sc->sc_noport)) {
3398 err = USB_ERR_IOERROR;
3401 port = EHCI_PORTSC(index);
3402 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3404 case UHF_PORT_ENABLE:
3405 EOWRITE4(sc, port, v | EHCI_PS_PE);
3407 case UHF_PORT_SUSPEND:
3408 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3410 case UHF_PORT_RESET:
3411 DPRINTFN(6, "reset port %d\n", index);
3413 if (ehcinohighspeed) {
3415 * Connect USB device to companion
3418 ehci_disown(sc, index, 1);
3422 if (EHCI_PS_IS_LOWSPEED(v) &&
3423 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3424 /* Low speed device, give up ownership. */
3425 ehci_disown(sc, index, 1);
3428 /* Start reset sequence. */
3429 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3430 EOWRITE4(sc, port, v | EHCI_PS_PR);
3432 /* Wait for reset to complete. */
3433 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3434 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3436 /* Terminate reset sequence. */
3437 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3438 EOWRITE4(sc, port, v);
3440 /* Wait for HC to complete reset. */
3441 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3442 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3444 v = EOREAD4(sc, port);
3445 DPRINTF("ehci after reset, status=0x%08x\n", v);
3446 if (v & EHCI_PS_PR) {
3447 device_printf(sc->sc_bus.bdev,
3448 "port reset timeout\n");
3449 err = USB_ERR_TIMEOUT;
3452 if (!(v & EHCI_PS_PE) &&
3453 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3454 /* Not a high speed device, give up ownership.*/
3455 ehci_disown(sc, index, 0);
3459 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3463 case UHF_PORT_POWER:
3464 DPRINTFN(3, "set port power %d\n", index);
3465 EOWRITE4(sc, port, v | EHCI_PS_PP);
3469 DPRINTFN(3, "set port test %d\n", index);
3472 case UHF_PORT_INDICATOR:
3473 DPRINTFN(3, "set port ind %d\n", index);
3474 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3478 err = USB_ERR_IOERROR;
3482 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3483 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3484 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3485 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3488 err = USB_ERR_IOERROR;
3498 ehci_xfer_setup(struct usb_setup_params *parm)
3500 struct usb_page_search page_info;
3501 struct usb_page_cache *pc;
3503 struct usb_xfer *xfer;
3511 sc = EHCI_BUS2SC(parm->udev->bus);
3512 xfer = parm->curr_xfer;
3520 * compute maximum number of some structures
3522 if (parm->methods == &ehci_device_ctrl_methods) {
3525 * The proof for the "nqtd" formula is illustrated like
3528 * +------------------------------------+
3532 * | | xxx | x | frm 0 |
3534 * | | xxx | xx | frm 1 |
3537 * +------------------------------------+
3539 * "xxx" means a completely full USB transfer descriptor
3541 * "x" and "xx" means a short USB packet
3543 * For the remainder of an USB transfer modulo
3544 * "max_data_length" we need two USB transfer descriptors.
3545 * One to transfer the remaining data and one to finalise
3546 * with a zero length packet in case the "force_short_xfer"
3547 * flag is set. We only need two USB transfer descriptors in
3548 * the case where the transfer length of the first one is a
3549 * factor of "max_frame_size". The rest of the needed USB
3550 * transfer descriptors is given by the buffer size divided
3551 * by the maximum data payload.
3553 parm->hc_max_packet_size = 0x400;
3554 parm->hc_max_packet_count = 1;
3555 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3556 xfer->flags_int.bdma_enable = 1;
3558 usbd_transfer_setup_sub(parm);
3561 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3562 + (xfer->max_data_length / xfer->max_hc_frame_size));
3564 } else if (parm->methods == &ehci_device_bulk_methods) {
3566 parm->hc_max_packet_size = 0x400;
3567 parm->hc_max_packet_count = 1;
3568 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3569 xfer->flags_int.bdma_enable = 1;
3571 usbd_transfer_setup_sub(parm);
3574 nqtd = ((2 * xfer->nframes)
3575 + (xfer->max_data_length / xfer->max_hc_frame_size));
3577 } else if (parm->methods == &ehci_device_intr_methods) {
3579 if (parm->speed == USB_SPEED_HIGH) {
3580 parm->hc_max_packet_size = 0x400;
3581 parm->hc_max_packet_count = 3;
3582 } else if (parm->speed == USB_SPEED_FULL) {
3583 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3584 parm->hc_max_packet_count = 1;
3586 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3587 parm->hc_max_packet_count = 1;
3590 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3591 xfer->flags_int.bdma_enable = 1;
3593 usbd_transfer_setup_sub(parm);
3596 nqtd = ((2 * xfer->nframes)
3597 + (xfer->max_data_length / xfer->max_hc_frame_size));
3599 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3601 parm->hc_max_packet_size = 0x3FF;
3602 parm->hc_max_packet_count = 1;
3603 parm->hc_max_frame_size = 0x3FF;
3604 xfer->flags_int.bdma_enable = 1;
3606 usbd_transfer_setup_sub(parm);
3608 nsitd = xfer->nframes;
3610 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3612 parm->hc_max_packet_size = 0x400;
3613 parm->hc_max_packet_count = 3;
3614 parm->hc_max_frame_size = 0xC00;
3615 xfer->flags_int.bdma_enable = 1;
3617 usbd_transfer_setup_sub(parm);
3619 nitd = ((xfer->nframes + 7) / 8) <<
3620 usbd_xfer_get_fps_shift(xfer);
3624 parm->hc_max_packet_size = 0x400;
3625 parm->hc_max_packet_count = 1;
3626 parm->hc_max_frame_size = 0x400;
3628 usbd_transfer_setup_sub(parm);
3637 * Allocate queue heads and transfer descriptors
3641 if (usbd_transfer_setup_sub_malloc(
3642 parm, &pc, sizeof(ehci_itd_t),
3643 EHCI_ITD_ALIGN, nitd)) {
3644 parm->err = USB_ERR_NOMEM;
3648 for (n = 0; n != nitd; n++) {
3651 usbd_get_page(pc + n, 0, &page_info);
3653 td = page_info.buffer;
3656 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3657 td->obj_next = last_obj;
3658 td->page_cache = pc + n;
3662 usb_pc_cpu_flush(pc + n);
3665 if (usbd_transfer_setup_sub_malloc(
3666 parm, &pc, sizeof(ehci_sitd_t),
3667 EHCI_SITD_ALIGN, nsitd)) {
3668 parm->err = USB_ERR_NOMEM;
3672 for (n = 0; n != nsitd; n++) {
3675 usbd_get_page(pc + n, 0, &page_info);
3677 td = page_info.buffer;
3680 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3681 td->obj_next = last_obj;
3682 td->page_cache = pc + n;
3686 usb_pc_cpu_flush(pc + n);
3689 if (usbd_transfer_setup_sub_malloc(
3690 parm, &pc, sizeof(ehci_qtd_t),
3691 EHCI_QTD_ALIGN, nqtd)) {
3692 parm->err = USB_ERR_NOMEM;
3696 for (n = 0; n != nqtd; n++) {
3699 usbd_get_page(pc + n, 0, &page_info);
3701 qtd = page_info.buffer;
3704 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3705 qtd->obj_next = last_obj;
3706 qtd->page_cache = pc + n;
3710 usb_pc_cpu_flush(pc + n);
3713 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3717 if (usbd_transfer_setup_sub_malloc(
3718 parm, &pc, sizeof(ehci_qh_t),
3719 EHCI_QH_ALIGN, nqh)) {
3720 parm->err = USB_ERR_NOMEM;
3724 for (n = 0; n != nqh; n++) {
3727 usbd_get_page(pc + n, 0, &page_info);
3729 qh = page_info.buffer;
3732 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3733 qh->obj_next = last_obj;
3734 qh->page_cache = pc + n;
3738 usb_pc_cpu_flush(pc + n);
3741 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3743 if (!xfer->flags_int.curr_dma_set) {
3744 xfer->flags_int.curr_dma_set = 1;
3750 ehci_xfer_unsetup(struct usb_xfer *xfer)
3756 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3757 struct usb_endpoint *ep)
3759 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3761 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3763 edesc->bEndpointAddress, udev->flags.usb_mode,
3766 if (udev->flags.usb_mode != USB_MODE_HOST) {
3770 if (udev->device_index != sc->sc_addr) {
3772 if ((udev->speed != USB_SPEED_HIGH) &&
3773 ((udev->hs_hub_addr == 0) ||
3774 (udev->hs_port_no == 0) ||
3775 (udev->parent_hs_hub == NULL) ||
3776 (udev->parent_hs_hub->hub == NULL))) {
3777 /* We need a transaction translator */
3780 switch (edesc->bmAttributes & UE_XFERTYPE) {
3782 ep->methods = &ehci_device_ctrl_methods;
3785 ep->methods = &ehci_device_intr_methods;
3787 case UE_ISOCHRONOUS:
3788 if (udev->speed == USB_SPEED_HIGH) {
3789 ep->methods = &ehci_device_isoc_hs_methods;
3790 } else if (udev->speed == USB_SPEED_FULL) {
3791 ep->methods = &ehci_device_isoc_fs_methods;
3795 ep->methods = &ehci_device_bulk_methods;
3807 ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus)
3810 * Wait until the hardware has finished any possible use of
3811 * the transfer descriptor(s) and QH
3813 *pus = (188); /* microseconds */
3817 ehci_device_resume(struct usb_device *udev)
3819 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3820 struct usb_xfer *xfer;
3821 struct usb_pipe_methods *methods;
3825 USB_BUS_LOCK(udev->bus);
3827 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3829 if (xfer->xroot->udev == udev) {
3831 methods = xfer->endpoint->methods;
3833 if ((methods == &ehci_device_bulk_methods) ||
3834 (methods == &ehci_device_ctrl_methods)) {
3835 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3836 sc->sc_async_p_last);
3838 if (methods == &ehci_device_intr_methods) {
3839 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3840 sc->sc_intr_p_last[xfer->qh_pos]);
3845 USB_BUS_UNLOCK(udev->bus);
3851 ehci_device_suspend(struct usb_device *udev)
3853 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3854 struct usb_xfer *xfer;
3855 struct usb_pipe_methods *methods;
3859 USB_BUS_LOCK(udev->bus);
3861 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3863 if (xfer->xroot->udev == udev) {
3865 methods = xfer->endpoint->methods;
3867 if ((methods == &ehci_device_bulk_methods) ||
3868 (methods == &ehci_device_ctrl_methods)) {
3869 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3870 sc->sc_async_p_last);
3872 if (methods == &ehci_device_intr_methods) {
3873 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3874 sc->sc_intr_p_last[xfer->qh_pos]);
3879 USB_BUS_UNLOCK(udev->bus);
3885 ehci_set_hw_power(struct usb_bus *bus)
3887 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3895 flags = bus->hw_power_state;
3897 temp = EOREAD4(sc, EHCI_USBCMD);
3899 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3901 if (flags & (USB_HW_POWER_CONTROL |
3902 USB_HW_POWER_BULK)) {
3903 DPRINTF("Async is active\n");
3904 temp |= EHCI_CMD_ASE;
3906 if (flags & (USB_HW_POWER_INTERRUPT |
3907 USB_HW_POWER_ISOC)) {
3908 DPRINTF("Periodic is active\n");
3909 temp |= EHCI_CMD_PSE;
3911 EOWRITE4(sc, EHCI_USBCMD, temp);
3913 USB_BUS_UNLOCK(bus);
3918 struct usb_bus_methods ehci_bus_methods =
3920 .endpoint_init = ehci_ep_init,
3921 .xfer_setup = ehci_xfer_setup,
3922 .xfer_unsetup = ehci_xfer_unsetup,
3923 .get_dma_delay = ehci_get_dma_delay,
3924 .device_resume = ehci_device_resume,
3925 .device_suspend = ehci_device_suspend,
3926 .set_hw_power = ehci_set_hw_power,
3927 .roothub_exec = ehci_roothub_exec,
3928 .xfer_poll = ehci_do_poll,