3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
36 * NOTE: The current implementation only supports Device Side Mode!
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
64 #define USB_DEBUG_VAR musbotgdebug
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif /* USB_GLOBAL_INCLUDE_FILE */
79 #include <dev/usb/controller/musb_otg.h>
81 #define MUSBOTG_INTR_ENDPT 1
83 #define MUSBOTG_BUS2SC(bus) \
84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
87 #define MUSBOTG_PC2SC(pc) \
88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
91 static int musbotgdebug = 0;
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
95 &musbotgdebug, 0, "Debug level");
102 struct usb_bus_methods musbotg_bus_methods;
103 struct usb_pipe_methods musbotg_device_bulk_methods;
104 struct usb_pipe_methods musbotg_device_ctrl_methods;
105 struct usb_pipe_methods musbotg_device_intr_methods;
106 struct usb_pipe_methods musbotg_device_isoc_methods;
108 /* Control transfers: Device mode */
109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
112 static musbotg_cmd_t musbotg_dev_ctrl_status;
114 /* Control transfers: Host mode */
115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
116 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
118 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
121 /* Bulk, Interrupt, Isochronous: Device mode */
122 static musbotg_cmd_t musbotg_dev_data_rx;
123 static musbotg_cmd_t musbotg_dev_data_tx;
125 /* Bulk, Interrupt, Isochronous: Host mode */
126 static musbotg_cmd_t musbotg_host_data_rx;
127 static musbotg_cmd_t musbotg_host_data_tx;
129 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
130 static void musbotg_do_poll(struct usb_bus *);
131 static void musbotg_standard_done(struct usb_xfer *);
132 static void musbotg_interrupt_poll(struct musbotg_softc *);
133 static void musbotg_root_intr(struct musbotg_softc *);
134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td);
135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
139 * Here is a configuration that the chip supports.
141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
144 .max_in_frame_size = 64,/* fixed */
145 .max_out_frame_size = 64, /* fixed */
147 .support_control = 1,
152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td)
159 /* In device mode each EP got its own channel */
160 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
161 musbotg_ep_int_set(sc, ep, 1);
166 * All control transactions go through EP0
169 if (sc->sc_channel_mask & (1 << 0))
171 sc->sc_channel_mask |= (1 << 0);
172 musbotg_ep_int_set(sc, ep, 1);
176 for (ch = 1; ch < MUSB2_EP_MAX; ch++) {
177 if (!(sc->sc_channel_mask & (1 << ch))) {
178 sc->sc_channel_mask |= (1 << ch);
179 musbotg_ep_int_set(sc, ch, 1);
184 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
190 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
193 DPRINTFN(1, "ep_no=%d\n", td->channel);
195 if (sc->sc_mode == MUSB2_DEVICE_MODE)
200 if (td->channel == -1)
203 musbotg_ep_int_set(sc, td->channel, 0);
204 sc->sc_channel_mask &= ~(1 << td->channel);
210 musbotg_get_hw_ep_profile(struct usb_device *udev,
211 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
213 struct musbotg_softc *sc;
215 sc = MUSBOTG_BUS2SC(udev->bus);
218 /* control endpoint */
219 *ppf = musbotg_ep_profile;
220 } else if (ep_addr <= sc->sc_ep_max) {
221 /* other endpoints */
222 *ppf = sc->sc_hw_ep_profile + ep_addr;
229 musbotg_clocks_on(struct musbotg_softc *sc)
231 if (sc->sc_flags.clocks_off &&
232 sc->sc_flags.port_powered) {
236 if (sc->sc_clocks_on) {
237 (sc->sc_clocks_on) (sc->sc_clocks_arg);
239 sc->sc_flags.clocks_off = 0;
241 /* XXX enable Transceiver */
246 musbotg_clocks_off(struct musbotg_softc *sc)
248 if (!sc->sc_flags.clocks_off) {
252 /* XXX disable Transceiver */
254 if (sc->sc_clocks_off) {
255 (sc->sc_clocks_off) (sc->sc_clocks_arg);
257 sc->sc_flags.clocks_off = 1;
262 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
266 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
268 temp |= MUSB2_MASK_SOFTC;
270 temp &= ~MUSB2_MASK_SOFTC;
272 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
276 musbotg_pull_up(struct musbotg_softc *sc)
278 /* pullup D+, if possible */
280 if (!sc->sc_flags.d_pulled_up &&
281 sc->sc_flags.port_powered) {
282 sc->sc_flags.d_pulled_up = 1;
283 musbotg_pull_common(sc, 1);
288 musbotg_pull_down(struct musbotg_softc *sc)
290 /* pulldown D+, if possible */
292 if (sc->sc_flags.d_pulled_up) {
293 sc->sc_flags.d_pulled_up = 0;
294 musbotg_pull_common(sc, 0);
299 musbotg_suspend_host(struct musbotg_softc *sc)
303 if (sc->sc_flags.status_suspend) {
307 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
308 temp |= MUSB2_MASK_SUSPMODE;
309 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
310 sc->sc_flags.status_suspend = 1;
314 musbotg_wakeup_host(struct musbotg_softc *sc)
318 if (!(sc->sc_flags.status_suspend)) {
322 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
323 temp &= ~MUSB2_MASK_SUSPMODE;
324 temp |= MUSB2_MASK_RESUME;
325 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
327 /* wait 20 milliseconds */
328 /* Wait for reset to complete. */
329 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
331 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
332 temp &= ~MUSB2_MASK_RESUME;
333 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
335 sc->sc_flags.status_suspend = 0;
339 musbotg_wakeup_peer(struct musbotg_softc *sc)
343 if (!(sc->sc_flags.status_suspend)) {
347 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
348 temp |= MUSB2_MASK_RESUME;
349 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
351 /* wait 8 milliseconds */
352 /* Wait for reset to complete. */
353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
356 temp &= ~MUSB2_MASK_RESUME;
357 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
361 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
363 DPRINTFN(4, "addr=%d\n", addr);
365 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
369 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
371 struct musbotg_softc *sc;
372 struct usb_device_request req;
376 /* get pointer to softc */
377 sc = MUSBOTG_PC2SC(td->pc);
379 if (td->channel == -1)
380 td->channel = musbotg_channel_alloc(sc, td);
382 /* EP0 is busy, wait */
383 if (td->channel == -1)
386 DPRINTFN(1, "ep_no=%d\n", td->channel);
388 /* select endpoint 0 */
389 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
391 /* read out FIFO status */
392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
394 DPRINTFN(4, "csr=0x%02x\n", csr);
397 * NOTE: If DATAEND is set we should not call the
398 * callback, hence the status stage is not complete.
400 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
401 /* do not stall at this point */
403 /* wait for interrupt */
404 DPRINTFN(1, "CSR0 DATAEND\n");
408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
409 /* clear SENTSTALL */
410 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
411 /* get latest status */
412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
413 /* update EP0 state */
416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
418 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
419 MUSB2_MASK_CSR0L_SETUPEND_CLR);
420 /* get latest status */
421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
422 /* update EP0 state */
425 if (sc->sc_ep0_busy) {
426 DPRINTFN(1, "EP0 BUSY\n");
429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
432 /* get the packet byte count */
433 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
435 /* verify data length */
436 if (count != td->remainder) {
437 DPRINTFN(1, "Invalid SETUP packet "
438 "length, %d bytes\n", count);
439 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
440 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
441 /* don't clear stall */
445 if (count != sizeof(req)) {
446 DPRINTFN(1, "Unsupported SETUP packet "
447 "length, %d bytes\n", count);
448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
449 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
450 /* don't clear stall */
454 /* clear did stall flag */
458 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
459 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
461 /* copy data into real buffer */
462 usbd_copy_in(td->pc, 0, &req, sizeof(req));
464 td->offset = sizeof(req);
467 /* set pending command */
468 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
470 /* we need set stall or dataend after this */
473 /* sneak peek the set address */
474 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
475 (req.bRequest == UR_SET_ADDRESS)) {
476 sc->sc_dv_addr = req.wValue[0] & 0x7F;
478 sc->sc_dv_addr = 0xFF;
481 musbotg_channel_free(sc, td);
482 return (0); /* complete */
485 /* abort any ongoing transfer */
486 if (!td->did_stall) {
487 DPRINTFN(4, "stalling\n");
488 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
489 MUSB2_MASK_CSR0L_SENDSTALL);
492 return (1); /* not complete */
496 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
498 struct musbotg_softc *sc;
499 struct usb_device_request req;
502 /* get pointer to softc */
503 sc = MUSBOTG_PC2SC(td->pc);
505 if (td->channel == -1)
506 td->channel = musbotg_channel_alloc(sc, td);
508 /* EP0 is busy, wait */
509 if (td->channel == -1)
512 DPRINTFN(1, "ep_no=%d\n", td->channel);
514 /* select endpoint 0 */
515 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
517 /* read out FIFO status */
518 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
519 DPRINTFN(4, "csr=0x%02x\n", csr);
521 /* Not ready yet yet */
522 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
526 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
527 MUSB2_MASK_CSR0L_ERROR))
529 /* Clear status bit */
530 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
531 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
535 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
536 DPRINTFN(1, "NAK timeout\n");
538 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
539 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
540 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
543 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
544 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
545 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
546 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
547 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
551 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
552 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
558 musbotg_channel_free(sc, td);
562 /* Fifo is not empty and there is no NAK timeout */
563 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
566 /* check if we are complete */
567 if (td->remainder == 0) {
568 /* we are complete */
569 musbotg_channel_free(sc, td);
573 /* copy data into real buffer */
574 usbd_copy_out(td->pc, 0, &req, sizeof(req));
577 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
578 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
580 /* update offset and remainder */
581 td->offset += sizeof(req);
582 td->remainder -= sizeof(req);
585 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
586 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
587 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
588 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
589 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
593 MUSB2_MASK_CSR0L_TXPKTRDY |
594 MUSB2_MASK_CSR0L_SETUPPKT);
596 /* Just to be consistent, not used above */
597 td->transaction_started = 1;
599 return (1); /* in progress */
602 /* Control endpoint only data handling functions (RX/TX/SYNC) */
605 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
607 struct usb_page_search buf_res;
608 struct musbotg_softc *sc;
613 /* get pointer to softc */
614 sc = MUSBOTG_PC2SC(td->pc);
616 /* select endpoint 0 */
617 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
619 /* check if a command is pending */
620 if (sc->sc_ep0_cmd) {
621 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
624 /* read out FIFO status */
625 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
627 DPRINTFN(4, "csr=0x%02x\n", csr);
631 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
632 MUSB2_MASK_CSR0L_SENTSTALL)) {
633 if (td->remainder == 0) {
635 * We are actually complete and have
636 * received the next SETUP
638 DPRINTFN(4, "faking complete\n");
639 return (0); /* complete */
642 * USB Host Aborted the transfer.
645 return (0); /* complete */
647 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
648 return (1); /* not complete */
650 /* get the packet byte count */
651 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
653 /* verify the packet byte count */
654 if (count != td->max_frame_size) {
655 if (count < td->max_frame_size) {
656 /* we have a short packet */
660 /* invalid USB packet */
662 return (0); /* we are complete */
665 /* verify the packet byte count */
666 if (count > td->remainder) {
667 /* invalid USB packet */
669 return (0); /* we are complete */
674 usbd_get_page(td->pc, td->offset, &buf_res);
676 /* get correct length */
677 if (buf_res.length > count) {
678 buf_res.length = count;
680 /* check for unaligned memory address */
681 if (USB_P2U(buf_res.buffer) & 3) {
686 /* receive data 4 bytes at a time */
687 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
688 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
693 /* receive data 1 byte at a time */
694 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
696 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
698 usbd_copy_in(td->pc, td->offset,
699 sc->sc_bounce_buf, count);
701 /* update offset and remainder */
703 td->remainder -= count;
706 /* check if we can optimise */
707 if (buf_res.length >= 4) {
709 /* receive data 4 bytes at a time */
710 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
711 MUSB2_REG_EPFIFO(0), buf_res.buffer,
714 temp = buf_res.length & ~3;
716 /* update counters */
719 td->remainder -= temp;
723 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
724 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
726 /* update counters */
727 count -= buf_res.length;
728 td->offset += buf_res.length;
729 td->remainder -= buf_res.length;
732 /* check if we are complete */
733 if ((td->remainder == 0) || got_short) {
735 /* we are complete */
736 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
739 /* else need to receive a zero length packet */
741 /* write command - need more data */
742 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
743 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
744 return (1); /* not complete */
748 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
750 struct usb_page_search buf_res;
751 struct musbotg_softc *sc;
755 /* get pointer to softc */
756 sc = MUSBOTG_PC2SC(td->pc);
758 /* select endpoint 0 */
759 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
761 /* check if a command is pending */
762 if (sc->sc_ep0_cmd) {
763 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
766 /* read out FIFO status */
767 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
769 DPRINTFN(4, "csr=0x%02x\n", csr);
771 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
772 MUSB2_MASK_CSR0L_SENTSTALL)) {
774 * The current transfer was aborted
778 return (0); /* complete */
780 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
781 return (1); /* not complete */
783 count = td->max_frame_size;
784 if (td->remainder < count) {
785 /* we have a short packet */
787 count = td->remainder;
792 usbd_get_page(td->pc, td->offset, &buf_res);
794 /* get correct length */
795 if (buf_res.length > count) {
796 buf_res.length = count;
798 /* check for unaligned memory address */
799 if (USB_P2U(buf_res.buffer) & 3) {
801 usbd_copy_out(td->pc, td->offset,
802 sc->sc_bounce_buf, count);
807 /* transmit data 4 bytes at a time */
808 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
809 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
814 /* receive data 1 byte at a time */
815 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
817 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
819 /* update offset and remainder */
821 td->remainder -= count;
824 /* check if we can optimise */
825 if (buf_res.length >= 4) {
827 /* transmit data 4 bytes at a time */
828 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
829 MUSB2_REG_EPFIFO(0), buf_res.buffer,
832 temp = buf_res.length & ~3;
834 /* update counters */
837 td->remainder -= temp;
841 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
842 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
844 /* update counters */
845 count -= buf_res.length;
846 td->offset += buf_res.length;
847 td->remainder -= buf_res.length;
850 /* check remainder */
851 if (td->remainder == 0) {
853 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
854 return (0); /* complete */
856 /* else we need to transmit a short packet */
859 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
860 MUSB2_MASK_CSR0L_TXPKTRDY);
862 return (1); /* not complete */
866 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
868 struct usb_page_search buf_res;
869 struct musbotg_softc *sc;
874 /* get pointer to softc */
875 sc = MUSBOTG_PC2SC(td->pc);
877 if (td->channel == -1)
878 td->channel = musbotg_channel_alloc(sc, td);
880 /* EP0 is busy, wait */
881 if (td->channel == -1)
884 DPRINTFN(1, "ep_no=%d\n", td->channel);
886 /* select endpoint 0 */
887 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
889 /* read out FIFO status */
890 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
892 DPRINTFN(4, "csr=0x%02x\n", csr);
895 if (!td->transaction_started) {
896 td->transaction_started = 1;
898 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
900 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
902 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
903 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
904 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
906 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
907 MUSB2_MASK_CSR0L_REQPKT);
912 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
913 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
914 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
916 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
923 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
924 MUSB2_MASK_CSR0L_ERROR))
926 /* Clear status bit */
927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
928 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
933 musbotg_channel_free(sc, td);
934 return (0); /* we are complete */
937 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
938 return (1); /* not yet */
940 /* get the packet byte count */
941 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
943 /* verify the packet byte count */
944 if (count != td->max_frame_size) {
945 if (count < td->max_frame_size) {
946 /* we have a short packet */
950 /* invalid USB packet */
952 musbotg_channel_free(sc, td);
953 return (0); /* we are complete */
956 /* verify the packet byte count */
957 if (count > td->remainder) {
958 /* invalid USB packet */
960 musbotg_channel_free(sc, td);
961 return (0); /* we are complete */
966 usbd_get_page(td->pc, td->offset, &buf_res);
968 /* get correct length */
969 if (buf_res.length > count) {
970 buf_res.length = count;
972 /* check for unaligned memory address */
973 if (USB_P2U(buf_res.buffer) & 3) {
978 /* receive data 4 bytes at a time */
979 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
980 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
985 /* receive data 1 byte at a time */
986 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
988 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
990 usbd_copy_in(td->pc, td->offset,
991 sc->sc_bounce_buf, count);
993 /* update offset and remainder */
995 td->remainder -= count;
998 /* check if we can optimise */
999 if (buf_res.length >= 4) {
1001 /* receive data 4 bytes at a time */
1002 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1003 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1004 buf_res.length / 4);
1006 temp = buf_res.length & ~3;
1008 /* update counters */
1011 td->remainder -= temp;
1015 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1016 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1018 /* update counters */
1019 count -= buf_res.length;
1020 td->offset += buf_res.length;
1021 td->remainder -= buf_res.length;
1024 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1025 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1027 /* check if we are complete */
1028 if ((td->remainder == 0) || got_short) {
1029 if (td->short_pkt) {
1030 /* we are complete */
1032 musbotg_channel_free(sc, td);
1035 /* else need to receive a zero length packet */
1038 td->transaction_started = 1;
1039 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1040 MUSB2_MASK_CSR0L_REQPKT);
1042 return (1); /* not complete */
1046 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1048 struct usb_page_search buf_res;
1049 struct musbotg_softc *sc;
1053 /* get pointer to softc */
1054 sc = MUSBOTG_PC2SC(td->pc);
1056 if (td->channel == -1)
1057 td->channel = musbotg_channel_alloc(sc, td);
1060 if (td->channel == -1)
1063 DPRINTFN(1, "ep_no=%d\n", td->channel);
1065 /* select endpoint */
1066 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1068 /* read out FIFO status */
1069 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1070 DPRINTFN(4, "csr=0x%02x\n", csr);
1072 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1073 MUSB2_MASK_CSR0L_ERROR)) {
1074 /* clear status bits */
1075 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1079 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1081 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1083 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1084 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1085 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1086 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1087 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1088 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1089 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1090 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1094 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1095 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1102 musbotg_channel_free(sc, td);
1103 return (0); /* complete */
1107 * Wait while FIFO is empty.
1108 * Do not flush it because it will cause transactions
1109 * with size more then packet size. It might upset
1112 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1115 /* Packet still being processed */
1116 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1119 if (td->transaction_started) {
1120 /* check remainder */
1121 if (td->remainder == 0) {
1122 if (td->short_pkt) {
1123 musbotg_channel_free(sc, td);
1124 return (0); /* complete */
1126 /* else we need to transmit a short packet */
1129 /* We're not complete - more transactions required */
1130 td->transaction_started = 0;
1133 /* check for short packet */
1134 count = td->max_frame_size;
1135 if (td->remainder < count) {
1136 /* we have a short packet */
1138 count = td->remainder;
1144 usbd_get_page(td->pc, td->offset, &buf_res);
1146 /* get correct length */
1147 if (buf_res.length > count) {
1148 buf_res.length = count;
1150 /* check for unaligned memory address */
1151 if (USB_P2U(buf_res.buffer) & 3) {
1153 usbd_copy_out(td->pc, td->offset,
1154 sc->sc_bounce_buf, count);
1159 /* transmit data 4 bytes at a time */
1160 bus_space_write_multi_4(sc->sc_io_tag,
1161 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1162 sc->sc_bounce_buf, temp / 4);
1166 /* receive data 1 byte at a time */
1167 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1168 MUSB2_REG_EPFIFO(0),
1169 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1171 /* update offset and remainder */
1172 td->offset += count;
1173 td->remainder -= count;
1176 /* check if we can optimise */
1177 if (buf_res.length >= 4) {
1179 /* transmit data 4 bytes at a time */
1180 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1181 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1182 buf_res.length / 4);
1184 temp = buf_res.length & ~3;
1186 /* update counters */
1189 td->remainder -= temp;
1193 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1194 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1197 /* update counters */
1198 count -= buf_res.length;
1199 td->offset += buf_res.length;
1200 td->remainder -= buf_res.length;
1203 /* Function address */
1204 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1205 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1206 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1207 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1209 /* TX NAK timeout */
1210 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1213 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1214 MUSB2_MASK_CSR0L_TXPKTRDY);
1216 td->transaction_started = 1;
1218 return (1); /* not complete */
1222 musbotg_dev_ctrl_status(struct musbotg_td *td)
1224 struct musbotg_softc *sc;
1227 /* get pointer to softc */
1228 sc = MUSBOTG_PC2SC(td->pc);
1230 /* select endpoint 0 */
1231 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1233 if (sc->sc_ep0_busy) {
1234 sc->sc_ep0_busy = 0;
1235 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1236 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1239 /* read out FIFO status */
1240 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1242 DPRINTFN(4, "csr=0x%02x\n", csr);
1244 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1245 /* wait for interrupt */
1246 return (1); /* not complete */
1248 if (sc->sc_dv_addr != 0xFF) {
1249 /* write function address */
1250 musbotg_set_address(sc, sc->sc_dv_addr);
1253 musbotg_channel_free(sc, td);
1254 return (0); /* complete */
1258 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1260 struct musbotg_softc *sc;
1263 /* get pointer to softc */
1264 sc = MUSBOTG_PC2SC(td->pc);
1266 if (td->channel == -1)
1267 td->channel = musbotg_channel_alloc(sc, td);
1269 /* EP0 is busy, wait */
1270 if (td->channel == -1)
1273 DPRINTFN(1, "ep_no=%d\n", td->channel);
1275 /* select endpoint 0 */
1276 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1278 if (!td->transaction_started) {
1279 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1282 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1283 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1284 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1286 /* RX NAK timeout */
1287 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1289 td->transaction_started = 1;
1292 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1293 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1294 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1297 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1298 MUSB2_MASK_CSR0L_STATUSPKT |
1299 MUSB2_MASK_CSR0L_REQPKT);
1301 return (1); /* Just started */
1305 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1307 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1309 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1310 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1311 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1312 musbotg_channel_free(sc, td);
1313 return (0); /* complete */
1316 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1317 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1318 MUSB2_MASK_CSR0L_REQPKT);
1319 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1321 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1322 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1327 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1328 MUSB2_MASK_CSR0L_ERROR))
1330 /* Clear status bit */
1331 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1332 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1337 musbotg_channel_free(sc, td);
1341 return (1); /* Not ready yet */
1345 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1347 struct musbotg_softc *sc;
1350 /* get pointer to softc */
1351 sc = MUSBOTG_PC2SC(td->pc);
1353 if (td->channel == -1)
1354 td->channel = musbotg_channel_alloc(sc, td);
1356 /* EP0 is busy, wait */
1357 if (td->channel == -1)
1360 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1361 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1363 /* select endpoint 0 */
1364 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1366 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1367 DPRINTFN(4, "csr=0x%02x\n", csr);
1370 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1374 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1375 MUSB2_MASK_CSR0L_ERROR))
1377 /* Clear status bit */
1378 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1379 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1381 musbotg_channel_free(sc, td);
1382 return (0); /* complete */
1385 if (td->transaction_started) {
1386 musbotg_channel_free(sc, td);
1387 return (0); /* complete */
1390 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1392 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1394 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1395 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1397 /* TX NAK timeout */
1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1400 td->transaction_started = 1;
1403 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1404 MUSB2_MASK_CSR0L_STATUSPKT |
1405 MUSB2_MASK_CSR0L_TXPKTRDY);
1407 return (1); /* wait for interrupt */
1411 musbotg_dev_data_rx(struct musbotg_td *td)
1413 struct usb_page_search buf_res;
1414 struct musbotg_softc *sc;
1420 to = 8; /* don't loop forever! */
1423 /* get pointer to softc */
1424 sc = MUSBOTG_PC2SC(td->pc);
1426 if (td->channel == -1)
1427 td->channel = musbotg_channel_alloc(sc, td);
1429 /* EP0 is busy, wait */
1430 if (td->channel == -1)
1433 /* select endpoint */
1434 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1437 /* read out FIFO status */
1438 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1440 DPRINTFN(4, "csr=0x%02x\n", csr);
1443 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1444 /* make sure we don't clear "RXPKTRDY" */
1445 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1446 MUSB2_MASK_CSRL_RXPKTRDY);
1450 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1451 return (1); /* not complete */
1453 /* get the packet byte count */
1454 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1456 DPRINTFN(4, "count=0x%04x\n", count);
1459 * Check for short or invalid packet:
1461 if (count != td->max_frame_size) {
1462 if (count < td->max_frame_size) {
1463 /* we have a short packet */
1467 /* invalid USB packet */
1469 musbotg_channel_free(sc, td);
1470 return (0); /* we are complete */
1473 /* verify the packet byte count */
1474 if (count > td->remainder) {
1475 /* invalid USB packet */
1477 musbotg_channel_free(sc, td);
1478 return (0); /* we are complete */
1483 usbd_get_page(td->pc, td->offset, &buf_res);
1485 /* get correct length */
1486 if (buf_res.length > count) {
1487 buf_res.length = count;
1489 /* check for unaligned memory address */
1490 if (USB_P2U(buf_res.buffer) & 3) {
1495 /* receive data 4 bytes at a time */
1496 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1497 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1502 /* receive data 1 byte at a time */
1503 bus_space_read_multi_1(sc->sc_io_tag,
1504 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1505 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1507 usbd_copy_in(td->pc, td->offset,
1508 sc->sc_bounce_buf, count);
1510 /* update offset and remainder */
1511 td->offset += count;
1512 td->remainder -= count;
1515 /* check if we can optimise */
1516 if (buf_res.length >= 4) {
1518 /* receive data 4 bytes at a time */
1519 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1520 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1521 buf_res.length / 4);
1523 temp = buf_res.length & ~3;
1525 /* update counters */
1528 td->remainder -= temp;
1532 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1533 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1536 /* update counters */
1537 count -= buf_res.length;
1538 td->offset += buf_res.length;
1539 td->remainder -= buf_res.length;
1542 /* clear status bits */
1543 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1545 /* check if we are complete */
1546 if ((td->remainder == 0) || got_short) {
1547 if (td->short_pkt) {
1548 /* we are complete */
1549 musbotg_channel_free(sc, td);
1552 /* else need to receive a zero length packet */
1557 return (1); /* not complete */
1561 musbotg_dev_data_tx(struct musbotg_td *td)
1563 struct usb_page_search buf_res;
1564 struct musbotg_softc *sc;
1569 to = 8; /* don't loop forever! */
1571 /* get pointer to softc */
1572 sc = MUSBOTG_PC2SC(td->pc);
1574 if (td->channel == -1)
1575 td->channel = musbotg_channel_alloc(sc, td);
1577 /* EP0 is busy, wait */
1578 if (td->channel == -1)
1581 /* select endpoint */
1582 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1586 /* read out FIFO status */
1587 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1589 DPRINTFN(4, "csr=0x%02x\n", csr);
1591 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1592 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1593 /* clear status bits */
1594 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1596 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1597 return (1); /* not complete */
1599 /* check for short packet */
1600 count = td->max_frame_size;
1601 if (td->remainder < count) {
1602 /* we have a short packet */
1604 count = td->remainder;
1609 usbd_get_page(td->pc, td->offset, &buf_res);
1611 /* get correct length */
1612 if (buf_res.length > count) {
1613 buf_res.length = count;
1615 /* check for unaligned memory address */
1616 if (USB_P2U(buf_res.buffer) & 3) {
1618 usbd_copy_out(td->pc, td->offset,
1619 sc->sc_bounce_buf, count);
1624 /* transmit data 4 bytes at a time */
1625 bus_space_write_multi_4(sc->sc_io_tag,
1626 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1627 sc->sc_bounce_buf, temp / 4);
1631 /* receive data 1 byte at a time */
1632 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1633 MUSB2_REG_EPFIFO(td->channel),
1634 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1636 /* update offset and remainder */
1637 td->offset += count;
1638 td->remainder -= count;
1641 /* check if we can optimise */
1642 if (buf_res.length >= 4) {
1644 /* transmit data 4 bytes at a time */
1645 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1646 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1647 buf_res.length / 4);
1649 temp = buf_res.length & ~3;
1651 /* update counters */
1654 td->remainder -= temp;
1658 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1659 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1662 /* update counters */
1663 count -= buf_res.length;
1664 td->offset += buf_res.length;
1665 td->remainder -= buf_res.length;
1668 /* Max packet size */
1669 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1672 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1673 MUSB2_MASK_CSRL_TXPKTRDY);
1675 /* check remainder */
1676 if (td->remainder == 0) {
1677 if (td->short_pkt) {
1678 musbotg_channel_free(sc, td);
1679 return (0); /* complete */
1681 /* else we need to transmit a short packet */
1686 return (1); /* not complete */
1690 musbotg_host_data_rx(struct musbotg_td *td)
1692 struct usb_page_search buf_res;
1693 struct musbotg_softc *sc;
1699 /* get pointer to softc */
1700 sc = MUSBOTG_PC2SC(td->pc);
1702 if (td->channel == -1)
1703 td->channel = musbotg_channel_alloc(sc, td);
1706 if (td->channel == -1)
1709 DPRINTFN(1, "ep_no=%d\n", td->channel);
1711 to = 8; /* don't loop forever! */
1714 /* select endpoint */
1715 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1718 /* read out FIFO status */
1719 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1720 DPRINTFN(4, "csr=0x%02x\n", csr);
1722 if (!td->transaction_started) {
1723 /* Function address */
1724 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1727 /* SPLIT transaction */
1728 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1733 /* RX NAK timeout */
1734 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1737 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1739 /* Protocol, speed, device endpoint */
1740 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1742 /* Max packet size */
1743 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1746 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1747 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1749 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1751 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1753 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1755 /* Set data toggle */
1756 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1759 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1760 MUSB2_MASK_CSRL_RXREQPKT);
1762 td->transaction_started = 1;
1766 /* clear NAK timeout */
1767 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1768 DPRINTFN(4, "NAK Timeout\n");
1769 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1770 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1771 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1773 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1774 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1780 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1781 DPRINTFN(4, "RXERROR\n");
1785 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1786 DPRINTFN(4, "RXSTALL\n");
1791 musbotg_channel_free(sc, td);
1792 return (0); /* we are complete */
1795 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1796 /* No data available yet */
1801 /* get the packet byte count */
1802 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1803 DPRINTFN(4, "count=0x%04x\n", count);
1806 * Check for short or invalid packet:
1808 if (count != td->max_frame_size) {
1809 if (count < td->max_frame_size) {
1810 /* we have a short packet */
1814 /* invalid USB packet */
1816 musbotg_channel_free(sc, td);
1817 return (0); /* we are complete */
1821 /* verify the packet byte count */
1822 if (count > td->remainder) {
1823 /* invalid USB packet */
1825 musbotg_channel_free(sc, td);
1826 return (0); /* we are complete */
1832 usbd_get_page(td->pc, td->offset, &buf_res);
1834 /* get correct length */
1835 if (buf_res.length > count) {
1836 buf_res.length = count;
1838 /* check for unaligned memory address */
1839 if (USB_P2U(buf_res.buffer) & 3) {
1844 /* receive data 4 bytes at a time */
1845 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1846 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1851 /* receive data 1 byte at a time */
1852 bus_space_read_multi_1(sc->sc_io_tag,
1853 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1854 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1856 usbd_copy_in(td->pc, td->offset,
1857 sc->sc_bounce_buf, count);
1859 /* update offset and remainder */
1860 td->offset += count;
1861 td->remainder -= count;
1864 /* check if we can optimise */
1865 if (buf_res.length >= 4) {
1867 /* receive data 4 bytes at a time */
1868 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1869 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1870 buf_res.length / 4);
1872 temp = buf_res.length & ~3;
1874 /* update counters */
1877 td->remainder -= temp;
1881 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1882 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1885 /* update counters */
1886 count -= buf_res.length;
1887 td->offset += buf_res.length;
1888 td->remainder -= buf_res.length;
1891 /* clear status bits */
1892 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1894 /* check if we are complete */
1895 if ((td->remainder == 0) || got_short) {
1896 if (td->short_pkt) {
1897 /* we are complete */
1898 musbotg_channel_free(sc, td);
1901 /* else need to receive a zero length packet */
1904 /* Reset transaction state and restart */
1905 td->transaction_started = 0;
1910 return (1); /* not complete */
1914 musbotg_host_data_tx(struct musbotg_td *td)
1916 struct usb_page_search buf_res;
1917 struct musbotg_softc *sc;
1921 /* get pointer to softc */
1922 sc = MUSBOTG_PC2SC(td->pc);
1924 if (td->channel == -1)
1925 td->channel = musbotg_channel_alloc(sc, td);
1928 if (td->channel == -1)
1931 DPRINTFN(1, "ep_no=%d\n", td->channel);
1933 /* select endpoint */
1934 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1936 /* read out FIFO status */
1937 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1938 DPRINTFN(4, "csr=0x%02x\n", csr);
1940 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1941 MUSB2_MASK_CSRL_TXERROR)) {
1942 /* clear status bits */
1943 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1945 musbotg_channel_free(sc, td);
1946 return (0); /* complete */
1949 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1951 * Flush TX FIFO before clearing NAK TO
1953 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1954 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1956 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1957 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1958 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1959 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1960 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1964 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1965 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1968 musbotg_channel_free(sc, td);
1969 return (0); /* complete */
1973 * Wait while FIFO is empty.
1974 * Do not flush it because it will cause transactions
1975 * with size more then packet size. It might upset
1978 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1981 /* Packet still being processed */
1982 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1985 if (td->transaction_started) {
1986 /* check remainder */
1987 if (td->remainder == 0) {
1988 if (td->short_pkt) {
1989 musbotg_channel_free(sc, td);
1990 return (0); /* complete */
1992 /* else we need to transmit a short packet */
1995 /* We're not complete - more transactions required */
1996 td->transaction_started = 0;
1999 /* check for short packet */
2000 count = td->max_frame_size;
2001 if (td->remainder < count) {
2002 /* we have a short packet */
2004 count = td->remainder;
2010 usbd_get_page(td->pc, td->offset, &buf_res);
2012 /* get correct length */
2013 if (buf_res.length > count) {
2014 buf_res.length = count;
2016 /* check for unaligned memory address */
2017 if (USB_P2U(buf_res.buffer) & 3) {
2019 usbd_copy_out(td->pc, td->offset,
2020 sc->sc_bounce_buf, count);
2025 /* transmit data 4 bytes at a time */
2026 bus_space_write_multi_4(sc->sc_io_tag,
2027 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2028 sc->sc_bounce_buf, temp / 4);
2032 /* receive data 1 byte at a time */
2033 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2034 MUSB2_REG_EPFIFO(td->channel),
2035 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2037 /* update offset and remainder */
2038 td->offset += count;
2039 td->remainder -= count;
2042 /* check if we can optimise */
2043 if (buf_res.length >= 4) {
2045 /* transmit data 4 bytes at a time */
2046 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2047 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2048 buf_res.length / 4);
2050 temp = buf_res.length & ~3;
2052 /* update counters */
2055 td->remainder -= temp;
2059 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2060 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2063 /* update counters */
2064 count -= buf_res.length;
2065 td->offset += buf_res.length;
2066 td->remainder -= buf_res.length;
2069 /* Function address */
2070 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2073 /* SPLIT transaction */
2074 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2079 /* TX NAK timeout */
2080 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2083 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2085 /* Protocol, speed, device endpoint */
2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2088 /* Max packet size */
2089 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2091 if (!td->transaction_started) {
2092 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2093 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2095 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2097 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2099 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2101 /* Set data toggle */
2102 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2106 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2107 MUSB2_MASK_CSRL_TXPKTRDY);
2109 /* Update Data Toggle */
2111 td->transaction_started = 1;
2113 return (1); /* not complete */
2117 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2119 struct musbotg_softc *sc;
2120 struct musbotg_td *td;
2123 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2125 td = xfer->td_transfer_cache;
2128 if ((td->func) (td)) {
2129 /* operation in progress */
2133 if (((void *)td) == xfer->td_transfer_last) {
2138 } else if (td->remainder > 0) {
2140 * We had a short transfer. If there is no alternate
2141 * next, stop processing !
2143 if (!td->alt_next) {
2148 * Fetch the next transfer descriptor and transfer
2149 * some flags to the next transfer descriptor
2152 xfer->td_transfer_cache = td;
2155 return (1); /* not complete */
2157 /* compute all actual lengths */
2158 musbotg_standard_done(xfer);
2160 return (0); /* complete */
2164 musbotg_interrupt_poll(struct musbotg_softc *sc)
2166 struct usb_xfer *xfer;
2169 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2170 if (!musbotg_xfer_do_fifo(xfer)) {
2171 /* queue has been modified */
2178 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2180 DPRINTFN(4, "vbus = %u\n", is_on);
2182 USB_BUS_LOCK(&sc->sc_bus);
2184 if (!sc->sc_flags.status_vbus) {
2185 sc->sc_flags.status_vbus = 1;
2187 /* complete root HUB interrupt endpoint */
2188 musbotg_root_intr(sc);
2191 if (sc->sc_flags.status_vbus) {
2192 sc->sc_flags.status_vbus = 0;
2193 sc->sc_flags.status_bus_reset = 0;
2194 sc->sc_flags.status_suspend = 0;
2195 sc->sc_flags.change_suspend = 0;
2196 sc->sc_flags.change_connect = 1;
2198 /* complete root HUB interrupt endpoint */
2199 musbotg_root_intr(sc);
2203 USB_BUS_UNLOCK(&sc->sc_bus);
2207 musbotg_connect_interrupt(struct musbotg_softc *sc)
2209 USB_BUS_LOCK(&sc->sc_bus);
2210 sc->sc_flags.change_connect = 1;
2212 /* complete root HUB interrupt endpoint */
2213 musbotg_root_intr(sc);
2214 USB_BUS_UNLOCK(&sc->sc_bus);
2218 musbotg_interrupt(struct musbotg_softc *sc,
2219 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2227 USB_BUS_LOCK(&sc->sc_bus);
2231 /* read all interrupt registers */
2232 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2234 /* read all FIFO interrupts */
2235 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2236 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2237 rx_status |= rxstat;
2238 tx_status |= txstat;
2241 /* Clear platform flags after first time */
2246 /* check for any bus state change interrupts */
2248 if (usb_status & (MUSB2_MASK_IRESET |
2249 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2250 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) {
2252 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2254 if (usb_status & MUSB2_MASK_IRESET) {
2256 /* set correct state */
2257 sc->sc_flags.status_bus_reset = 1;
2258 sc->sc_flags.status_suspend = 0;
2259 sc->sc_flags.change_suspend = 0;
2260 sc->sc_flags.change_connect = 1;
2262 /* determine line speed */
2263 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2264 if (temp & MUSB2_MASK_HSMODE)
2265 sc->sc_flags.status_high_speed = 1;
2267 sc->sc_flags.status_high_speed = 0;
2270 * After reset all interrupts are on and we need to
2273 temp = MUSB2_MASK_IRESET;
2274 /* disable resume interrupt */
2275 temp &= ~MUSB2_MASK_IRESUME;
2276 /* enable suspend interrupt */
2277 temp |= MUSB2_MASK_ISUSP;
2278 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2279 /* disable TX and RX interrupts */
2280 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2281 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2284 * If RXRSM and RXSUSP is set at the same time we interpret
2285 * that like RESUME. Resume is set when there is at least 3
2286 * milliseconds of inactivity on the USB BUS.
2288 if (usb_status & MUSB2_MASK_IRESUME) {
2289 if (sc->sc_flags.status_suspend) {
2290 sc->sc_flags.status_suspend = 0;
2291 sc->sc_flags.change_suspend = 1;
2293 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2294 /* disable resume interrupt */
2295 temp &= ~MUSB2_MASK_IRESUME;
2296 /* enable suspend interrupt */
2297 temp |= MUSB2_MASK_ISUSP;
2298 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2300 } else if (usb_status & MUSB2_MASK_ISUSP) {
2301 if (!sc->sc_flags.status_suspend) {
2302 sc->sc_flags.status_suspend = 1;
2303 sc->sc_flags.change_suspend = 1;
2305 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2306 /* disable suspend interrupt */
2307 temp &= ~MUSB2_MASK_ISUSP;
2308 /* enable resume interrupt */
2309 temp |= MUSB2_MASK_IRESUME;
2310 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2314 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2315 sc->sc_flags.change_connect = 1;
2318 * Host Mode: There is no IRESET so assume bus is
2319 * always in reset state once device is connected.
2321 if (sc->sc_mode == MUSB2_HOST_MODE) {
2322 if (usb_status & MUSB2_MASK_ICONN)
2323 sc->sc_flags.status_bus_reset = 1;
2324 if (usb_status & MUSB2_MASK_IDISC)
2325 sc->sc_flags.status_bus_reset = 0;
2328 /* complete root HUB interrupt endpoint */
2329 musbotg_root_intr(sc);
2331 /* check for any endpoint interrupts */
2333 if (rx_status || tx_status) {
2334 DPRINTFN(4, "real endpoint interrupt "
2335 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2337 /* poll one time regardless of FIFO status */
2339 musbotg_interrupt_poll(sc);
2344 USB_BUS_UNLOCK(&sc->sc_bus);
2348 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2350 struct musbotg_td *td;
2352 /* get current Transfer Descriptor */
2356 /* prepare for next TD */
2357 temp->td_next = td->obj_next;
2359 /* fill out the Transfer Descriptor */
2360 td->func = temp->func;
2362 td->offset = temp->offset;
2363 td->remainder = temp->len;
2365 td->transaction_started = 0;
2366 td->did_stall = temp->did_stall;
2367 td->short_pkt = temp->short_pkt;
2368 td->alt_next = temp->setup_alt_next;
2369 td->channel = temp->channel;
2370 td->dev_addr = temp->dev_addr;
2371 td->haddr = temp->haddr;
2372 td->hport = temp->hport;
2373 td->transfer_type = temp->transfer_type;
2377 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2379 struct musbotg_std_temp temp;
2380 struct musbotg_softc *sc;
2381 struct musbotg_td *td;
2385 enum usb_dev_speed speed;
2389 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2390 xfer->address, UE_GET_ADDR(xfer->endpointno),
2391 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2393 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2394 ep_no = (xfer->endpointno & UE_ADDR);
2396 temp.max_frame_size = xfer->max_frame_size;
2398 td = xfer->td_start[0];
2399 xfer->td_transfer_first = td;
2400 xfer->td_transfer_cache = td;
2403 dev_addr = xfer->address;
2405 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2409 temp.td_next = xfer->td_start[0];
2411 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
2412 temp.did_stall = !xfer->flags_int.control_stall;
2414 temp.dev_addr = dev_addr;
2415 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2416 temp.hport = xfer->xroot->udev->hs_port_no;
2418 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2419 speed = usbd_get_speed(xfer->xroot->udev);
2423 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2425 case USB_SPEED_FULL:
2426 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2428 case USB_SPEED_HIGH:
2429 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2432 temp.transfer_type = 0;
2433 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2437 switch (xfer_type) {
2439 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2441 case UE_ISOCHRONOUS:
2442 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2445 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2448 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2451 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2456 temp.transfer_type |= ep_no;
2457 td->toggle = xfer->endpoint->toggle_next;
2460 /* check if we should prepend a setup message */
2462 if (xfer->flags_int.control_xfr) {
2463 if (xfer->flags_int.control_hdr) {
2465 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2466 temp.func = &musbotg_dev_ctrl_setup_rx;
2468 temp.func = &musbotg_host_ctrl_setup_tx;
2470 temp.len = xfer->frlengths[0];
2471 temp.pc = xfer->frbuffers + 0;
2472 temp.short_pkt = temp.len ? 1 : 0;
2474 musbotg_setup_standard_chain_sub(&temp);
2483 if (x != xfer->nframes) {
2484 if (xfer->endpointno & UE_DIR_IN)
2487 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2491 if (xfer->flags_int.control_xfr)
2492 temp.func = &musbotg_host_ctrl_data_tx;
2494 temp.func = &musbotg_host_data_tx;
2496 if (xfer->flags_int.control_xfr)
2497 temp.func = &musbotg_host_ctrl_data_rx;
2499 temp.func = &musbotg_host_data_rx;
2504 if (xfer->flags_int.control_xfr)
2505 temp.func = &musbotg_dev_ctrl_data_tx;
2507 temp.func = &musbotg_dev_data_tx;
2509 if (xfer->flags_int.control_xfr)
2510 temp.func = &musbotg_dev_ctrl_data_rx;
2512 temp.func = &musbotg_dev_data_rx;
2516 /* setup "pc" pointer */
2517 temp.pc = xfer->frbuffers + x;
2519 while (x != xfer->nframes) {
2521 /* DATA0 / DATA1 message */
2523 temp.len = xfer->frlengths[x];
2527 if (x == xfer->nframes) {
2528 if (xfer->flags_int.control_xfr) {
2529 if (xfer->flags_int.control_act) {
2530 temp.setup_alt_next = 0;
2533 temp.setup_alt_next = 0;
2536 if (temp.len == 0) {
2538 /* make sure that we send an USB packet */
2544 if (xfer->flags_int.isochronous_xfr) {
2545 /* isochronous data transfer */
2546 /* don't force short */
2549 /* regular data transfer */
2550 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2554 musbotg_setup_standard_chain_sub(&temp);
2556 if (xfer->flags_int.isochronous_xfr) {
2557 temp.offset += temp.len;
2559 /* get next Page Cache pointer */
2560 temp.pc = xfer->frbuffers + x;
2564 /* check for control transfer */
2565 if (xfer->flags_int.control_xfr) {
2567 /* always setup a valid "pc" pointer for status and sync */
2568 temp.pc = xfer->frbuffers + 0;
2571 temp.setup_alt_next = 0;
2573 /* check if we should append a status stage */
2574 if (!xfer->flags_int.control_act) {
2576 * Send a DATA1 message and invert the current
2577 * endpoint direction.
2579 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2580 temp.func = &musbotg_dev_ctrl_status;
2582 if (xfer->endpointno & UE_DIR_IN)
2583 temp.func = musbotg_host_ctrl_status_tx;
2585 temp.func = musbotg_host_ctrl_status_rx;
2587 musbotg_setup_standard_chain_sub(&temp);
2590 /* must have at least one frame! */
2592 xfer->td_transfer_last = td;
2596 musbotg_timeout(void *arg)
2598 struct usb_xfer *xfer = arg;
2600 DPRINTFN(1, "xfer=%p\n", xfer);
2602 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2604 /* transfer is transferred */
2605 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2609 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2614 * Only enable the endpoint interrupt when we are
2615 * actually waiting for data, hence we are dealing
2616 * with level triggered interrupts !
2618 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2624 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2626 temp |= MUSB2_MASK_EPINT(0);
2628 temp &= ~MUSB2_MASK_EPINT(0);
2630 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2632 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2634 temp |= MUSB2_MASK_EPINT(channel);
2636 temp &= ~MUSB2_MASK_EPINT(channel);
2637 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2639 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2641 temp |= MUSB2_MASK_EPINT(channel);
2643 temp &= ~MUSB2_MASK_EPINT(channel);
2644 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2647 if (sc->sc_ep_int_set)
2648 sc->sc_ep_int_set(sc, channel, on);
2652 musbotg_start_standard_chain(struct usb_xfer *xfer)
2657 if (musbotg_xfer_do_fifo(xfer)) {
2659 DPRINTFN(14, "enabled interrupts on endpoint\n");
2661 /* put transfer on interrupt queue */
2662 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2664 /* start timeout, if any */
2665 if (xfer->timeout != 0) {
2666 usbd_transfer_timeout_ms(xfer,
2667 &musbotg_timeout, xfer->timeout);
2673 musbotg_root_intr(struct musbotg_softc *sc)
2677 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2680 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2682 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2683 sizeof(sc->sc_hub_idata));
2687 musbotg_standard_done_sub(struct usb_xfer *xfer)
2689 struct musbotg_td *td;
2695 td = xfer->td_transfer_cache;
2698 len = td->remainder;
2700 xfer->endpoint->toggle_next = td->toggle;
2702 if (xfer->aframes != xfer->nframes) {
2704 * Verify the length and subtract
2705 * the remainder from "frlengths[]":
2707 if (len > xfer->frlengths[xfer->aframes]) {
2710 xfer->frlengths[xfer->aframes] -= len;
2713 /* Check for transfer error */
2715 /* the transfer is finished */
2720 /* Check for short transfer */
2722 if (xfer->flags_int.short_frames_ok) {
2723 /* follow alt next */
2730 /* the transfer is finished */
2738 /* this USB frame is complete */
2744 /* update transfer cache */
2746 xfer->td_transfer_cache = td;
2749 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2753 musbotg_standard_done(struct usb_xfer *xfer)
2755 usb_error_t err = 0;
2757 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2758 xfer, xfer->endpoint);
2762 xfer->td_transfer_cache = xfer->td_transfer_first;
2764 if (xfer->flags_int.control_xfr) {
2766 if (xfer->flags_int.control_hdr) {
2768 err = musbotg_standard_done_sub(xfer);
2772 if (xfer->td_transfer_cache == NULL) {
2776 while (xfer->aframes != xfer->nframes) {
2778 err = musbotg_standard_done_sub(xfer);
2781 if (xfer->td_transfer_cache == NULL) {
2786 if (xfer->flags_int.control_xfr &&
2787 !xfer->flags_int.control_act) {
2789 err = musbotg_standard_done_sub(xfer);
2792 musbotg_device_done(xfer, err);
2795 /*------------------------------------------------------------------------*
2796 * musbotg_device_done
2798 * NOTE: this function can be called more than one time on the
2799 * same USB transfer!
2800 *------------------------------------------------------------------------*/
2802 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2804 struct musbotg_td *td;
2805 struct musbotg_softc *sc;
2807 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2809 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2810 xfer, xfer->endpoint, error);
2812 DPRINTFN(14, "disabled interrupts on endpoint\n");
2814 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2815 td = xfer->td_transfer_cache;
2817 if (td && (td->channel != -1))
2818 musbotg_channel_free(sc, td);
2820 /* dequeue transfer and start next transfer */
2821 usbd_transfer_done(xfer, error);
2825 musbotg_xfer_stall(struct usb_xfer *xfer)
2827 musbotg_device_done(xfer, USB_ERR_STALLED);
2831 musbotg_set_stall(struct usb_device *udev,
2832 struct usb_endpoint *ep, uint8_t *did_stall)
2834 struct musbotg_softc *sc;
2837 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2839 DPRINTFN(4, "endpoint=%p\n", ep);
2841 /* set FORCESTALL */
2842 sc = MUSBOTG_BUS2SC(udev->bus);
2844 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2846 /* select endpoint */
2847 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2849 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2850 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2851 MUSB2_MASK_CSRL_TXSENDSTALL);
2853 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2854 MUSB2_MASK_CSRL_RXSENDSTALL);
2859 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2860 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2866 if (ep_type == UE_CONTROL) {
2867 /* clearing stall is not needed */
2870 /* select endpoint */
2871 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2873 /* compute max frame size */
2874 mps = wMaxPacket & 0x7FF;
2875 switch ((wMaxPacket >> 11) & 3) {
2886 if (ep_dir == UE_DIR_IN) {
2890 /* Configure endpoint */
2893 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2894 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2895 MUSB2_MASK_CSRH_TXMODE | temp);
2897 case UE_ISOCHRONOUS:
2898 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2899 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2900 MUSB2_MASK_CSRH_TXMODE |
2901 MUSB2_MASK_CSRH_TXISO | temp);
2904 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2905 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2906 MUSB2_MASK_CSRH_TXMODE | temp);
2912 /* Need to flush twice in case of double bufring */
2913 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2914 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2915 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2916 MUSB2_MASK_CSRL_TXFFLUSH);
2917 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2918 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2919 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2920 MUSB2_MASK_CSRL_TXFFLUSH);
2921 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2924 /* reset data toggle */
2925 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2926 MUSB2_MASK_CSRL_TXDT_CLR);
2927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2928 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2930 /* set double/single buffering */
2931 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2932 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2933 max_in_frame_size / 2)) {
2935 temp &= ~(1 << ep_no);
2938 temp |= (1 << ep_no);
2940 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2942 /* clear sent stall */
2943 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2944 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2945 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2951 /* Configure endpoint */
2954 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2955 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2956 MUSB2_MASK_CSRH_RXNYET | temp);
2958 case UE_ISOCHRONOUS:
2959 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2960 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2961 MUSB2_MASK_CSRH_RXNYET |
2962 MUSB2_MASK_CSRH_RXISO | temp);
2965 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2966 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2972 /* Need to flush twice in case of double bufring */
2973 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2974 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2975 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2976 MUSB2_MASK_CSRL_RXFFLUSH);
2977 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2978 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2979 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2980 MUSB2_MASK_CSRL_RXFFLUSH);
2981 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2984 /* reset data toggle */
2985 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2986 MUSB2_MASK_CSRL_RXDT_CLR);
2987 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2988 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2990 /* set double/single buffering */
2991 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2992 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2993 max_out_frame_size / 2)) {
2995 temp &= ~(1 << ep_no);
2998 temp |= (1 << ep_no);
3000 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3002 /* clear sent stall */
3003 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3004 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3010 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3012 struct musbotg_softc *sc;
3013 struct usb_endpoint_descriptor *ed;
3015 DPRINTFN(4, "endpoint=%p\n", ep);
3017 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3020 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3025 sc = MUSBOTG_BUS2SC(udev->bus);
3027 /* get endpoint descriptor */
3030 /* reset endpoint */
3031 musbotg_clear_stall_sub(sc,
3032 UGETW(ed->wMaxPacketSize),
3033 (ed->bEndpointAddress & UE_ADDR),
3034 (ed->bmAttributes & UE_XFERTYPE),
3035 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3039 musbotg_init(struct musbotg_softc *sc)
3041 struct usb_hw_ep_profile *pf;
3051 DPRINTFN(1, "start\n");
3053 /* set up the bus structure */
3054 sc->sc_bus.usbrev = USB_REV_2_0;
3055 sc->sc_bus.methods = &musbotg_bus_methods;
3057 USB_BUS_LOCK(&sc->sc_bus);
3059 /* turn on clocks */
3061 if (sc->sc_clocks_on) {
3062 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3065 /* wait a little for things to stabilise */
3066 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3068 /* disable all interrupts */
3070 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3071 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3073 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3074 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3075 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3077 /* disable pullup */
3079 musbotg_pull_common(sc, 0);
3081 /* wait a little bit (10ms) */
3082 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3085 /* disable double packet buffering */
3086 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3087 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3089 /* enable HighSpeed and ISO Update flags */
3091 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3092 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3094 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3095 /* clear Session bit, if set */
3096 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3097 temp &= ~MUSB2_MASK_SESS;
3098 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3100 /* Enter session for Host mode */
3101 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3102 temp |= MUSB2_MASK_SESS;
3103 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3106 /* wait a little for things to stabilise */
3107 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3109 DPRINTF("DEVCTL=0x%02x\n", temp);
3111 /* disable testmode */
3113 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3115 /* set default value */
3117 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3119 /* select endpoint index 0 */
3121 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3123 /* read out number of endpoints */
3126 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3129 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3131 /* these numbers exclude the control endpoint */
3133 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3135 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3136 if (sc->sc_ep_max == 0) {
3137 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3139 /* read out configuration data */
3141 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3143 DPRINTFN(2, "Config Data: 0x%02x\n",
3146 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3149 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3150 "assuming 16Kbytes of FIFO RAM\n");
3153 DPRINTFN(2, "HW version: 0x%04x\n",
3154 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3156 /* initialise endpoint profiles */
3160 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3161 pf = sc->sc_hw_ep_profile + temp;
3163 /* select endpoint */
3164 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3166 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3167 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3168 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3170 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3171 temp, ftx, frx, dynfifo);
3174 if (frx && (temp <= nrx)) {
3177 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3178 MUSB2_VAL_FIFOSZ_4096 |
3180 } else if (temp < 8) {
3182 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3183 MUSB2_VAL_FIFOSZ_512 |
3186 frx = 7; /* 128 bytes */
3187 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3188 MUSB2_VAL_FIFOSZ_128);
3191 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3194 offset += (1 << frx);
3196 if (ftx && (temp <= ntx)) {
3199 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3200 MUSB2_VAL_FIFOSZ_4096 |
3202 } else if (temp < 8) {
3204 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3205 MUSB2_VAL_FIFOSZ_512 |
3208 ftx = 7; /* 128 bytes */
3209 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3210 MUSB2_VAL_FIFOSZ_128);
3213 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3216 offset += (1 << ftx);
3220 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3221 pf->max_in_frame_size = 1 << ftx;
3222 pf->max_out_frame_size = 1 << frx;
3223 pf->is_simplex = 0; /* duplex */
3224 pf->support_multi_buffer = 1;
3225 pf->support_bulk = 1;
3226 pf->support_interrupt = 1;
3227 pf->support_isochronous = 1;
3229 pf->support_out = 1;
3230 } else if (frx && (temp <= nrx)) {
3231 pf->max_out_frame_size = 1 << frx;
3232 pf->is_simplex = 1; /* simplex */
3233 pf->support_multi_buffer = 1;
3234 pf->support_bulk = 1;
3235 pf->support_interrupt = 1;
3236 pf->support_isochronous = 1;
3237 pf->support_out = 1;
3238 } else if (ftx && (temp <= ntx)) {
3239 pf->max_in_frame_size = 1 << ftx;
3240 pf->is_simplex = 1; /* simplex */
3241 pf->support_multi_buffer = 1;
3242 pf->support_bulk = 1;
3243 pf->support_interrupt = 1;
3244 pf->support_isochronous = 1;
3249 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3251 /* turn on default interrupts */
3253 if (sc->sc_mode == MUSB2_HOST_MODE)
3254 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3256 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3259 musbotg_clocks_off(sc);
3261 USB_BUS_UNLOCK(&sc->sc_bus);
3263 /* catch any lost interrupts */
3265 musbotg_do_poll(&sc->sc_bus);
3267 return (0); /* success */
3271 musbotg_uninit(struct musbotg_softc *sc)
3273 USB_BUS_LOCK(&sc->sc_bus);
3275 /* disable all interrupts */
3276 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3277 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3278 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3280 sc->sc_flags.port_powered = 0;
3281 sc->sc_flags.status_vbus = 0;
3282 sc->sc_flags.status_bus_reset = 0;
3283 sc->sc_flags.status_suspend = 0;
3284 sc->sc_flags.change_suspend = 0;
3285 sc->sc_flags.change_connect = 1;
3287 musbotg_pull_down(sc);
3288 musbotg_clocks_off(sc);
3289 USB_BUS_UNLOCK(&sc->sc_bus);
3293 musbotg_suspend(struct musbotg_softc *sc)
3299 musbotg_resume(struct musbotg_softc *sc)
3305 musbotg_do_poll(struct usb_bus *bus)
3307 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3309 USB_BUS_LOCK(&sc->sc_bus);
3310 musbotg_interrupt_poll(sc);
3311 USB_BUS_UNLOCK(&sc->sc_bus);
3314 /*------------------------------------------------------------------------*
3315 * musbotg bulk support
3316 *------------------------------------------------------------------------*/
3318 musbotg_device_bulk_open(struct usb_xfer *xfer)
3324 musbotg_device_bulk_close(struct usb_xfer *xfer)
3326 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3330 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3336 musbotg_device_bulk_start(struct usb_xfer *xfer)
3339 musbotg_setup_standard_chain(xfer);
3340 musbotg_start_standard_chain(xfer);
3343 struct usb_pipe_methods musbotg_device_bulk_methods =
3345 .open = musbotg_device_bulk_open,
3346 .close = musbotg_device_bulk_close,
3347 .enter = musbotg_device_bulk_enter,
3348 .start = musbotg_device_bulk_start,
3351 /*------------------------------------------------------------------------*
3352 * musbotg control support
3353 *------------------------------------------------------------------------*/
3355 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3361 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3363 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3367 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3373 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3376 musbotg_setup_standard_chain(xfer);
3377 musbotg_start_standard_chain(xfer);
3380 struct usb_pipe_methods musbotg_device_ctrl_methods =
3382 .open = musbotg_device_ctrl_open,
3383 .close = musbotg_device_ctrl_close,
3384 .enter = musbotg_device_ctrl_enter,
3385 .start = musbotg_device_ctrl_start,
3388 /*------------------------------------------------------------------------*
3389 * musbotg interrupt support
3390 *------------------------------------------------------------------------*/
3392 musbotg_device_intr_open(struct usb_xfer *xfer)
3398 musbotg_device_intr_close(struct usb_xfer *xfer)
3400 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3404 musbotg_device_intr_enter(struct usb_xfer *xfer)
3410 musbotg_device_intr_start(struct usb_xfer *xfer)
3413 musbotg_setup_standard_chain(xfer);
3414 musbotg_start_standard_chain(xfer);
3417 struct usb_pipe_methods musbotg_device_intr_methods =
3419 .open = musbotg_device_intr_open,
3420 .close = musbotg_device_intr_close,
3421 .enter = musbotg_device_intr_enter,
3422 .start = musbotg_device_intr_start,
3425 /*------------------------------------------------------------------------*
3426 * musbotg full speed isochronous support
3427 *------------------------------------------------------------------------*/
3429 musbotg_device_isoc_open(struct usb_xfer *xfer)
3435 musbotg_device_isoc_close(struct usb_xfer *xfer)
3437 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3441 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3443 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3448 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3449 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3451 /* get the current frame index */
3453 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3456 * check if the frame index is within the window where the frames
3459 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3461 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3462 fs_frames = (xfer->nframes + 7) / 8;
3464 fs_frames = xfer->nframes;
3467 if ((xfer->endpoint->is_synced == 0) ||
3468 (temp < fs_frames)) {
3470 * If there is data underflow or the pipe queue is
3471 * empty we schedule the transfer a few frames ahead
3472 * of the current frame position. Else two isochronous
3473 * transfers might overlap.
3475 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3476 xfer->endpoint->is_synced = 1;
3477 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3480 * compute how many milliseconds the insertion is ahead of the
3481 * current frame position:
3483 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3486 * pre-compute when the isochronous transfer will be finished:
3488 xfer->isoc_time_complete =
3489 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3492 /* compute frame number for next insertion */
3493 xfer->endpoint->isoc_next += fs_frames;
3496 musbotg_setup_standard_chain(xfer);
3500 musbotg_device_isoc_start(struct usb_xfer *xfer)
3502 /* start TD chain */
3503 musbotg_start_standard_chain(xfer);
3506 struct usb_pipe_methods musbotg_device_isoc_methods =
3508 .open = musbotg_device_isoc_open,
3509 .close = musbotg_device_isoc_close,
3510 .enter = musbotg_device_isoc_enter,
3511 .start = musbotg_device_isoc_start,
3514 /*------------------------------------------------------------------------*
3515 * musbotg root control support
3516 *------------------------------------------------------------------------*
3517 * Simulate a hardware HUB by handling all the necessary requests.
3518 *------------------------------------------------------------------------*/
3520 static const struct usb_device_descriptor musbotg_devd = {
3521 .bLength = sizeof(struct usb_device_descriptor),
3522 .bDescriptorType = UDESC_DEVICE,
3523 .bcdUSB = {0x00, 0x02},
3524 .bDeviceClass = UDCLASS_HUB,
3525 .bDeviceSubClass = UDSUBCLASS_HUB,
3526 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3527 .bMaxPacketSize = 64,
3528 .bcdDevice = {0x00, 0x01},
3531 .bNumConfigurations = 1,
3534 static const struct usb_device_qualifier musbotg_odevd = {
3535 .bLength = sizeof(struct usb_device_qualifier),
3536 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3537 .bcdUSB = {0x00, 0x02},
3538 .bDeviceClass = UDCLASS_HUB,
3539 .bDeviceSubClass = UDSUBCLASS_HUB,
3540 .bDeviceProtocol = UDPROTO_FSHUB,
3541 .bMaxPacketSize0 = 0,
3542 .bNumConfigurations = 0,
3545 static const struct musbotg_config_desc musbotg_confd = {
3547 .bLength = sizeof(struct usb_config_descriptor),
3548 .bDescriptorType = UDESC_CONFIG,
3549 .wTotalLength[0] = sizeof(musbotg_confd),
3551 .bConfigurationValue = 1,
3552 .iConfiguration = 0,
3553 .bmAttributes = UC_SELF_POWERED,
3557 .bLength = sizeof(struct usb_interface_descriptor),
3558 .bDescriptorType = UDESC_INTERFACE,
3560 .bInterfaceClass = UICLASS_HUB,
3561 .bInterfaceSubClass = UISUBCLASS_HUB,
3562 .bInterfaceProtocol = 0,
3565 .bLength = sizeof(struct usb_endpoint_descriptor),
3566 .bDescriptorType = UDESC_ENDPOINT,
3567 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3568 .bmAttributes = UE_INTERRUPT,
3569 .wMaxPacketSize[0] = 8,
3574 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3576 static const struct usb_hub_descriptor_min musbotg_hubd = {
3577 .bDescLength = sizeof(musbotg_hubd),
3578 .bDescriptorType = UDESC_HUB,
3580 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3581 .bPwrOn2PwrGood = 50,
3582 .bHubContrCurrent = 0,
3583 .DeviceRemovable = {0}, /* port is removable */
3586 #define STRING_VENDOR \
3587 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3589 #define STRING_PRODUCT \
3590 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3592 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3593 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3596 musbotg_roothub_exec(struct usb_device *udev,
3597 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3599 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3607 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3610 ptr = (const void *)&sc->sc_hub_temp;
3614 value = UGETW(req->wValue);
3615 index = UGETW(req->wIndex);
3617 /* demultiplex the control request */
3619 switch (req->bmRequestType) {
3620 case UT_READ_DEVICE:
3621 switch (req->bRequest) {
3622 case UR_GET_DESCRIPTOR:
3623 goto tr_handle_get_descriptor;
3625 goto tr_handle_get_config;
3627 goto tr_handle_get_status;
3633 case UT_WRITE_DEVICE:
3634 switch (req->bRequest) {
3635 case UR_SET_ADDRESS:
3636 goto tr_handle_set_address;
3638 goto tr_handle_set_config;
3639 case UR_CLEAR_FEATURE:
3640 goto tr_valid; /* nop */
3641 case UR_SET_DESCRIPTOR:
3642 goto tr_valid; /* nop */
3643 case UR_SET_FEATURE:
3649 case UT_WRITE_ENDPOINT:
3650 switch (req->bRequest) {
3651 case UR_CLEAR_FEATURE:
3652 switch (UGETW(req->wValue)) {
3653 case UF_ENDPOINT_HALT:
3654 goto tr_handle_clear_halt;
3655 case UF_DEVICE_REMOTE_WAKEUP:
3656 goto tr_handle_clear_wakeup;
3661 case UR_SET_FEATURE:
3662 switch (UGETW(req->wValue)) {
3663 case UF_ENDPOINT_HALT:
3664 goto tr_handle_set_halt;
3665 case UF_DEVICE_REMOTE_WAKEUP:
3666 goto tr_handle_set_wakeup;
3671 case UR_SYNCH_FRAME:
3672 goto tr_valid; /* nop */
3678 case UT_READ_ENDPOINT:
3679 switch (req->bRequest) {
3681 goto tr_handle_get_ep_status;
3687 case UT_WRITE_INTERFACE:
3688 switch (req->bRequest) {
3689 case UR_SET_INTERFACE:
3690 goto tr_handle_set_interface;
3691 case UR_CLEAR_FEATURE:
3692 goto tr_valid; /* nop */
3693 case UR_SET_FEATURE:
3699 case UT_READ_INTERFACE:
3700 switch (req->bRequest) {
3701 case UR_GET_INTERFACE:
3702 goto tr_handle_get_interface;
3704 goto tr_handle_get_iface_status;
3710 case UT_WRITE_CLASS_INTERFACE:
3711 case UT_WRITE_VENDOR_INTERFACE:
3715 case UT_READ_CLASS_INTERFACE:
3716 case UT_READ_VENDOR_INTERFACE:
3720 case UT_WRITE_CLASS_DEVICE:
3721 switch (req->bRequest) {
3722 case UR_CLEAR_FEATURE:
3724 case UR_SET_DESCRIPTOR:
3725 case UR_SET_FEATURE:
3732 case UT_WRITE_CLASS_OTHER:
3733 switch (req->bRequest) {
3734 case UR_CLEAR_FEATURE:
3735 goto tr_handle_clear_port_feature;
3736 case UR_SET_FEATURE:
3737 goto tr_handle_set_port_feature;
3738 case UR_CLEAR_TT_BUFFER:
3748 case UT_READ_CLASS_OTHER:
3749 switch (req->bRequest) {
3750 case UR_GET_TT_STATE:
3751 goto tr_handle_get_tt_state;
3753 goto tr_handle_get_port_status;
3759 case UT_READ_CLASS_DEVICE:
3760 switch (req->bRequest) {
3761 case UR_GET_DESCRIPTOR:
3762 goto tr_handle_get_class_descriptor;
3764 goto tr_handle_get_class_status;
3775 tr_handle_get_descriptor:
3776 switch (value >> 8) {
3781 len = sizeof(musbotg_devd);
3782 ptr = (const void *)&musbotg_devd;
3784 case UDESC_DEVICE_QUALIFIER:
3788 len = sizeof(musbotg_odevd);
3789 ptr = (const void *)&musbotg_odevd;
3795 len = sizeof(musbotg_confd);
3796 ptr = (const void *)&musbotg_confd;
3799 switch (value & 0xff) {
3800 case 0: /* Language table */
3801 len = sizeof(usb_string_lang_en);
3802 ptr = (const void *)&usb_string_lang_en;
3805 case 1: /* Vendor */
3806 len = sizeof(musbotg_vendor);
3807 ptr = (const void *)&musbotg_vendor;
3810 case 2: /* Product */
3811 len = sizeof(musbotg_product);
3812 ptr = (const void *)&musbotg_product;
3823 tr_handle_get_config:
3825 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3828 tr_handle_get_status:
3830 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3833 tr_handle_set_address:
3834 if (value & 0xFF00) {
3837 sc->sc_rt_addr = value;
3840 tr_handle_set_config:
3844 sc->sc_conf = value;
3847 tr_handle_get_interface:
3849 sc->sc_hub_temp.wValue[0] = 0;
3852 tr_handle_get_tt_state:
3853 tr_handle_get_class_status:
3854 tr_handle_get_iface_status:
3855 tr_handle_get_ep_status:
3857 USETW(sc->sc_hub_temp.wValue, 0);
3861 tr_handle_set_interface:
3862 tr_handle_set_wakeup:
3863 tr_handle_clear_wakeup:
3864 tr_handle_clear_halt:
3867 tr_handle_clear_port_feature:
3871 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3874 case UHF_PORT_SUSPEND:
3875 if (sc->sc_mode == MUSB2_HOST_MODE)
3876 musbotg_wakeup_host(sc);
3878 musbotg_wakeup_peer(sc);
3881 case UHF_PORT_ENABLE:
3882 sc->sc_flags.port_enabled = 0;
3885 case UHF_C_PORT_ENABLE:
3886 sc->sc_flags.change_enabled = 0;
3889 case UHF_C_PORT_OVER_CURRENT:
3890 sc->sc_flags.change_over_current = 0;
3893 case UHF_C_PORT_RESET:
3894 sc->sc_flags.change_reset = 0;
3898 case UHF_PORT_INDICATOR:
3902 case UHF_PORT_POWER:
3903 sc->sc_flags.port_powered = 0;
3904 musbotg_pull_down(sc);
3905 musbotg_clocks_off(sc);
3907 case UHF_C_PORT_CONNECTION:
3908 sc->sc_flags.change_connect = 0;
3910 case UHF_C_PORT_SUSPEND:
3911 sc->sc_flags.change_suspend = 0;
3914 err = USB_ERR_IOERROR;
3919 tr_handle_set_port_feature:
3923 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3926 case UHF_PORT_ENABLE:
3927 sc->sc_flags.port_enabled = 1;
3929 case UHF_PORT_SUSPEND:
3930 if (sc->sc_mode == MUSB2_HOST_MODE)
3931 musbotg_suspend_host(sc);
3934 case UHF_PORT_RESET:
3935 if (sc->sc_mode == MUSB2_HOST_MODE) {
3936 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3937 reg |= MUSB2_MASK_RESET;
3938 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3940 /* Wait for 20 msec */
3941 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3943 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3944 reg &= ~MUSB2_MASK_RESET;
3945 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3947 /* determine line speed */
3948 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3949 if (reg & MUSB2_MASK_HSMODE)
3950 sc->sc_flags.status_high_speed = 1;
3952 sc->sc_flags.status_high_speed = 0;
3954 sc->sc_flags.change_reset = 1;
3956 err = USB_ERR_IOERROR;
3960 case UHF_PORT_INDICATOR:
3963 case UHF_PORT_POWER:
3964 sc->sc_flags.port_powered = 1;
3967 err = USB_ERR_IOERROR;
3972 tr_handle_get_port_status:
3974 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3979 if (sc->sc_flags.status_vbus) {
3980 musbotg_clocks_on(sc);
3981 musbotg_pull_up(sc);
3983 musbotg_pull_down(sc);
3984 musbotg_clocks_off(sc);
3987 /* Select Device Side Mode */
3988 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3989 value = UPS_PORT_MODE_DEVICE;
3993 if (sc->sc_flags.status_high_speed) {
3994 value |= UPS_HIGH_SPEED;
3996 if (sc->sc_flags.port_powered) {
3997 value |= UPS_PORT_POWER;
3999 if (sc->sc_flags.port_enabled) {
4000 value |= UPS_PORT_ENABLED;
4003 if (sc->sc_flags.port_over_current)
4004 value |= UPS_OVERCURRENT_INDICATOR;
4006 if (sc->sc_flags.status_vbus &&
4007 sc->sc_flags.status_bus_reset) {
4008 value |= UPS_CURRENT_CONNECT_STATUS;
4010 if (sc->sc_flags.status_suspend) {
4011 value |= UPS_SUSPEND;
4013 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4017 if (sc->sc_flags.change_connect) {
4018 value |= UPS_C_CONNECT_STATUS;
4020 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4021 if (sc->sc_flags.status_vbus &&
4022 sc->sc_flags.status_bus_reset) {
4023 /* reset EP0 state */
4024 sc->sc_ep0_busy = 0;
4029 if (sc->sc_flags.change_suspend)
4030 value |= UPS_C_SUSPEND;
4031 if (sc->sc_flags.change_reset)
4032 value |= UPS_C_PORT_RESET;
4033 if (sc->sc_flags.change_over_current)
4034 value |= UPS_C_OVERCURRENT_INDICATOR;
4036 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4037 len = sizeof(sc->sc_hub_temp.ps);
4040 tr_handle_get_class_descriptor:
4044 ptr = (const void *)&musbotg_hubd;
4045 len = sizeof(musbotg_hubd);
4049 err = USB_ERR_STALLED;
4058 musbotg_xfer_setup(struct usb_setup_params *parm)
4060 struct musbotg_softc *sc;
4061 struct usb_xfer *xfer;
4067 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4068 xfer = parm->curr_xfer;
4071 * NOTE: This driver does not use any of the parameters that
4072 * are computed from the following values. Just set some
4073 * reasonable dummies:
4075 parm->hc_max_packet_size = 0x400;
4076 parm->hc_max_frame_size = 0xc00;
4078 if ((parm->methods == &musbotg_device_isoc_methods) ||
4079 (parm->methods == &musbotg_device_intr_methods))
4080 parm->hc_max_packet_count = 3;
4082 parm->hc_max_packet_count = 1;
4084 usbd_transfer_setup_sub(parm);
4087 * compute maximum number of TDs
4089 if (parm->methods == &musbotg_device_ctrl_methods) {
4091 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4093 } else if (parm->methods == &musbotg_device_bulk_methods) {
4095 ntd = xfer->nframes + 1 /* SYNC */ ;
4097 } else if (parm->methods == &musbotg_device_intr_methods) {
4099 ntd = xfer->nframes + 1 /* SYNC */ ;
4101 } else if (parm->methods == &musbotg_device_isoc_methods) {
4103 ntd = xfer->nframes + 1 /* SYNC */ ;
4111 * check if "usbd_transfer_setup_sub" set an error
4117 * allocate transfer descriptors
4121 ep_no = xfer->endpointno & UE_ADDR;
4124 * Check for a valid endpoint profile in USB device mode:
4126 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4127 const struct usb_hw_ep_profile *pf;
4129 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4132 /* should not happen */
4133 parm->err = USB_ERR_INVAL;
4139 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4141 for (n = 0; n != ntd; n++) {
4143 struct musbotg_td *td;
4147 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4150 td->max_frame_size = xfer->max_frame_size;
4151 td->reg_max_packet = xfer->max_packet_size |
4152 ((xfer->max_packet_count - 1) << 11);
4154 td->obj_next = last_obj;
4158 parm->size[0] += sizeof(*td);
4161 xfer->td_start[0] = last_obj;
4165 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4171 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4173 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4175 if (sc->sc_mode == MUSB2_HOST_MODE)
4176 *pus = 2000; /* microseconds */
4182 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4183 struct usb_endpoint *ep)
4185 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4187 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4189 edesc->bEndpointAddress, udev->flags.usb_mode,
4192 if (udev->device_index != sc->sc_rt_addr) {
4193 switch (edesc->bmAttributes & UE_XFERTYPE) {
4195 ep->methods = &musbotg_device_ctrl_methods;
4198 ep->methods = &musbotg_device_intr_methods;
4200 case UE_ISOCHRONOUS:
4201 ep->methods = &musbotg_device_isoc_methods;
4204 ep->methods = &musbotg_device_bulk_methods;
4214 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4216 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4219 case USB_HW_POWER_SUSPEND:
4220 musbotg_suspend(sc);
4222 case USB_HW_POWER_SHUTDOWN:
4225 case USB_HW_POWER_RESUME:
4233 struct usb_bus_methods musbotg_bus_methods =
4235 .endpoint_init = &musbotg_ep_init,
4236 .get_dma_delay = &musbotg_get_dma_delay,
4237 .xfer_setup = &musbotg_xfer_setup,
4238 .xfer_unsetup = &musbotg_xfer_unsetup,
4239 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4240 .xfer_stall = &musbotg_xfer_stall,
4241 .set_stall = &musbotg_set_stall,
4242 .clear_stall = &musbotg_clear_stall,
4243 .roothub_exec = &musbotg_roothub_exec,
4244 .xfer_poll = &musbotg_do_poll,
4245 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,