3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
36 * NOTE: The current implementation only supports Device Side Mode!
39 #include <sys/stdint.h>
40 #include <sys/stddef.h>
41 #include <sys/param.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
49 #include <sys/mutex.h>
50 #include <sys/condvar.h>
51 #include <sys/sysctl.h>
53 #include <sys/unistd.h>
54 #include <sys/callout.h>
55 #include <sys/malloc.h>
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
61 #define USB_DEBUG_VAR musbotgdebug
63 #include <dev/usb/usb_core.h>
64 #include <dev/usb/usb_debug.h>
65 #include <dev/usb/usb_busdma.h>
66 #include <dev/usb/usb_process.h>
67 #include <dev/usb/usb_transfer.h>
68 #include <dev/usb/usb_device.h>
69 #include <dev/usb/usb_hub.h>
70 #include <dev/usb/usb_util.h>
72 #include <dev/usb/usb_controller.h>
73 #include <dev/usb/usb_bus.h>
74 #include <dev/usb/controller/musb_otg.h>
76 #define MUSBOTG_INTR_ENDPT 1
78 #define MUSBOTG_BUS2SC(bus) \
79 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
80 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
82 #define MUSBOTG_PC2SC(pc) \
83 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
86 static int musbotgdebug = 0;
88 SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
89 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
90 &musbotgdebug, 0, "Debug level");
95 struct usb_bus_methods musbotg_bus_methods;
96 struct usb_pipe_methods musbotg_device_bulk_methods;
97 struct usb_pipe_methods musbotg_device_ctrl_methods;
98 struct usb_pipe_methods musbotg_device_intr_methods;
99 struct usb_pipe_methods musbotg_device_isoc_methods;
101 static musbotg_cmd_t musbotg_setup_rx;
102 static musbotg_cmd_t musbotg_setup_data_rx;
103 static musbotg_cmd_t musbotg_setup_data_tx;
104 static musbotg_cmd_t musbotg_setup_status;
105 static musbotg_cmd_t musbotg_data_rx;
106 static musbotg_cmd_t musbotg_data_tx;
107 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
108 static void musbotg_do_poll(struct usb_bus *);
109 static void musbotg_standard_done(struct usb_xfer *);
110 static void musbotg_interrupt_poll(struct musbotg_softc *);
111 static void musbotg_root_intr(struct musbotg_softc *);
114 * Here is a configuration that the chip supports.
116 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
119 .max_in_frame_size = 64,/* fixed */
120 .max_out_frame_size = 64, /* fixed */
122 .support_control = 1,
127 musbotg_get_hw_ep_profile(struct usb_device *udev,
128 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
130 struct musbotg_softc *sc;
132 sc = MUSBOTG_BUS2SC(udev->bus);
135 /* control endpoint */
136 *ppf = musbotg_ep_profile;
137 } else if (ep_addr <= sc->sc_ep_max) {
138 /* other endpoints */
139 *ppf = sc->sc_hw_ep_profile + ep_addr;
146 musbotg_clocks_on(struct musbotg_softc *sc)
148 if (sc->sc_flags.clocks_off &&
149 sc->sc_flags.port_powered) {
153 if (sc->sc_clocks_on) {
154 (sc->sc_clocks_on) (sc->sc_clocks_arg);
156 sc->sc_flags.clocks_off = 0;
158 /* XXX enable Transceiver */
163 musbotg_clocks_off(struct musbotg_softc *sc)
165 if (!sc->sc_flags.clocks_off) {
169 /* XXX disable Transceiver */
171 if (sc->sc_clocks_off) {
172 (sc->sc_clocks_off) (sc->sc_clocks_arg);
174 sc->sc_flags.clocks_off = 1;
179 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
183 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
185 temp |= MUSB2_MASK_SOFTC;
187 temp &= ~MUSB2_MASK_SOFTC;
189 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
193 musbotg_pull_up(struct musbotg_softc *sc)
195 /* pullup D+, if possible */
197 if (!sc->sc_flags.d_pulled_up &&
198 sc->sc_flags.port_powered) {
199 sc->sc_flags.d_pulled_up = 1;
200 musbotg_pull_common(sc, 1);
205 musbotg_pull_down(struct musbotg_softc *sc)
207 /* pulldown D+, if possible */
209 if (sc->sc_flags.d_pulled_up) {
210 sc->sc_flags.d_pulled_up = 0;
211 musbotg_pull_common(sc, 0);
216 musbotg_wakeup_peer(struct musbotg_softc *sc)
220 if (!(sc->sc_flags.status_suspend)) {
224 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
225 temp |= MUSB2_MASK_RESUME;
226 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
228 /* wait 8 milliseconds */
229 /* Wait for reset to complete. */
230 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
232 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
233 temp &= ~MUSB2_MASK_RESUME;
234 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
238 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
240 DPRINTFN(4, "addr=%d\n", addr);
242 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
246 musbotg_setup_rx(struct musbotg_td *td)
248 struct musbotg_softc *sc;
249 struct usb_device_request req;
253 /* get pointer to softc */
254 sc = MUSBOTG_PC2SC(td->pc);
256 /* select endpoint 0 */
257 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
259 /* read out FIFO status */
260 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
262 DPRINTFN(4, "csr=0x%02x\n", csr);
265 * NOTE: If DATAEND is set we should not call the
266 * callback, hence the status stage is not complete.
268 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
269 /* do not stall at this point */
271 /* wait for interrupt */
274 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
275 /* clear SENTSTALL */
276 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
277 /* get latest status */
278 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
279 /* update EP0 state */
282 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
284 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
285 MUSB2_MASK_CSR0L_SETUPEND_CLR);
286 /* get latest status */
287 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
288 /* update EP0 state */
291 if (sc->sc_ep0_busy) {
294 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
297 /* clear did stall flag */
299 /* get the packet byte count */
300 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
302 /* verify data length */
303 if (count != td->remainder) {
304 DPRINTFN(0, "Invalid SETUP packet "
305 "length, %d bytes\n", count);
306 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
307 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
310 if (count != sizeof(req)) {
311 DPRINTFN(0, "Unsupported SETUP packet "
312 "length, %d bytes\n", count);
313 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
314 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
318 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
319 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
321 /* copy data into real buffer */
322 usbd_copy_in(td->pc, 0, &req, sizeof(req));
324 td->offset = sizeof(req);
327 /* set pending command */
328 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
330 /* we need set stall or dataend after this */
333 /* sneak peek the set address */
334 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
335 (req.bRequest == UR_SET_ADDRESS)) {
336 sc->sc_dv_addr = req.wValue[0] & 0x7F;
338 sc->sc_dv_addr = 0xFF;
340 return (0); /* complete */
343 /* abort any ongoing transfer */
344 if (!td->did_stall) {
345 DPRINTFN(4, "stalling\n");
346 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
347 MUSB2_MASK_CSR0L_SENDSTALL);
350 return (1); /* not complete */
353 /* Control endpoint only data handling functions (RX/TX/SYNC) */
356 musbotg_setup_data_rx(struct musbotg_td *td)
358 struct usb_page_search buf_res;
359 struct musbotg_softc *sc;
364 /* get pointer to softc */
365 sc = MUSBOTG_PC2SC(td->pc);
367 /* select endpoint 0 */
368 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
370 /* check if a command is pending */
371 if (sc->sc_ep0_cmd) {
372 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
375 /* read out FIFO status */
376 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
378 DPRINTFN(4, "csr=0x%02x\n", csr);
382 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
383 MUSB2_MASK_CSR0L_SENTSTALL)) {
384 if (td->remainder == 0) {
386 * We are actually complete and have
387 * received the next SETUP
389 DPRINTFN(4, "faking complete\n");
390 return (0); /* complete */
393 * USB Host Aborted the transfer.
396 return (0); /* complete */
398 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
399 return (1); /* not complete */
401 /* get the packet byte count */
402 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
404 /* verify the packet byte count */
405 if (count != td->max_frame_size) {
406 if (count < td->max_frame_size) {
407 /* we have a short packet */
411 /* invalid USB packet */
413 return (0); /* we are complete */
416 /* verify the packet byte count */
417 if (count > td->remainder) {
418 /* invalid USB packet */
420 return (0); /* we are complete */
425 usbd_get_page(td->pc, td->offset, &buf_res);
427 /* get correct length */
428 if (buf_res.length > count) {
429 buf_res.length = count;
431 /* check for unaligned memory address */
432 if (USB_P2U(buf_res.buffer) & 3) {
437 /* receive data 4 bytes at a time */
438 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
439 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
444 /* receive data 1 byte at a time */
445 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
447 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
449 usbd_copy_in(td->pc, td->offset,
450 sc->sc_bounce_buf, count);
452 /* update offset and remainder */
454 td->remainder -= count;
457 /* check if we can optimise */
458 if (buf_res.length >= 4) {
460 /* receive data 4 bytes at a time */
461 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
462 MUSB2_REG_EPFIFO(0), buf_res.buffer,
465 temp = buf_res.length & ~3;
467 /* update counters */
470 td->remainder -= temp;
474 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
475 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
477 /* update counters */
478 count -= buf_res.length;
479 td->offset += buf_res.length;
480 td->remainder -= buf_res.length;
483 /* check if we are complete */
484 if ((td->remainder == 0) || got_short) {
486 /* we are complete */
487 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
490 /* else need to receive a zero length packet */
492 /* write command - need more data */
493 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
494 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
495 return (1); /* not complete */
499 musbotg_setup_data_tx(struct musbotg_td *td)
501 struct usb_page_search buf_res;
502 struct musbotg_softc *sc;
506 /* get pointer to softc */
507 sc = MUSBOTG_PC2SC(td->pc);
509 /* select endpoint 0 */
510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
512 /* check if a command is pending */
513 if (sc->sc_ep0_cmd) {
514 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
517 /* read out FIFO status */
518 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
520 DPRINTFN(4, "csr=0x%02x\n", csr);
522 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
523 MUSB2_MASK_CSR0L_SENTSTALL)) {
525 * The current transfer was aborted
529 return (0); /* complete */
531 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
532 return (1); /* not complete */
534 count = td->max_frame_size;
535 if (td->remainder < count) {
536 /* we have a short packet */
538 count = td->remainder;
543 usbd_get_page(td->pc, td->offset, &buf_res);
545 /* get correct length */
546 if (buf_res.length > count) {
547 buf_res.length = count;
549 /* check for unaligned memory address */
550 if (USB_P2U(buf_res.buffer) & 3) {
552 usbd_copy_out(td->pc, td->offset,
553 sc->sc_bounce_buf, count);
558 /* transmit data 4 bytes at a time */
559 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
560 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
565 /* receive data 1 byte at a time */
566 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
568 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
570 /* update offset and remainder */
572 td->remainder -= count;
575 /* check if we can optimise */
576 if (buf_res.length >= 4) {
578 /* transmit data 4 bytes at a time */
579 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
580 MUSB2_REG_EPFIFO(0), buf_res.buffer,
583 temp = buf_res.length & ~3;
585 /* update counters */
588 td->remainder -= temp;
592 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
593 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
595 /* update counters */
596 count -= buf_res.length;
597 td->offset += buf_res.length;
598 td->remainder -= buf_res.length;
601 /* check remainder */
602 if (td->remainder == 0) {
604 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
605 return (0); /* complete */
607 /* else we need to transmit a short packet */
610 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
611 MUSB2_MASK_CSR0L_TXPKTRDY);
613 return (1); /* not complete */
617 musbotg_setup_status(struct musbotg_td *td)
619 struct musbotg_softc *sc;
622 /* get pointer to softc */
623 sc = MUSBOTG_PC2SC(td->pc);
625 /* select endpoint 0 */
626 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
628 if (sc->sc_ep0_busy) {
630 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
631 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
634 /* read out FIFO status */
635 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
637 DPRINTFN(4, "csr=0x%02x\n", csr);
639 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
640 /* wait for interrupt */
641 return (1); /* not complete */
643 if (sc->sc_dv_addr != 0xFF) {
644 /* write function address */
645 musbotg_set_address(sc, sc->sc_dv_addr);
647 return (0); /* complete */
651 musbotg_data_rx(struct musbotg_td *td)
653 struct usb_page_search buf_res;
654 struct musbotg_softc *sc;
660 to = 8; /* don't loop forever! */
663 /* get pointer to softc */
664 sc = MUSBOTG_PC2SC(td->pc);
666 /* select endpoint */
667 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no);
670 /* read out FIFO status */
671 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
673 DPRINTFN(4, "csr=0x%02x\n", csr);
676 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
677 /* make sure we don't clear "RXPKTRDY" */
678 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
679 MUSB2_MASK_CSRL_RXPKTRDY);
682 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
683 return (1); /* not complete */
685 /* get the packet byte count */
686 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
688 DPRINTFN(4, "count=0x%04x\n", count);
691 * Check for short or invalid packet:
693 if (count != td->max_frame_size) {
694 if (count < td->max_frame_size) {
695 /* we have a short packet */
699 /* invalid USB packet */
701 return (0); /* we are complete */
704 /* verify the packet byte count */
705 if (count > td->remainder) {
706 /* invalid USB packet */
708 return (0); /* we are complete */
713 usbd_get_page(td->pc, td->offset, &buf_res);
715 /* get correct length */
716 if (buf_res.length > count) {
717 buf_res.length = count;
719 /* check for unaligned memory address */
720 if (USB_P2U(buf_res.buffer) & 3) {
725 /* receive data 4 bytes at a time */
726 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
727 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf,
732 /* receive data 1 byte at a time */
733 bus_space_read_multi_1(sc->sc_io_tag,
734 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no),
735 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
737 usbd_copy_in(td->pc, td->offset,
738 sc->sc_bounce_buf, count);
740 /* update offset and remainder */
742 td->remainder -= count;
745 /* check if we can optimise */
746 if (buf_res.length >= 4) {
748 /* receive data 4 bytes at a time */
749 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
750 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
753 temp = buf_res.length & ~3;
755 /* update counters */
758 td->remainder -= temp;
762 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
763 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
766 /* update counters */
767 count -= buf_res.length;
768 td->offset += buf_res.length;
769 td->remainder -= buf_res.length;
772 /* clear status bits */
773 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
775 /* check if we are complete */
776 if ((td->remainder == 0) || got_short) {
778 /* we are complete */
781 /* else need to receive a zero length packet */
786 return (1); /* not complete */
790 musbotg_data_tx(struct musbotg_td *td)
792 struct usb_page_search buf_res;
793 struct musbotg_softc *sc;
798 to = 8; /* don't loop forever! */
800 /* get pointer to softc */
801 sc = MUSBOTG_PC2SC(td->pc);
803 /* select endpoint */
804 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no);
808 /* read out FIFO status */
809 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
811 DPRINTFN(4, "csr=0x%02x\n", csr);
813 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
814 MUSB2_MASK_CSRL_TXUNDERRUN)) {
815 /* clear status bits */
816 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
818 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
819 return (1); /* not complete */
821 /* check for short packet */
822 count = td->max_frame_size;
823 if (td->remainder < count) {
824 /* we have a short packet */
826 count = td->remainder;
831 usbd_get_page(td->pc, td->offset, &buf_res);
833 /* get correct length */
834 if (buf_res.length > count) {
835 buf_res.length = count;
837 /* check for unaligned memory address */
838 if (USB_P2U(buf_res.buffer) & 3) {
840 usbd_copy_out(td->pc, td->offset,
841 sc->sc_bounce_buf, count);
846 /* transmit data 4 bytes at a time */
847 bus_space_write_multi_4(sc->sc_io_tag,
848 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no),
849 sc->sc_bounce_buf, temp / 4);
853 /* receive data 1 byte at a time */
854 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
855 MUSB2_REG_EPFIFO(td->ep_no),
856 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
858 /* update offset and remainder */
860 td->remainder -= count;
863 /* check if we can optimise */
864 if (buf_res.length >= 4) {
866 /* transmit data 4 bytes at a time */
867 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
868 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
871 temp = buf_res.length & ~3;
873 /* update counters */
876 td->remainder -= temp;
880 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
881 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
884 /* update counters */
885 count -= buf_res.length;
886 td->offset += buf_res.length;
887 td->remainder -= buf_res.length;
891 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
892 MUSB2_MASK_CSRL_TXPKTRDY);
894 /* check remainder */
895 if (td->remainder == 0) {
897 return (0); /* complete */
899 /* else we need to transmit a short packet */
904 return (1); /* not complete */
908 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
910 struct musbotg_softc *sc;
911 struct musbotg_td *td;
915 td = xfer->td_transfer_cache;
917 if ((td->func) (td)) {
918 /* operation in progress */
921 if (((void *)td) == xfer->td_transfer_last) {
926 } else if (td->remainder > 0) {
928 * We had a short transfer. If there is no alternate
929 * next, stop processing !
936 * Fetch the next transfer descriptor and transfer
937 * some flags to the next transfer descriptor
940 xfer->td_transfer_cache = td;
942 return (1); /* not complete */
945 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
947 /* compute all actual lengths */
949 musbotg_standard_done(xfer);
951 return (0); /* complete */
955 musbotg_interrupt_poll(struct musbotg_softc *sc)
957 struct usb_xfer *xfer;
960 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
961 if (!musbotg_xfer_do_fifo(xfer)) {
962 /* queue has been modified */
969 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
971 DPRINTFN(4, "vbus = %u\n", is_on);
973 USB_BUS_LOCK(&sc->sc_bus);
975 if (!sc->sc_flags.status_vbus) {
976 sc->sc_flags.status_vbus = 1;
978 /* complete root HUB interrupt endpoint */
979 musbotg_root_intr(sc);
982 if (sc->sc_flags.status_vbus) {
983 sc->sc_flags.status_vbus = 0;
984 sc->sc_flags.status_bus_reset = 0;
985 sc->sc_flags.status_suspend = 0;
986 sc->sc_flags.change_suspend = 0;
987 sc->sc_flags.change_connect = 1;
989 /* complete root HUB interrupt endpoint */
990 musbotg_root_intr(sc);
994 USB_BUS_UNLOCK(&sc->sc_bus);
998 musbotg_interrupt(struct musbotg_softc *sc)
1006 USB_BUS_LOCK(&sc->sc_bus);
1010 /* read all interrupt registers */
1011 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
1013 /* read all FIFO interrupts */
1014 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
1015 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
1017 /* check for any bus state change interrupts */
1019 if (usb_status & (MUSB2_MASK_IRESET |
1020 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) {
1022 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
1024 if (usb_status & MUSB2_MASK_IRESET) {
1026 /* set correct state */
1027 sc->sc_flags.status_bus_reset = 1;
1028 sc->sc_flags.status_suspend = 0;
1029 sc->sc_flags.change_suspend = 0;
1030 sc->sc_flags.change_connect = 1;
1032 /* determine line speed */
1033 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
1034 if (temp & MUSB2_MASK_HSMODE)
1035 sc->sc_flags.status_high_speed = 1;
1037 sc->sc_flags.status_high_speed = 0;
1040 * After reset all interrupts are on and we need to
1043 temp = MUSB2_MASK_IRESET;
1044 /* disable resume interrupt */
1045 temp &= ~MUSB2_MASK_IRESUME;
1046 /* enable suspend interrupt */
1047 temp |= MUSB2_MASK_ISUSP;
1048 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1049 /* disable TX and RX interrupts */
1050 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1051 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1054 * If RXRSM and RXSUSP is set at the same time we interpret
1055 * that like RESUME. Resume is set when there is at least 3
1056 * milliseconds of inactivity on the USB BUS.
1058 if (usb_status & MUSB2_MASK_IRESUME) {
1059 if (sc->sc_flags.status_suspend) {
1060 sc->sc_flags.status_suspend = 0;
1061 sc->sc_flags.change_suspend = 1;
1063 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
1064 /* disable resume interrupt */
1065 temp &= ~MUSB2_MASK_IRESUME;
1066 /* enable suspend interrupt */
1067 temp |= MUSB2_MASK_ISUSP;
1068 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1070 } else if (usb_status & MUSB2_MASK_ISUSP) {
1071 if (!sc->sc_flags.status_suspend) {
1072 sc->sc_flags.status_suspend = 1;
1073 sc->sc_flags.change_suspend = 1;
1075 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
1076 /* disable suspend interrupt */
1077 temp &= ~MUSB2_MASK_ISUSP;
1078 /* enable resume interrupt */
1079 temp |= MUSB2_MASK_IRESUME;
1080 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1083 /* complete root HUB interrupt endpoint */
1084 musbotg_root_intr(sc);
1086 /* check for any endpoint interrupts */
1088 if (rx_status || tx_status) {
1089 DPRINTFN(4, "real endpoint interrupt "
1090 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
1092 /* poll one time regardless of FIFO status */
1094 musbotg_interrupt_poll(sc);
1099 USB_BUS_UNLOCK(&sc->sc_bus);
1103 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
1105 struct musbotg_td *td;
1107 /* get current Transfer Descriptor */
1111 /* prepare for next TD */
1112 temp->td_next = td->obj_next;
1114 /* fill out the Transfer Descriptor */
1115 td->func = temp->func;
1117 td->offset = temp->offset;
1118 td->remainder = temp->len;
1120 td->did_stall = temp->did_stall;
1121 td->short_pkt = temp->short_pkt;
1122 td->alt_next = temp->setup_alt_next;
1126 musbotg_setup_standard_chain(struct usb_xfer *xfer)
1128 struct musbotg_std_temp temp;
1129 struct musbotg_softc *sc;
1130 struct musbotg_td *td;
1134 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1135 xfer->address, UE_GET_ADDR(xfer->endpointno),
1136 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1138 temp.max_frame_size = xfer->max_frame_size;
1140 td = xfer->td_start[0];
1141 xfer->td_transfer_first = td;
1142 xfer->td_transfer_cache = td;
1148 temp.td_next = xfer->td_start[0];
1150 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1151 temp.did_stall = !xfer->flags_int.control_stall;
1153 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
1154 ep_no = (xfer->endpointno & UE_ADDR);
1156 /* check if we should prepend a setup message */
1158 if (xfer->flags_int.control_xfr) {
1159 if (xfer->flags_int.control_hdr) {
1161 temp.func = &musbotg_setup_rx;
1162 temp.len = xfer->frlengths[0];
1163 temp.pc = xfer->frbuffers + 0;
1164 temp.short_pkt = temp.len ? 1 : 0;
1166 musbotg_setup_standard_chain_sub(&temp);
1173 if (x != xfer->nframes) {
1174 if (xfer->endpointno & UE_DIR_IN) {
1175 if (xfer->flags_int.control_xfr)
1176 temp.func = &musbotg_setup_data_tx;
1178 temp.func = &musbotg_data_tx;
1180 if (xfer->flags_int.control_xfr)
1181 temp.func = &musbotg_setup_data_rx;
1183 temp.func = &musbotg_data_rx;
1186 /* setup "pc" pointer */
1187 temp.pc = xfer->frbuffers + x;
1189 while (x != xfer->nframes) {
1191 /* DATA0 / DATA1 message */
1193 temp.len = xfer->frlengths[x];
1197 if (x == xfer->nframes) {
1198 if (xfer->flags_int.control_xfr) {
1199 if (xfer->flags_int.control_act) {
1200 temp.setup_alt_next = 0;
1203 temp.setup_alt_next = 0;
1206 if (temp.len == 0) {
1208 /* make sure that we send an USB packet */
1214 /* regular data transfer */
1216 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1219 musbotg_setup_standard_chain_sub(&temp);
1221 if (xfer->flags_int.isochronous_xfr) {
1222 temp.offset += temp.len;
1224 /* get next Page Cache pointer */
1225 temp.pc = xfer->frbuffers + x;
1229 /* check for control transfer */
1230 if (xfer->flags_int.control_xfr) {
1232 /* always setup a valid "pc" pointer for status and sync */
1233 temp.pc = xfer->frbuffers + 0;
1236 temp.setup_alt_next = 0;
1238 /* check if we should append a status stage */
1239 if (!xfer->flags_int.control_act) {
1241 * Send a DATA1 message and invert the current
1242 * endpoint direction.
1244 temp.func = &musbotg_setup_status;
1245 musbotg_setup_standard_chain_sub(&temp);
1248 /* must have at least one frame! */
1250 xfer->td_transfer_last = td;
1254 musbotg_timeout(void *arg)
1256 struct usb_xfer *xfer = arg;
1258 DPRINTFN(1, "xfer=%p\n", xfer);
1260 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1262 /* transfer is transferred */
1263 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
1267 musbotg_ep_int_set(struct usb_xfer *xfer, uint8_t on)
1269 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
1271 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1274 * Only enable the endpoint interrupt when we are
1275 * actually waiting for data, hence we are dealing
1276 * with level triggered interrupts !
1279 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
1281 temp |= MUSB2_MASK_EPINT(0);
1283 temp &= ~MUSB2_MASK_EPINT(0);
1285 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
1287 if (USB_GET_DATA_ISREAD(xfer)) {
1288 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
1290 temp |= MUSB2_MASK_EPINT(ep_no);
1292 temp &= ~MUSB2_MASK_EPINT(ep_no);
1293 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
1296 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
1298 temp |= MUSB2_MASK_EPINT(ep_no);
1300 temp &= ~MUSB2_MASK_EPINT(ep_no);
1301 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
1307 musbotg_start_standard_chain(struct usb_xfer *xfer)
1312 if (musbotg_xfer_do_fifo(xfer)) {
1314 musbotg_ep_int_set(xfer, 1);
1316 DPRINTFN(14, "enabled interrupts on endpoint\n");
1318 /* put transfer on interrupt queue */
1319 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1321 /* start timeout, if any */
1322 if (xfer->timeout != 0) {
1323 usbd_transfer_timeout_ms(xfer,
1324 &musbotg_timeout, xfer->timeout);
1330 musbotg_root_intr(struct musbotg_softc *sc)
1334 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1337 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
1339 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1340 sizeof(sc->sc_hub_idata));
1344 musbotg_standard_done_sub(struct usb_xfer *xfer)
1346 struct musbotg_td *td;
1352 td = xfer->td_transfer_cache;
1355 len = td->remainder;
1357 if (xfer->aframes != xfer->nframes) {
1359 * Verify the length and subtract
1360 * the remainder from "frlengths[]":
1362 if (len > xfer->frlengths[xfer->aframes]) {
1365 xfer->frlengths[xfer->aframes] -= len;
1368 /* Check for transfer error */
1370 /* the transfer is finished */
1375 /* Check for short transfer */
1377 if (xfer->flags_int.short_frames_ok) {
1378 /* follow alt next */
1385 /* the transfer is finished */
1393 /* this USB frame is complete */
1399 /* update transfer cache */
1401 xfer->td_transfer_cache = td;
1404 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1408 musbotg_standard_done(struct usb_xfer *xfer)
1410 usb_error_t err = 0;
1412 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
1413 xfer, xfer->endpoint);
1417 xfer->td_transfer_cache = xfer->td_transfer_first;
1419 if (xfer->flags_int.control_xfr) {
1421 if (xfer->flags_int.control_hdr) {
1423 err = musbotg_standard_done_sub(xfer);
1427 if (xfer->td_transfer_cache == NULL) {
1431 while (xfer->aframes != xfer->nframes) {
1433 err = musbotg_standard_done_sub(xfer);
1436 if (xfer->td_transfer_cache == NULL) {
1441 if (xfer->flags_int.control_xfr &&
1442 !xfer->flags_int.control_act) {
1444 err = musbotg_standard_done_sub(xfer);
1447 musbotg_device_done(xfer, err);
1450 /*------------------------------------------------------------------------*
1451 * musbotg_device_done
1453 * NOTE: this function can be called more than one time on the
1454 * same USB transfer!
1455 *------------------------------------------------------------------------*/
1457 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
1459 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1461 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1462 xfer, xfer->endpoint, error);
1464 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1466 musbotg_ep_int_set(xfer, 0);
1468 DPRINTFN(14, "disabled interrupts on endpoint\n");
1470 /* dequeue transfer and start next transfer */
1471 usbd_transfer_done(xfer, error);
1475 musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1476 struct usb_endpoint *ep, uint8_t *did_stall)
1478 struct musbotg_softc *sc;
1481 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1483 DPRINTFN(4, "endpoint=%p\n", ep);
1486 /* cancel any ongoing transfers */
1487 musbotg_device_done(xfer, USB_ERR_STALLED);
1489 /* set FORCESTALL */
1490 sc = MUSBOTG_BUS2SC(udev->bus);
1492 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1494 /* select endpoint */
1495 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
1497 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
1498 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1499 MUSB2_MASK_CSRL_TXSENDSTALL);
1501 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1502 MUSB2_MASK_CSRL_RXSENDSTALL);
1507 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
1508 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
1514 if (ep_type == UE_CONTROL) {
1515 /* clearing stall is not needed */
1518 /* select endpoint */
1519 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
1521 /* compute max frame size */
1522 mps = wMaxPacket & 0x7FF;
1523 switch ((wMaxPacket >> 11) & 3) {
1534 if (ep_dir == UE_DIR_IN) {
1538 /* Configure endpoint */
1541 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1543 MUSB2_MASK_CSRH_TXMODE | temp);
1545 case UE_ISOCHRONOUS:
1546 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1548 MUSB2_MASK_CSRH_TXMODE |
1549 MUSB2_MASK_CSRH_TXISO | temp);
1552 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1553 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1554 MUSB2_MASK_CSRH_TXMODE | temp);
1560 /* Need to flush twice in case of double bufring */
1561 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1562 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1563 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1564 MUSB2_MASK_CSRL_TXFFLUSH);
1565 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1566 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1567 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1568 MUSB2_MASK_CSRL_TXFFLUSH);
1569 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1572 /* reset data toggle */
1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1574 MUSB2_MASK_CSRL_TXDT_CLR);
1575 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1578 /* set double/single buffering */
1579 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
1580 if (mps <= (sc->sc_hw_ep_profile[ep_no].
1581 max_in_frame_size / 2)) {
1583 temp &= ~(1 << ep_no);
1586 temp |= (1 << ep_no);
1588 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
1590 /* clear sent stall */
1591 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
1592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1593 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1599 /* Configure endpoint */
1602 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1603 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
1604 MUSB2_MASK_CSRH_RXNYET | temp);
1606 case UE_ISOCHRONOUS:
1607 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
1609 MUSB2_MASK_CSRH_RXNYET |
1610 MUSB2_MASK_CSRH_RXISO | temp);
1613 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
1620 /* Need to flush twice in case of double bufring */
1621 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1622 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
1623 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1624 MUSB2_MASK_CSRL_RXFFLUSH);
1625 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1626 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
1627 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1628 MUSB2_MASK_CSRL_RXFFLUSH);
1629 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1632 /* reset data toggle */
1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1634 MUSB2_MASK_CSRL_RXDT_CLR);
1635 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1636 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1638 /* set double/single buffering */
1639 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
1640 if (mps <= (sc->sc_hw_ep_profile[ep_no].
1641 max_out_frame_size / 2)) {
1643 temp &= ~(1 << ep_no);
1646 temp |= (1 << ep_no);
1648 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
1650 /* clear sent stall */
1651 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
1652 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1658 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1660 struct musbotg_softc *sc;
1661 struct usb_endpoint_descriptor *ed;
1663 DPRINTFN(4, "endpoint=%p\n", ep);
1665 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1668 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1673 sc = MUSBOTG_BUS2SC(udev->bus);
1675 /* get endpoint descriptor */
1678 /* reset endpoint */
1679 musbotg_clear_stall_sub(sc,
1680 UGETW(ed->wMaxPacketSize),
1681 (ed->bEndpointAddress & UE_ADDR),
1682 (ed->bmAttributes & UE_XFERTYPE),
1683 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1687 musbotg_init(struct musbotg_softc *sc)
1689 struct usb_hw_ep_profile *pf;
1699 DPRINTFN(1, "start\n");
1701 /* set up the bus structure */
1702 sc->sc_bus.usbrev = USB_REV_2_0;
1703 sc->sc_bus.methods = &musbotg_bus_methods;
1705 USB_BUS_LOCK(&sc->sc_bus);
1707 /* turn on clocks */
1709 if (sc->sc_clocks_on) {
1710 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1712 /* wait a little for things to stabilise */
1713 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1715 /* disable all interrupts */
1717 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
1718 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1719 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1721 /* disable pullup */
1723 musbotg_pull_common(sc, 0);
1725 /* wait a little bit (10ms) */
1726 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1728 /* disable double packet buffering */
1729 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
1730 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
1732 /* enable HighSpeed and ISO Update flags */
1734 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
1735 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
1737 /* clear Session bit, if set */
1739 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
1740 temp &= ~MUSB2_MASK_SESS;
1741 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
1743 DPRINTF("DEVCTL=0x%02x\n", temp);
1745 /* disable testmode */
1747 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
1749 /* set default value */
1751 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
1753 /* select endpoint index 0 */
1755 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1757 /* read out number of endpoints */
1760 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
1763 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
1765 /* these numbers exclude the control endpoint */
1767 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
1769 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
1770 if (sc->sc_ep_max == 0) {
1771 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
1773 /* read out configuration data */
1775 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
1777 DPRINTFN(2, "Config Data: 0x%02x\n",
1780 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
1783 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
1784 "assuming 16Kbytes of FIFO RAM\n");
1787 DPRINTFN(2, "HW version: 0x%04x\n",
1788 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
1790 /* initialise endpoint profiles */
1794 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
1795 pf = sc->sc_hw_ep_profile + temp;
1797 /* select endpoint */
1798 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
1800 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
1801 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
1802 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
1804 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
1805 temp, ftx, frx, dynfifo);
1808 if (frx && (temp <= nrx)) {
1811 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
1812 MUSB2_VAL_FIFOSZ_512 |
1815 frx = 7; /* 128 bytes */
1816 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
1817 MUSB2_VAL_FIFOSZ_128);
1820 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
1823 offset += (1 << frx);
1825 if (ftx && (temp <= ntx)) {
1828 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
1829 MUSB2_VAL_FIFOSZ_512 |
1832 ftx = 7; /* 128 bytes */
1833 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
1834 MUSB2_VAL_FIFOSZ_128);
1837 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
1840 offset += (1 << ftx);
1844 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
1845 pf->max_in_frame_size = 1 << ftx;
1846 pf->max_out_frame_size = 1 << frx;
1847 pf->is_simplex = 0; /* duplex */
1848 pf->support_multi_buffer = 1;
1849 pf->support_bulk = 1;
1850 pf->support_interrupt = 1;
1851 pf->support_isochronous = 1;
1853 pf->support_out = 1;
1854 } else if (frx && (temp <= nrx)) {
1855 pf->max_out_frame_size = 1 << frx;
1856 pf->is_simplex = 1; /* simplex */
1857 pf->support_multi_buffer = 1;
1858 pf->support_bulk = 1;
1859 pf->support_interrupt = 1;
1860 pf->support_isochronous = 1;
1861 pf->support_out = 1;
1862 } else if (ftx && (temp <= ntx)) {
1863 pf->max_in_frame_size = 1 << ftx;
1864 pf->is_simplex = 1; /* simplex */
1865 pf->support_multi_buffer = 1;
1866 pf->support_bulk = 1;
1867 pf->support_interrupt = 1;
1868 pf->support_isochronous = 1;
1873 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
1875 /* turn on default interrupts */
1877 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
1880 musbotg_clocks_off(sc);
1882 USB_BUS_UNLOCK(&sc->sc_bus);
1884 /* catch any lost interrupts */
1886 musbotg_do_poll(&sc->sc_bus);
1888 return (0); /* success */
1892 musbotg_uninit(struct musbotg_softc *sc)
1894 USB_BUS_LOCK(&sc->sc_bus);
1896 /* disable all interrupts */
1897 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
1898 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1899 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1901 sc->sc_flags.port_powered = 0;
1902 sc->sc_flags.status_vbus = 0;
1903 sc->sc_flags.status_bus_reset = 0;
1904 sc->sc_flags.status_suspend = 0;
1905 sc->sc_flags.change_suspend = 0;
1906 sc->sc_flags.change_connect = 1;
1908 musbotg_pull_down(sc);
1909 musbotg_clocks_off(sc);
1910 USB_BUS_UNLOCK(&sc->sc_bus);
1914 musbotg_suspend(struct musbotg_softc *sc)
1920 musbotg_resume(struct musbotg_softc *sc)
1926 musbotg_do_poll(struct usb_bus *bus)
1928 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
1930 USB_BUS_LOCK(&sc->sc_bus);
1931 musbotg_interrupt_poll(sc);
1932 USB_BUS_UNLOCK(&sc->sc_bus);
1935 /*------------------------------------------------------------------------*
1936 * musbotg bulk support
1937 *------------------------------------------------------------------------*/
1939 musbotg_device_bulk_open(struct usb_xfer *xfer)
1945 musbotg_device_bulk_close(struct usb_xfer *xfer)
1947 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1951 musbotg_device_bulk_enter(struct usb_xfer *xfer)
1957 musbotg_device_bulk_start(struct usb_xfer *xfer)
1960 musbotg_setup_standard_chain(xfer);
1961 musbotg_start_standard_chain(xfer);
1964 struct usb_pipe_methods musbotg_device_bulk_methods =
1966 .open = musbotg_device_bulk_open,
1967 .close = musbotg_device_bulk_close,
1968 .enter = musbotg_device_bulk_enter,
1969 .start = musbotg_device_bulk_start,
1972 /*------------------------------------------------------------------------*
1973 * musbotg control support
1974 *------------------------------------------------------------------------*/
1976 musbotg_device_ctrl_open(struct usb_xfer *xfer)
1982 musbotg_device_ctrl_close(struct usb_xfer *xfer)
1984 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1988 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
1994 musbotg_device_ctrl_start(struct usb_xfer *xfer)
1997 musbotg_setup_standard_chain(xfer);
1998 musbotg_start_standard_chain(xfer);
2001 struct usb_pipe_methods musbotg_device_ctrl_methods =
2003 .open = musbotg_device_ctrl_open,
2004 .close = musbotg_device_ctrl_close,
2005 .enter = musbotg_device_ctrl_enter,
2006 .start = musbotg_device_ctrl_start,
2009 /*------------------------------------------------------------------------*
2010 * musbotg interrupt support
2011 *------------------------------------------------------------------------*/
2013 musbotg_device_intr_open(struct usb_xfer *xfer)
2019 musbotg_device_intr_close(struct usb_xfer *xfer)
2021 musbotg_device_done(xfer, USB_ERR_CANCELLED);
2025 musbotg_device_intr_enter(struct usb_xfer *xfer)
2031 musbotg_device_intr_start(struct usb_xfer *xfer)
2034 musbotg_setup_standard_chain(xfer);
2035 musbotg_start_standard_chain(xfer);
2038 struct usb_pipe_methods musbotg_device_intr_methods =
2040 .open = musbotg_device_intr_open,
2041 .close = musbotg_device_intr_close,
2042 .enter = musbotg_device_intr_enter,
2043 .start = musbotg_device_intr_start,
2046 /*------------------------------------------------------------------------*
2047 * musbotg full speed isochronous support
2048 *------------------------------------------------------------------------*/
2050 musbotg_device_isoc_open(struct usb_xfer *xfer)
2056 musbotg_device_isoc_close(struct usb_xfer *xfer)
2058 musbotg_device_done(xfer, USB_ERR_CANCELLED);
2062 musbotg_device_isoc_enter(struct usb_xfer *xfer)
2064 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2069 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
2070 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2072 /* get the current frame index */
2074 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
2077 * check if the frame index is within the window where the frames
2080 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
2082 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2083 fs_frames = (xfer->nframes + 7) / 8;
2085 fs_frames = xfer->nframes;
2088 if ((xfer->endpoint->is_synced == 0) ||
2089 (temp < fs_frames)) {
2091 * If there is data underflow or the pipe queue is
2092 * empty we schedule the transfer a few frames ahead
2093 * of the current frame position. Else two isochronous
2094 * transfers might overlap.
2096 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
2097 xfer->endpoint->is_synced = 1;
2098 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
2101 * compute how many milliseconds the insertion is ahead of the
2102 * current frame position:
2104 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
2107 * pre-compute when the isochronous transfer will be finished:
2109 xfer->isoc_time_complete =
2110 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2113 /* compute frame number for next insertion */
2114 xfer->endpoint->isoc_next += fs_frames;
2117 musbotg_setup_standard_chain(xfer);
2121 musbotg_device_isoc_start(struct usb_xfer *xfer)
2123 /* start TD chain */
2124 musbotg_start_standard_chain(xfer);
2127 struct usb_pipe_methods musbotg_device_isoc_methods =
2129 .open = musbotg_device_isoc_open,
2130 .close = musbotg_device_isoc_close,
2131 .enter = musbotg_device_isoc_enter,
2132 .start = musbotg_device_isoc_start,
2135 /*------------------------------------------------------------------------*
2136 * musbotg root control support
2137 *------------------------------------------------------------------------*
2138 * Simulate a hardware HUB by handling all the necessary requests.
2139 *------------------------------------------------------------------------*/
2141 static const struct usb_device_descriptor musbotg_devd = {
2142 .bLength = sizeof(struct usb_device_descriptor),
2143 .bDescriptorType = UDESC_DEVICE,
2144 .bcdUSB = {0x00, 0x02},
2145 .bDeviceClass = UDCLASS_HUB,
2146 .bDeviceSubClass = UDSUBCLASS_HUB,
2147 .bDeviceProtocol = UDPROTO_HSHUBSTT,
2148 .bMaxPacketSize = 64,
2149 .bcdDevice = {0x00, 0x01},
2152 .bNumConfigurations = 1,
2155 static const struct usb_device_qualifier musbotg_odevd = {
2156 .bLength = sizeof(struct usb_device_qualifier),
2157 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2158 .bcdUSB = {0x00, 0x02},
2159 .bDeviceClass = UDCLASS_HUB,
2160 .bDeviceSubClass = UDSUBCLASS_HUB,
2161 .bDeviceProtocol = UDPROTO_FSHUB,
2162 .bMaxPacketSize0 = 0,
2163 .bNumConfigurations = 0,
2166 static const struct musbotg_config_desc musbotg_confd = {
2168 .bLength = sizeof(struct usb_config_descriptor),
2169 .bDescriptorType = UDESC_CONFIG,
2170 .wTotalLength[0] = sizeof(musbotg_confd),
2172 .bConfigurationValue = 1,
2173 .iConfiguration = 0,
2174 .bmAttributes = UC_SELF_POWERED,
2178 .bLength = sizeof(struct usb_interface_descriptor),
2179 .bDescriptorType = UDESC_INTERFACE,
2181 .bInterfaceClass = UICLASS_HUB,
2182 .bInterfaceSubClass = UISUBCLASS_HUB,
2183 .bInterfaceProtocol = 0,
2186 .bLength = sizeof(struct usb_endpoint_descriptor),
2187 .bDescriptorType = UDESC_ENDPOINT,
2188 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
2189 .bmAttributes = UE_INTERRUPT,
2190 .wMaxPacketSize[0] = 8,
2195 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2197 static const struct usb_hub_descriptor_min musbotg_hubd = {
2198 .bDescLength = sizeof(musbotg_hubd),
2199 .bDescriptorType = UDESC_HUB,
2201 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2202 .bPwrOn2PwrGood = 50,
2203 .bHubContrCurrent = 0,
2204 .DeviceRemovable = {0}, /* port is removable */
2207 #define STRING_LANG \
2208 0x09, 0x04, /* American English */
2210 #define STRING_VENDOR \
2211 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \
2212 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0
2214 #define STRING_PRODUCT \
2215 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \
2216 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
2219 USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab);
2220 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
2221 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
2224 musbotg_roothub_exec(struct usb_device *udev,
2225 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2227 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
2234 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2237 ptr = (const void *)&sc->sc_hub_temp;
2241 value = UGETW(req->wValue);
2242 index = UGETW(req->wIndex);
2244 /* demultiplex the control request */
2246 switch (req->bmRequestType) {
2247 case UT_READ_DEVICE:
2248 switch (req->bRequest) {
2249 case UR_GET_DESCRIPTOR:
2250 goto tr_handle_get_descriptor;
2252 goto tr_handle_get_config;
2254 goto tr_handle_get_status;
2260 case UT_WRITE_DEVICE:
2261 switch (req->bRequest) {
2262 case UR_SET_ADDRESS:
2263 goto tr_handle_set_address;
2265 goto tr_handle_set_config;
2266 case UR_CLEAR_FEATURE:
2267 goto tr_valid; /* nop */
2268 case UR_SET_DESCRIPTOR:
2269 goto tr_valid; /* nop */
2270 case UR_SET_FEATURE:
2276 case UT_WRITE_ENDPOINT:
2277 switch (req->bRequest) {
2278 case UR_CLEAR_FEATURE:
2279 switch (UGETW(req->wValue)) {
2280 case UF_ENDPOINT_HALT:
2281 goto tr_handle_clear_halt;
2282 case UF_DEVICE_REMOTE_WAKEUP:
2283 goto tr_handle_clear_wakeup;
2288 case UR_SET_FEATURE:
2289 switch (UGETW(req->wValue)) {
2290 case UF_ENDPOINT_HALT:
2291 goto tr_handle_set_halt;
2292 case UF_DEVICE_REMOTE_WAKEUP:
2293 goto tr_handle_set_wakeup;
2298 case UR_SYNCH_FRAME:
2299 goto tr_valid; /* nop */
2305 case UT_READ_ENDPOINT:
2306 switch (req->bRequest) {
2308 goto tr_handle_get_ep_status;
2314 case UT_WRITE_INTERFACE:
2315 switch (req->bRequest) {
2316 case UR_SET_INTERFACE:
2317 goto tr_handle_set_interface;
2318 case UR_CLEAR_FEATURE:
2319 goto tr_valid; /* nop */
2320 case UR_SET_FEATURE:
2326 case UT_READ_INTERFACE:
2327 switch (req->bRequest) {
2328 case UR_GET_INTERFACE:
2329 goto tr_handle_get_interface;
2331 goto tr_handle_get_iface_status;
2337 case UT_WRITE_CLASS_INTERFACE:
2338 case UT_WRITE_VENDOR_INTERFACE:
2342 case UT_READ_CLASS_INTERFACE:
2343 case UT_READ_VENDOR_INTERFACE:
2347 case UT_WRITE_CLASS_DEVICE:
2348 switch (req->bRequest) {
2349 case UR_CLEAR_FEATURE:
2351 case UR_SET_DESCRIPTOR:
2352 case UR_SET_FEATURE:
2359 case UT_WRITE_CLASS_OTHER:
2360 switch (req->bRequest) {
2361 case UR_CLEAR_FEATURE:
2362 goto tr_handle_clear_port_feature;
2363 case UR_SET_FEATURE:
2364 goto tr_handle_set_port_feature;
2365 case UR_CLEAR_TT_BUFFER:
2375 case UT_READ_CLASS_OTHER:
2376 switch (req->bRequest) {
2377 case UR_GET_TT_STATE:
2378 goto tr_handle_get_tt_state;
2380 goto tr_handle_get_port_status;
2386 case UT_READ_CLASS_DEVICE:
2387 switch (req->bRequest) {
2388 case UR_GET_DESCRIPTOR:
2389 goto tr_handle_get_class_descriptor;
2391 goto tr_handle_get_class_status;
2402 tr_handle_get_descriptor:
2403 switch (value >> 8) {
2408 len = sizeof(musbotg_devd);
2409 ptr = (const void *)&musbotg_devd;
2415 len = sizeof(musbotg_confd);
2416 ptr = (const void *)&musbotg_confd;
2419 switch (value & 0xff) {
2420 case 0: /* Language table */
2421 len = sizeof(musbotg_langtab);
2422 ptr = (const void *)&musbotg_langtab;
2425 case 1: /* Vendor */
2426 len = sizeof(musbotg_vendor);
2427 ptr = (const void *)&musbotg_vendor;
2430 case 2: /* Product */
2431 len = sizeof(musbotg_product);
2432 ptr = (const void *)&musbotg_product;
2443 tr_handle_get_config:
2445 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2448 tr_handle_get_status:
2450 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2453 tr_handle_set_address:
2454 if (value & 0xFF00) {
2457 sc->sc_rt_addr = value;
2460 tr_handle_set_config:
2464 sc->sc_conf = value;
2467 tr_handle_get_interface:
2469 sc->sc_hub_temp.wValue[0] = 0;
2472 tr_handle_get_tt_state:
2473 tr_handle_get_class_status:
2474 tr_handle_get_iface_status:
2475 tr_handle_get_ep_status:
2477 USETW(sc->sc_hub_temp.wValue, 0);
2481 tr_handle_set_interface:
2482 tr_handle_set_wakeup:
2483 tr_handle_clear_wakeup:
2484 tr_handle_clear_halt:
2487 tr_handle_clear_port_feature:
2491 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2494 case UHF_PORT_SUSPEND:
2495 musbotg_wakeup_peer(sc);
2498 case UHF_PORT_ENABLE:
2499 sc->sc_flags.port_enabled = 0;
2503 case UHF_PORT_INDICATOR:
2504 case UHF_C_PORT_ENABLE:
2505 case UHF_C_PORT_OVER_CURRENT:
2506 case UHF_C_PORT_RESET:
2509 case UHF_PORT_POWER:
2510 sc->sc_flags.port_powered = 0;
2511 musbotg_pull_down(sc);
2512 musbotg_clocks_off(sc);
2514 case UHF_C_PORT_CONNECTION:
2515 sc->sc_flags.change_connect = 0;
2517 case UHF_C_PORT_SUSPEND:
2518 sc->sc_flags.change_suspend = 0;
2521 err = USB_ERR_IOERROR;
2526 tr_handle_set_port_feature:
2530 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
2533 case UHF_PORT_ENABLE:
2534 sc->sc_flags.port_enabled = 1;
2536 case UHF_PORT_SUSPEND:
2537 case UHF_PORT_RESET:
2539 case UHF_PORT_INDICATOR:
2542 case UHF_PORT_POWER:
2543 sc->sc_flags.port_powered = 1;
2546 err = USB_ERR_IOERROR;
2551 tr_handle_get_port_status:
2553 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
2558 if (sc->sc_flags.status_vbus) {
2559 musbotg_clocks_on(sc);
2560 musbotg_pull_up(sc);
2562 musbotg_pull_down(sc);
2563 musbotg_clocks_off(sc);
2566 /* Select Device Side Mode */
2567 value = UPS_PORT_MODE_DEVICE;
2569 if (sc->sc_flags.status_high_speed) {
2570 value |= UPS_HIGH_SPEED;
2572 if (sc->sc_flags.port_powered) {
2573 value |= UPS_PORT_POWER;
2575 if (sc->sc_flags.port_enabled) {
2576 value |= UPS_PORT_ENABLED;
2578 if (sc->sc_flags.status_vbus &&
2579 sc->sc_flags.status_bus_reset) {
2580 value |= UPS_CURRENT_CONNECT_STATUS;
2582 if (sc->sc_flags.status_suspend) {
2583 value |= UPS_SUSPEND;
2585 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2589 if (sc->sc_flags.change_connect) {
2590 value |= UPS_C_CONNECT_STATUS;
2592 if (sc->sc_flags.status_vbus &&
2593 sc->sc_flags.status_bus_reset) {
2594 /* reset EP0 state */
2595 sc->sc_ep0_busy = 0;
2599 if (sc->sc_flags.change_suspend) {
2600 value |= UPS_C_SUSPEND;
2602 USETW(sc->sc_hub_temp.ps.wPortChange, value);
2603 len = sizeof(sc->sc_hub_temp.ps);
2606 tr_handle_get_class_descriptor:
2610 ptr = (const void *)&musbotg_hubd;
2611 len = sizeof(musbotg_hubd);
2615 err = USB_ERR_STALLED;
2624 musbotg_xfer_setup(struct usb_setup_params *parm)
2626 const struct usb_hw_ep_profile *pf;
2627 struct musbotg_softc *sc;
2628 struct usb_xfer *xfer;
2634 sc = MUSBOTG_BUS2SC(parm->udev->bus);
2635 xfer = parm->curr_xfer;
2638 * NOTE: This driver does not use any of the parameters that
2639 * are computed from the following values. Just set some
2640 * reasonable dummies:
2642 parm->hc_max_packet_size = 0x400;
2643 parm->hc_max_frame_size = 0x400;
2645 if ((parm->methods == &musbotg_device_isoc_methods) ||
2646 (parm->methods == &musbotg_device_intr_methods))
2647 parm->hc_max_packet_count = 3;
2649 parm->hc_max_packet_count = 1;
2651 usbd_transfer_setup_sub(parm);
2654 * compute maximum number of TDs
2656 if (parm->methods == &musbotg_device_ctrl_methods) {
2658 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
2660 } else if (parm->methods == &musbotg_device_bulk_methods) {
2662 ntd = xfer->nframes + 1 /* SYNC */ ;
2664 } else if (parm->methods == &musbotg_device_intr_methods) {
2666 ntd = xfer->nframes + 1 /* SYNC */ ;
2668 } else if (parm->methods == &musbotg_device_isoc_methods) {
2670 ntd = xfer->nframes + 1 /* SYNC */ ;
2678 * check if "usbd_transfer_setup_sub" set an error
2684 * allocate transfer descriptors
2693 ep_no = xfer->endpointno & UE_ADDR;
2694 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
2697 /* should not happen */
2698 parm->err = USB_ERR_INVAL;
2707 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2709 for (n = 0; n != ntd; n++) {
2711 struct musbotg_td *td;
2715 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2718 td->max_frame_size = xfer->max_frame_size;
2720 td->obj_next = last_obj;
2724 parm->size[0] += sizeof(*td);
2727 xfer->td_start[0] = last_obj;
2731 musbotg_xfer_unsetup(struct usb_xfer *xfer)
2737 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2738 struct usb_endpoint *ep)
2740 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
2742 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2744 edesc->bEndpointAddress, udev->flags.usb_mode,
2747 if (udev->device_index != sc->sc_rt_addr) {
2749 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2753 if ((udev->speed != USB_SPEED_FULL) &&
2754 (udev->speed != USB_SPEED_HIGH)) {
2758 switch (edesc->bmAttributes & UE_XFERTYPE) {
2760 ep->methods = &musbotg_device_ctrl_methods;
2763 ep->methods = &musbotg_device_intr_methods;
2765 case UE_ISOCHRONOUS:
2766 ep->methods = &musbotg_device_isoc_methods;
2769 ep->methods = &musbotg_device_bulk_methods;
2779 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2781 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
2784 case USB_HW_POWER_SUSPEND:
2785 musbotg_suspend(sc);
2787 case USB_HW_POWER_SHUTDOWN:
2790 case USB_HW_POWER_RESUME:
2798 struct usb_bus_methods musbotg_bus_methods =
2800 .endpoint_init = &musbotg_ep_init,
2801 .xfer_setup = &musbotg_xfer_setup,
2802 .xfer_unsetup = &musbotg_xfer_unsetup,
2803 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
2804 .set_stall = &musbotg_set_stall,
2805 .clear_stall = &musbotg_clear_stall,
2806 .roothub_exec = &musbotg_roothub_exec,
2807 .xfer_poll = &musbotg_do_poll,
2808 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,