3 * Copyright (c) 2008 Hans Petter Selasky <hselasky@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * This file contains the driver for the USS820 series USB Device
32 * NOTE: The datasheet does not document everything.
35 #include <sys/stdint.h>
36 #include <sys/stddef.h>
37 #include <sys/param.h>
38 #include <sys/queue.h>
39 #include <sys/types.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/condvar.h>
47 #include <sys/sysctl.h>
49 #include <sys/unistd.h>
50 #include <sys/callout.h>
51 #include <sys/malloc.h>
54 #include <dev/usb/usb.h>
55 #include <dev/usb/usbdi.h>
57 #define USB_DEBUG_VAR uss820dcidebug
59 #include <dev/usb/usb_core.h>
60 #include <dev/usb/usb_debug.h>
61 #include <dev/usb/usb_busdma.h>
62 #include <dev/usb/usb_process.h>
63 #include <dev/usb/usb_transfer.h>
64 #include <dev/usb/usb_device.h>
65 #include <dev/usb/usb_hub.h>
66 #include <dev/usb/usb_util.h>
68 #include <dev/usb/usb_controller.h>
69 #include <dev/usb/usb_bus.h>
70 #include <dev/usb/controller/uss820dci.h>
72 #define USS820_DCI_BUS2SC(bus) \
73 ((struct uss820dci_softc *)(((uint8_t *)(bus)) - \
74 ((uint8_t *)&(((struct uss820dci_softc *)0)->sc_bus))))
76 #define USS820_DCI_PC2SC(pc) \
77 USS820_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
80 static int uss820dcidebug = 0;
82 SYSCTL_NODE(_hw_usb, OID_AUTO, uss820dci, CTLFLAG_RW, 0, "USB uss820dci");
83 SYSCTL_INT(_hw_usb_uss820dci, OID_AUTO, debug, CTLFLAG_RW,
84 &uss820dcidebug, 0, "uss820dci debug level");
87 #define USS820_DCI_INTR_ENDPT 1
91 struct usb_bus_methods uss820dci_bus_methods;
92 struct usb_pipe_methods uss820dci_device_bulk_methods;
93 struct usb_pipe_methods uss820dci_device_ctrl_methods;
94 struct usb_pipe_methods uss820dci_device_intr_methods;
95 struct usb_pipe_methods uss820dci_device_isoc_fs_methods;
97 static uss820dci_cmd_t uss820dci_setup_rx;
98 static uss820dci_cmd_t uss820dci_data_rx;
99 static uss820dci_cmd_t uss820dci_data_tx;
100 static uss820dci_cmd_t uss820dci_data_tx_sync;
101 static void uss820dci_device_done(struct usb_xfer *, usb_error_t);
102 static void uss820dci_do_poll(struct usb_bus *);
103 static void uss820dci_standard_done(struct usb_xfer *);
104 static void uss820dci_intr_set(struct usb_xfer *, uint8_t);
105 static void uss820dci_update_shared_1(struct uss820dci_softc *, uint8_t,
107 static void uss820dci_root_intr(struct uss820dci_softc *);
110 * Here is a list of what the USS820D chip can support. The main
111 * limitation is that the sum of the buffer sizes must be less than
114 static const struct usb_hw_ep_profile
115 uss820dci_ep_profile[] = {
118 .max_in_frame_size = 32,
119 .max_out_frame_size = 32,
121 .support_control = 1,
124 .max_in_frame_size = 64,
125 .max_out_frame_size = 64,
127 .support_multi_buffer = 1,
129 .support_interrupt = 1,
134 .max_in_frame_size = 8,
135 .max_out_frame_size = 8,
137 .support_multi_buffer = 1,
139 .support_interrupt = 1,
144 .max_in_frame_size = 256,
145 .max_out_frame_size = 256,
147 .support_multi_buffer = 1,
148 .support_isochronous = 1,
155 uss820dci_update_shared_1(struct uss820dci_softc *sc, uint8_t reg,
156 uint8_t keep_mask, uint8_t set_mask)
160 USS820_WRITE_1(sc, USS820_PEND, 1);
161 temp = USS820_READ_1(sc, reg);
164 USS820_WRITE_1(sc, reg, temp);
165 USS820_WRITE_1(sc, USS820_PEND, 0);
169 uss820dci_get_hw_ep_profile(struct usb_device *udev,
170 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
173 *ppf = uss820dci_ep_profile + 0;
174 } else if (ep_addr < 5) {
175 *ppf = uss820dci_ep_profile + 1;
176 } else if (ep_addr < 7) {
177 *ppf = uss820dci_ep_profile + 2;
178 } else if (ep_addr == 7) {
179 *ppf = uss820dci_ep_profile + 3;
186 uss820dci_pull_up(struct uss820dci_softc *sc)
190 /* pullup D+, if possible */
192 if (!sc->sc_flags.d_pulled_up &&
193 sc->sc_flags.port_powered) {
194 sc->sc_flags.d_pulled_up = 1;
198 temp = USS820_READ_1(sc, USS820_MCSR);
199 temp |= USS820_MCSR_DPEN;
200 USS820_WRITE_1(sc, USS820_MCSR, temp);
205 uss820dci_pull_down(struct uss820dci_softc *sc)
209 /* pulldown D+, if possible */
211 if (sc->sc_flags.d_pulled_up) {
212 sc->sc_flags.d_pulled_up = 0;
216 temp = USS820_READ_1(sc, USS820_MCSR);
217 temp &= ~USS820_MCSR_DPEN;
218 USS820_WRITE_1(sc, USS820_MCSR, temp);
223 uss820dci_wakeup_peer(struct uss820dci_softc *sc)
225 if (!(sc->sc_flags.status_suspend)) {
228 DPRINTFN(0, "not supported\n");
232 uss820dci_set_address(struct uss820dci_softc *sc, uint8_t addr)
234 DPRINTFN(5, "addr=%d\n", addr);
236 USS820_WRITE_1(sc, USS820_FADDR, addr);
240 uss820dci_setup_rx(struct uss820dci_td *td)
242 struct uss820dci_softc *sc;
243 struct usb_device_request req;
248 /* select the correct endpoint */
249 bus_space_write_1(td->io_tag, td->io_hdl,
250 USS820_EPINDEX, td->ep_index);
252 /* read out FIFO status */
253 rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
256 /* get pointer to softc */
257 sc = USS820_DCI_PC2SC(td->pc);
259 DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder);
261 if (!(rx_stat & USS820_RXSTAT_RXSETUP)) {
264 /* clear did stall */
267 /* clear stall and all I/O */
268 uss820dci_update_shared_1(sc, USS820_EPCON,
269 0xFF ^ (USS820_EPCON_TXSTL |
272 USS820_EPCON_TXOE), 0);
274 /* clear end overwrite flag */
275 uss820dci_update_shared_1(sc, USS820_RXSTAT,
276 0xFF ^ USS820_RXSTAT_EDOVW, 0);
278 /* get the packet byte count */
279 count = bus_space_read_1(td->io_tag, td->io_hdl,
281 count |= (bus_space_read_1(td->io_tag, td->io_hdl,
282 USS820_RXCNTH) << 8);
285 /* verify data length */
286 if (count != td->remainder) {
287 DPRINTFN(0, "Invalid SETUP packet "
288 "length, %d bytes\n", count);
289 goto setup_not_complete;
291 if (count != sizeof(req)) {
292 DPRINTFN(0, "Unsupported SETUP packet "
293 "length, %d bytes\n", count);
294 goto setup_not_complete;
297 bus_space_read_multi_1(td->io_tag, td->io_hdl,
298 USS820_RXDAT, (void *)&req, sizeof(req));
300 /* read out FIFO status */
301 rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
304 if (rx_stat & (USS820_RXSTAT_EDOVW |
305 USS820_RXSTAT_STOVW)) {
306 DPRINTF("new SETUP packet received\n");
307 return (1); /* not complete */
309 /* clear receive setup bit */
310 uss820dci_update_shared_1(sc, USS820_RXSTAT,
311 0xFF ^ (USS820_RXSTAT_RXSETUP |
312 USS820_RXSTAT_EDOVW |
313 USS820_RXSTAT_STOVW), 0);
316 temp = bus_space_read_1(td->io_tag, td->io_hdl,
318 temp |= USS820_RXCON_RXFFRC;
319 bus_space_write_1(td->io_tag, td->io_hdl,
322 /* copy data into real buffer */
323 usbd_copy_in(td->pc, 0, &req, sizeof(req));
325 td->offset = sizeof(req);
328 /* sneak peek the set address */
329 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
330 (req.bRequest == UR_SET_ADDRESS)) {
331 sc->sc_dv_addr = req.wValue[0] & 0x7F;
333 sc->sc_dv_addr = 0xFF;
337 temp = USS820_READ_1(sc, USS820_TXCON);
338 temp |= USS820_TXCON_TXCLR;
339 USS820_WRITE_1(sc, USS820_TXCON, temp);
340 temp &= ~USS820_TXCON_TXCLR;
341 USS820_WRITE_1(sc, USS820_TXCON, temp);
343 return (0); /* complete */
348 temp = bus_space_read_1(td->io_tag, td->io_hdl,
350 temp |= USS820_RXCON_RXFFRC;
351 bus_space_write_1(td->io_tag, td->io_hdl,
357 /* abort any ongoing transfer */
358 if (!td->did_stall) {
359 DPRINTFN(5, "stalling\n");
361 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF,
362 (USS820_EPCON_TXSTL | USS820_EPCON_RXSTL));
367 /* clear end overwrite flag, if any */
368 if (rx_stat & USS820_RXSTAT_RXSETUP) {
369 uss820dci_update_shared_1(sc, USS820_RXSTAT,
370 0xFF ^ (USS820_RXSTAT_EDOVW |
371 USS820_RXSTAT_STOVW |
372 USS820_RXSTAT_RXSETUP), 0);
374 return (1); /* not complete */
379 uss820dci_data_rx(struct uss820dci_td *td)
381 struct usb_page_search buf_res;
389 to = 2; /* don't loop forever! */
392 /* select the correct endpoint */
393 bus_space_write_1(td->io_tag, td->io_hdl, USS820_EPINDEX, td->ep_index);
395 /* check if any of the FIFO banks have data */
397 /* read out FIFO flag */
398 rx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
400 /* read out FIFO status */
401 rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
404 DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n",
405 rx_stat, rx_flag, td->remainder);
407 if (rx_stat & (USS820_RXSTAT_RXSETUP |
408 USS820_RXSTAT_RXSOVW |
409 USS820_RXSTAT_EDOVW)) {
410 if (td->remainder == 0) {
412 * We are actually complete and have
413 * received the next SETUP
415 DPRINTFN(5, "faking complete\n");
416 return (0); /* complete */
419 * USB Host Aborted the transfer.
422 return (0); /* complete */
424 /* check for errors */
425 if (rx_flag & (USS820_RXFLG_RXOVF |
426 USS820_RXFLG_RXURF)) {
427 DPRINTFN(5, "overflow or underflow\n");
428 /* should not happen */
430 return (0); /* complete */
433 if (!(rx_flag & (USS820_RXFLG_RXFIF0 |
434 USS820_RXFLG_RXFIF1))) {
436 /* read out EPCON register */
437 /* enable RX input */
438 if (!td->did_enable) {
439 uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc),
440 USS820_EPCON, 0xFF, USS820_EPCON_RXIE);
443 return (1); /* not complete */
445 /* get the packet byte count */
446 count = bus_space_read_1(td->io_tag, td->io_hdl,
449 count |= (bus_space_read_1(td->io_tag, td->io_hdl,
450 USS820_RXCNTH) << 8);
453 DPRINTFN(5, "count=0x%04x\n", count);
455 /* verify the packet byte count */
456 if (count != td->max_packet_size) {
457 if (count < td->max_packet_size) {
458 /* we have a short packet */
462 /* invalid USB packet */
464 return (0); /* we are complete */
467 /* verify the packet byte count */
468 if (count > td->remainder) {
469 /* invalid USB packet */
471 return (0); /* we are complete */
474 usbd_get_page(td->pc, td->offset, &buf_res);
476 /* get correct length */
477 if (buf_res.length > count) {
478 buf_res.length = count;
481 bus_space_read_multi_1(td->io_tag, td->io_hdl,
482 USS820_RXDAT, buf_res.buffer, buf_res.length);
484 /* update counters */
485 count -= buf_res.length;
486 td->offset += buf_res.length;
487 td->remainder -= buf_res.length;
491 rx_cntl = bus_space_read_1(td->io_tag, td->io_hdl,
493 rx_cntl |= USS820_RXCON_RXFFRC;
494 bus_space_write_1(td->io_tag, td->io_hdl,
495 USS820_RXCON, rx_cntl);
497 /* check if we are complete */
498 if ((td->remainder == 0) || got_short) {
500 /* we are complete */
503 /* else need to receive a zero length packet */
508 return (1); /* not complete */
512 uss820dci_data_tx(struct uss820dci_td *td)
514 struct usb_page_search buf_res;
521 /* select the correct endpoint */
522 bus_space_write_1(td->io_tag, td->io_hdl,
523 USS820_EPINDEX, td->ep_index);
525 to = 2; /* don't loop forever! */
528 /* read out TX FIFO flags */
529 tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
532 /* read out RX FIFO status last */
533 rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
536 DPRINTFN(5, "rx_stat=0x%02x tx_flag=0x%02x rem=%u\n",
537 rx_stat, tx_flag, td->remainder);
539 if (rx_stat & (USS820_RXSTAT_RXSETUP |
540 USS820_RXSTAT_RXSOVW |
541 USS820_RXSTAT_EDOVW)) {
543 * The current transfer was aborted
547 return (0); /* complete */
549 if (tx_flag & (USS820_TXFLG_TXOVF |
550 USS820_TXFLG_TXURF)) {
552 return (0); /* complete */
554 if (tx_flag & USS820_TXFLG_TXFIF0) {
555 if (tx_flag & USS820_TXFLG_TXFIF1) {
556 return (1); /* not complete */
559 if ((!td->support_multi_buffer) &&
560 (tx_flag & (USS820_TXFLG_TXFIF0 |
561 USS820_TXFLG_TXFIF1))) {
562 return (1); /* not complete */
564 count = td->max_packet_size;
565 if (td->remainder < count) {
566 /* we have a short packet */
568 count = td->remainder;
573 usbd_get_page(td->pc, td->offset, &buf_res);
575 /* get correct length */
576 if (buf_res.length > count) {
577 buf_res.length = count;
580 bus_space_write_multi_1(td->io_tag, td->io_hdl,
581 USS820_TXDAT, buf_res.buffer, buf_res.length);
583 /* update counters */
584 count -= buf_res.length;
585 td->offset += buf_res.length;
586 td->remainder -= buf_res.length;
589 /* post-write high packet byte count first */
590 bus_space_write_1(td->io_tag, td->io_hdl,
591 USS820_TXCNTH, count_copy >> 8);
593 /* post-write low packet byte count last */
594 bus_space_write_1(td->io_tag, td->io_hdl,
595 USS820_TXCNTL, count_copy);
598 * Enable TX output, which must happen after that we have written
599 * data into the FIFO. This is undocumented.
601 if (!td->did_enable) {
602 uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc),
603 USS820_EPCON, 0xFF, USS820_EPCON_TXOE);
606 /* check remainder */
607 if (td->remainder == 0) {
609 return (0); /* complete */
611 /* else we need to transmit a short packet */
616 return (1); /* not complete */
620 uss820dci_data_tx_sync(struct uss820dci_td *td)
622 struct uss820dci_softc *sc;
626 /* select the correct endpoint */
627 bus_space_write_1(td->io_tag, td->io_hdl,
628 USS820_EPINDEX, td->ep_index);
630 /* read out TX FIFO flag */
631 tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
634 /* read out RX FIFO status last */
635 rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
638 DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder);
640 if (rx_stat & (USS820_RXSTAT_RXSETUP |
641 USS820_RXSTAT_RXSOVW |
642 USS820_RXSTAT_EDOVW)) {
643 DPRINTFN(5, "faking complete\n");
645 return (0); /* complete */
647 DPRINTFN(5, "tx_flag=0x%02x rem=%u\n",
648 tx_flag, td->remainder);
650 if (tx_flag & (USS820_TXFLG_TXOVF |
651 USS820_TXFLG_TXURF)) {
653 return (0); /* complete */
655 if (tx_flag & (USS820_TXFLG_TXFIF0 |
656 USS820_TXFLG_TXFIF1)) {
657 return (1); /* not complete */
659 sc = USS820_DCI_PC2SC(td->pc);
660 if (sc->sc_dv_addr != 0xFF) {
661 /* write function address */
662 uss820dci_set_address(sc, sc->sc_dv_addr);
664 return (0); /* complete */
668 uss820dci_xfer_do_fifo(struct usb_xfer *xfer)
670 struct uss820dci_td *td;
674 td = xfer->td_transfer_cache;
676 if ((td->func) (td)) {
677 /* operation in progress */
680 if (((void *)td) == xfer->td_transfer_last) {
685 } else if (td->remainder > 0) {
687 * We had a short transfer. If there is no alternate
688 * next, stop processing !
695 * Fetch the next transfer descriptor.
698 xfer->td_transfer_cache = td;
700 return (1); /* not complete */
703 /* compute all actual lengths */
705 uss820dci_standard_done(xfer);
707 return (0); /* complete */
711 uss820dci_interrupt_poll(struct uss820dci_softc *sc)
713 struct usb_xfer *xfer;
716 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
717 if (!uss820dci_xfer_do_fifo(xfer)) {
718 /* queue has been modified */
725 uss820dci_wait_suspend(struct uss820dci_softc *sc, uint8_t on)
730 scr = USS820_READ_1(sc, USS820_SCR);
731 scratch = USS820_READ_1(sc, USS820_SCRATCH);
734 scr |= USS820_SCR_IE_SUSP;
735 scratch &= ~USS820_SCRATCH_IE_RESUME;
737 scr &= ~USS820_SCR_IE_SUSP;
738 scratch |= USS820_SCRATCH_IE_RESUME;
741 USS820_WRITE_1(sc, USS820_SCR, scr);
742 USS820_WRITE_1(sc, USS820_SCRATCH, scratch);
746 uss820dci_interrupt(struct uss820dci_softc *sc)
751 USB_BUS_LOCK(&sc->sc_bus);
753 ssr = USS820_READ_1(sc, USS820_SSR);
755 ssr &= (USS820_SSR_SUSPEND |
759 /* acknowledge all interrupts */
761 uss820dci_update_shared_1(sc, USS820_SSR, 0, 0);
763 /* check for any bus state change interrupts */
769 if (ssr & USS820_SSR_RESET) {
770 sc->sc_flags.status_bus_reset = 1;
771 sc->sc_flags.status_suspend = 0;
772 sc->sc_flags.change_suspend = 0;
773 sc->sc_flags.change_connect = 1;
775 /* disable resume interrupt */
776 uss820dci_wait_suspend(sc, 1);
781 * If "RESUME" and "SUSPEND" is set at the same time
782 * we interpret that like "RESUME". Resume is set when
783 * there is at least 3 milliseconds of inactivity on
786 if (ssr & USS820_SSR_RESUME) {
787 if (sc->sc_flags.status_suspend) {
788 sc->sc_flags.status_suspend = 0;
789 sc->sc_flags.change_suspend = 1;
790 /* disable resume interrupt */
791 uss820dci_wait_suspend(sc, 1);
794 } else if (ssr & USS820_SSR_SUSPEND) {
795 if (!sc->sc_flags.status_suspend) {
796 sc->sc_flags.status_suspend = 1;
797 sc->sc_flags.change_suspend = 1;
798 /* enable resume interrupt */
799 uss820dci_wait_suspend(sc, 0);
805 DPRINTF("real bus interrupt 0x%02x\n", ssr);
807 /* complete root HUB interrupt endpoint */
808 uss820dci_root_intr(sc);
811 /* acknowledge all SBI interrupts */
812 uss820dci_update_shared_1(sc, USS820_SBI, 0, 0);
814 /* acknowledge all SBI1 interrupts */
815 uss820dci_update_shared_1(sc, USS820_SBI1, 0, 0);
817 /* poll all active transfers */
818 uss820dci_interrupt_poll(sc);
820 USB_BUS_UNLOCK(&sc->sc_bus);
824 uss820dci_setup_standard_chain_sub(struct uss820_std_temp *temp)
826 struct uss820dci_td *td;
828 /* get current Transfer Descriptor */
832 /* prepare for next TD */
833 temp->td_next = td->obj_next;
835 /* fill out the Transfer Descriptor */
836 td->func = temp->func;
838 td->offset = temp->offset;
839 td->remainder = temp->len;
842 td->did_stall = temp->did_stall;
843 td->short_pkt = temp->short_pkt;
844 td->alt_next = temp->setup_alt_next;
848 uss820dci_setup_standard_chain(struct usb_xfer *xfer)
850 struct uss820_std_temp temp;
851 struct uss820dci_softc *sc;
852 struct uss820dci_td *td;
856 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
857 xfer->address, UE_GET_ADDR(xfer->endpointno),
858 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
860 temp.max_frame_size = xfer->max_frame_size;
862 td = xfer->td_start[0];
863 xfer->td_transfer_first = td;
864 xfer->td_transfer_cache = td;
870 temp.td_next = xfer->td_start[0];
872 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
873 temp.did_stall = !xfer->flags_int.control_stall;
875 sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
876 ep_no = (xfer->endpointno & UE_ADDR);
878 /* check if we should prepend a setup message */
880 if (xfer->flags_int.control_xfr) {
881 if (xfer->flags_int.control_hdr) {
883 temp.func = &uss820dci_setup_rx;
884 temp.len = xfer->frlengths[0];
885 temp.pc = xfer->frbuffers + 0;
886 temp.short_pkt = temp.len ? 1 : 0;
887 /* check for last frame */
888 if (xfer->nframes == 1) {
889 /* no STATUS stage yet, SETUP is last */
890 if (xfer->flags_int.control_act)
891 temp.setup_alt_next = 0;
894 uss820dci_setup_standard_chain_sub(&temp);
901 if (x != xfer->nframes) {
902 if (xfer->endpointno & UE_DIR_IN) {
903 temp.func = &uss820dci_data_tx;
905 temp.func = &uss820dci_data_rx;
908 /* setup "pc" pointer */
909 temp.pc = xfer->frbuffers + x;
911 while (x != xfer->nframes) {
913 /* DATA0 / DATA1 message */
915 temp.len = xfer->frlengths[x];
919 if (x == xfer->nframes) {
920 if (xfer->flags_int.control_xfr) {
921 if (xfer->flags_int.control_act) {
922 temp.setup_alt_next = 0;
925 temp.setup_alt_next = 0;
930 /* make sure that we send an USB packet */
936 /* regular data transfer */
938 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
941 uss820dci_setup_standard_chain_sub(&temp);
943 if (xfer->flags_int.isochronous_xfr) {
944 temp.offset += temp.len;
946 /* get next Page Cache pointer */
947 temp.pc = xfer->frbuffers + x;
951 /* check for control transfer */
952 if (xfer->flags_int.control_xfr) {
955 /* always setup a valid "pc" pointer for status and sync */
956 temp.pc = xfer->frbuffers + 0;
959 temp.setup_alt_next = 0;
961 /* check if we should append a status stage */
962 if (!xfer->flags_int.control_act) {
965 * Send a DATA1 message and invert the current
966 * endpoint direction.
968 if (xfer->endpointno & UE_DIR_IN) {
969 temp.func = &uss820dci_data_rx;
972 temp.func = &uss820dci_data_tx;
978 uss820dci_setup_standard_chain_sub(&temp);
980 /* we need a SYNC point after TX */
981 temp.func = &uss820dci_data_tx_sync;
982 uss820dci_setup_standard_chain_sub(&temp);
986 /* must have at least one frame! */
988 xfer->td_transfer_last = td;
992 uss820dci_timeout(void *arg)
994 struct usb_xfer *xfer = arg;
996 DPRINTF("xfer=%p\n", xfer);
998 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1000 /* transfer is transferred */
1001 uss820dci_device_done(xfer, USB_ERR_TIMEOUT);
1005 uss820dci_intr_set(struct usb_xfer *xfer, uint8_t set)
1007 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
1008 uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1012 DPRINTFN(15, "endpoint 0x%02x\n", xfer->endpointno);
1015 ep_reg = USS820_SBIE1;
1017 ep_reg = USS820_SBIE;
1021 ep_no = 1 << (2 * ep_no);
1023 if (xfer->flags_int.control_xfr) {
1024 if (xfer->flags_int.control_hdr) {
1025 ep_no <<= 1; /* RX interrupt only */
1027 ep_no |= (ep_no << 1); /* RX and TX interrupt */
1030 if (!(xfer->endpointno & UE_DIR_IN)) {
1034 temp = USS820_READ_1(sc, ep_reg);
1040 USS820_WRITE_1(sc, ep_reg, temp);
1044 uss820dci_start_standard_chain(struct usb_xfer *xfer)
1049 if (uss820dci_xfer_do_fifo(xfer)) {
1052 * Only enable the endpoint interrupt when we are
1053 * actually waiting for data, hence we are dealing
1054 * with level triggered interrupts !
1056 uss820dci_intr_set(xfer, 1);
1058 /* put transfer on interrupt queue */
1059 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1061 /* start timeout, if any */
1062 if (xfer->timeout != 0) {
1063 usbd_transfer_timeout_ms(xfer,
1064 &uss820dci_timeout, xfer->timeout);
1070 uss820dci_root_intr(struct uss820dci_softc *sc)
1074 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1077 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
1079 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1080 sizeof(sc->sc_hub_idata));
1084 uss820dci_standard_done_sub(struct usb_xfer *xfer)
1086 struct uss820dci_td *td;
1092 td = xfer->td_transfer_cache;
1095 len = td->remainder;
1097 if (xfer->aframes != xfer->nframes) {
1099 * Verify the length and subtract
1100 * the remainder from "frlengths[]":
1102 if (len > xfer->frlengths[xfer->aframes]) {
1105 xfer->frlengths[xfer->aframes] -= len;
1108 /* Check for transfer error */
1110 /* the transfer is finished */
1115 /* Check for short transfer */
1117 if (xfer->flags_int.short_frames_ok) {
1118 /* follow alt next */
1125 /* the transfer is finished */
1133 /* this USB frame is complete */
1139 /* update transfer cache */
1141 xfer->td_transfer_cache = td;
1144 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1148 uss820dci_standard_done(struct usb_xfer *xfer)
1150 usb_error_t err = 0;
1152 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1153 xfer, xfer->endpoint);
1157 xfer->td_transfer_cache = xfer->td_transfer_first;
1159 if (xfer->flags_int.control_xfr) {
1161 if (xfer->flags_int.control_hdr) {
1163 err = uss820dci_standard_done_sub(xfer);
1167 if (xfer->td_transfer_cache == NULL) {
1171 while (xfer->aframes != xfer->nframes) {
1173 err = uss820dci_standard_done_sub(xfer);
1176 if (xfer->td_transfer_cache == NULL) {
1181 if (xfer->flags_int.control_xfr &&
1182 !xfer->flags_int.control_act) {
1184 err = uss820dci_standard_done_sub(xfer);
1187 uss820dci_device_done(xfer, err);
1190 /*------------------------------------------------------------------------*
1191 * uss820dci_device_done
1193 * NOTE: this function can be called more than one time on the
1194 * same USB transfer!
1195 *------------------------------------------------------------------------*/
1197 uss820dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1199 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1201 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1202 xfer, xfer->endpoint, error);
1204 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1205 uss820dci_intr_set(xfer, 0);
1207 /* dequeue transfer and start next transfer */
1208 usbd_transfer_done(xfer, error);
1212 uss820dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1213 struct usb_endpoint *ep, uint8_t *did_stall)
1215 struct uss820dci_softc *sc;
1221 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1223 DPRINTFN(5, "endpoint=%p\n", ep);
1226 /* cancel any ongoing transfers */
1227 uss820dci_device_done(xfer, USB_ERR_STALLED);
1229 /* set FORCESTALL */
1230 sc = USS820_DCI_BUS2SC(udev->bus);
1231 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1232 ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
1233 ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
1235 if (ep_type == UE_CONTROL) {
1236 /* should not happen */
1239 USS820_WRITE_1(sc, USS820_EPINDEX, ep_no);
1241 if (ep_dir == UE_DIR_IN) {
1242 temp = USS820_EPCON_TXSTL;
1244 temp = USS820_EPCON_RXSTL;
1246 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp);
1250 uss820dci_clear_stall_sub(struct uss820dci_softc *sc,
1251 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
1255 if (ep_type == UE_CONTROL) {
1256 /* clearing stall is not needed */
1259 /* select endpoint index */
1260 USS820_WRITE_1(sc, USS820_EPINDEX, ep_no);
1262 /* clear stall and disable I/O transfers */
1263 if (ep_dir == UE_DIR_IN) {
1264 temp = 0xFF ^ (USS820_EPCON_TXOE |
1265 USS820_EPCON_TXSTL);
1267 temp = 0xFF ^ (USS820_EPCON_RXIE |
1268 USS820_EPCON_RXSTL);
1270 uss820dci_update_shared_1(sc, USS820_EPCON, temp, 0);
1272 if (ep_dir == UE_DIR_IN) {
1273 /* reset data toggle */
1274 USS820_WRITE_1(sc, USS820_TXSTAT,
1275 USS820_TXSTAT_TXSOVW);
1278 temp = USS820_READ_1(sc, USS820_TXCON);
1279 temp |= USS820_TXCON_TXCLR;
1280 USS820_WRITE_1(sc, USS820_TXCON, temp);
1281 temp &= ~USS820_TXCON_TXCLR;
1282 USS820_WRITE_1(sc, USS820_TXCON, temp);
1285 /* reset data toggle */
1286 uss820dci_update_shared_1(sc, USS820_RXSTAT,
1287 0, USS820_RXSTAT_RXSOVW);
1290 temp = USS820_READ_1(sc, USS820_RXCON);
1291 temp |= USS820_RXCON_RXCLR;
1292 temp &= ~USS820_RXCON_RXFFRC;
1293 USS820_WRITE_1(sc, USS820_RXCON, temp);
1294 temp &= ~USS820_RXCON_RXCLR;
1295 USS820_WRITE_1(sc, USS820_RXCON, temp);
1300 uss820dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1302 struct uss820dci_softc *sc;
1303 struct usb_endpoint_descriptor *ed;
1305 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1307 DPRINTFN(5, "endpoint=%p\n", ep);
1310 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1315 sc = USS820_DCI_BUS2SC(udev->bus);
1317 /* get endpoint descriptor */
1320 /* reset endpoint */
1321 uss820dci_clear_stall_sub(sc,
1322 (ed->bEndpointAddress & UE_ADDR),
1323 (ed->bmAttributes & UE_XFERTYPE),
1324 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1328 uss820dci_init(struct uss820dci_softc *sc)
1330 const struct usb_hw_ep_profile *pf;
1336 /* set up the bus structure */
1337 sc->sc_bus.usbrev = USB_REV_1_1;
1338 sc->sc_bus.methods = &uss820dci_bus_methods;
1340 USB_BUS_LOCK(&sc->sc_bus);
1342 /* we always have VBUS */
1343 sc->sc_flags.status_vbus = 1;
1345 /* reset the chip */
1346 USS820_WRITE_1(sc, USS820_SCR, USS820_SCR_SRESET);
1348 USS820_WRITE_1(sc, USS820_SCR, 0);
1350 /* wait for reset to complete */
1353 temp = USS820_READ_1(sc, USS820_MCSR);
1355 if (temp & USS820_MCSR_INIT) {
1359 USB_BUS_UNLOCK(&sc->sc_bus);
1360 return (USB_ERR_INVAL);
1362 /* wait a little for things to stabilise */
1367 uss820dci_pull_down(sc);
1369 /* wait 10ms for pulldown to stabilise */
1370 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1372 /* check hardware revision */
1373 temp = USS820_READ_1(sc, USS820_REV);
1376 USB_BUS_UNLOCK(&sc->sc_bus);
1377 return (USB_ERR_INVAL);
1379 /* enable interrupts */
1380 USS820_WRITE_1(sc, USS820_SCR,
1382 USS820_SCR_IE_RESET |
1383 /* USS820_SCR_RWUPE | */
1384 USS820_SCR_IE_SUSP |
1387 /* enable interrupts */
1388 USS820_WRITE_1(sc, USS820_SCRATCH,
1389 USS820_SCRATCH_IE_RESUME);
1391 /* enable features */
1392 USS820_WRITE_1(sc, USS820_MCSR,
1393 USS820_MCSR_BDFEAT |
1396 sc->sc_flags.mcsr_feat = 1;
1398 /* disable interrupts */
1399 USS820_WRITE_1(sc, USS820_SBIE, 0);
1401 /* disable interrupts */
1402 USS820_WRITE_1(sc, USS820_SBIE1, 0);
1404 /* disable all endpoints */
1405 for (n = 0; n != USS820_EP_MAX; n++) {
1407 /* select endpoint */
1408 USS820_WRITE_1(sc, USS820_EPINDEX, n);
1410 /* disable endpoint */
1411 uss820dci_update_shared_1(sc, USS820_EPCON, 0, 0);
1415 * Initialise default values for some registers that cannot be
1416 * changed during operation!
1418 for (n = 0; n != USS820_EP_MAX; n++) {
1420 uss820dci_get_hw_ep_profile(NULL, &pf, n);
1422 /* the maximum frame sizes should be the same */
1423 if (pf->max_in_frame_size != pf->max_out_frame_size) {
1424 DPRINTF("Max frame size mismatch %u != %u\n",
1425 pf->max_in_frame_size, pf->max_out_frame_size);
1427 if (pf->support_isochronous) {
1428 if (pf->max_in_frame_size <= 64) {
1429 temp = (USS820_TXCON_FFSZ_16_64 |
1430 USS820_TXCON_TXISO |
1432 } else if (pf->max_in_frame_size <= 256) {
1433 temp = (USS820_TXCON_FFSZ_64_256 |
1434 USS820_TXCON_TXISO |
1436 } else if (pf->max_in_frame_size <= 512) {
1437 temp = (USS820_TXCON_FFSZ_8_512 |
1438 USS820_TXCON_TXISO |
1440 } else { /* 1024 bytes */
1441 temp = (USS820_TXCON_FFSZ_32_1024 |
1442 USS820_TXCON_TXISO |
1446 if ((pf->max_in_frame_size <= 8) &&
1447 (sc->sc_flags.mcsr_feat)) {
1448 temp = (USS820_TXCON_FFSZ_8_512 |
1450 } else if (pf->max_in_frame_size <= 16) {
1451 temp = (USS820_TXCON_FFSZ_16_64 |
1453 } else if ((pf->max_in_frame_size <= 32) &&
1454 (sc->sc_flags.mcsr_feat)) {
1455 temp = (USS820_TXCON_FFSZ_32_1024 |
1457 } else { /* 64 bytes */
1458 temp = (USS820_TXCON_FFSZ_64_256 |
1463 /* need to configure the chip early */
1465 USS820_WRITE_1(sc, USS820_EPINDEX, n);
1466 USS820_WRITE_1(sc, USS820_TXCON, temp);
1467 USS820_WRITE_1(sc, USS820_RXCON, temp);
1469 if (pf->support_control) {
1470 temp = USS820_EPCON_CTLEP |
1471 USS820_EPCON_RXSPM |
1473 USS820_EPCON_RXEPEN |
1475 USS820_EPCON_TXEPEN;
1477 temp = USS820_EPCON_RXEPEN | USS820_EPCON_TXEPEN;
1480 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp);
1483 USB_BUS_UNLOCK(&sc->sc_bus);
1485 /* catch any lost interrupts */
1487 uss820dci_do_poll(&sc->sc_bus);
1489 return (0); /* success */
1493 uss820dci_uninit(struct uss820dci_softc *sc)
1497 USB_BUS_LOCK(&sc->sc_bus);
1499 /* disable all interrupts */
1500 temp = USS820_READ_1(sc, USS820_SCR);
1501 temp &= ~USS820_SCR_T_IRQ;
1502 USS820_WRITE_1(sc, USS820_SCR, temp);
1504 sc->sc_flags.port_powered = 0;
1505 sc->sc_flags.status_vbus = 0;
1506 sc->sc_flags.status_bus_reset = 0;
1507 sc->sc_flags.status_suspend = 0;
1508 sc->sc_flags.change_suspend = 0;
1509 sc->sc_flags.change_connect = 1;
1511 uss820dci_pull_down(sc);
1512 USB_BUS_UNLOCK(&sc->sc_bus);
1516 uss820dci_suspend(struct uss820dci_softc *sc)
1522 uss820dci_resume(struct uss820dci_softc *sc)
1528 uss820dci_do_poll(struct usb_bus *bus)
1530 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus);
1532 USB_BUS_LOCK(&sc->sc_bus);
1533 uss820dci_interrupt_poll(sc);
1534 USB_BUS_UNLOCK(&sc->sc_bus);
1537 /*------------------------------------------------------------------------*
1538 * at91dci bulk support
1539 *------------------------------------------------------------------------*/
1541 uss820dci_device_bulk_open(struct usb_xfer *xfer)
1547 uss820dci_device_bulk_close(struct usb_xfer *xfer)
1549 uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1553 uss820dci_device_bulk_enter(struct usb_xfer *xfer)
1559 uss820dci_device_bulk_start(struct usb_xfer *xfer)
1562 uss820dci_setup_standard_chain(xfer);
1563 uss820dci_start_standard_chain(xfer);
1566 struct usb_pipe_methods uss820dci_device_bulk_methods =
1568 .open = uss820dci_device_bulk_open,
1569 .close = uss820dci_device_bulk_close,
1570 .enter = uss820dci_device_bulk_enter,
1571 .start = uss820dci_device_bulk_start,
1574 /*------------------------------------------------------------------------*
1575 * at91dci control support
1576 *------------------------------------------------------------------------*/
1578 uss820dci_device_ctrl_open(struct usb_xfer *xfer)
1584 uss820dci_device_ctrl_close(struct usb_xfer *xfer)
1586 uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1590 uss820dci_device_ctrl_enter(struct usb_xfer *xfer)
1596 uss820dci_device_ctrl_start(struct usb_xfer *xfer)
1599 uss820dci_setup_standard_chain(xfer);
1600 uss820dci_start_standard_chain(xfer);
1603 struct usb_pipe_methods uss820dci_device_ctrl_methods =
1605 .open = uss820dci_device_ctrl_open,
1606 .close = uss820dci_device_ctrl_close,
1607 .enter = uss820dci_device_ctrl_enter,
1608 .start = uss820dci_device_ctrl_start,
1611 /*------------------------------------------------------------------------*
1612 * at91dci interrupt support
1613 *------------------------------------------------------------------------*/
1615 uss820dci_device_intr_open(struct usb_xfer *xfer)
1621 uss820dci_device_intr_close(struct usb_xfer *xfer)
1623 uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1627 uss820dci_device_intr_enter(struct usb_xfer *xfer)
1633 uss820dci_device_intr_start(struct usb_xfer *xfer)
1636 uss820dci_setup_standard_chain(xfer);
1637 uss820dci_start_standard_chain(xfer);
1640 struct usb_pipe_methods uss820dci_device_intr_methods =
1642 .open = uss820dci_device_intr_open,
1643 .close = uss820dci_device_intr_close,
1644 .enter = uss820dci_device_intr_enter,
1645 .start = uss820dci_device_intr_start,
1648 /*------------------------------------------------------------------------*
1649 * at91dci full speed isochronous support
1650 *------------------------------------------------------------------------*/
1652 uss820dci_device_isoc_fs_open(struct usb_xfer *xfer)
1658 uss820dci_device_isoc_fs_close(struct usb_xfer *xfer)
1660 uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1664 uss820dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1666 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
1670 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1671 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1673 /* get the current frame index - we don't need the high bits */
1675 nframes = USS820_READ_1(sc, USS820_SOFL);
1678 * check if the frame index is within the window where the
1679 * frames will be inserted
1681 temp = (nframes - xfer->endpoint->isoc_next) & USS820_SOFL_MASK;
1683 if ((xfer->endpoint->is_synced == 0) ||
1684 (temp < xfer->nframes)) {
1686 * If there is data underflow or the pipe queue is
1687 * empty we schedule the transfer a few frames ahead
1688 * of the current frame position. Else two isochronous
1689 * transfers might overlap.
1691 xfer->endpoint->isoc_next = (nframes + 3) & USS820_SOFL_MASK;
1692 xfer->endpoint->is_synced = 1;
1693 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1696 * compute how many milliseconds the insertion is ahead of the
1697 * current frame position:
1699 temp = (xfer->endpoint->isoc_next - nframes) & USS820_SOFL_MASK;
1702 * pre-compute when the isochronous transfer will be finished:
1704 xfer->isoc_time_complete =
1705 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1708 /* compute frame number for next insertion */
1709 xfer->endpoint->isoc_next += xfer->nframes;
1712 uss820dci_setup_standard_chain(xfer);
1716 uss820dci_device_isoc_fs_start(struct usb_xfer *xfer)
1718 /* start TD chain */
1719 uss820dci_start_standard_chain(xfer);
1722 struct usb_pipe_methods uss820dci_device_isoc_fs_methods =
1724 .open = uss820dci_device_isoc_fs_open,
1725 .close = uss820dci_device_isoc_fs_close,
1726 .enter = uss820dci_device_isoc_fs_enter,
1727 .start = uss820dci_device_isoc_fs_start,
1730 /*------------------------------------------------------------------------*
1731 * at91dci root control support
1732 *------------------------------------------------------------------------*
1733 * Simulate a hardware HUB by handling all the necessary requests.
1734 *------------------------------------------------------------------------*/
1736 static const struct usb_device_descriptor uss820dci_devd = {
1737 .bLength = sizeof(struct usb_device_descriptor),
1738 .bDescriptorType = UDESC_DEVICE,
1739 .bcdUSB = {0x00, 0x02},
1740 .bDeviceClass = UDCLASS_HUB,
1741 .bDeviceSubClass = UDSUBCLASS_HUB,
1742 .bDeviceProtocol = UDPROTO_FSHUB,
1743 .bMaxPacketSize = 64,
1744 .bcdDevice = {0x00, 0x01},
1747 .bNumConfigurations = 1,
1750 static const struct usb_device_qualifier uss820dci_odevd = {
1751 .bLength = sizeof(struct usb_device_qualifier),
1752 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1753 .bcdUSB = {0x00, 0x02},
1754 .bDeviceClass = UDCLASS_HUB,
1755 .bDeviceSubClass = UDSUBCLASS_HUB,
1756 .bDeviceProtocol = UDPROTO_FSHUB,
1757 .bMaxPacketSize0 = 0,
1758 .bNumConfigurations = 0,
1761 static const struct uss820dci_config_desc uss820dci_confd = {
1763 .bLength = sizeof(struct usb_config_descriptor),
1764 .bDescriptorType = UDESC_CONFIG,
1765 .wTotalLength[0] = sizeof(uss820dci_confd),
1767 .bConfigurationValue = 1,
1768 .iConfiguration = 0,
1769 .bmAttributes = UC_SELF_POWERED,
1773 .bLength = sizeof(struct usb_interface_descriptor),
1774 .bDescriptorType = UDESC_INTERFACE,
1776 .bInterfaceClass = UICLASS_HUB,
1777 .bInterfaceSubClass = UISUBCLASS_HUB,
1778 .bInterfaceProtocol = 0,
1782 .bLength = sizeof(struct usb_endpoint_descriptor),
1783 .bDescriptorType = UDESC_ENDPOINT,
1784 .bEndpointAddress = (UE_DIR_IN | USS820_DCI_INTR_ENDPT),
1785 .bmAttributes = UE_INTERRUPT,
1786 .wMaxPacketSize[0] = 8,
1791 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1793 static const struct usb_hub_descriptor_min uss820dci_hubd = {
1794 .bDescLength = sizeof(uss820dci_hubd),
1795 .bDescriptorType = UDESC_HUB,
1797 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1798 .bPwrOn2PwrGood = 50,
1799 .bHubContrCurrent = 0,
1800 .DeviceRemovable = {0}, /* port is removable */
1803 #define STRING_LANG \
1804 0x09, 0x04, /* American English */
1806 #define STRING_VENDOR \
1807 'A', 0, 'G', 0, 'E', 0, 'R', 0, 'E', 0
1809 #define STRING_PRODUCT \
1810 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1811 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1814 USB_MAKE_STRING_DESC(STRING_LANG, uss820dci_langtab);
1815 USB_MAKE_STRING_DESC(STRING_VENDOR, uss820dci_vendor);
1816 USB_MAKE_STRING_DESC(STRING_PRODUCT, uss820dci_product);
1819 uss820dci_roothub_exec(struct usb_device *udev,
1820 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1822 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus);
1829 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1832 ptr = (const void *)&sc->sc_hub_temp;
1836 value = UGETW(req->wValue);
1837 index = UGETW(req->wIndex);
1839 /* demultiplex the control request */
1841 switch (req->bmRequestType) {
1842 case UT_READ_DEVICE:
1843 switch (req->bRequest) {
1844 case UR_GET_DESCRIPTOR:
1845 goto tr_handle_get_descriptor;
1847 goto tr_handle_get_config;
1849 goto tr_handle_get_status;
1855 case UT_WRITE_DEVICE:
1856 switch (req->bRequest) {
1857 case UR_SET_ADDRESS:
1858 goto tr_handle_set_address;
1860 goto tr_handle_set_config;
1861 case UR_CLEAR_FEATURE:
1862 goto tr_valid; /* nop */
1863 case UR_SET_DESCRIPTOR:
1864 goto tr_valid; /* nop */
1865 case UR_SET_FEATURE:
1871 case UT_WRITE_ENDPOINT:
1872 switch (req->bRequest) {
1873 case UR_CLEAR_FEATURE:
1874 switch (UGETW(req->wValue)) {
1875 case UF_ENDPOINT_HALT:
1876 goto tr_handle_clear_halt;
1877 case UF_DEVICE_REMOTE_WAKEUP:
1878 goto tr_handle_clear_wakeup;
1883 case UR_SET_FEATURE:
1884 switch (UGETW(req->wValue)) {
1885 case UF_ENDPOINT_HALT:
1886 goto tr_handle_set_halt;
1887 case UF_DEVICE_REMOTE_WAKEUP:
1888 goto tr_handle_set_wakeup;
1893 case UR_SYNCH_FRAME:
1894 goto tr_valid; /* nop */
1900 case UT_READ_ENDPOINT:
1901 switch (req->bRequest) {
1903 goto tr_handle_get_ep_status;
1909 case UT_WRITE_INTERFACE:
1910 switch (req->bRequest) {
1911 case UR_SET_INTERFACE:
1912 goto tr_handle_set_interface;
1913 case UR_CLEAR_FEATURE:
1914 goto tr_valid; /* nop */
1915 case UR_SET_FEATURE:
1921 case UT_READ_INTERFACE:
1922 switch (req->bRequest) {
1923 case UR_GET_INTERFACE:
1924 goto tr_handle_get_interface;
1926 goto tr_handle_get_iface_status;
1932 case UT_WRITE_CLASS_INTERFACE:
1933 case UT_WRITE_VENDOR_INTERFACE:
1937 case UT_READ_CLASS_INTERFACE:
1938 case UT_READ_VENDOR_INTERFACE:
1942 case UT_WRITE_CLASS_DEVICE:
1943 switch (req->bRequest) {
1944 case UR_CLEAR_FEATURE:
1946 case UR_SET_DESCRIPTOR:
1947 case UR_SET_FEATURE:
1954 case UT_WRITE_CLASS_OTHER:
1955 switch (req->bRequest) {
1956 case UR_CLEAR_FEATURE:
1957 goto tr_handle_clear_port_feature;
1958 case UR_SET_FEATURE:
1959 goto tr_handle_set_port_feature;
1960 case UR_CLEAR_TT_BUFFER:
1970 case UT_READ_CLASS_OTHER:
1971 switch (req->bRequest) {
1972 case UR_GET_TT_STATE:
1973 goto tr_handle_get_tt_state;
1975 goto tr_handle_get_port_status;
1981 case UT_READ_CLASS_DEVICE:
1982 switch (req->bRequest) {
1983 case UR_GET_DESCRIPTOR:
1984 goto tr_handle_get_class_descriptor;
1986 goto tr_handle_get_class_status;
1997 tr_handle_get_descriptor:
1998 switch (value >> 8) {
2003 len = sizeof(uss820dci_devd);
2004 ptr = (const void *)&uss820dci_devd;
2010 len = sizeof(uss820dci_confd);
2011 ptr = (const void *)&uss820dci_confd;
2014 switch (value & 0xff) {
2015 case 0: /* Language table */
2016 len = sizeof(uss820dci_langtab);
2017 ptr = (const void *)&uss820dci_langtab;
2020 case 1: /* Vendor */
2021 len = sizeof(uss820dci_vendor);
2022 ptr = (const void *)&uss820dci_vendor;
2025 case 2: /* Product */
2026 len = sizeof(uss820dci_product);
2027 ptr = (const void *)&uss820dci_product;
2038 tr_handle_get_config:
2040 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2043 tr_handle_get_status:
2045 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2048 tr_handle_set_address:
2049 if (value & 0xFF00) {
2052 sc->sc_rt_addr = value;
2055 tr_handle_set_config:
2059 sc->sc_conf = value;
2062 tr_handle_get_interface:
2064 sc->sc_hub_temp.wValue[0] = 0;
2067 tr_handle_get_tt_state:
2068 tr_handle_get_class_status:
2069 tr_handle_get_iface_status:
2070 tr_handle_get_ep_status:
2072 USETW(sc->sc_hub_temp.wValue, 0);
2076 tr_handle_set_interface:
2077 tr_handle_set_wakeup:
2078 tr_handle_clear_wakeup:
2079 tr_handle_clear_halt:
2082 tr_handle_clear_port_feature:
2086 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2089 case UHF_PORT_SUSPEND:
2090 uss820dci_wakeup_peer(sc);
2093 case UHF_PORT_ENABLE:
2094 sc->sc_flags.port_enabled = 0;
2098 case UHF_PORT_INDICATOR:
2099 case UHF_C_PORT_ENABLE:
2100 case UHF_C_PORT_OVER_CURRENT:
2101 case UHF_C_PORT_RESET:
2104 case UHF_PORT_POWER:
2105 sc->sc_flags.port_powered = 0;
2106 uss820dci_pull_down(sc);
2108 case UHF_C_PORT_CONNECTION:
2109 sc->sc_flags.change_connect = 0;
2111 case UHF_C_PORT_SUSPEND:
2112 sc->sc_flags.change_suspend = 0;
2115 err = USB_ERR_IOERROR;
2120 tr_handle_set_port_feature:
2124 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2127 case UHF_PORT_ENABLE:
2128 sc->sc_flags.port_enabled = 1;
2130 case UHF_PORT_SUSPEND:
2131 case UHF_PORT_RESET:
2133 case UHF_PORT_INDICATOR:
2136 case UHF_PORT_POWER:
2137 sc->sc_flags.port_powered = 1;
2140 err = USB_ERR_IOERROR;
2145 tr_handle_get_port_status:
2147 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2152 if (sc->sc_flags.status_vbus) {
2153 uss820dci_pull_up(sc);
2155 uss820dci_pull_down(sc);
2158 /* Select FULL-speed and Device Side Mode */
2160 value = UPS_PORT_MODE_DEVICE;
2162 if (sc->sc_flags.port_powered) {
2163 value |= UPS_PORT_POWER;
2165 if (sc->sc_flags.port_enabled) {
2166 value |= UPS_PORT_ENABLED;
2168 if (sc->sc_flags.status_vbus &&
2169 sc->sc_flags.status_bus_reset) {
2170 value |= UPS_CURRENT_CONNECT_STATUS;
2172 if (sc->sc_flags.status_suspend) {
2173 value |= UPS_SUSPEND;
2175 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2179 if (sc->sc_flags.change_connect) {
2180 value |= UPS_C_CONNECT_STATUS;
2182 if (sc->sc_flags.change_suspend) {
2183 value |= UPS_C_SUSPEND;
2185 USETW(sc->sc_hub_temp.ps.wPortChange, value);
2186 len = sizeof(sc->sc_hub_temp.ps);
2189 tr_handle_get_class_descriptor:
2193 ptr = (const void *)&uss820dci_hubd;
2194 len = sizeof(uss820dci_hubd);
2198 err = USB_ERR_STALLED;
2207 uss820dci_xfer_setup(struct usb_setup_params *parm)
2209 const struct usb_hw_ep_profile *pf;
2210 struct uss820dci_softc *sc;
2211 struct usb_xfer *xfer;
2217 sc = USS820_DCI_BUS2SC(parm->udev->bus);
2218 xfer = parm->curr_xfer;
2221 * NOTE: This driver does not use any of the parameters that
2222 * are computed from the following values. Just set some
2223 * reasonable dummies:
2225 parm->hc_max_packet_size = 0x500;
2226 parm->hc_max_packet_count = 1;
2227 parm->hc_max_frame_size = 0x500;
2229 usbd_transfer_setup_sub(parm);
2232 * compute maximum number of TDs
2234 if (parm->methods == &uss820dci_device_ctrl_methods) {
2236 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
2238 } else if (parm->methods == &uss820dci_device_bulk_methods) {
2240 ntd = xfer->nframes + 1 /* SYNC */ ;
2242 } else if (parm->methods == &uss820dci_device_intr_methods) {
2244 ntd = xfer->nframes + 1 /* SYNC */ ;
2246 } else if (parm->methods == &uss820dci_device_isoc_fs_methods) {
2248 ntd = xfer->nframes + 1 /* SYNC */ ;
2256 * check if "usbd_transfer_setup_sub" set an error
2262 * allocate transfer descriptors
2271 ep_no = xfer->endpointno & UE_ADDR;
2272 uss820dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2275 /* should not happen */
2276 parm->err = USB_ERR_INVAL;
2285 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2287 for (n = 0; n != ntd; n++) {
2289 struct uss820dci_td *td;
2293 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2296 td->io_tag = sc->sc_io_tag;
2297 td->io_hdl = sc->sc_io_hdl;
2298 td->max_packet_size = xfer->max_packet_size;
2299 td->ep_index = ep_no;
2300 if (pf->support_multi_buffer &&
2301 (parm->methods != &uss820dci_device_ctrl_methods)) {
2302 td->support_multi_buffer = 1;
2304 td->obj_next = last_obj;
2308 parm->size[0] += sizeof(*td);
2311 xfer->td_start[0] = last_obj;
2315 uss820dci_xfer_unsetup(struct usb_xfer *xfer)
2321 uss820dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2322 struct usb_endpoint *ep)
2324 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus);
2326 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2328 edesc->bEndpointAddress, udev->flags.usb_mode,
2331 if (udev->device_index != sc->sc_rt_addr) {
2333 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2337 if (udev->speed != USB_SPEED_FULL) {
2341 switch (edesc->bmAttributes & UE_XFERTYPE) {
2343 ep->methods = &uss820dci_device_ctrl_methods;
2346 ep->methods = &uss820dci_device_intr_methods;
2348 case UE_ISOCHRONOUS:
2349 ep->methods = &uss820dci_device_isoc_fs_methods;
2352 ep->methods = &uss820dci_device_bulk_methods;
2362 uss820dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2364 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus);
2367 case USB_HW_POWER_SUSPEND:
2368 uss820dci_suspend(sc);
2370 case USB_HW_POWER_SHUTDOWN:
2371 uss820dci_uninit(sc);
2373 case USB_HW_POWER_RESUME:
2374 uss820dci_resume(sc);
2381 struct usb_bus_methods uss820dci_bus_methods =
2383 .endpoint_init = &uss820dci_ep_init,
2384 .xfer_setup = &uss820dci_xfer_setup,
2385 .xfer_unsetup = &uss820dci_xfer_unsetup,
2386 .get_hw_ep_profile = &uss820dci_get_hw_ep_profile,
2387 .set_stall = &uss820dci_set_stall,
2388 .clear_stall = &uss820dci_clear_stall,
2389 .roothub_exec = &uss820dci_roothub_exec,
2390 .xfer_poll = &uss820dci_do_poll,
2391 .set_hw_power_sleep = uss820dci_set_hw_power_sleep,