2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
89 static int xhcipolling;
91 SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
93 &xhcidebug, 0, "Debug level");
94 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
96 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
97 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
99 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
100 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
105 #define XHCI_INTR_ENDPT 1
107 struct xhci_std_temp {
108 struct xhci_softc *sc;
109 struct usb_page_cache *pc;
111 struct xhci_td *td_next;
114 uint32_t max_packet_size;
126 uint8_t do_isoc_sync;
129 static void xhci_do_poll(struct usb_bus *);
130 static void xhci_device_done(struct usb_xfer *, usb_error_t);
131 static void xhci_root_intr(struct xhci_softc *);
132 static void xhci_free_device_ext(struct usb_device *);
133 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
134 struct usb_endpoint_descriptor *);
135 static usb_proc_callback_t xhci_configure_msg;
136 static usb_error_t xhci_configure_device(struct usb_device *);
137 static usb_error_t xhci_configure_endpoint(struct usb_device *,
138 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
139 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
140 static usb_error_t xhci_configure_mask(struct usb_device *,
142 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
144 static void xhci_endpoint_doorbell(struct usb_xfer *);
145 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
146 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
147 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
149 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
152 extern struct usb_bus_methods xhci_bus_methods;
156 xhci_dump_trb(struct xhci_trb *trb)
158 DPRINTFN(5, "trb = %p\n", trb);
159 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
160 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
161 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
165 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
167 DPRINTFN(5, "pep = %p\n", pep);
168 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
169 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
170 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
171 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
172 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
173 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
174 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
178 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
180 DPRINTFN(5, "psl = %p\n", psl);
181 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
182 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
183 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
184 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
189 xhci_use_polling(void)
192 return (xhcipolling != 0);
199 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
201 struct xhci_softc *sc = XHCI_BUS2SC(bus);
204 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
205 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
207 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
208 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
210 for (i = 0; i != sc->sc_noscratch; i++) {
211 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
212 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
217 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
219 if (sc->sc_ctx_is_64_byte) {
221 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
222 /* all contexts are initially 32-bytes */
223 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
224 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
230 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
232 if (sc->sc_ctx_is_64_byte) {
234 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
235 /* all contexts are initially 32-bytes */
236 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
237 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
239 return (le32toh(*ptr));
243 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
245 if (sc->sc_ctx_is_64_byte) {
247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
248 /* all contexts are initially 32-bytes */
249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
250 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
257 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
259 if (sc->sc_ctx_is_64_byte) {
261 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
262 /* all contexts are initially 32-bytes */
263 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
264 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
266 return (le64toh(*ptr));
271 xhci_reset_command_queue_locked(struct xhci_softc *sc)
273 struct usb_page_search buf_res;
274 struct xhci_hw_root *phwr;
280 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
281 if (temp & XHCI_CRCR_LO_CRR) {
282 DPRINTF("Command ring running\n");
283 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
286 * Try to abort the last command as per section
287 * 4.6.1.2 "Aborting a Command" of the XHCI
291 /* stop and cancel */
292 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
293 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
295 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
296 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
299 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
301 /* check if command ring is still running */
302 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
303 if (temp & XHCI_CRCR_LO_CRR) {
304 DPRINTF("Comand ring still running\n");
305 return (USB_ERR_IOERROR);
309 /* reset command ring */
310 sc->sc_command_ccs = 1;
311 sc->sc_command_idx = 0;
313 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
315 /* setup command ring control base address */
316 addr = buf_res.physaddr;
317 phwr = buf_res.buffer;
318 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
320 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
322 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
323 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
325 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
327 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
328 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
334 xhci_start_controller(struct xhci_softc *sc)
336 struct usb_page_search buf_res;
337 struct xhci_hw_root *phwr;
338 struct xhci_dev_ctx_addr *pdctxa;
346 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
347 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
348 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
350 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
351 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
352 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
354 sc->sc_event_ccs = 1;
355 sc->sc_event_idx = 0;
356 sc->sc_command_ccs = 1;
357 sc->sc_command_idx = 0;
359 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
361 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
363 DPRINTF("HCS0 = 0x%08x\n", temp);
365 if (XHCI_HCS0_CSZ(temp)) {
366 sc->sc_ctx_is_64_byte = 1;
367 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
369 sc->sc_ctx_is_64_byte = 0;
370 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
373 /* Reset controller */
374 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
376 for (i = 0; i != 100; i++) {
377 usb_pause_mtx(NULL, hz / 100);
378 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
379 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
385 device_printf(sc->sc_bus.parent, "Controller "
387 return (USB_ERR_IOERROR);
390 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
391 device_printf(sc->sc_bus.parent, "Controller does "
392 "not support 4K page size.\n");
393 return (USB_ERR_IOERROR);
396 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
398 i = XHCI_HCS1_N_PORTS(temp);
401 device_printf(sc->sc_bus.parent, "Invalid number "
402 "of ports: %u\n", i);
403 return (USB_ERR_IOERROR);
407 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
409 if (sc->sc_noslot > XHCI_MAX_DEVICES)
410 sc->sc_noslot = XHCI_MAX_DEVICES;
412 /* setup number of device slots */
414 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
415 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
417 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
419 DPRINTF("Max slots: %u\n", sc->sc_noslot);
421 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
423 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
425 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
426 device_printf(sc->sc_bus.parent, "XHCI request "
427 "too many scratchpads\n");
428 return (USB_ERR_NOMEM);
431 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
433 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
435 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
436 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
438 temp = XREAD4(sc, oper, XHCI_USBSTS);
440 /* clear interrupts */
441 XWRITE4(sc, oper, XHCI_USBSTS, temp);
442 /* disable all device notifications */
443 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
445 /* setup device context base address */
446 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
447 pdctxa = buf_res.buffer;
448 memset(pdctxa, 0, sizeof(*pdctxa));
450 addr = buf_res.physaddr;
451 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
453 /* slot 0 points to the table of scratchpad pointers */
454 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
456 for (i = 0; i != sc->sc_noscratch; i++) {
457 struct usb_page_search buf_scp;
458 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
459 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
462 addr = buf_res.physaddr;
464 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
465 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
466 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
467 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
469 /* Setup event table size */
471 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
473 DPRINTF("HCS2=0x%08x\n", temp);
475 temp = XHCI_HCS2_ERST_MAX(temp);
477 if (temp > XHCI_MAX_RSEG)
478 temp = XHCI_MAX_RSEG;
480 sc->sc_erst_max = temp;
482 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
483 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
485 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
487 /* Check if we should use the default IMOD value */
488 if (sc->sc_imod_default == 0)
489 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
491 /* Setup interrupt rate */
492 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
494 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
496 phwr = buf_res.buffer;
497 addr = buf_res.physaddr;
498 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
500 /* reset hardware root structure */
501 memset(phwr, 0, sizeof(*phwr));
503 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
504 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
506 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
508 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
509 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
511 addr = buf_res.physaddr;
513 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
515 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
516 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
518 /* Setup interrupter registers */
520 temp = XREAD4(sc, runt, XHCI_IMAN(0));
521 temp |= XHCI_IMAN_INTR_ENA;
522 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
524 /* setup command ring control base address */
525 addr = buf_res.physaddr;
526 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
528 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
530 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
531 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
533 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
535 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
538 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
539 XHCI_CMD_INTE | XHCI_CMD_HSEE);
541 for (i = 0; i != 100; i++) {
542 usb_pause_mtx(NULL, hz / 100);
543 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
548 XWRITE4(sc, oper, XHCI_USBCMD, 0);
549 device_printf(sc->sc_bus.parent, "Run timeout.\n");
550 return (USB_ERR_IOERROR);
553 /* catch any lost interrupts */
554 xhci_do_poll(&sc->sc_bus);
556 if (sc->sc_port_route != NULL) {
557 /* Route all ports to the XHCI by default */
558 sc->sc_port_route(sc->sc_bus.parent,
559 ~xhciroute, xhciroute);
565 xhci_halt_controller(struct xhci_softc *sc)
573 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
574 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
575 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
577 /* Halt controller */
578 XWRITE4(sc, oper, XHCI_USBCMD, 0);
580 for (i = 0; i != 100; i++) {
581 usb_pause_mtx(NULL, hz / 100);
582 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
588 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
589 return (USB_ERR_IOERROR);
595 xhci_init(struct xhci_softc *sc, device_t self)
597 /* initialise some bus fields */
598 sc->sc_bus.parent = self;
600 /* set the bus revision */
601 sc->sc_bus.usbrev = USB_REV_3_0;
603 /* set up the bus struct */
604 sc->sc_bus.methods = &xhci_bus_methods;
606 /* setup devices array */
607 sc->sc_bus.devices = sc->sc_devices;
608 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
610 /* set default cycle state in case of early interrupts */
611 sc->sc_event_ccs = 1;
612 sc->sc_command_ccs = 1;
614 /* setup command queue mutex and condition varible */
615 cv_init(&sc->sc_cmd_cv, "CMDQ");
616 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
618 /* get all DMA memory */
619 if (usb_bus_mem_alloc_all(&sc->sc_bus,
620 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
624 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
625 sc->sc_config_msg[0].bus = &sc->sc_bus;
626 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
627 sc->sc_config_msg[1].bus = &sc->sc_bus;
629 if (usb_proc_create(&sc->sc_config_proc,
630 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
631 printf("WARNING: Creation of XHCI configure "
632 "callback process failed.\n");
638 xhci_uninit(struct xhci_softc *sc)
640 usb_proc_free(&sc->sc_config_proc);
642 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
644 cv_destroy(&sc->sc_cmd_cv);
645 sx_destroy(&sc->sc_cmd_sx);
649 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
651 struct xhci_softc *sc = XHCI_BUS2SC(bus);
654 case USB_HW_POWER_SUSPEND:
655 DPRINTF("Stopping the XHCI\n");
656 xhci_halt_controller(sc);
658 case USB_HW_POWER_SHUTDOWN:
659 DPRINTF("Stopping the XHCI\n");
660 xhci_halt_controller(sc);
662 case USB_HW_POWER_RESUME:
663 DPRINTF("Starting the XHCI\n");
664 xhci_start_controller(sc);
672 xhci_generic_done_sub(struct usb_xfer *xfer)
675 struct xhci_td *td_alt_next;
679 td = xfer->td_transfer_cache;
680 td_alt_next = td->alt_next;
682 if (xfer->aframes != xfer->nframes)
683 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
687 usb_pc_cpu_invalidate(td->page_cache);
692 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
693 xfer, (unsigned int)xfer->aframes,
694 (unsigned int)xfer->nframes,
695 (unsigned int)len, (unsigned int)td->len,
696 (unsigned int)status);
699 * Verify the status length and
700 * add the length to "frlengths[]":
703 /* should not happen */
704 DPRINTF("Invalid status length, "
705 "0x%04x/0x%04x bytes\n", len, td->len);
706 status = XHCI_TRB_ERROR_LENGTH;
707 } else if (xfer->aframes != xfer->nframes) {
708 xfer->frlengths[xfer->aframes] += td->len - len;
710 /* Check for last transfer */
711 if (((void *)td) == xfer->td_transfer_last) {
715 /* Check for transfer error */
716 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
717 status != XHCI_TRB_ERROR_SUCCESS) {
718 /* the transfer is finished */
722 /* Check for short transfer */
724 if (xfer->flags_int.short_frames_ok ||
725 xfer->flags_int.isochronous_xfr ||
726 xfer->flags_int.control_xfr) {
727 /* follow alt next */
730 /* the transfer is finished */
737 if (td->alt_next != td_alt_next) {
738 /* this USB frame is complete */
743 /* update transfer cache */
745 xfer->td_transfer_cache = td;
747 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
748 (status != XHCI_TRB_ERROR_SHORT_PKT &&
749 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
750 USB_ERR_NORMAL_COMPLETION);
754 xhci_generic_done(struct usb_xfer *xfer)
758 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
759 xfer, xfer->endpoint);
763 xfer->td_transfer_cache = xfer->td_transfer_first;
765 if (xfer->flags_int.control_xfr) {
767 if (xfer->flags_int.control_hdr)
768 err = xhci_generic_done_sub(xfer);
772 if (xfer->td_transfer_cache == NULL)
776 while (xfer->aframes != xfer->nframes) {
778 err = xhci_generic_done_sub(xfer);
781 if (xfer->td_transfer_cache == NULL)
785 if (xfer->flags_int.control_xfr &&
786 !xfer->flags_int.control_act)
787 err = xhci_generic_done_sub(xfer);
789 /* transfer is complete */
790 xhci_device_done(xfer, err);
794 xhci_activate_transfer(struct usb_xfer *xfer)
798 td = xfer->td_transfer_cache;
800 usb_pc_cpu_invalidate(td->page_cache);
802 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
804 /* activate the transfer */
806 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
807 usb_pc_cpu_flush(td->page_cache);
809 xhci_endpoint_doorbell(xfer);
814 xhci_skip_transfer(struct usb_xfer *xfer)
817 struct xhci_td *td_last;
819 td = xfer->td_transfer_cache;
820 td_last = xfer->td_transfer_last;
824 usb_pc_cpu_invalidate(td->page_cache);
826 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
828 usb_pc_cpu_invalidate(td_last->page_cache);
830 /* copy LINK TRB to current waiting location */
832 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
833 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
834 usb_pc_cpu_flush(td->page_cache);
836 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
837 usb_pc_cpu_flush(td->page_cache);
839 xhci_endpoint_doorbell(xfer);
843 /*------------------------------------------------------------------------*
844 * xhci_check_transfer
845 *------------------------------------------------------------------------*/
847 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
860 td_event = le64toh(trb->qwTrb0);
861 temp = le32toh(trb->dwTrb2);
863 remainder = XHCI_TRB_2_REM_GET(temp);
864 status = XHCI_TRB_2_ERROR_GET(temp);
866 temp = le32toh(trb->dwTrb3);
867 epno = XHCI_TRB_3_EP_GET(temp);
868 index = XHCI_TRB_3_SLOT_GET(temp);
870 /* check if error means halted */
871 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
872 status != XHCI_TRB_ERROR_SUCCESS);
874 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
875 index, epno, remainder, status);
877 if (index > sc->sc_noslot) {
878 DPRINTF("Invalid slot.\n");
882 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
883 DPRINTF("Invalid endpoint.\n");
887 /* try to find the USB transfer that generated the event */
888 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
889 struct usb_xfer *xfer;
891 struct xhci_endpoint_ext *pepext;
893 pepext = &sc->sc_hw.devs[index].endp[epno];
895 xfer = pepext->xfer[i];
899 td = xfer->td_transfer_cache;
901 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
903 (long long)td->td_self,
904 (long long)td->td_self + sizeof(td->td_trb));
907 * NOTE: Some XHCI implementations might not trigger
908 * an event on the last LINK TRB so we need to
909 * consider both the last and second last event
910 * address as conditions for a successful transfer.
912 * NOTE: We assume that the XHCI will only trigger one
913 * event per chain of TRBs.
916 offset = td_event - td->td_self;
919 offset < (int64_t)sizeof(td->td_trb)) {
921 usb_pc_cpu_invalidate(td->page_cache);
923 /* compute rest of remainder, if any */
924 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
925 temp = le32toh(td->td_trb[i].dwTrb2);
926 remainder += XHCI_TRB_2_BYTES_GET(temp);
929 DPRINTFN(5, "New remainder: %u\n", remainder);
931 /* clear isochronous transfer errors */
932 if (xfer->flags_int.isochronous_xfr) {
935 status = XHCI_TRB_ERROR_SUCCESS;
940 /* "td->remainder" is verified later */
941 td->remainder = remainder;
944 usb_pc_cpu_flush(td->page_cache);
947 * 1) Last transfer descriptor makes the
950 if (((void *)td) == xfer->td_transfer_last) {
951 DPRINTF("TD is last\n");
952 xhci_generic_done(xfer);
957 * 2) Any kind of error makes the transfer
961 DPRINTF("TD has I/O error\n");
962 xhci_generic_done(xfer);
967 * 3) If there is no alternate next transfer,
968 * a short packet also makes the transfer done
970 if (td->remainder > 0) {
971 if (td->alt_next == NULL) {
973 "short TD has no alternate next\n");
974 xhci_generic_done(xfer);
977 DPRINTF("TD has short pkt\n");
978 if (xfer->flags_int.short_frames_ok ||
979 xfer->flags_int.isochronous_xfr ||
980 xfer->flags_int.control_xfr) {
981 /* follow the alt next */
982 xfer->td_transfer_cache = td->alt_next;
983 xhci_activate_transfer(xfer);
986 xhci_skip_transfer(xfer);
987 xhci_generic_done(xfer);
992 * 4) Transfer complete - go to next TD
994 DPRINTF("Following next TD\n");
995 xfer->td_transfer_cache = td->obj_next;
996 xhci_activate_transfer(xfer);
997 break; /* there should only be one match */
1003 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1005 if (sc->sc_cmd_addr == trb->qwTrb0) {
1006 DPRINTF("Received command event\n");
1007 sc->sc_cmd_result[0] = trb->dwTrb2;
1008 sc->sc_cmd_result[1] = trb->dwTrb3;
1009 cv_signal(&sc->sc_cmd_cv);
1010 return (1); /* command match */
1016 xhci_interrupt_poll(struct xhci_softc *sc)
1018 struct usb_page_search buf_res;
1019 struct xhci_hw_root *phwr;
1029 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1031 phwr = buf_res.buffer;
1033 /* Receive any events */
1035 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1037 i = sc->sc_event_idx;
1038 j = sc->sc_event_ccs;
1043 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1045 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1050 event = XHCI_TRB_3_TYPE_GET(temp);
1052 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1053 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1054 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1055 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1058 case XHCI_TRB_EVENT_TRANSFER:
1059 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1061 case XHCI_TRB_EVENT_CMD_COMPLETE:
1062 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1065 DPRINTF("Unhandled event = %u\n", event);
1071 if (i == XHCI_MAX_EVENTS) {
1075 /* check for timeout */
1081 sc->sc_event_idx = i;
1082 sc->sc_event_ccs = j;
1085 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1086 * latched. That means to activate the register we need to
1087 * write both the low and high double word of the 64-bit
1091 addr = buf_res.physaddr;
1092 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1094 /* try to clear busy bit */
1095 addr |= XHCI_ERDP_LO_BUSY;
1097 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1098 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1104 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1105 uint16_t timeout_ms)
1107 struct usb_page_search buf_res;
1108 struct xhci_hw_root *phwr;
1113 uint8_t timeout = 0;
1116 XHCI_CMD_ASSERT_LOCKED(sc);
1118 /* get hardware root structure */
1120 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1122 phwr = buf_res.buffer;
1126 USB_BUS_LOCK(&sc->sc_bus);
1128 i = sc->sc_command_idx;
1129 j = sc->sc_command_ccs;
1131 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1132 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1133 (long long)le64toh(trb->qwTrb0),
1134 (long)le32toh(trb->dwTrb2),
1135 (long)le32toh(trb->dwTrb3));
1137 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1138 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1140 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1145 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1147 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1149 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1151 phwr->hwr_commands[i].dwTrb3 = temp;
1153 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1155 addr = buf_res.physaddr;
1156 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1158 sc->sc_cmd_addr = htole64(addr);
1162 if (i == (XHCI_MAX_COMMANDS - 1)) {
1165 temp = htole32(XHCI_TRB_3_TC_BIT |
1166 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1167 XHCI_TRB_3_CYCLE_BIT);
1169 temp = htole32(XHCI_TRB_3_TC_BIT |
1170 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1173 phwr->hwr_commands[i].dwTrb3 = temp;
1175 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1181 sc->sc_command_idx = i;
1182 sc->sc_command_ccs = j;
1184 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1186 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1187 USB_MS_TO_TICKS(timeout_ms));
1190 * In some error cases event interrupts are not generated.
1191 * Poll one time to see if the command has completed.
1193 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1194 DPRINTF("Command was completed when polling\n");
1198 DPRINTF("Command timeout!\n");
1200 * After some weeks of continuous operation, it has
1201 * been observed that the ASMedia Technology, ASM1042
1202 * SuperSpeed USB Host Controller can suddenly stop
1203 * accepting commands via the command queue. Try to
1204 * first reset the command queue. If that fails do a
1205 * host controller reset.
1208 xhci_reset_command_queue_locked(sc) == 0) {
1209 temp = le32toh(trb->dwTrb3);
1212 * Avoid infinite XHCI reset loops if the set
1213 * address command fails to respond due to a
1214 * non-enumerating device:
1216 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1217 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1218 DPRINTF("Set address timeout\n");
1224 DPRINTF("Controller reset!\n");
1225 usb_bus_reset_async_locked(&sc->sc_bus);
1227 err = USB_ERR_TIMEOUT;
1231 temp = le32toh(sc->sc_cmd_result[0]);
1232 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1233 err = USB_ERR_IOERROR;
1235 trb->dwTrb2 = sc->sc_cmd_result[0];
1236 trb->dwTrb3 = sc->sc_cmd_result[1];
1239 USB_BUS_UNLOCK(&sc->sc_bus);
1246 xhci_cmd_nop(struct xhci_softc *sc)
1248 struct xhci_trb trb;
1255 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1257 trb.dwTrb3 = htole32(temp);
1259 return (xhci_do_command(sc, &trb, 100 /* ms */));
1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1266 struct xhci_trb trb;
1274 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1276 err = xhci_do_command(sc, &trb, 100 /* ms */);
1280 temp = le32toh(trb.dwTrb3);
1282 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1291 struct xhci_trb trb;
1298 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1299 XHCI_TRB_3_SLOT_SET(slot_id);
1301 trb.dwTrb3 = htole32(temp);
1303 return (xhci_do_command(sc, &trb, 100 /* ms */));
1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1308 uint8_t bsr, uint8_t slot_id)
1310 struct xhci_trb trb;
1315 trb.qwTrb0 = htole64(input_ctx);
1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1318 XHCI_TRB_3_SLOT_SET(slot_id);
1321 temp |= XHCI_TRB_3_BSR_BIT;
1323 trb.dwTrb3 = htole32(temp);
1325 return (xhci_do_command(sc, &trb, 500 /* ms */));
1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1331 struct usb_page_search buf_inp;
1332 struct usb_page_search buf_dev;
1333 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1334 struct xhci_hw_dev *hdev;
1335 struct xhci_dev_ctx *pdev;
1336 struct xhci_endpoint_ext *pepext;
1342 /* the root HUB case is not handled here */
1343 if (udev->parent_hub == NULL)
1344 return (USB_ERR_INVAL);
1346 index = udev->controller_slot_id;
1348 hdev = &sc->sc_hw.devs[index];
1355 switch (hdev->state) {
1356 case XHCI_ST_DEFAULT:
1357 case XHCI_ST_ENABLED:
1359 hdev->state = XHCI_ST_ENABLED;
1361 /* set configure mask to slot and EP0 */
1362 xhci_configure_mask(udev, 3, 0);
1364 /* configure input slot context structure */
1365 err = xhci_configure_device(udev);
1368 DPRINTF("Could not configure device\n");
1372 /* configure input endpoint context structure */
1373 switch (udev->speed) {
1375 case USB_SPEED_FULL:
1378 case USB_SPEED_HIGH:
1386 pepext = xhci_get_endpoint_ext(udev,
1387 &udev->ctrl_ep_desc);
1389 /* ensure the control endpoint is setup again */
1390 USB_BUS_LOCK(udev->bus);
1391 pepext->trb_halted = 1;
1392 pepext->trb_running = 0;
1393 USB_BUS_UNLOCK(udev->bus);
1395 err = xhci_configure_endpoint(udev,
1396 &udev->ctrl_ep_desc, pepext,
1397 0, 1, 1, 0, mps, mps);
1400 DPRINTF("Could not configure default endpoint\n");
1404 /* execute set address command */
1405 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1407 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1408 (address == 0), index);
1411 temp = le32toh(sc->sc_cmd_result[0]);
1412 if (address == 0 && sc->sc_port_route != NULL &&
1413 XHCI_TRB_2_ERROR_GET(temp) ==
1414 XHCI_TRB_ERROR_PARAMETER) {
1415 /* LynxPoint XHCI - ports are not switchable */
1416 /* Un-route all ports from the XHCI */
1417 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1419 DPRINTF("Could not set address "
1420 "for slot %u.\n", index);
1425 /* update device address to new value */
1427 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1428 pdev = buf_dev.buffer;
1429 usb_pc_cpu_invalidate(&hdev->device_pc);
1431 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1432 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1434 /* update device state to new value */
1437 hdev->state = XHCI_ST_ADDRESSED;
1439 hdev->state = XHCI_ST_DEFAULT;
1443 DPRINTF("Wrong state for set address.\n");
1444 err = USB_ERR_IOERROR;
1447 XHCI_CMD_UNLOCK(sc);
1456 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1457 uint8_t deconfigure, uint8_t slot_id)
1459 struct xhci_trb trb;
1464 trb.qwTrb0 = htole64(input_ctx);
1466 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1467 XHCI_TRB_3_SLOT_SET(slot_id);
1470 temp |= XHCI_TRB_3_DCEP_BIT;
1472 trb.dwTrb3 = htole32(temp);
1474 return (xhci_do_command(sc, &trb, 100 /* ms */));
1478 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1481 struct xhci_trb trb;
1486 trb.qwTrb0 = htole64(input_ctx);
1488 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1489 XHCI_TRB_3_SLOT_SET(slot_id);
1490 trb.dwTrb3 = htole32(temp);
1492 return (xhci_do_command(sc, &trb, 100 /* ms */));
1496 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1497 uint8_t ep_id, uint8_t slot_id)
1499 struct xhci_trb trb;
1506 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1507 XHCI_TRB_3_SLOT_SET(slot_id) |
1508 XHCI_TRB_3_EP_SET(ep_id);
1511 temp |= XHCI_TRB_3_PRSV_BIT;
1513 trb.dwTrb3 = htole32(temp);
1515 return (xhci_do_command(sc, &trb, 100 /* ms */));
1519 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1520 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1522 struct xhci_trb trb;
1527 trb.qwTrb0 = htole64(dequeue_ptr);
1529 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1530 trb.dwTrb2 = htole32(temp);
1532 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1533 XHCI_TRB_3_SLOT_SET(slot_id) |
1534 XHCI_TRB_3_EP_SET(ep_id);
1535 trb.dwTrb3 = htole32(temp);
1537 return (xhci_do_command(sc, &trb, 100 /* ms */));
1541 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1542 uint8_t ep_id, uint8_t slot_id)
1544 struct xhci_trb trb;
1551 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1552 XHCI_TRB_3_SLOT_SET(slot_id) |
1553 XHCI_TRB_3_EP_SET(ep_id);
1556 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1558 trb.dwTrb3 = htole32(temp);
1560 return (xhci_do_command(sc, &trb, 100 /* ms */));
1564 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1566 struct xhci_trb trb;
1573 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1574 XHCI_TRB_3_SLOT_SET(slot_id);
1576 trb.dwTrb3 = htole32(temp);
1578 return (xhci_do_command(sc, &trb, 100 /* ms */));
1581 /*------------------------------------------------------------------------*
1582 * xhci_interrupt - XHCI interrupt handler
1583 *------------------------------------------------------------------------*/
1585 xhci_interrupt(struct xhci_softc *sc)
1590 USB_BUS_LOCK(&sc->sc_bus);
1592 status = XREAD4(sc, oper, XHCI_USBSTS);
1594 /* acknowledge interrupts, if any */
1596 XWRITE4(sc, oper, XHCI_USBSTS, status);
1597 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1600 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1602 /* force clearing of pending interrupts */
1603 if (temp & XHCI_IMAN_INTR_PEND)
1604 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1606 /* check for event(s) */
1607 xhci_interrupt_poll(sc);
1609 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1610 XHCI_STS_HSE | XHCI_STS_HCE)) {
1612 if (status & XHCI_STS_PCD) {
1616 if (status & XHCI_STS_HCH) {
1617 printf("%s: host controller halted\n",
1621 if (status & XHCI_STS_HSE) {
1622 printf("%s: host system error\n",
1626 if (status & XHCI_STS_HCE) {
1627 printf("%s: host controller error\n",
1631 USB_BUS_UNLOCK(&sc->sc_bus);
1634 /*------------------------------------------------------------------------*
1635 * xhci_timeout - XHCI timeout handler
1636 *------------------------------------------------------------------------*/
1638 xhci_timeout(void *arg)
1640 struct usb_xfer *xfer = arg;
1642 DPRINTF("xfer=%p\n", xfer);
1644 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1646 /* transfer is transferred */
1647 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1651 xhci_do_poll(struct usb_bus *bus)
1653 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1655 USB_BUS_LOCK(&sc->sc_bus);
1656 xhci_interrupt_poll(sc);
1657 USB_BUS_UNLOCK(&sc->sc_bus);
1661 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1663 struct usb_page_search buf_res;
1665 struct xhci_td *td_next;
1666 struct xhci_td *td_alt_next;
1667 struct xhci_td *td_first;
1668 uint32_t buf_offset;
1673 uint8_t shortpkt_old;
1679 shortpkt_old = temp->shortpkt;
1680 len_old = temp->len;
1687 td_next = td_first = temp->td_next;
1691 if (temp->len == 0) {
1696 /* send a Zero Length Packet, ZLP, last */
1703 average = temp->average;
1705 if (temp->len < average) {
1706 if (temp->len % temp->max_packet_size) {
1709 average = temp->len;
1713 if (td_next == NULL)
1714 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1719 td_next = td->obj_next;
1721 /* check if we are pre-computing */
1725 /* update remaining length */
1727 temp->len -= average;
1731 /* fill out current TD */
1737 /* update remaining length */
1739 temp->len -= average;
1741 /* reset TRB index */
1745 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1746 /* immediate data */
1751 td->td_trb[0].qwTrb0 = 0;
1753 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1754 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1757 dword = XHCI_TRB_2_BYTES_SET(8) |
1758 XHCI_TRB_2_TDSZ_SET(0) |
1759 XHCI_TRB_2_IRQ_SET(0);
1761 td->td_trb[0].dwTrb2 = htole32(dword);
1763 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1764 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1767 if (td->td_trb[0].qwTrb0 &
1768 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1769 if (td->td_trb[0].qwTrb0 &
1770 htole64(XHCI_TRB_0_DIR_IN_MASK))
1771 dword |= XHCI_TRB_3_TRT_IN;
1773 dword |= XHCI_TRB_3_TRT_OUT;
1776 td->td_trb[0].dwTrb3 = htole32(dword);
1778 xhci_dump_trb(&td->td_trb[x]);
1786 /* fill out buffer pointers */
1789 memset(&buf_res, 0, sizeof(buf_res));
1791 usbd_get_page(temp->pc, temp->offset +
1792 buf_offset, &buf_res);
1794 /* get length to end of page */
1795 if (buf_res.length > average)
1796 buf_res.length = average;
1798 /* check for maximum length */
1799 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1800 buf_res.length = XHCI_TD_PAGE_SIZE;
1802 npkt_off += buf_res.length;
1806 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1807 temp->max_packet_size;
1814 /* fill out TRB's */
1815 td->td_trb[x].qwTrb0 =
1816 htole64((uint64_t)buf_res.physaddr);
1819 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1820 XHCI_TRB_2_TDSZ_SET(npkt) |
1821 XHCI_TRB_2_IRQ_SET(0);
1823 td->td_trb[x].dwTrb2 = htole32(dword);
1825 switch (temp->trb_type) {
1826 case XHCI_TRB_TYPE_ISOCH:
1827 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1828 XHCI_TRB_3_TBC_SET(temp->tbc) |
1829 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1830 if (td != td_first) {
1831 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1832 } else if (temp->do_isoc_sync != 0) {
1833 temp->do_isoc_sync = 0;
1834 /* wait until "isoc_frame" */
1835 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1836 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1838 /* start data transfer at next interval */
1839 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1840 XHCI_TRB_3_ISO_SIA_BIT;
1842 if (temp->direction == UE_DIR_IN)
1843 dword |= XHCI_TRB_3_ISP_BIT;
1845 case XHCI_TRB_TYPE_DATA_STAGE:
1846 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1847 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1848 if (temp->direction == UE_DIR_IN)
1849 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1851 * Section 3.2.9 in the XHCI
1852 * specification about control
1853 * transfers says that we should use a
1854 * normal-TRB if there are more TRBs
1855 * extending the data-stage
1856 * TRB. Update the "trb_type".
1858 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1860 case XHCI_TRB_TYPE_STATUS_STAGE:
1861 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1862 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1863 if (temp->direction == UE_DIR_IN)
1864 dword |= XHCI_TRB_3_DIR_IN;
1866 default: /* XHCI_TRB_TYPE_NORMAL */
1867 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1868 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1869 if (temp->direction == UE_DIR_IN)
1870 dword |= XHCI_TRB_3_ISP_BIT;
1873 td->td_trb[x].dwTrb3 = htole32(dword);
1875 average -= buf_res.length;
1876 buf_offset += buf_res.length;
1878 xhci_dump_trb(&td->td_trb[x]);
1882 } while (average != 0);
1884 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1886 /* store number of data TRB's */
1890 DPRINTF("NTRB=%u\n", x);
1892 /* fill out link TRB */
1894 if (td_next != NULL) {
1895 /* link the current TD with the next one */
1896 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1897 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1899 /* this field will get updated later */
1900 DPRINTF("NOLINK\n");
1903 dword = XHCI_TRB_2_IRQ_SET(0);
1905 td->td_trb[x].dwTrb2 = htole32(dword);
1907 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1908 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1910 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1911 * frame only receives a single short packet event
1912 * by setting the CHAIN bit in the LINK field. In
1913 * addition some XHCI controllers have problems
1914 * sending a ZLP unless the CHAIN-BIT is set in
1917 XHCI_TRB_3_CHAIN_BIT;
1919 td->td_trb[x].dwTrb3 = htole32(dword);
1921 td->alt_next = td_alt_next;
1923 xhci_dump_trb(&td->td_trb[x]);
1925 usb_pc_cpu_flush(td->page_cache);
1931 /* setup alt next pointer, if any */
1932 if (temp->last_frame) {
1935 /* we use this field internally */
1936 td_alt_next = td_next;
1940 temp->shortpkt = shortpkt_old;
1941 temp->len = len_old;
1946 * Remove cycle bit from the first TRB if we are
1949 if (temp->step_td != 0) {
1950 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1951 usb_pc_cpu_flush(td_first->page_cache);
1954 /* clear TD SIZE to zero, hence this is the last TRB */
1955 /* remove chain bit because this is the last data TRB in the chain */
1956 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1957 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1958 /* remove CHAIN-BIT from last LINK TRB */
1959 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1961 usb_pc_cpu_flush(td->page_cache);
1964 temp->td_next = td_next;
1968 xhci_setup_generic_chain(struct usb_xfer *xfer)
1970 struct xhci_std_temp temp;
1976 temp.do_isoc_sync = 0;
1980 temp.average = xfer->max_hc_frame_size;
1981 temp.max_packet_size = xfer->max_packet_size;
1982 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1984 temp.last_frame = 0;
1986 temp.multishort = xfer->flags_int.isochronous_xfr ||
1987 xfer->flags_int.control_xfr ||
1988 xfer->flags_int.short_frames_ok;
1990 /* toggle the DMA set we are using */
1991 xfer->flags_int.curr_dma_set ^= 1;
1993 /* get next DMA set */
1994 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1999 xfer->td_transfer_first = td;
2000 xfer->td_transfer_cache = td;
2002 if (xfer->flags_int.isochronous_xfr) {
2005 /* compute multiplier for ISOCHRONOUS transfers */
2006 mult = xfer->endpoint->ecomp ?
2007 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
2008 /* check for USB 2.0 multiplier */
2010 mult = (xfer->endpoint->edesc->
2011 wMaxPacketSize[1] >> 3) & 3;
2019 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2021 DPRINTF("MFINDEX=0x%08x\n", x);
2023 switch (usbd_get_speed(xfer->xroot->udev)) {
2024 case USB_SPEED_FULL:
2026 temp.isoc_delta = 8; /* 1ms */
2027 x += temp.isoc_delta - 1;
2028 x &= ~(temp.isoc_delta - 1);
2031 shift = usbd_xfer_get_fps_shift(xfer);
2032 temp.isoc_delta = 1U << shift;
2033 x += temp.isoc_delta - 1;
2034 x &= ~(temp.isoc_delta - 1);
2035 /* simple frame load balancing */
2036 x += xfer->endpoint->usb_uframe;
2040 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2042 if ((xfer->endpoint->is_synced == 0) ||
2043 (y < (xfer->nframes << shift)) ||
2044 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2046 * If there is data underflow or the pipe
2047 * queue is empty we schedule the transfer a
2048 * few frames ahead of the current frame
2049 * position. Else two isochronous transfers
2052 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2053 xfer->endpoint->is_synced = 1;
2054 temp.do_isoc_sync = 1;
2056 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2059 /* compute isochronous completion time */
2061 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2063 xfer->isoc_time_complete =
2064 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2065 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2068 temp.isoc_frame = xfer->endpoint->isoc_next;
2069 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2071 xfer->endpoint->isoc_next += xfer->nframes << shift;
2073 } else if (xfer->flags_int.control_xfr) {
2075 /* check if we should prepend a setup message */
2077 if (xfer->flags_int.control_hdr) {
2079 temp.len = xfer->frlengths[0];
2080 temp.pc = xfer->frbuffers + 0;
2081 temp.shortpkt = temp.len ? 1 : 0;
2082 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2085 /* check for last frame */
2086 if (xfer->nframes == 1) {
2087 /* no STATUS stage yet, SETUP is last */
2088 if (xfer->flags_int.control_act)
2089 temp.last_frame = 1;
2092 xhci_setup_generic_chain_sub(&temp);
2096 temp.isoc_delta = 0;
2097 temp.isoc_frame = 0;
2098 temp.trb_type = xfer->flags_int.control_did_data ?
2099 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2103 temp.isoc_delta = 0;
2104 temp.isoc_frame = 0;
2105 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2108 if (x != xfer->nframes) {
2109 /* setup page_cache pointer */
2110 temp.pc = xfer->frbuffers + x;
2111 /* set endpoint direction */
2112 temp.direction = UE_GET_DIR(xfer->endpointno);
2115 while (x != xfer->nframes) {
2117 /* DATA0 / DATA1 message */
2119 temp.len = xfer->frlengths[x];
2120 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2121 x != 0 && temp.multishort == 0);
2125 if (x == xfer->nframes) {
2126 if (xfer->flags_int.control_xfr) {
2127 /* no STATUS stage yet, DATA is last */
2128 if (xfer->flags_int.control_act)
2129 temp.last_frame = 1;
2131 temp.last_frame = 1;
2134 if (temp.len == 0) {
2136 /* make sure that we send an USB packet */
2141 temp.tlbpc = mult - 1;
2143 } else if (xfer->flags_int.isochronous_xfr) {
2148 * Isochronous transfers don't have short
2149 * packet termination:
2154 /* isochronous transfers have a transfer limit */
2156 if (temp.len > xfer->max_frame_size)
2157 temp.len = xfer->max_frame_size;
2159 /* compute TD packet count */
2160 tdpc = (temp.len + xfer->max_packet_size - 1) /
2161 xfer->max_packet_size;
2163 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2164 temp.tlbpc = (tdpc % mult);
2166 if (temp.tlbpc == 0)
2167 temp.tlbpc = mult - 1;
2172 /* regular data transfer */
2174 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2177 xhci_setup_generic_chain_sub(&temp);
2179 if (xfer->flags_int.isochronous_xfr) {
2180 temp.offset += xfer->frlengths[x - 1];
2181 temp.isoc_frame += temp.isoc_delta;
2183 /* get next Page Cache pointer */
2184 temp.pc = xfer->frbuffers + x;
2188 /* check if we should append a status stage */
2190 if (xfer->flags_int.control_xfr &&
2191 !xfer->flags_int.control_act) {
2194 * Send a DATA1 message and invert the current
2195 * endpoint direction.
2197 temp.step_td = (xfer->nframes != 0);
2198 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2202 temp.last_frame = 1;
2203 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2205 xhci_setup_generic_chain_sub(&temp);
2210 /* must have at least one frame! */
2212 xfer->td_transfer_last = td;
2214 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2218 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2220 struct usb_page_search buf_res;
2221 struct xhci_dev_ctx_addr *pdctxa;
2223 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2225 pdctxa = buf_res.buffer;
2227 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2229 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2231 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2235 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2237 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2238 struct usb_page_search buf_inp;
2239 struct xhci_input_dev_ctx *pinp;
2244 index = udev->controller_slot_id;
2246 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2248 pinp = buf_inp.buffer;
2251 mask &= XHCI_INCTX_NON_CTRL_MASK;
2252 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2253 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2256 * Some hardware requires that we drop the endpoint
2257 * context before adding it again:
2259 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2260 mask & XHCI_INCTX_NON_CTRL_MASK);
2262 /* Add new endpoint context */
2263 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2265 /* find most significant set bit */
2266 for (x = 31; x != 1; x--) {
2267 if (mask & (1 << x))
2274 /* figure out the maximum number of contexts */
2275 if (x > sc->sc_hw.devs[index].context_num)
2276 sc->sc_hw.devs[index].context_num = x;
2278 x = sc->sc_hw.devs[index].context_num;
2280 /* update number of contexts */
2281 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2282 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2283 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2284 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2286 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2291 xhci_configure_endpoint(struct usb_device *udev,
2292 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2293 uint16_t interval, uint8_t max_packet_count,
2294 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2295 uint16_t max_frame_size)
2297 struct usb_page_search buf_inp;
2298 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2299 struct xhci_input_dev_ctx *pinp;
2300 uint64_t ring_addr = pepext->physaddr;
2306 index = udev->controller_slot_id;
2308 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2310 pinp = buf_inp.buffer;
2312 epno = edesc->bEndpointAddress;
2313 type = edesc->bmAttributes & UE_XFERTYPE;
2315 if (type == UE_CONTROL)
2318 epno = XHCI_EPNO2EPID(epno);
2321 return (USB_ERR_NO_PIPE); /* invalid */
2323 if (max_packet_count == 0)
2324 return (USB_ERR_BAD_BUFSIZE);
2329 return (USB_ERR_BAD_BUFSIZE);
2331 /* store bMaxPacketSize for control endpoints */
2332 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2333 usb_pc_cpu_flush(pepext->page_cache);
2335 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2336 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2337 XHCI_EPCTX_0_LSA_SET(0);
2339 switch (udev->speed) {
2340 case USB_SPEED_FULL:
2353 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2355 case UE_ISOCHRONOUS:
2356 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2358 switch (udev->speed) {
2359 case USB_SPEED_SUPER:
2362 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2363 max_packet_count /= mult;
2373 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2376 XHCI_EPCTX_1_HID_SET(0) |
2377 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2378 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2381 * Always enable the "three strikes and you are gone" feature
2382 * except for ISOCHRONOUS endpoints. This is suggested by
2383 * section 4.3.3 in the XHCI specification about device slot
2386 if (type != UE_ISOCHRONOUS)
2387 temp |= XHCI_EPCTX_1_CERR_SET(3);
2391 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2393 case UE_ISOCHRONOUS:
2394 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2397 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2400 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2404 /* check for IN direction */
2406 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2408 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2410 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2412 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2414 switch (edesc->bmAttributes & UE_XFERTYPE) {
2416 case UE_ISOCHRONOUS:
2417 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2418 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2422 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2425 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2429 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2432 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2434 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2436 return (0); /* success */
2440 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2442 struct xhci_endpoint_ext *pepext;
2443 struct usb_endpoint_ss_comp_descriptor *ecomp;
2445 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2446 xfer->endpoint->edesc);
2448 ecomp = xfer->endpoint->ecomp;
2450 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2451 usb_pc_cpu_flush(pepext->page_cache);
2453 return (xhci_configure_endpoint(xfer->xroot->udev,
2454 xfer->endpoint->edesc, pepext,
2455 xfer->interval, xfer->max_packet_count,
2456 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2457 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2458 xfer->max_frame_size));
2462 xhci_configure_device(struct usb_device *udev)
2464 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2465 struct usb_page_search buf_inp;
2466 struct usb_page_cache *pcinp;
2467 struct xhci_input_dev_ctx *pinp;
2468 struct usb_device *hubdev;
2476 index = udev->controller_slot_id;
2478 DPRINTF("index=%u\n", index);
2480 pcinp = &sc->sc_hw.devs[index].input_pc;
2482 usbd_get_page(pcinp, 0, &buf_inp);
2484 pinp = buf_inp.buffer;
2489 /* figure out route string and root HUB port number */
2491 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2493 if (hubdev->parent_hub == NULL)
2496 depth = hubdev->parent_hub->depth;
2499 * NOTE: HS/FS/LS devices and the SS root HUB can have
2500 * more than 15 ports
2503 rh_port = hubdev->port_no;
2512 route |= rh_port << (4 * (depth - 1));
2515 DPRINTF("Route=0x%08x\n", route);
2517 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2518 XHCI_SCTX_0_CTX_NUM_SET(
2519 sc->sc_hw.devs[index].context_num + 1);
2521 switch (udev->speed) {
2523 temp |= XHCI_SCTX_0_SPEED_SET(2);
2524 if (udev->parent_hs_hub != NULL &&
2525 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2527 DPRINTF("Device inherits MTT\n");
2528 temp |= XHCI_SCTX_0_MTT_SET(1);
2531 case USB_SPEED_HIGH:
2532 temp |= XHCI_SCTX_0_SPEED_SET(3);
2533 if (sc->sc_hw.devs[index].nports != 0 &&
2534 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2535 DPRINTF("HUB supports MTT\n");
2536 temp |= XHCI_SCTX_0_MTT_SET(1);
2539 case USB_SPEED_FULL:
2540 temp |= XHCI_SCTX_0_SPEED_SET(1);
2541 if (udev->parent_hs_hub != NULL &&
2542 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2544 DPRINTF("Device inherits MTT\n");
2545 temp |= XHCI_SCTX_0_MTT_SET(1);
2549 temp |= XHCI_SCTX_0_SPEED_SET(4);
2553 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2554 (udev->speed == USB_SPEED_SUPER ||
2555 udev->speed == USB_SPEED_HIGH);
2558 temp |= XHCI_SCTX_0_HUB_SET(1);
2560 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2562 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2565 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2566 sc->sc_hw.devs[index].nports);
2569 switch (udev->speed) {
2570 case USB_SPEED_SUPER:
2571 switch (sc->sc_hw.devs[index].state) {
2572 case XHCI_ST_ADDRESSED:
2573 case XHCI_ST_CONFIGURED:
2574 /* enable power save */
2575 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2578 /* disable power save */
2586 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2588 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2591 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2592 sc->sc_hw.devs[index].tt);
2595 hubdev = udev->parent_hs_hub;
2597 /* check if we should activate the transaction translator */
2598 switch (udev->speed) {
2599 case USB_SPEED_FULL:
2601 if (hubdev != NULL) {
2602 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2603 hubdev->controller_slot_id);
2604 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2612 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2615 * These fields should be initialized to zero, according to
2616 * XHCI section 6.2.2 - slot context:
2618 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2619 XHCI_SCTX_3_SLOT_STATE_SET(0);
2621 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2624 xhci_dump_device(sc, &pinp->ctx_slot);
2626 usb_pc_cpu_flush(pcinp);
2628 return (0); /* success */
2632 xhci_alloc_device_ext(struct usb_device *udev)
2634 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2635 struct usb_page_search buf_dev;
2636 struct usb_page_search buf_ep;
2637 struct xhci_trb *trb;
2638 struct usb_page_cache *pc;
2639 struct usb_page *pg;
2644 index = udev->controller_slot_id;
2646 pc = &sc->sc_hw.devs[index].device_pc;
2647 pg = &sc->sc_hw.devs[index].device_pg;
2649 /* need to initialize the page cache */
2650 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2652 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2653 (2 * sizeof(struct xhci_dev_ctx)) :
2654 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2657 usbd_get_page(pc, 0, &buf_dev);
2659 pc = &sc->sc_hw.devs[index].input_pc;
2660 pg = &sc->sc_hw.devs[index].input_pg;
2662 /* need to initialize the page cache */
2663 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2665 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2666 (2 * sizeof(struct xhci_input_dev_ctx)) :
2667 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2671 pc = &sc->sc_hw.devs[index].endpoint_pc;
2672 pg = &sc->sc_hw.devs[index].endpoint_pg;
2674 /* need to initialize the page cache */
2675 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2677 if (usb_pc_alloc_mem(pc, pg,
2678 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2682 /* initialise all endpoint LINK TRBs */
2684 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2686 /* lookup endpoint TRB ring */
2687 usbd_get_page(pc, (uintptr_t)&
2688 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2690 /* get TRB pointer */
2691 trb = buf_ep.buffer;
2692 trb += XHCI_MAX_TRANSFERS - 1;
2694 /* get TRB start address */
2695 addr = buf_ep.physaddr;
2697 /* create LINK TRB */
2698 trb->qwTrb0 = htole64(addr);
2699 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2700 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2701 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2704 usb_pc_cpu_flush(pc);
2706 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2711 xhci_free_device_ext(udev);
2713 return (USB_ERR_NOMEM);
2717 xhci_free_device_ext(struct usb_device *udev)
2719 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2722 index = udev->controller_slot_id;
2723 xhci_set_slot_pointer(sc, index, 0);
2725 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2726 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2727 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2730 static struct xhci_endpoint_ext *
2731 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2733 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734 struct xhci_endpoint_ext *pepext;
2735 struct usb_page_cache *pc;
2736 struct usb_page_search buf_ep;
2740 epno = edesc->bEndpointAddress;
2741 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2744 epno = XHCI_EPNO2EPID(epno);
2746 index = udev->controller_slot_id;
2748 pc = &sc->sc_hw.devs[index].endpoint_pc;
2750 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2752 pepext = &sc->sc_hw.devs[index].endp[epno];
2753 pepext->page_cache = pc;
2754 pepext->trb = buf_ep.buffer;
2755 pepext->physaddr = buf_ep.physaddr;
2761 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2763 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2767 epno = xfer->endpointno;
2768 if (xfer->flags_int.control_xfr)
2771 epno = XHCI_EPNO2EPID(epno);
2772 index = xfer->xroot->udev->controller_slot_id;
2774 if (xfer->xroot->udev->flags.self_suspended == 0) {
2775 XWRITE4(sc, door, XHCI_DOORBELL(index),
2776 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2781 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2783 struct xhci_endpoint_ext *pepext;
2785 if (xfer->flags_int.bandwidth_reclaimed) {
2786 xfer->flags_int.bandwidth_reclaimed = 0;
2788 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2789 xfer->endpoint->edesc);
2793 pepext->xfer[xfer->qh_pos] = NULL;
2795 if (error && pepext->trb_running != 0) {
2796 pepext->trb_halted = 1;
2797 pepext->trb_running = 0;
2803 xhci_transfer_insert(struct usb_xfer *xfer)
2805 struct xhci_td *td_first;
2806 struct xhci_td *td_last;
2807 struct xhci_trb *trb_link;
2808 struct xhci_endpoint_ext *pepext;
2816 /* check if already inserted */
2817 if (xfer->flags_int.bandwidth_reclaimed) {
2818 DPRINTFN(8, "Already in schedule\n");
2822 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2823 xfer->endpoint->edesc);
2825 td_first = xfer->td_transfer_first;
2826 td_last = xfer->td_transfer_last;
2827 addr = pepext->physaddr;
2829 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2832 /* single buffered */
2836 /* multi buffered */
2837 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2841 if (pepext->trb_used >= trb_limit) {
2842 DPRINTFN(8, "Too many TDs queued.\n");
2843 return (USB_ERR_NOMEM);
2846 /* check if bMaxPacketSize changed */
2847 if (xfer->flags_int.control_xfr != 0 &&
2848 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2850 DPRINTFN(8, "Reconfigure control endpoint\n");
2852 /* force driver to reconfigure endpoint */
2853 pepext->trb_halted = 1;
2854 pepext->trb_running = 0;
2857 /* check for stopped condition, after putting transfer on interrupt queue */
2858 if (pepext->trb_running == 0) {
2859 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2861 DPRINTFN(8, "Not running\n");
2863 /* start configuration */
2864 (void)usb_proc_msignal(&sc->sc_config_proc,
2865 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2871 /* get current TRB index */
2872 i = pepext->trb_index;
2874 /* get next TRB index */
2877 /* the last entry of the ring is a hardcoded link TRB */
2878 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2881 /* compute terminating return address */
2882 addr += inext * sizeof(struct xhci_trb);
2884 /* compute link TRB pointer */
2885 trb_link = td_last->td_trb + td_last->ntrb;
2887 /* update next pointer of last link TRB */
2888 trb_link->qwTrb0 = htole64(addr);
2889 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2890 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2891 XHCI_TRB_3_CYCLE_BIT |
2892 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2895 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2897 usb_pc_cpu_flush(td_last->page_cache);
2899 /* write ahead chain end marker */
2901 pepext->trb[inext].qwTrb0 = 0;
2902 pepext->trb[inext].dwTrb2 = 0;
2903 pepext->trb[inext].dwTrb3 = 0;
2905 /* update next pointer of link TRB */
2907 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2908 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2911 xhci_dump_trb(&pepext->trb[i]);
2913 usb_pc_cpu_flush(pepext->page_cache);
2915 /* toggle cycle bit which activates the transfer chain */
2917 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2918 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2920 usb_pc_cpu_flush(pepext->page_cache);
2922 DPRINTF("qh_pos = %u\n", i);
2924 pepext->xfer[i] = xfer;
2928 xfer->flags_int.bandwidth_reclaimed = 1;
2930 pepext->trb_index = inext;
2932 xhci_endpoint_doorbell(xfer);
2938 xhci_root_intr(struct xhci_softc *sc)
2942 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2944 /* clear any old interrupt data */
2945 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2947 for (i = 1; i <= sc->sc_noport; i++) {
2948 /* pick out CHANGE bits from the status register */
2949 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2950 XHCI_PS_CSC | XHCI_PS_PEC |
2951 XHCI_PS_OCC | XHCI_PS_WRC |
2952 XHCI_PS_PRC | XHCI_PS_PLC |
2954 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2955 DPRINTF("port %d changed\n", i);
2958 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2959 sizeof(sc->sc_hub_idata));
2962 /*------------------------------------------------------------------------*
2963 * xhci_device_done - XHCI done handler
2965 * NOTE: This function can be called two times in a row on
2966 * the same USB transfer. From close and from interrupt.
2967 *------------------------------------------------------------------------*/
2969 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2971 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2972 xfer, xfer->endpoint, error);
2974 /* remove transfer from HW queue */
2975 xhci_transfer_remove(xfer, error);
2977 /* dequeue transfer and start next transfer */
2978 usbd_transfer_done(xfer, error);
2981 /*------------------------------------------------------------------------*
2982 * XHCI data transfer support (generic type)
2983 *------------------------------------------------------------------------*/
2985 xhci_device_generic_open(struct usb_xfer *xfer)
2987 if (xfer->flags_int.isochronous_xfr) {
2988 switch (xfer->xroot->udev->speed) {
2989 case USB_SPEED_FULL:
2992 usb_hs_bandwidth_alloc(xfer);
2999 xhci_device_generic_close(struct usb_xfer *xfer)
3003 xhci_device_done(xfer, USB_ERR_CANCELLED);
3005 if (xfer->flags_int.isochronous_xfr) {
3006 switch (xfer->xroot->udev->speed) {
3007 case USB_SPEED_FULL:
3010 usb_hs_bandwidth_free(xfer);
3017 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3018 struct usb_xfer *enter_xfer)
3020 struct usb_xfer *xfer;
3022 /* check if there is a current transfer */
3023 xfer = ep->endpoint_q.curr;
3028 * Check if the current transfer is started and then pickup
3029 * the next one, if any. Else wait for next start event due to
3030 * block on failure feature.
3032 if (!xfer->flags_int.bandwidth_reclaimed)
3035 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
3038 * In case of enter we have to consider that the
3039 * transfer is queued by the USB core after the enter
3048 /* try to multi buffer */
3049 xhci_transfer_insert(xfer);
3053 xhci_device_generic_enter(struct usb_xfer *xfer)
3057 /* setup TD's and QH */
3058 xhci_setup_generic_chain(xfer);
3060 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3064 xhci_device_generic_start(struct usb_xfer *xfer)
3068 /* try to insert xfer on HW queue */
3069 xhci_transfer_insert(xfer);
3071 /* try to multi buffer */
3072 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3074 /* add transfer last on interrupt queue */
3075 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3077 /* start timeout, if any */
3078 if (xfer->timeout != 0)
3079 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3082 struct usb_pipe_methods xhci_device_generic_methods =
3084 .open = xhci_device_generic_open,
3085 .close = xhci_device_generic_close,
3086 .enter = xhci_device_generic_enter,
3087 .start = xhci_device_generic_start,
3090 /*------------------------------------------------------------------------*
3091 * xhci root HUB support
3092 *------------------------------------------------------------------------*
3093 * Simulate a hardware HUB by handling all the necessary requests.
3094 *------------------------------------------------------------------------*/
3096 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3099 struct usb_device_descriptor xhci_devd =
3101 .bLength = sizeof(xhci_devd),
3102 .bDescriptorType = UDESC_DEVICE, /* type */
3103 HSETW(.bcdUSB, 0x0300), /* USB version */
3104 .bDeviceClass = UDCLASS_HUB, /* class */
3105 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3106 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3107 .bMaxPacketSize = 9, /* max packet size */
3108 HSETW(.idVendor, 0x0000), /* vendor */
3109 HSETW(.idProduct, 0x0000), /* product */
3110 HSETW(.bcdDevice, 0x0100), /* device version */
3114 .bNumConfigurations = 1, /* # of configurations */
3118 struct xhci_bos_desc xhci_bosd = {
3120 .bLength = sizeof(xhci_bosd.bosd),
3121 .bDescriptorType = UDESC_BOS,
3122 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3123 .bNumDeviceCaps = 3,
3126 .bLength = sizeof(xhci_bosd.usb2extd),
3127 .bDescriptorType = 1,
3128 .bDevCapabilityType = 2,
3129 .bmAttributes[0] = 2,
3132 .bLength = sizeof(xhci_bosd.usbdcd),
3133 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3134 .bDevCapabilityType = 3,
3135 .bmAttributes = 0, /* XXX */
3136 HSETW(.wSpeedsSupported, 0x000C),
3137 .bFunctionalitySupport = 8,
3138 .bU1DevExitLat = 255, /* dummy - not used */
3139 .wU2DevExitLat = { 0x00, 0x08 },
3142 .bLength = sizeof(xhci_bosd.cidd),
3143 .bDescriptorType = 1,
3144 .bDevCapabilityType = 4,
3146 .bContainerID = 0, /* XXX */
3151 struct xhci_config_desc xhci_confd = {
3153 .bLength = sizeof(xhci_confd.confd),
3154 .bDescriptorType = UDESC_CONFIG,
3155 .wTotalLength[0] = sizeof(xhci_confd),
3157 .bConfigurationValue = 1,
3158 .iConfiguration = 0,
3159 .bmAttributes = UC_SELF_POWERED,
3160 .bMaxPower = 0 /* max power */
3163 .bLength = sizeof(xhci_confd.ifcd),
3164 .bDescriptorType = UDESC_INTERFACE,
3166 .bInterfaceClass = UICLASS_HUB,
3167 .bInterfaceSubClass = UISUBCLASS_HUB,
3168 .bInterfaceProtocol = 0,
3171 .bLength = sizeof(xhci_confd.endpd),
3172 .bDescriptorType = UDESC_ENDPOINT,
3173 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3174 .bmAttributes = UE_INTERRUPT,
3175 .wMaxPacketSize[0] = 2, /* max 15 ports */
3179 .bLength = sizeof(xhci_confd.endpcd),
3180 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3187 struct usb_hub_ss_descriptor xhci_hubd = {
3188 .bLength = sizeof(xhci_hubd),
3189 .bDescriptorType = UDESC_SS_HUB,
3193 xhci_roothub_exec(struct usb_device *udev,
3194 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3196 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3197 const char *str_ptr;
3208 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3211 ptr = (const void *)&sc->sc_hub_desc;
3215 value = UGETW(req->wValue);
3216 index = UGETW(req->wIndex);
3218 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3219 "wValue=0x%04x wIndex=0x%04x\n",
3220 req->bmRequestType, req->bRequest,
3221 UGETW(req->wLength), value, index);
3223 #define C(x,y) ((x) | ((y) << 8))
3224 switch (C(req->bRequest, req->bmRequestType)) {
3225 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3226 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3227 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3229 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3230 * for the integrated root hub.
3233 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3235 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3237 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3238 switch (value >> 8) {
3240 if ((value & 0xff) != 0) {
3241 err = USB_ERR_IOERROR;
3244 len = sizeof(xhci_devd);
3245 ptr = (const void *)&xhci_devd;
3249 if ((value & 0xff) != 0) {
3250 err = USB_ERR_IOERROR;
3253 len = sizeof(xhci_bosd);
3254 ptr = (const void *)&xhci_bosd;
3258 if ((value & 0xff) != 0) {
3259 err = USB_ERR_IOERROR;
3262 len = sizeof(xhci_confd);
3263 ptr = (const void *)&xhci_confd;
3267 switch (value & 0xff) {
3268 case 0: /* Language table */
3272 case 1: /* Vendor */
3273 str_ptr = sc->sc_vendor;
3276 case 2: /* Product */
3277 str_ptr = "XHCI root HUB";
3285 len = usb_make_str_desc(
3286 sc->sc_hub_desc.temp,
3287 sizeof(sc->sc_hub_desc.temp),
3292 err = USB_ERR_IOERROR;
3296 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3298 sc->sc_hub_desc.temp[0] = 0;
3300 case C(UR_GET_STATUS, UT_READ_DEVICE):
3302 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3304 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3305 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3307 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3309 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3310 if (value >= XHCI_MAX_DEVICES) {
3311 err = USB_ERR_IOERROR;
3315 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3316 if (value != 0 && value != 1) {
3317 err = USB_ERR_IOERROR;
3320 sc->sc_conf = value;
3322 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3324 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3325 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3326 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3327 err = USB_ERR_IOERROR;
3329 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3331 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3334 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3336 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3337 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3340 (index > sc->sc_noport)) {
3341 err = USB_ERR_IOERROR;
3344 port = XHCI_PORTSC(index);
3346 v = XREAD4(sc, oper, port);
3347 i = XHCI_PS_PLS_GET(v);
3348 v &= ~XHCI_PS_CLEAR;
3351 case UHF_C_BH_PORT_RESET:
3352 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3354 case UHF_C_PORT_CONFIG_ERROR:
3355 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3357 case UHF_C_PORT_SUSPEND:
3358 case UHF_C_PORT_LINK_STATE:
3359 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3361 case UHF_C_PORT_CONNECTION:
3362 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3364 case UHF_C_PORT_ENABLE:
3365 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3367 case UHF_C_PORT_OVER_CURRENT:
3368 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3370 case UHF_C_PORT_RESET:
3371 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3373 case UHF_PORT_ENABLE:
3374 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3376 case UHF_PORT_POWER:
3377 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3379 case UHF_PORT_INDICATOR:
3380 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3382 case UHF_PORT_SUSPEND:
3386 XWRITE4(sc, oper, port, v |
3387 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3390 /* wait 20ms for resume sequence to complete */
3391 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3394 XWRITE4(sc, oper, port, v |
3395 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3398 err = USB_ERR_IOERROR;
3403 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3404 if ((value & 0xff) != 0) {
3405 err = USB_ERR_IOERROR;
3409 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3411 sc->sc_hub_desc.hubd = xhci_hubd;
3413 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3415 if (XHCI_HCS0_PPC(v))
3416 i = UHD_PWR_INDIVIDUAL;
3420 if (XHCI_HCS0_PIND(v))
3423 i |= UHD_OC_INDIVIDUAL;
3425 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3427 /* see XHCI section 5.4.9: */
3428 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3430 for (j = 1; j <= sc->sc_noport; j++) {
3432 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3433 if (v & XHCI_PS_DR) {
3434 sc->sc_hub_desc.hubd.
3435 DeviceRemovable[j / 8] |= 1U << (j % 8);
3438 len = sc->sc_hub_desc.hubd.bLength;
3441 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3443 memset(sc->sc_hub_desc.temp, 0, 16);
3446 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3447 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3450 (index > sc->sc_noport)) {
3451 err = USB_ERR_IOERROR;
3455 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3457 DPRINTFN(9, "port status=0x%08x\n", v);
3459 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3461 switch (XHCI_PS_SPEED_GET(v)) {
3463 i |= UPS_HIGH_SPEED;
3472 i |= UPS_OTHER_SPEED;
3476 if (v & XHCI_PS_CCS)
3477 i |= UPS_CURRENT_CONNECT_STATUS;
3478 if (v & XHCI_PS_PED)
3479 i |= UPS_PORT_ENABLED;
3480 if (v & XHCI_PS_OCA)
3481 i |= UPS_OVERCURRENT_INDICATOR;
3484 if (v & XHCI_PS_PP) {
3486 * The USB 3.0 RH is using the
3487 * USB 2.0's power bit
3489 i |= UPS_PORT_POWER;
3491 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3494 if (v & XHCI_PS_CSC)
3495 i |= UPS_C_CONNECT_STATUS;
3496 if (v & XHCI_PS_PEC)
3497 i |= UPS_C_PORT_ENABLED;
3498 if (v & XHCI_PS_OCC)
3499 i |= UPS_C_OVERCURRENT_INDICATOR;
3500 if (v & XHCI_PS_WRC)
3501 i |= UPS_C_BH_PORT_RESET;
3502 if (v & XHCI_PS_PRC)
3503 i |= UPS_C_PORT_RESET;
3504 if (v & XHCI_PS_PLC)
3505 i |= UPS_C_PORT_LINK_STATE;
3506 if (v & XHCI_PS_CEC)
3507 i |= UPS_C_PORT_CONFIG_ERROR;
3509 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3510 len = sizeof(sc->sc_hub_desc.ps);
3513 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3514 err = USB_ERR_IOERROR;
3517 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3520 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3526 (index > sc->sc_noport)) {
3527 err = USB_ERR_IOERROR;
3531 port = XHCI_PORTSC(index);
3532 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3535 case UHF_PORT_U1_TIMEOUT:
3536 if (XHCI_PS_SPEED_GET(v) != 4) {
3537 err = USB_ERR_IOERROR;
3540 port = XHCI_PORTPMSC(index);
3541 v = XREAD4(sc, oper, port);
3542 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3543 v |= XHCI_PM3_U1TO_SET(i);
3544 XWRITE4(sc, oper, port, v);
3546 case UHF_PORT_U2_TIMEOUT:
3547 if (XHCI_PS_SPEED_GET(v) != 4) {
3548 err = USB_ERR_IOERROR;
3551 port = XHCI_PORTPMSC(index);
3552 v = XREAD4(sc, oper, port);
3553 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3554 v |= XHCI_PM3_U2TO_SET(i);
3555 XWRITE4(sc, oper, port, v);
3557 case UHF_BH_PORT_RESET:
3558 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3560 case UHF_PORT_LINK_STATE:
3561 XWRITE4(sc, oper, port, v |
3562 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3563 /* 4ms settle time */
3564 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3566 case UHF_PORT_ENABLE:
3567 DPRINTFN(3, "set port enable %d\n", index);
3569 case UHF_PORT_SUSPEND:
3570 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3571 j = XHCI_PS_SPEED_GET(v);
3572 if ((j < 1) || (j > 3)) {
3573 /* non-supported speed */
3574 err = USB_ERR_IOERROR;
3577 XWRITE4(sc, oper, port, v |
3578 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3580 case UHF_PORT_RESET:
3581 DPRINTFN(6, "reset port %d\n", index);
3582 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3584 case UHF_PORT_POWER:
3585 DPRINTFN(3, "set port power %d\n", index);
3586 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3589 DPRINTFN(3, "set port test %d\n", index);
3591 case UHF_PORT_INDICATOR:
3592 DPRINTFN(3, "set port indicator %d\n", index);
3594 v &= ~XHCI_PS_PIC_SET(3);
3595 v |= XHCI_PS_PIC_SET(1);
3597 XWRITE4(sc, oper, port, v);
3600 err = USB_ERR_IOERROR;
3605 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3606 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3607 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3608 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3611 err = USB_ERR_IOERROR;
3621 xhci_xfer_setup(struct usb_setup_params *parm)
3623 struct usb_page_search page_info;
3624 struct usb_page_cache *pc;
3625 struct xhci_softc *sc;
3626 struct usb_xfer *xfer;
3631 sc = XHCI_BUS2SC(parm->udev->bus);
3632 xfer = parm->curr_xfer;
3635 * The proof for the "ntd" formula is illustrated like this:
3637 * +------------------------------------+
3641 * | | xxx | x | frm 0 |
3643 * | | xxx | xx | frm 1 |
3646 * +------------------------------------+
3648 * "xxx" means a completely full USB transfer descriptor
3650 * "x" and "xx" means a short USB packet
3652 * For the remainder of an USB transfer modulo
3653 * "max_data_length" we need two USB transfer descriptors.
3654 * One to transfer the remaining data and one to finalise with
3655 * a zero length packet in case the "force_short_xfer" flag is
3656 * set. We only need two USB transfer descriptors in the case
3657 * where the transfer length of the first one is a factor of
3658 * "max_frame_size". The rest of the needed USB transfer
3659 * descriptors is given by the buffer size divided by the
3660 * maximum data payload.
3662 parm->hc_max_packet_size = 0x400;
3663 parm->hc_max_packet_count = 16 * 3;
3664 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3666 xfer->flags_int.bdma_enable = 1;
3668 usbd_transfer_setup_sub(parm);
3670 if (xfer->flags_int.isochronous_xfr) {
3671 ntd = ((1 * xfer->nframes)
3672 + (xfer->max_data_length / xfer->max_hc_frame_size));
3673 } else if (xfer->flags_int.control_xfr) {
3674 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3675 + (xfer->max_data_length / xfer->max_hc_frame_size));
3677 ntd = ((2 * xfer->nframes)
3678 + (xfer->max_data_length / xfer->max_hc_frame_size));
3687 * Allocate queue heads and transfer descriptors
3691 if (usbd_transfer_setup_sub_malloc(
3692 parm, &pc, sizeof(struct xhci_td),
3693 XHCI_TD_ALIGN, ntd)) {
3694 parm->err = USB_ERR_NOMEM;
3698 for (n = 0; n != ntd; n++) {
3701 usbd_get_page(pc + n, 0, &page_info);
3703 td = page_info.buffer;
3706 td->td_self = page_info.physaddr;
3707 td->obj_next = last_obj;
3708 td->page_cache = pc + n;
3712 usb_pc_cpu_flush(pc + n);
3715 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3717 if (!xfer->flags_int.curr_dma_set) {
3718 xfer->flags_int.curr_dma_set = 1;
3724 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3726 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3727 struct usb_page_search buf_inp;
3728 struct usb_device *udev;
3729 struct xhci_endpoint_ext *pepext;
3730 struct usb_endpoint_descriptor *edesc;
3731 struct usb_page_cache *pcinp;
3736 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3737 xfer->endpoint->edesc);
3739 udev = xfer->xroot->udev;
3740 index = udev->controller_slot_id;
3742 pcinp = &sc->sc_hw.devs[index].input_pc;
3744 usbd_get_page(pcinp, 0, &buf_inp);
3746 edesc = xfer->endpoint->edesc;
3748 epno = edesc->bEndpointAddress;
3750 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3753 epno = XHCI_EPNO2EPID(epno);
3756 return (USB_ERR_NO_PIPE); /* invalid */
3760 /* configure endpoint */
3762 err = xhci_configure_endpoint_by_xfer(xfer);
3765 XHCI_CMD_UNLOCK(sc);
3770 * Get the endpoint into the stopped state according to the
3771 * endpoint context state diagram in the XHCI specification:
3774 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3777 DPRINTF("Could not stop endpoint %u\n", epno);
3779 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3782 DPRINTF("Could not reset endpoint %u\n", epno);
3784 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3785 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3788 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3791 * Get the endpoint into the running state according to the
3792 * endpoint context state diagram in the XHCI specification:
3795 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3798 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3800 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3803 DPRINTF("Could not configure endpoint %u\n", epno);
3805 XHCI_CMD_UNLOCK(sc);
3811 xhci_xfer_unsetup(struct usb_xfer *xfer)
3817 xhci_start_dma_delay(struct usb_xfer *xfer)
3819 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3821 /* put transfer on interrupt queue (again) */
3822 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3824 (void)usb_proc_msignal(&sc->sc_config_proc,
3825 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3829 xhci_configure_msg(struct usb_proc_msg *pm)
3831 struct xhci_softc *sc;
3832 struct xhci_endpoint_ext *pepext;
3833 struct usb_xfer *xfer;
3835 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3838 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3840 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3841 xfer->endpoint->edesc);
3843 if ((pepext->trb_halted != 0) ||
3844 (pepext->trb_running == 0)) {
3848 /* clear halted and running */
3849 pepext->trb_halted = 0;
3850 pepext->trb_running = 0;
3852 /* nuke remaining buffered transfers */
3854 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3856 * NOTE: We need to use the timeout
3857 * error code here else existing
3858 * isochronous clients can get
3861 if (pepext->xfer[i] != NULL) {
3862 xhci_device_done(pepext->xfer[i],
3868 * NOTE: The USB transfer cannot vanish in
3872 USB_BUS_UNLOCK(&sc->sc_bus);
3874 xhci_configure_reset_endpoint(xfer);
3876 USB_BUS_LOCK(&sc->sc_bus);
3878 /* check if halted is still cleared */
3879 if (pepext->trb_halted == 0) {
3880 pepext->trb_running = 1;
3881 pepext->trb_index = 0;
3886 if (xfer->flags_int.did_dma_delay) {
3888 /* remove transfer from interrupt queue (again) */
3889 usbd_transfer_dequeue(xfer);
3891 /* we are finally done */
3892 usb_dma_delay_done_cb(xfer);
3894 /* queue changed - restart */
3899 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3901 /* try to insert xfer on HW queue */
3902 xhci_transfer_insert(xfer);
3904 /* try to multi buffer */
3905 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3910 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3911 struct usb_endpoint *ep)
3913 struct xhci_endpoint_ext *pepext;
3915 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3916 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3918 if (udev->flags.usb_mode != USB_MODE_HOST) {
3922 if (udev->parent_hub == NULL) {
3923 /* root HUB has special endpoint handling */
3927 ep->methods = &xhci_device_generic_methods;
3929 pepext = xhci_get_endpoint_ext(udev, edesc);
3931 USB_BUS_LOCK(udev->bus);
3932 pepext->trb_halted = 1;
3933 pepext->trb_running = 0;
3934 USB_BUS_UNLOCK(udev->bus);
3938 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3944 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3946 struct xhci_endpoint_ext *pepext;
3950 if (udev->flags.usb_mode != USB_MODE_HOST) {
3954 if (udev->parent_hub == NULL) {
3955 /* root HUB has special endpoint handling */
3959 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3961 USB_BUS_LOCK(udev->bus);
3962 pepext->trb_halted = 1;
3963 pepext->trb_running = 0;
3964 USB_BUS_UNLOCK(udev->bus);
3968 xhci_device_init(struct usb_device *udev)
3970 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3974 /* no init for root HUB */
3975 if (udev->parent_hub == NULL)
3980 /* set invalid default */
3982 udev->controller_slot_id = sc->sc_noslot + 1;
3984 /* try to get a new slot ID from the XHCI */
3986 err = xhci_cmd_enable_slot(sc, &temp);
3989 XHCI_CMD_UNLOCK(sc);
3993 if (temp > sc->sc_noslot) {
3994 XHCI_CMD_UNLOCK(sc);
3995 return (USB_ERR_BAD_ADDRESS);
3998 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3999 DPRINTF("slot %u already allocated.\n", temp);
4000 XHCI_CMD_UNLOCK(sc);
4001 return (USB_ERR_BAD_ADDRESS);
4004 /* store slot ID for later reference */
4006 udev->controller_slot_id = temp;
4008 /* reset data structure */
4010 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4012 /* set mark slot allocated */
4014 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4016 err = xhci_alloc_device_ext(udev);
4018 XHCI_CMD_UNLOCK(sc);
4020 /* get device into default state */
4023 err = xhci_set_address(udev, NULL, 0);
4029 xhci_device_uninit(struct usb_device *udev)
4031 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4034 /* no init for root HUB */
4035 if (udev->parent_hub == NULL)
4040 index = udev->controller_slot_id;
4042 if (index <= sc->sc_noslot) {
4043 xhci_cmd_disable_slot(sc, index);
4044 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4046 /* free device extension */
4047 xhci_free_device_ext(udev);
4050 XHCI_CMD_UNLOCK(sc);
4054 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4057 * Wait until the hardware has finished any possible use of
4058 * the transfer descriptor(s)
4060 *pus = 2048; /* microseconds */
4064 xhci_device_resume(struct usb_device *udev)
4066 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4073 /* check for root HUB */
4074 if (udev->parent_hub == NULL)
4077 index = udev->controller_slot_id;
4081 /* blindly resume all endpoints */
4083 USB_BUS_LOCK(udev->bus);
4085 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4086 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4087 XWRITE4(sc, door, XHCI_DOORBELL(index),
4088 n | XHCI_DB_SID_SET(p));
4092 USB_BUS_UNLOCK(udev->bus);
4094 XHCI_CMD_UNLOCK(sc);
4098 xhci_device_suspend(struct usb_device *udev)
4100 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4107 /* check for root HUB */
4108 if (udev->parent_hub == NULL)
4111 index = udev->controller_slot_id;
4115 /* blindly suspend all endpoints */
4117 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4118 err = xhci_cmd_stop_ep(sc, 1, n, index);
4120 DPRINTF("Failed to suspend endpoint "
4121 "%u on slot %u (ignored).\n", n, index);
4125 XHCI_CMD_UNLOCK(sc);
4129 xhci_set_hw_power(struct usb_bus *bus)
4135 xhci_device_state_change(struct usb_device *udev)
4137 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4138 struct usb_page_search buf_inp;
4142 /* check for root HUB */
4143 if (udev->parent_hub == NULL)
4146 index = udev->controller_slot_id;
4150 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4151 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4152 &sc->sc_hw.devs[index].tt);
4154 sc->sc_hw.devs[index].nports = 0;
4159 switch (usb_get_device_state(udev)) {
4160 case USB_STATE_POWERED:
4161 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4164 /* set default state */
4165 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4167 /* reset number of contexts */
4168 sc->sc_hw.devs[index].context_num = 0;
4170 err = xhci_cmd_reset_dev(sc, index);
4173 DPRINTF("Device reset failed "
4174 "for slot %u.\n", index);
4178 case USB_STATE_ADDRESSED:
4179 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4182 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4184 /* set configure mask to slot only */
4185 xhci_configure_mask(udev, 1, 0);
4187 /* deconfigure all endpoints, except EP0 */
4188 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4191 DPRINTF("Failed to deconfigure "
4192 "slot %u.\n", index);
4196 case USB_STATE_CONFIGURED:
4197 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4200 /* set configured state */
4201 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4203 /* reset number of contexts */
4204 sc->sc_hw.devs[index].context_num = 0;
4206 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4208 xhci_configure_mask(udev, 3, 0);
4210 err = xhci_configure_device(udev);
4212 DPRINTF("Could not configure device "
4213 "at slot %u.\n", index);
4216 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4218 DPRINTF("Could not evaluate device "
4219 "context at slot %u.\n", index);
4226 XHCI_CMD_UNLOCK(sc);
4229 struct usb_bus_methods xhci_bus_methods = {
4230 .endpoint_init = xhci_ep_init,
4231 .endpoint_uninit = xhci_ep_uninit,
4232 .xfer_setup = xhci_xfer_setup,
4233 .xfer_unsetup = xhci_xfer_unsetup,
4234 .get_dma_delay = xhci_get_dma_delay,
4235 .device_init = xhci_device_init,
4236 .device_uninit = xhci_device_uninit,
4237 .device_resume = xhci_device_resume,
4238 .device_suspend = xhci_device_suspend,
4239 .set_hw_power = xhci_set_hw_power,
4240 .roothub_exec = xhci_roothub_exec,
4241 .xfer_poll = xhci_do_poll,
4242 .start_dma_delay = xhci_start_dma_delay,
4243 .set_address = xhci_set_address,
4244 .clear_stall = xhci_ep_clear_stall,
4245 .device_state_change = xhci_device_state_change,
4246 .set_hw_power_sleep = xhci_set_hw_power_sleep,