3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
68 #define USB_DEBUG_VAR xhcidebug
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif /* USB_GLOBAL_INCLUDE_FILE */
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
86 #define XHCI_BUS2SC(bus) \
87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
94 &xhcistreams, 0, "Set to enable streams mode support");
95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
100 static int xhcipolling;
102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
103 &xhcidebug, 0, "Debug level");
104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
115 #define XHCI_INTR_ENDPT 1
117 struct xhci_std_temp {
118 struct xhci_softc *sc;
119 struct usb_page_cache *pc;
121 struct xhci_td *td_next;
124 uint32_t max_packet_size;
136 uint8_t do_isoc_sync;
139 static void xhci_do_poll(struct usb_bus *);
140 static void xhci_device_done(struct usb_xfer *, usb_error_t);
141 static void xhci_root_intr(struct xhci_softc *);
142 static void xhci_free_device_ext(struct usb_device *);
143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
144 struct usb_endpoint_descriptor *);
145 static usb_proc_callback_t xhci_configure_msg;
146 static usb_error_t xhci_configure_device(struct usb_device *);
147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
151 static usb_error_t xhci_configure_mask(struct usb_device *,
153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
155 static void xhci_endpoint_doorbell(struct usb_xfer *);
156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
163 extern struct usb_bus_methods xhci_bus_methods;
167 xhci_dump_trb(struct xhci_trb *trb)
169 DPRINTFN(5, "trb = %p\n", trb);
170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
178 DPRINTFN(5, "pep = %p\n", pep);
179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
191 DPRINTFN(5, "psl = %p\n", psl);
192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
200 xhci_use_polling(void)
203 return (xhcipolling != 0);
210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
212 struct xhci_softc *sc = XHCI_BUS2SC(bus);
215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
230 if (sc->sc_ctx_is_64_byte) {
232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
233 /* all contexts are initially 32-bytes */
234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
243 if (sc->sc_ctx_is_64_byte) {
245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
246 /* all contexts are initially 32-bytes */
247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
250 return (le32toh(*ptr));
254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
256 if (sc->sc_ctx_is_64_byte) {
258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
259 /* all contexts are initially 32-bytes */
260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
270 if (sc->sc_ctx_is_64_byte) {
272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
273 /* all contexts are initially 32-bytes */
274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
277 return (le64toh(*ptr));
282 xhci_start_controller(struct xhci_softc *sc)
284 struct usb_page_search buf_res;
285 struct xhci_hw_root *phwr;
286 struct xhci_dev_ctx_addr *pdctxa;
294 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
295 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
296 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
298 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
299 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
300 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
302 sc->sc_event_ccs = 1;
303 sc->sc_event_idx = 0;
304 sc->sc_command_ccs = 1;
305 sc->sc_command_idx = 0;
307 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
309 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
311 DPRINTF("HCS0 = 0x%08x\n", temp);
313 if (XHCI_HCS0_CSZ(temp)) {
314 sc->sc_ctx_is_64_byte = 1;
315 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
317 sc->sc_ctx_is_64_byte = 0;
318 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
321 /* Reset controller */
322 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
324 for (i = 0; i != 100; i++) {
325 usb_pause_mtx(NULL, hz / 100);
326 temp = XREAD4(sc, oper, XHCI_USBCMD) &
327 (XHCI_CMD_HCRST | XHCI_STS_CNR);
333 device_printf(sc->sc_bus.parent, "Controller "
335 return (USB_ERR_IOERROR);
338 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
339 device_printf(sc->sc_bus.parent, "Controller does "
340 "not support 4K page size.\n");
341 return (USB_ERR_IOERROR);
344 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
346 i = XHCI_HCS1_N_PORTS(temp);
349 device_printf(sc->sc_bus.parent, "Invalid number "
350 "of ports: %u\n", i);
351 return (USB_ERR_IOERROR);
355 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
357 if (sc->sc_noslot > XHCI_MAX_DEVICES)
358 sc->sc_noslot = XHCI_MAX_DEVICES;
360 /* setup number of device slots */
362 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
363 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
365 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
367 DPRINTF("Max slots: %u\n", sc->sc_noslot);
369 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
371 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
373 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
374 device_printf(sc->sc_bus.parent, "XHCI request "
375 "too many scratchpads\n");
376 return (USB_ERR_NOMEM);
379 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
381 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
383 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
384 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
386 temp = XREAD4(sc, oper, XHCI_USBSTS);
388 /* clear interrupts */
389 XWRITE4(sc, oper, XHCI_USBSTS, temp);
390 /* disable all device notifications */
391 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
393 /* setup device context base address */
394 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
395 pdctxa = buf_res.buffer;
396 memset(pdctxa, 0, sizeof(*pdctxa));
398 addr = buf_res.physaddr;
399 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
401 /* slot 0 points to the table of scratchpad pointers */
402 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
404 for (i = 0; i != sc->sc_noscratch; i++) {
405 struct usb_page_search buf_scp;
406 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
407 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
410 addr = buf_res.physaddr;
412 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
413 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
414 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
415 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
417 /* Setup event table size */
419 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
421 DPRINTF("HCS2=0x%08x\n", temp);
423 temp = XHCI_HCS2_ERST_MAX(temp);
425 if (temp > XHCI_MAX_RSEG)
426 temp = XHCI_MAX_RSEG;
428 sc->sc_erst_max = temp;
430 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
431 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
433 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
435 /* Setup interrupt rate */
436 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
438 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
440 phwr = buf_res.buffer;
441 addr = buf_res.physaddr;
442 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
444 /* reset hardware root structure */
445 memset(phwr, 0, sizeof(*phwr));
447 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
448 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
450 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
452 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
453 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
455 addr = (uint64_t)buf_res.physaddr;
457 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
459 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
460 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
462 /* Setup interrupter registers */
464 temp = XREAD4(sc, runt, XHCI_IMAN(0));
465 temp |= XHCI_IMAN_INTR_ENA;
466 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
468 /* setup command ring control base address */
469 addr = buf_res.physaddr;
470 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
472 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
474 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
475 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
477 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
479 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
482 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
483 XHCI_CMD_INTE | XHCI_CMD_HSEE);
485 for (i = 0; i != 100; i++) {
486 usb_pause_mtx(NULL, hz / 100);
487 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
492 XWRITE4(sc, oper, XHCI_USBCMD, 0);
493 device_printf(sc->sc_bus.parent, "Run timeout.\n");
494 return (USB_ERR_IOERROR);
497 /* catch any lost interrupts */
498 xhci_do_poll(&sc->sc_bus);
500 if (sc->sc_port_route != NULL) {
501 /* Route all ports to the XHCI by default */
502 sc->sc_port_route(sc->sc_bus.parent,
503 ~xhciroute, xhciroute);
509 xhci_halt_controller(struct xhci_softc *sc)
517 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
518 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
519 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
521 /* Halt controller */
522 XWRITE4(sc, oper, XHCI_USBCMD, 0);
524 for (i = 0; i != 100; i++) {
525 usb_pause_mtx(NULL, hz / 100);
526 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
532 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
533 return (USB_ERR_IOERROR);
539 xhci_init(struct xhci_softc *sc, device_t self)
541 /* initialise some bus fields */
542 sc->sc_bus.parent = self;
544 /* set the bus revision */
545 sc->sc_bus.usbrev = USB_REV_3_0;
547 /* set up the bus struct */
548 sc->sc_bus.methods = &xhci_bus_methods;
550 /* setup devices array */
551 sc->sc_bus.devices = sc->sc_devices;
552 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
554 /* setup command queue mutex and condition varible */
555 cv_init(&sc->sc_cmd_cv, "CMDQ");
556 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
558 /* get all DMA memory */
559 if (usb_bus_mem_alloc_all(&sc->sc_bus,
560 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
564 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
565 sc->sc_config_msg[0].bus = &sc->sc_bus;
566 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
567 sc->sc_config_msg[1].bus = &sc->sc_bus;
573 xhci_uninit(struct xhci_softc *sc)
576 * NOTE: At this point the control transfer process is gone
577 * and "xhci_configure_msg" is no longer called. Consequently
578 * waiting for the configuration messages to complete is not
581 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
583 cv_destroy(&sc->sc_cmd_cv);
584 sx_destroy(&sc->sc_cmd_sx);
588 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
590 struct xhci_softc *sc = XHCI_BUS2SC(bus);
593 case USB_HW_POWER_SUSPEND:
594 DPRINTF("Stopping the XHCI\n");
595 xhci_halt_controller(sc);
597 case USB_HW_POWER_SHUTDOWN:
598 DPRINTF("Stopping the XHCI\n");
599 xhci_halt_controller(sc);
601 case USB_HW_POWER_RESUME:
602 DPRINTF("Starting the XHCI\n");
603 xhci_start_controller(sc);
611 xhci_generic_done_sub(struct usb_xfer *xfer)
614 struct xhci_td *td_alt_next;
618 td = xfer->td_transfer_cache;
619 td_alt_next = td->alt_next;
621 if (xfer->aframes != xfer->nframes)
622 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
626 usb_pc_cpu_invalidate(td->page_cache);
631 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
632 xfer, (unsigned int)xfer->aframes,
633 (unsigned int)xfer->nframes,
634 (unsigned int)len, (unsigned int)td->len,
635 (unsigned int)status);
638 * Verify the status length and
639 * add the length to "frlengths[]":
642 /* should not happen */
643 DPRINTF("Invalid status length, "
644 "0x%04x/0x%04x bytes\n", len, td->len);
645 status = XHCI_TRB_ERROR_LENGTH;
646 } else if (xfer->aframes != xfer->nframes) {
647 xfer->frlengths[xfer->aframes] += td->len - len;
649 /* Check for last transfer */
650 if (((void *)td) == xfer->td_transfer_last) {
654 /* Check for transfer error */
655 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
656 status != XHCI_TRB_ERROR_SUCCESS) {
657 /* the transfer is finished */
661 /* Check for short transfer */
663 if (xfer->flags_int.short_frames_ok ||
664 xfer->flags_int.isochronous_xfr ||
665 xfer->flags_int.control_xfr) {
666 /* follow alt next */
669 /* the transfer is finished */
676 if (td->alt_next != td_alt_next) {
677 /* this USB frame is complete */
682 /* update transfer cache */
684 xfer->td_transfer_cache = td;
686 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
687 (status != XHCI_TRB_ERROR_SHORT_PKT &&
688 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
689 USB_ERR_NORMAL_COMPLETION);
693 xhci_generic_done(struct usb_xfer *xfer)
697 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
698 xfer, xfer->endpoint);
702 xfer->td_transfer_cache = xfer->td_transfer_first;
704 if (xfer->flags_int.control_xfr) {
706 if (xfer->flags_int.control_hdr)
707 err = xhci_generic_done_sub(xfer);
711 if (xfer->td_transfer_cache == NULL)
715 while (xfer->aframes != xfer->nframes) {
717 err = xhci_generic_done_sub(xfer);
720 if (xfer->td_transfer_cache == NULL)
724 if (xfer->flags_int.control_xfr &&
725 !xfer->flags_int.control_act)
726 err = xhci_generic_done_sub(xfer);
728 /* transfer is complete */
729 xhci_device_done(xfer, err);
733 xhci_activate_transfer(struct usb_xfer *xfer)
737 td = xfer->td_transfer_cache;
739 usb_pc_cpu_invalidate(td->page_cache);
741 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
743 /* activate the transfer */
745 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
746 usb_pc_cpu_flush(td->page_cache);
748 xhci_endpoint_doorbell(xfer);
753 xhci_skip_transfer(struct usb_xfer *xfer)
756 struct xhci_td *td_last;
758 td = xfer->td_transfer_cache;
759 td_last = xfer->td_transfer_last;
763 usb_pc_cpu_invalidate(td->page_cache);
765 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
767 usb_pc_cpu_invalidate(td_last->page_cache);
769 /* copy LINK TRB to current waiting location */
771 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
772 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
773 usb_pc_cpu_flush(td->page_cache);
775 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
776 usb_pc_cpu_flush(td->page_cache);
778 xhci_endpoint_doorbell(xfer);
782 /*------------------------------------------------------------------------*
783 * xhci_check_transfer
784 *------------------------------------------------------------------------*/
786 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
788 struct xhci_endpoint_ext *pepext;
801 td_event = le64toh(trb->qwTrb0);
802 temp = le32toh(trb->dwTrb2);
804 remainder = XHCI_TRB_2_REM_GET(temp);
805 status = XHCI_TRB_2_ERROR_GET(temp);
806 stream_id = XHCI_TRB_2_STREAM_GET(temp);
808 temp = le32toh(trb->dwTrb3);
809 epno = XHCI_TRB_3_EP_GET(temp);
810 index = XHCI_TRB_3_SLOT_GET(temp);
812 /* check if error means halted */
813 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
814 status != XHCI_TRB_ERROR_SUCCESS);
816 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
817 index, epno, stream_id, remainder, status);
819 if (index > sc->sc_noslot) {
820 DPRINTF("Invalid slot.\n");
824 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
825 DPRINTF("Invalid endpoint.\n");
829 pepext = &sc->sc_hw.devs[index].endp[epno];
831 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
833 DPRINTF("stream_id=0\n");
834 } else if (stream_id >= XHCI_MAX_STREAMS) {
835 DPRINTF("Invalid stream ID.\n");
839 /* try to find the USB transfer that generated the event */
840 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
841 struct usb_xfer *xfer;
844 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
848 td = xfer->td_transfer_cache;
850 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
852 (long long)td->td_self,
853 (long long)td->td_self + sizeof(td->td_trb));
856 * NOTE: Some XHCI implementations might not trigger
857 * an event on the last LINK TRB so we need to
858 * consider both the last and second last event
859 * address as conditions for a successful transfer.
861 * NOTE: We assume that the XHCI will only trigger one
862 * event per chain of TRBs.
865 offset = td_event - td->td_self;
868 offset < (int64_t)sizeof(td->td_trb)) {
870 usb_pc_cpu_invalidate(td->page_cache);
872 /* compute rest of remainder, if any */
873 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
874 temp = le32toh(td->td_trb[i].dwTrb2);
875 remainder += XHCI_TRB_2_BYTES_GET(temp);
878 DPRINTFN(5, "New remainder: %u\n", remainder);
880 /* clear isochronous transfer errors */
881 if (xfer->flags_int.isochronous_xfr) {
884 status = XHCI_TRB_ERROR_SUCCESS;
889 /* "td->remainder" is verified later */
890 td->remainder = remainder;
893 usb_pc_cpu_flush(td->page_cache);
896 * 1) Last transfer descriptor makes the
899 if (((void *)td) == xfer->td_transfer_last) {
900 DPRINTF("TD is last\n");
901 xhci_generic_done(xfer);
906 * 2) Any kind of error makes the transfer
910 DPRINTF("TD has I/O error\n");
911 xhci_generic_done(xfer);
916 * 3) If there is no alternate next transfer,
917 * a short packet also makes the transfer done
919 if (td->remainder > 0) {
920 if (td->alt_next == NULL) {
922 "short TD has no alternate next\n");
923 xhci_generic_done(xfer);
926 DPRINTF("TD has short pkt\n");
927 if (xfer->flags_int.short_frames_ok ||
928 xfer->flags_int.isochronous_xfr ||
929 xfer->flags_int.control_xfr) {
930 /* follow the alt next */
931 xfer->td_transfer_cache = td->alt_next;
932 xhci_activate_transfer(xfer);
935 xhci_skip_transfer(xfer);
936 xhci_generic_done(xfer);
941 * 4) Transfer complete - go to next TD
943 DPRINTF("Following next TD\n");
944 xfer->td_transfer_cache = td->obj_next;
945 xhci_activate_transfer(xfer);
946 break; /* there should only be one match */
952 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
954 if (sc->sc_cmd_addr == trb->qwTrb0) {
955 DPRINTF("Received command event\n");
956 sc->sc_cmd_result[0] = trb->dwTrb2;
957 sc->sc_cmd_result[1] = trb->dwTrb3;
958 cv_signal(&sc->sc_cmd_cv);
959 return (1); /* command match */
965 xhci_interrupt_poll(struct xhci_softc *sc)
967 struct usb_page_search buf_res;
968 struct xhci_hw_root *phwr;
978 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
980 phwr = buf_res.buffer;
982 /* Receive any events */
984 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
986 i = sc->sc_event_idx;
987 j = sc->sc_event_ccs;
992 temp = le32toh(phwr->hwr_events[i].dwTrb3);
994 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
999 event = XHCI_TRB_3_TYPE_GET(temp);
1001 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1002 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1003 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1004 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1007 case XHCI_TRB_EVENT_TRANSFER:
1008 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1010 case XHCI_TRB_EVENT_CMD_COMPLETE:
1011 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1014 DPRINTF("Unhandled event = %u\n", event);
1020 if (i == XHCI_MAX_EVENTS) {
1024 /* check for timeout */
1030 sc->sc_event_idx = i;
1031 sc->sc_event_ccs = j;
1034 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1035 * latched. That means to activate the register we need to
1036 * write both the low and high double word of the 64-bit
1040 addr = (uint32_t)buf_res.physaddr;
1041 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1043 /* try to clear busy bit */
1044 addr |= XHCI_ERDP_LO_BUSY;
1046 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1047 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1053 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1054 uint16_t timeout_ms)
1056 struct usb_page_search buf_res;
1057 struct xhci_hw_root *phwr;
1064 XHCI_CMD_ASSERT_LOCKED(sc);
1066 /* get hardware root structure */
1068 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1070 phwr = buf_res.buffer;
1074 USB_BUS_LOCK(&sc->sc_bus);
1076 i = sc->sc_command_idx;
1077 j = sc->sc_command_ccs;
1079 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1080 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1081 (long long)le64toh(trb->qwTrb0),
1082 (long)le32toh(trb->dwTrb2),
1083 (long)le32toh(trb->dwTrb3));
1085 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1086 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1088 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1093 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1095 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1097 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1099 phwr->hwr_commands[i].dwTrb3 = temp;
1101 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1103 addr = buf_res.physaddr;
1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1106 sc->sc_cmd_addr = htole64(addr);
1110 if (i == (XHCI_MAX_COMMANDS - 1)) {
1113 temp = htole32(XHCI_TRB_3_TC_BIT |
1114 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1115 XHCI_TRB_3_CYCLE_BIT);
1117 temp = htole32(XHCI_TRB_3_TC_BIT |
1118 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1121 phwr->hwr_commands[i].dwTrb3 = temp;
1123 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1129 sc->sc_command_idx = i;
1130 sc->sc_command_ccs = j;
1132 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1134 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1135 USB_MS_TO_TICKS(timeout_ms));
1138 * In some error cases event interrupts are not generated.
1139 * Poll one time to see if the command has completed.
1141 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1142 DPRINTF("Command was completed when polling\n");
1146 DPRINTFN(0, "Command timeout!\n");
1147 err = USB_ERR_TIMEOUT;
1151 temp = le32toh(sc->sc_cmd_result[0]);
1152 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1153 err = USB_ERR_IOERROR;
1155 trb->dwTrb2 = sc->sc_cmd_result[0];
1156 trb->dwTrb3 = sc->sc_cmd_result[1];
1159 USB_BUS_UNLOCK(&sc->sc_bus);
1166 xhci_cmd_nop(struct xhci_softc *sc)
1168 struct xhci_trb trb;
1175 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1177 trb.dwTrb3 = htole32(temp);
1179 return (xhci_do_command(sc, &trb, 100 /* ms */));
1184 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1186 struct xhci_trb trb;
1194 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1196 err = xhci_do_command(sc, &trb, 100 /* ms */);
1200 temp = le32toh(trb.dwTrb3);
1202 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1209 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1211 struct xhci_trb trb;
1218 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1219 XHCI_TRB_3_SLOT_SET(slot_id);
1221 trb.dwTrb3 = htole32(temp);
1223 return (xhci_do_command(sc, &trb, 100 /* ms */));
1227 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1228 uint8_t bsr, uint8_t slot_id)
1230 struct xhci_trb trb;
1235 trb.qwTrb0 = htole64(input_ctx);
1237 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1238 XHCI_TRB_3_SLOT_SET(slot_id);
1241 temp |= XHCI_TRB_3_BSR_BIT;
1243 trb.dwTrb3 = htole32(temp);
1245 return (xhci_do_command(sc, &trb, 500 /* ms */));
1249 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1251 struct usb_page_search buf_inp;
1252 struct usb_page_search buf_dev;
1253 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1254 struct xhci_hw_dev *hdev;
1255 struct xhci_dev_ctx *pdev;
1256 struct xhci_endpoint_ext *pepext;
1262 /* the root HUB case is not handled here */
1263 if (udev->parent_hub == NULL)
1264 return (USB_ERR_INVAL);
1266 index = udev->controller_slot_id;
1268 hdev = &sc->sc_hw.devs[index];
1275 switch (hdev->state) {
1276 case XHCI_ST_DEFAULT:
1277 case XHCI_ST_ENABLED:
1279 hdev->state = XHCI_ST_ENABLED;
1281 /* set configure mask to slot and EP0 */
1282 xhci_configure_mask(udev, 3, 0);
1284 /* configure input slot context structure */
1285 err = xhci_configure_device(udev);
1288 DPRINTF("Could not configure device\n");
1292 /* configure input endpoint context structure */
1293 switch (udev->speed) {
1295 case USB_SPEED_FULL:
1298 case USB_SPEED_HIGH:
1306 pepext = xhci_get_endpoint_ext(udev,
1307 &udev->ctrl_ep_desc);
1308 err = xhci_configure_endpoint(udev,
1309 &udev->ctrl_ep_desc, pepext,
1310 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1313 DPRINTF("Could not configure default endpoint\n");
1317 /* execute set address command */
1318 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1320 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1321 (address == 0), index);
1324 temp = le32toh(sc->sc_cmd_result[0]);
1325 if (address == 0 && sc->sc_port_route != NULL &&
1326 XHCI_TRB_2_ERROR_GET(temp) ==
1327 XHCI_TRB_ERROR_PARAMETER) {
1328 /* LynxPoint XHCI - ports are not switchable */
1329 /* Un-route all ports from the XHCI */
1330 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1332 DPRINTF("Could not set address "
1333 "for slot %u.\n", index);
1338 /* update device address to new value */
1340 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1341 pdev = buf_dev.buffer;
1342 usb_pc_cpu_invalidate(&hdev->device_pc);
1344 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1345 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1347 /* update device state to new value */
1350 hdev->state = XHCI_ST_ADDRESSED;
1352 hdev->state = XHCI_ST_DEFAULT;
1356 DPRINTF("Wrong state for set address.\n");
1357 err = USB_ERR_IOERROR;
1360 XHCI_CMD_UNLOCK(sc);
1369 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1370 uint8_t deconfigure, uint8_t slot_id)
1372 struct xhci_trb trb;
1377 trb.qwTrb0 = htole64(input_ctx);
1379 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1380 XHCI_TRB_3_SLOT_SET(slot_id);
1383 temp |= XHCI_TRB_3_DCEP_BIT;
1385 trb.dwTrb3 = htole32(temp);
1387 return (xhci_do_command(sc, &trb, 100 /* ms */));
1391 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1394 struct xhci_trb trb;
1399 trb.qwTrb0 = htole64(input_ctx);
1401 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1402 XHCI_TRB_3_SLOT_SET(slot_id);
1403 trb.dwTrb3 = htole32(temp);
1405 return (xhci_do_command(sc, &trb, 100 /* ms */));
1409 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1410 uint8_t ep_id, uint8_t slot_id)
1412 struct xhci_trb trb;
1419 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1420 XHCI_TRB_3_SLOT_SET(slot_id) |
1421 XHCI_TRB_3_EP_SET(ep_id);
1424 temp |= XHCI_TRB_3_PRSV_BIT;
1426 trb.dwTrb3 = htole32(temp);
1428 return (xhci_do_command(sc, &trb, 100 /* ms */));
1432 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1433 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1435 struct xhci_trb trb;
1440 trb.qwTrb0 = htole64(dequeue_ptr);
1442 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1443 trb.dwTrb2 = htole32(temp);
1445 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1446 XHCI_TRB_3_SLOT_SET(slot_id) |
1447 XHCI_TRB_3_EP_SET(ep_id);
1448 trb.dwTrb3 = htole32(temp);
1450 return (xhci_do_command(sc, &trb, 100 /* ms */));
1454 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1455 uint8_t ep_id, uint8_t slot_id)
1457 struct xhci_trb trb;
1464 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1465 XHCI_TRB_3_SLOT_SET(slot_id) |
1466 XHCI_TRB_3_EP_SET(ep_id);
1469 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1471 trb.dwTrb3 = htole32(temp);
1473 return (xhci_do_command(sc, &trb, 100 /* ms */));
1477 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1479 struct xhci_trb trb;
1486 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1487 XHCI_TRB_3_SLOT_SET(slot_id);
1489 trb.dwTrb3 = htole32(temp);
1491 return (xhci_do_command(sc, &trb, 100 /* ms */));
1494 /*------------------------------------------------------------------------*
1495 * xhci_interrupt - XHCI interrupt handler
1496 *------------------------------------------------------------------------*/
1498 xhci_interrupt(struct xhci_softc *sc)
1502 USB_BUS_LOCK(&sc->sc_bus);
1504 status = XREAD4(sc, oper, XHCI_USBSTS);
1508 /* acknowledge interrupts */
1510 XWRITE4(sc, oper, XHCI_USBSTS, status);
1512 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1514 if (status & XHCI_STS_EINT) {
1515 /* check for event(s) */
1516 xhci_interrupt_poll(sc);
1519 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1520 XHCI_STS_HSE | XHCI_STS_HCE)) {
1522 if (status & XHCI_STS_PCD) {
1526 if (status & XHCI_STS_HCH) {
1527 printf("%s: host controller halted\n",
1531 if (status & XHCI_STS_HSE) {
1532 printf("%s: host system error\n",
1536 if (status & XHCI_STS_HCE) {
1537 printf("%s: host controller error\n",
1542 USB_BUS_UNLOCK(&sc->sc_bus);
1545 /*------------------------------------------------------------------------*
1546 * xhci_timeout - XHCI timeout handler
1547 *------------------------------------------------------------------------*/
1549 xhci_timeout(void *arg)
1551 struct usb_xfer *xfer = arg;
1553 DPRINTF("xfer=%p\n", xfer);
1555 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1557 /* transfer is transferred */
1558 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1562 xhci_do_poll(struct usb_bus *bus)
1564 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1566 USB_BUS_LOCK(&sc->sc_bus);
1567 xhci_interrupt_poll(sc);
1568 USB_BUS_UNLOCK(&sc->sc_bus);
1572 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1574 struct usb_page_search buf_res;
1576 struct xhci_td *td_next;
1577 struct xhci_td *td_alt_next;
1578 struct xhci_td *td_first;
1579 uint32_t buf_offset;
1584 uint8_t shortpkt_old;
1590 shortpkt_old = temp->shortpkt;
1591 len_old = temp->len;
1598 td_next = td_first = temp->td_next;
1602 if (temp->len == 0) {
1607 /* send a Zero Length Packet, ZLP, last */
1614 average = temp->average;
1616 if (temp->len < average) {
1617 if (temp->len % temp->max_packet_size) {
1620 average = temp->len;
1624 if (td_next == NULL)
1625 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1630 td_next = td->obj_next;
1632 /* check if we are pre-computing */
1636 /* update remaining length */
1638 temp->len -= average;
1642 /* fill out current TD */
1648 /* update remaining length */
1650 temp->len -= average;
1652 /* reset TRB index */
1656 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1657 /* immediate data */
1662 td->td_trb[0].qwTrb0 = 0;
1664 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1665 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1668 dword = XHCI_TRB_2_BYTES_SET(8) |
1669 XHCI_TRB_2_TDSZ_SET(0) |
1670 XHCI_TRB_2_IRQ_SET(0);
1672 td->td_trb[0].dwTrb2 = htole32(dword);
1674 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1675 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1678 if (td->td_trb[0].qwTrb0 &
1679 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1680 if (td->td_trb[0].qwTrb0 & htole64(1))
1681 dword |= XHCI_TRB_3_TRT_IN;
1683 dword |= XHCI_TRB_3_TRT_OUT;
1686 td->td_trb[0].dwTrb3 = htole32(dword);
1688 xhci_dump_trb(&td->td_trb[x]);
1696 /* fill out buffer pointers */
1699 memset(&buf_res, 0, sizeof(buf_res));
1701 usbd_get_page(temp->pc, temp->offset +
1702 buf_offset, &buf_res);
1704 /* get length to end of page */
1705 if (buf_res.length > average)
1706 buf_res.length = average;
1708 /* check for maximum length */
1709 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1710 buf_res.length = XHCI_TD_PAGE_SIZE;
1712 npkt_off += buf_res.length;
1716 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1717 temp->max_packet_size;
1724 /* fill out TRB's */
1725 td->td_trb[x].qwTrb0 =
1726 htole64((uint64_t)buf_res.physaddr);
1729 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1730 XHCI_TRB_2_TDSZ_SET(npkt) |
1731 XHCI_TRB_2_IRQ_SET(0);
1733 td->td_trb[x].dwTrb2 = htole32(dword);
1735 switch (temp->trb_type) {
1736 case XHCI_TRB_TYPE_ISOCH:
1737 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1738 XHCI_TRB_3_TBC_SET(temp->tbc) |
1739 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1740 if (td != td_first) {
1741 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1742 } else if (temp->do_isoc_sync != 0) {
1743 temp->do_isoc_sync = 0;
1744 /* wait until "isoc_frame" */
1745 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1746 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1748 /* start data transfer at next interval */
1749 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1750 XHCI_TRB_3_ISO_SIA_BIT;
1752 if (temp->direction == UE_DIR_IN)
1753 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1755 case XHCI_TRB_TYPE_DATA_STAGE:
1756 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1757 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1758 XHCI_TRB_3_TBC_SET(temp->tbc) |
1759 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1760 if (temp->direction == UE_DIR_IN)
1761 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1763 case XHCI_TRB_TYPE_STATUS_STAGE:
1764 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1766 XHCI_TRB_3_TBC_SET(temp->tbc) |
1767 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1768 if (temp->direction == UE_DIR_IN)
1769 dword |= XHCI_TRB_3_DIR_IN;
1771 default: /* XHCI_TRB_TYPE_NORMAL */
1772 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1773 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1774 XHCI_TRB_3_TBC_SET(temp->tbc) |
1775 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1776 if (temp->direction == UE_DIR_IN)
1777 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1780 td->td_trb[x].dwTrb3 = htole32(dword);
1782 average -= buf_res.length;
1783 buf_offset += buf_res.length;
1785 xhci_dump_trb(&td->td_trb[x]);
1789 } while (average != 0);
1791 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1793 /* store number of data TRB's */
1797 DPRINTF("NTRB=%u\n", x);
1799 /* fill out link TRB */
1801 if (td_next != NULL) {
1802 /* link the current TD with the next one */
1803 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1804 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1806 /* this field will get updated later */
1807 DPRINTF("NOLINK\n");
1810 dword = XHCI_TRB_2_IRQ_SET(0);
1812 td->td_trb[x].dwTrb2 = htole32(dword);
1814 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1815 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1817 td->td_trb[x].dwTrb3 = htole32(dword);
1819 td->alt_next = td_alt_next;
1821 xhci_dump_trb(&td->td_trb[x]);
1823 usb_pc_cpu_flush(td->page_cache);
1829 /* setup alt next pointer, if any */
1830 if (temp->last_frame) {
1833 /* we use this field internally */
1834 td_alt_next = td_next;
1838 temp->shortpkt = shortpkt_old;
1839 temp->len = len_old;
1844 * Remove cycle bit from the first TRB if we are
1847 if (temp->step_td != 0) {
1848 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1849 usb_pc_cpu_flush(td_first->page_cache);
1852 /* clear TD SIZE to zero, hence this is the last TRB */
1853 /* remove chain bit because this is the last TRB in the chain */
1854 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1855 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1857 usb_pc_cpu_flush(td->page_cache);
1860 temp->td_next = td_next;
1864 xhci_setup_generic_chain(struct usb_xfer *xfer)
1866 struct xhci_std_temp temp;
1872 temp.do_isoc_sync = 0;
1876 temp.average = xfer->max_hc_frame_size;
1877 temp.max_packet_size = xfer->max_packet_size;
1878 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1880 temp.last_frame = 0;
1882 temp.multishort = xfer->flags_int.isochronous_xfr ||
1883 xfer->flags_int.control_xfr ||
1884 xfer->flags_int.short_frames_ok;
1886 /* toggle the DMA set we are using */
1887 xfer->flags_int.curr_dma_set ^= 1;
1889 /* get next DMA set */
1890 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1895 xfer->td_transfer_first = td;
1896 xfer->td_transfer_cache = td;
1898 if (xfer->flags_int.isochronous_xfr) {
1901 /* compute multiplier for ISOCHRONOUS transfers */
1902 mult = xfer->endpoint->ecomp ?
1903 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
1905 /* check for USB 2.0 multiplier */
1907 mult = (xfer->endpoint->edesc->
1908 wMaxPacketSize[1] >> 3) & 3;
1916 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1918 DPRINTF("MFINDEX=0x%08x\n", x);
1920 switch (usbd_get_speed(xfer->xroot->udev)) {
1921 case USB_SPEED_FULL:
1923 temp.isoc_delta = 8; /* 1ms */
1924 x += temp.isoc_delta - 1;
1925 x &= ~(temp.isoc_delta - 1);
1928 shift = usbd_xfer_get_fps_shift(xfer);
1929 temp.isoc_delta = 1U << shift;
1930 x += temp.isoc_delta - 1;
1931 x &= ~(temp.isoc_delta - 1);
1932 /* simple frame load balancing */
1933 x += xfer->endpoint->usb_uframe;
1937 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
1939 if ((xfer->endpoint->is_synced == 0) ||
1940 (y < (xfer->nframes << shift)) ||
1941 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
1943 * If there is data underflow or the pipe
1944 * queue is empty we schedule the transfer a
1945 * few frames ahead of the current frame
1946 * position. Else two isochronous transfers
1949 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
1950 xfer->endpoint->is_synced = 1;
1951 temp.do_isoc_sync = 1;
1953 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1956 /* compute isochronous completion time */
1958 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
1960 xfer->isoc_time_complete =
1961 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
1962 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
1965 temp.isoc_frame = xfer->endpoint->isoc_next;
1966 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
1968 xfer->endpoint->isoc_next += xfer->nframes << shift;
1970 } else if (xfer->flags_int.control_xfr) {
1972 /* check if we should prepend a setup message */
1974 if (xfer->flags_int.control_hdr) {
1976 temp.len = xfer->frlengths[0];
1977 temp.pc = xfer->frbuffers + 0;
1978 temp.shortpkt = temp.len ? 1 : 0;
1979 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
1982 /* check for last frame */
1983 if (xfer->nframes == 1) {
1984 /* no STATUS stage yet, SETUP is last */
1985 if (xfer->flags_int.control_act)
1986 temp.last_frame = 1;
1989 xhci_setup_generic_chain_sub(&temp);
1993 temp.isoc_delta = 0;
1994 temp.isoc_frame = 0;
1995 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
1999 temp.isoc_delta = 0;
2000 temp.isoc_frame = 0;
2001 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2004 if (x != xfer->nframes) {
2005 /* setup page_cache pointer */
2006 temp.pc = xfer->frbuffers + x;
2007 /* set endpoint direction */
2008 temp.direction = UE_GET_DIR(xfer->endpointno);
2011 while (x != xfer->nframes) {
2013 /* DATA0 / DATA1 message */
2015 temp.len = xfer->frlengths[x];
2016 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2017 x != 0 && temp.multishort == 0);
2021 if (x == xfer->nframes) {
2022 if (xfer->flags_int.control_xfr) {
2023 /* no STATUS stage yet, DATA is last */
2024 if (xfer->flags_int.control_act)
2025 temp.last_frame = 1;
2027 temp.last_frame = 1;
2030 if (temp.len == 0) {
2032 /* make sure that we send an USB packet */
2037 temp.tlbpc = mult - 1;
2039 } else if (xfer->flags_int.isochronous_xfr) {
2044 * Isochronous transfers don't have short
2045 * packet termination:
2050 /* isochronous transfers have a transfer limit */
2052 if (temp.len > xfer->max_frame_size)
2053 temp.len = xfer->max_frame_size;
2055 /* compute TD packet count */
2056 tdpc = (temp.len + xfer->max_packet_size - 1) /
2057 xfer->max_packet_size;
2059 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2060 temp.tlbpc = (tdpc % mult);
2062 if (temp.tlbpc == 0)
2063 temp.tlbpc = mult - 1;
2068 /* regular data transfer */
2070 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2073 xhci_setup_generic_chain_sub(&temp);
2075 if (xfer->flags_int.isochronous_xfr) {
2076 temp.offset += xfer->frlengths[x - 1];
2077 temp.isoc_frame += temp.isoc_delta;
2079 /* get next Page Cache pointer */
2080 temp.pc = xfer->frbuffers + x;
2084 /* check if we should append a status stage */
2086 if (xfer->flags_int.control_xfr &&
2087 !xfer->flags_int.control_act) {
2090 * Send a DATA1 message and invert the current
2091 * endpoint direction.
2093 temp.step_td = (xfer->nframes != 0);
2094 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2098 temp.last_frame = 1;
2099 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2101 xhci_setup_generic_chain_sub(&temp);
2106 /* must have at least one frame! */
2108 xfer->td_transfer_last = td;
2110 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2114 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2116 struct usb_page_search buf_res;
2117 struct xhci_dev_ctx_addr *pdctxa;
2119 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2121 pdctxa = buf_res.buffer;
2123 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2125 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2127 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2131 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2133 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2134 struct usb_page_search buf_inp;
2135 struct xhci_input_dev_ctx *pinp;
2140 index = udev->controller_slot_id;
2142 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2144 pinp = buf_inp.buffer;
2147 mask &= XHCI_INCTX_NON_CTRL_MASK;
2148 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2149 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2151 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2152 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2154 /* find most significant set bit */
2155 for (x = 31; x != 1; x--) {
2156 if (mask & (1 << x))
2163 /* figure out maximum */
2164 if (x > sc->sc_hw.devs[index].context_num) {
2165 sc->sc_hw.devs[index].context_num = x;
2166 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2167 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2168 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2169 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2176 xhci_configure_endpoint(struct usb_device *udev,
2177 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2178 uint16_t interval, uint8_t max_packet_count,
2179 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2180 uint16_t max_frame_size, uint8_t ep_mode)
2182 struct usb_page_search buf_inp;
2183 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2184 struct xhci_input_dev_ctx *pinp;
2185 uint64_t ring_addr = pepext->physaddr;
2191 index = udev->controller_slot_id;
2193 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2195 pinp = buf_inp.buffer;
2197 epno = edesc->bEndpointAddress;
2198 type = edesc->bmAttributes & UE_XFERTYPE;
2200 if (type == UE_CONTROL)
2203 epno = XHCI_EPNO2EPID(epno);
2206 return (USB_ERR_NO_PIPE); /* invalid */
2208 if (max_packet_count == 0)
2209 return (USB_ERR_BAD_BUFSIZE);
2214 return (USB_ERR_BAD_BUFSIZE);
2216 /* store endpoint mode */
2217 pepext->trb_ep_mode = ep_mode;
2218 usb_pc_cpu_flush(pepext->page_cache);
2220 if (ep_mode == USB_EP_MODE_STREAMS) {
2221 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2222 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2223 XHCI_EPCTX_0_LSA_SET(1);
2225 ring_addr += sizeof(struct xhci_trb) *
2226 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2228 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2229 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2230 XHCI_EPCTX_0_LSA_SET(0);
2232 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2235 switch (udev->speed) {
2236 case USB_SPEED_FULL:
2249 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2251 case UE_ISOCHRONOUS:
2252 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2254 switch (udev->speed) {
2255 case USB_SPEED_SUPER:
2258 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2259 max_packet_count /= mult;
2269 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2272 XHCI_EPCTX_1_HID_SET(0) |
2273 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2274 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2276 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2277 if (type != UE_ISOCHRONOUS)
2278 temp |= XHCI_EPCTX_1_CERR_SET(3);
2283 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2285 case UE_ISOCHRONOUS:
2286 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2289 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2292 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2296 /* check for IN direction */
2298 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2300 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2301 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2303 switch (edesc->bmAttributes & UE_XFERTYPE) {
2305 case UE_ISOCHRONOUS:
2306 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2307 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2311 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2314 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2318 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2321 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2323 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2325 return (0); /* success */
2329 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2331 struct xhci_endpoint_ext *pepext;
2332 struct usb_endpoint_ss_comp_descriptor *ecomp;
2335 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2336 xfer->endpoint->edesc);
2338 ecomp = xfer->endpoint->ecomp;
2340 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2343 /* halt any transfers */
2344 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2346 /* compute start of TRB ring for stream "x" */
2347 temp = pepext->physaddr +
2348 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2349 XHCI_SCTX_0_SCT_SEC_TR_RING;
2351 /* make tree structure */
2352 pepext->trb[(XHCI_MAX_TRANSFERS *
2353 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2355 /* reserved fields */
2356 pepext->trb[(XHCI_MAX_TRANSFERS *
2357 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2358 pepext->trb[(XHCI_MAX_TRANSFERS *
2359 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2361 usb_pc_cpu_flush(pepext->page_cache);
2363 return (xhci_configure_endpoint(xfer->xroot->udev,
2364 xfer->endpoint->edesc, pepext,
2365 xfer->interval, xfer->max_packet_count,
2366 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2367 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2368 xfer->max_frame_size, xfer->endpoint->ep_mode));
2372 xhci_configure_device(struct usb_device *udev)
2374 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2375 struct usb_page_search buf_inp;
2376 struct usb_page_cache *pcinp;
2377 struct xhci_input_dev_ctx *pinp;
2378 struct usb_device *hubdev;
2386 index = udev->controller_slot_id;
2388 DPRINTF("index=%u\n", index);
2390 pcinp = &sc->sc_hw.devs[index].input_pc;
2392 usbd_get_page(pcinp, 0, &buf_inp);
2394 pinp = buf_inp.buffer;
2399 /* figure out route string and root HUB port number */
2401 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2403 if (hubdev->parent_hub == NULL)
2406 depth = hubdev->parent_hub->depth;
2409 * NOTE: HS/FS/LS devices and the SS root HUB can have
2410 * more than 15 ports
2413 rh_port = hubdev->port_no;
2422 route |= rh_port << (4 * (depth - 1));
2425 DPRINTF("Route=0x%08x\n", route);
2427 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2428 XHCI_SCTX_0_CTX_NUM_SET(
2429 sc->sc_hw.devs[index].context_num + 1);
2431 switch (udev->speed) {
2433 temp |= XHCI_SCTX_0_SPEED_SET(2);
2434 if (udev->parent_hs_hub != NULL &&
2435 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2437 DPRINTF("Device inherits MTT\n");
2438 temp |= XHCI_SCTX_0_MTT_SET(1);
2441 case USB_SPEED_HIGH:
2442 temp |= XHCI_SCTX_0_SPEED_SET(3);
2443 if (sc->sc_hw.devs[index].nports != 0 &&
2444 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2445 DPRINTF("HUB supports MTT\n");
2446 temp |= XHCI_SCTX_0_MTT_SET(1);
2449 case USB_SPEED_FULL:
2450 temp |= XHCI_SCTX_0_SPEED_SET(1);
2451 if (udev->parent_hs_hub != NULL &&
2452 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2454 DPRINTF("Device inherits MTT\n");
2455 temp |= XHCI_SCTX_0_MTT_SET(1);
2459 temp |= XHCI_SCTX_0_SPEED_SET(4);
2463 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2464 (udev->speed == USB_SPEED_SUPER ||
2465 udev->speed == USB_SPEED_HIGH);
2468 temp |= XHCI_SCTX_0_HUB_SET(1);
2470 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2472 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2475 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2476 sc->sc_hw.devs[index].nports);
2479 switch (udev->speed) {
2480 case USB_SPEED_SUPER:
2481 switch (sc->sc_hw.devs[index].state) {
2482 case XHCI_ST_ADDRESSED:
2483 case XHCI_ST_CONFIGURED:
2484 /* enable power save */
2485 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2488 /* disable power save */
2496 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2498 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2501 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2502 sc->sc_hw.devs[index].tt);
2505 hubdev = udev->parent_hs_hub;
2507 /* check if we should activate the transaction translator */
2508 switch (udev->speed) {
2509 case USB_SPEED_FULL:
2511 if (hubdev != NULL) {
2512 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2513 hubdev->controller_slot_id);
2514 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2522 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2524 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2525 XHCI_SCTX_3_SLOT_STATE_SET(0);
2527 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2530 xhci_dump_device(sc, &pinp->ctx_slot);
2532 usb_pc_cpu_flush(pcinp);
2534 return (0); /* success */
2538 xhci_alloc_device_ext(struct usb_device *udev)
2540 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2541 struct usb_page_search buf_dev;
2542 struct usb_page_search buf_ep;
2543 struct xhci_trb *trb;
2544 struct usb_page_cache *pc;
2545 struct usb_page *pg;
2550 index = udev->controller_slot_id;
2552 pc = &sc->sc_hw.devs[index].device_pc;
2553 pg = &sc->sc_hw.devs[index].device_pg;
2555 /* need to initialize the page cache */
2556 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2558 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2559 (2 * sizeof(struct xhci_dev_ctx)) :
2560 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2563 usbd_get_page(pc, 0, &buf_dev);
2565 pc = &sc->sc_hw.devs[index].input_pc;
2566 pg = &sc->sc_hw.devs[index].input_pg;
2568 /* need to initialize the page cache */
2569 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2571 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2572 (2 * sizeof(struct xhci_input_dev_ctx)) :
2573 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2577 pc = &sc->sc_hw.devs[index].endpoint_pc;
2578 pg = &sc->sc_hw.devs[index].endpoint_pg;
2580 /* need to initialize the page cache */
2581 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2583 if (usb_pc_alloc_mem(pc, pg,
2584 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2588 /* initialise all endpoint LINK TRBs */
2590 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2592 /* lookup endpoint TRB ring */
2593 usbd_get_page(pc, (uintptr_t)&
2594 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2596 /* get TRB pointer */
2597 trb = buf_ep.buffer;
2598 trb += XHCI_MAX_TRANSFERS - 1;
2600 /* get TRB start address */
2601 addr = buf_ep.physaddr;
2603 /* create LINK TRB */
2604 trb->qwTrb0 = htole64(addr);
2605 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2606 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2607 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2610 usb_pc_cpu_flush(pc);
2612 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2617 xhci_free_device_ext(udev);
2619 return (USB_ERR_NOMEM);
2623 xhci_free_device_ext(struct usb_device *udev)
2625 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2628 index = udev->controller_slot_id;
2629 xhci_set_slot_pointer(sc, index, 0);
2631 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2632 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2633 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2636 static struct xhci_endpoint_ext *
2637 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2639 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2640 struct xhci_endpoint_ext *pepext;
2641 struct usb_page_cache *pc;
2642 struct usb_page_search buf_ep;
2646 epno = edesc->bEndpointAddress;
2647 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2650 epno = XHCI_EPNO2EPID(epno);
2652 index = udev->controller_slot_id;
2654 pc = &sc->sc_hw.devs[index].endpoint_pc;
2656 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->
2657 trb[epno][0], &buf_ep);
2659 pepext = &sc->sc_hw.devs[index].endp[epno];
2660 pepext->page_cache = pc;
2661 pepext->trb = buf_ep.buffer;
2662 pepext->physaddr = buf_ep.physaddr;
2668 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2670 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2674 epno = xfer->endpointno;
2675 if (xfer->flags_int.control_xfr)
2678 epno = XHCI_EPNO2EPID(epno);
2679 index = xfer->xroot->udev->controller_slot_id;
2681 if (xfer->xroot->udev->flags.self_suspended == 0) {
2682 XWRITE4(sc, door, XHCI_DOORBELL(index),
2683 epno | XHCI_DB_SID_SET(xfer->stream_id));
2688 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2690 struct xhci_endpoint_ext *pepext;
2692 if (xfer->flags_int.bandwidth_reclaimed) {
2693 xfer->flags_int.bandwidth_reclaimed = 0;
2695 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2696 xfer->endpoint->edesc);
2698 pepext->trb_used[xfer->stream_id]--;
2700 pepext->xfer[xfer->qh_pos] = NULL;
2702 if (error && pepext->trb_running != 0) {
2703 pepext->trb_halted = 1;
2704 pepext->trb_running = 0;
2710 xhci_transfer_insert(struct usb_xfer *xfer)
2712 struct xhci_td *td_first;
2713 struct xhci_td *td_last;
2714 struct xhci_trb *trb_link;
2715 struct xhci_endpoint_ext *pepext;
2724 id = xfer->stream_id;
2726 /* check if already inserted */
2727 if (xfer->flags_int.bandwidth_reclaimed) {
2728 DPRINTFN(8, "Already in schedule\n");
2732 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2733 xfer->endpoint->edesc);
2735 td_first = xfer->td_transfer_first;
2736 td_last = xfer->td_transfer_last;
2737 addr = pepext->physaddr;
2739 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2742 /* single buffered */
2746 /* multi buffered */
2747 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2751 if (pepext->trb_used[id] >= trb_limit) {
2752 DPRINTFN(8, "Too many TDs queued.\n");
2753 return (USB_ERR_NOMEM);
2756 /* check for stopped condition, after putting transfer on interrupt queue */
2757 if (pepext->trb_running == 0) {
2758 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2760 DPRINTFN(8, "Not running\n");
2762 /* start configuration */
2763 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2764 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2768 pepext->trb_used[id]++;
2770 /* get current TRB index */
2771 i = pepext->trb_index[id];
2773 /* get next TRB index */
2776 /* the last entry of the ring is a hardcoded link TRB */
2777 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2780 /* store next TRB index, before stream ID offset is added */
2781 pepext->trb_index[id] = inext;
2783 /* offset for stream */
2784 i += id * XHCI_MAX_TRANSFERS;
2785 inext += id * XHCI_MAX_TRANSFERS;
2787 /* compute terminating return address */
2788 addr += (inext * sizeof(struct xhci_trb));
2790 /* compute link TRB pointer */
2791 trb_link = td_last->td_trb + td_last->ntrb;
2793 /* update next pointer of last link TRB */
2794 trb_link->qwTrb0 = htole64(addr);
2795 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2796 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2797 XHCI_TRB_3_CYCLE_BIT |
2798 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2801 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2803 usb_pc_cpu_flush(td_last->page_cache);
2805 /* write ahead chain end marker */
2807 pepext->trb[inext].qwTrb0 = 0;
2808 pepext->trb[inext].dwTrb2 = 0;
2809 pepext->trb[inext].dwTrb3 = 0;
2811 /* update next pointer of link TRB */
2813 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2814 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2817 xhci_dump_trb(&pepext->trb[i]);
2819 usb_pc_cpu_flush(pepext->page_cache);
2821 /* toggle cycle bit which activates the transfer chain */
2823 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2824 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2826 usb_pc_cpu_flush(pepext->page_cache);
2828 DPRINTF("qh_pos = %u\n", i);
2830 pepext->xfer[i] = xfer;
2834 xfer->flags_int.bandwidth_reclaimed = 1;
2836 xhci_endpoint_doorbell(xfer);
2842 xhci_root_intr(struct xhci_softc *sc)
2846 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2848 /* clear any old interrupt data */
2849 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2851 for (i = 1; i <= sc->sc_noport; i++) {
2852 /* pick out CHANGE bits from the status register */
2853 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2854 XHCI_PS_CSC | XHCI_PS_PEC |
2855 XHCI_PS_OCC | XHCI_PS_WRC |
2856 XHCI_PS_PRC | XHCI_PS_PLC |
2858 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2859 DPRINTF("port %d changed\n", i);
2862 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2863 sizeof(sc->sc_hub_idata));
2866 /*------------------------------------------------------------------------*
2867 * xhci_device_done - XHCI done handler
2869 * NOTE: This function can be called two times in a row on
2870 * the same USB transfer. From close and from interrupt.
2871 *------------------------------------------------------------------------*/
2873 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2875 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2876 xfer, xfer->endpoint, error);
2878 /* remove transfer from HW queue */
2879 xhci_transfer_remove(xfer, error);
2881 /* dequeue transfer and start next transfer */
2882 usbd_transfer_done(xfer, error);
2885 /*------------------------------------------------------------------------*
2886 * XHCI data transfer support (generic type)
2887 *------------------------------------------------------------------------*/
2889 xhci_device_generic_open(struct usb_xfer *xfer)
2891 if (xfer->flags_int.isochronous_xfr) {
2892 switch (xfer->xroot->udev->speed) {
2893 case USB_SPEED_FULL:
2896 usb_hs_bandwidth_alloc(xfer);
2903 xhci_device_generic_close(struct usb_xfer *xfer)
2907 xhci_device_done(xfer, USB_ERR_CANCELLED);
2909 if (xfer->flags_int.isochronous_xfr) {
2910 switch (xfer->xroot->udev->speed) {
2911 case USB_SPEED_FULL:
2914 usb_hs_bandwidth_free(xfer);
2921 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2922 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
2924 struct usb_xfer *xfer;
2926 /* check if there is a current transfer */
2927 xfer = ep->endpoint_q[stream_id].curr;
2932 * Check if the current transfer is started and then pickup
2933 * the next one, if any. Else wait for next start event due to
2934 * block on failure feature.
2936 if (!xfer->flags_int.bandwidth_reclaimed)
2939 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
2942 * In case of enter we have to consider that the
2943 * transfer is queued by the USB core after the enter
2952 /* try to multi buffer */
2953 xhci_transfer_insert(xfer);
2957 xhci_device_generic_enter(struct usb_xfer *xfer)
2961 /* setup TD's and QH */
2962 xhci_setup_generic_chain(xfer);
2964 xhci_device_generic_multi_enter(xfer->endpoint,
2965 xfer->stream_id, xfer);
2969 xhci_device_generic_start(struct usb_xfer *xfer)
2973 /* try to insert xfer on HW queue */
2974 xhci_transfer_insert(xfer);
2976 /* try to multi buffer */
2977 xhci_device_generic_multi_enter(xfer->endpoint,
2978 xfer->stream_id, NULL);
2980 /* add transfer last on interrupt queue */
2981 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2983 /* start timeout, if any */
2984 if (xfer->timeout != 0)
2985 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
2988 struct usb_pipe_methods xhci_device_generic_methods =
2990 .open = xhci_device_generic_open,
2991 .close = xhci_device_generic_close,
2992 .enter = xhci_device_generic_enter,
2993 .start = xhci_device_generic_start,
2996 /*------------------------------------------------------------------------*
2997 * xhci root HUB support
2998 *------------------------------------------------------------------------*
2999 * Simulate a hardware HUB by handling all the necessary requests.
3000 *------------------------------------------------------------------------*/
3002 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3005 struct usb_device_descriptor xhci_devd =
3007 .bLength = sizeof(xhci_devd),
3008 .bDescriptorType = UDESC_DEVICE, /* type */
3009 HSETW(.bcdUSB, 0x0300), /* USB version */
3010 .bDeviceClass = UDCLASS_HUB, /* class */
3011 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3012 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3013 .bMaxPacketSize = 9, /* max packet size */
3014 HSETW(.idVendor, 0x0000), /* vendor */
3015 HSETW(.idProduct, 0x0000), /* product */
3016 HSETW(.bcdDevice, 0x0100), /* device version */
3020 .bNumConfigurations = 1, /* # of configurations */
3024 struct xhci_bos_desc xhci_bosd = {
3026 .bLength = sizeof(xhci_bosd.bosd),
3027 .bDescriptorType = UDESC_BOS,
3028 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3029 .bNumDeviceCaps = 3,
3032 .bLength = sizeof(xhci_bosd.usb2extd),
3033 .bDescriptorType = 1,
3034 .bDevCapabilityType = 2,
3035 .bmAttributes[0] = 2,
3038 .bLength = sizeof(xhci_bosd.usbdcd),
3039 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3040 .bDevCapabilityType = 3,
3041 .bmAttributes = 0, /* XXX */
3042 HSETW(.wSpeedsSupported, 0x000C),
3043 .bFunctionalitySupport = 8,
3044 .bU1DevExitLat = 255, /* dummy - not used */
3045 .wU2DevExitLat = { 0x00, 0x08 },
3048 .bLength = sizeof(xhci_bosd.cidd),
3049 .bDescriptorType = 1,
3050 .bDevCapabilityType = 4,
3052 .bContainerID = 0, /* XXX */
3057 struct xhci_config_desc xhci_confd = {
3059 .bLength = sizeof(xhci_confd.confd),
3060 .bDescriptorType = UDESC_CONFIG,
3061 .wTotalLength[0] = sizeof(xhci_confd),
3063 .bConfigurationValue = 1,
3064 .iConfiguration = 0,
3065 .bmAttributes = UC_SELF_POWERED,
3066 .bMaxPower = 0 /* max power */
3069 .bLength = sizeof(xhci_confd.ifcd),
3070 .bDescriptorType = UDESC_INTERFACE,
3072 .bInterfaceClass = UICLASS_HUB,
3073 .bInterfaceSubClass = UISUBCLASS_HUB,
3074 .bInterfaceProtocol = 0,
3077 .bLength = sizeof(xhci_confd.endpd),
3078 .bDescriptorType = UDESC_ENDPOINT,
3079 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3080 .bmAttributes = UE_INTERRUPT,
3081 .wMaxPacketSize[0] = 2, /* max 15 ports */
3085 .bLength = sizeof(xhci_confd.endpcd),
3086 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3093 struct usb_hub_ss_descriptor xhci_hubd = {
3094 .bLength = sizeof(xhci_hubd),
3095 .bDescriptorType = UDESC_SS_HUB,
3099 xhci_roothub_exec(struct usb_device *udev,
3100 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3102 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3103 const char *str_ptr;
3114 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3117 ptr = (const void *)&sc->sc_hub_desc;
3121 value = UGETW(req->wValue);
3122 index = UGETW(req->wIndex);
3124 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3125 "wValue=0x%04x wIndex=0x%04x\n",
3126 req->bmRequestType, req->bRequest,
3127 UGETW(req->wLength), value, index);
3129 #define C(x,y) ((x) | ((y) << 8))
3130 switch (C(req->bRequest, req->bmRequestType)) {
3131 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3132 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3133 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3135 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3136 * for the integrated root hub.
3139 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3141 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3143 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3144 switch (value >> 8) {
3146 if ((value & 0xff) != 0) {
3147 err = USB_ERR_IOERROR;
3150 len = sizeof(xhci_devd);
3151 ptr = (const void *)&xhci_devd;
3155 if ((value & 0xff) != 0) {
3156 err = USB_ERR_IOERROR;
3159 len = sizeof(xhci_bosd);
3160 ptr = (const void *)&xhci_bosd;
3164 if ((value & 0xff) != 0) {
3165 err = USB_ERR_IOERROR;
3168 len = sizeof(xhci_confd);
3169 ptr = (const void *)&xhci_confd;
3173 switch (value & 0xff) {
3174 case 0: /* Language table */
3178 case 1: /* Vendor */
3179 str_ptr = sc->sc_vendor;
3182 case 2: /* Product */
3183 str_ptr = "XHCI root HUB";
3191 len = usb_make_str_desc(
3192 sc->sc_hub_desc.temp,
3193 sizeof(sc->sc_hub_desc.temp),
3198 err = USB_ERR_IOERROR;
3202 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3204 sc->sc_hub_desc.temp[0] = 0;
3206 case C(UR_GET_STATUS, UT_READ_DEVICE):
3208 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3210 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3211 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3213 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3215 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3216 if (value >= XHCI_MAX_DEVICES) {
3217 err = USB_ERR_IOERROR;
3221 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3222 if (value != 0 && value != 1) {
3223 err = USB_ERR_IOERROR;
3226 sc->sc_conf = value;
3228 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3230 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3231 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3232 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3233 err = USB_ERR_IOERROR;
3235 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3237 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3243 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3246 (index > sc->sc_noport)) {
3247 err = USB_ERR_IOERROR;
3250 port = XHCI_PORTSC(index);
3252 v = XREAD4(sc, oper, port);
3253 i = XHCI_PS_PLS_GET(v);
3254 v &= ~XHCI_PS_CLEAR;
3257 case UHF_C_BH_PORT_RESET:
3258 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3260 case UHF_C_PORT_CONFIG_ERROR:
3261 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3263 case UHF_C_PORT_SUSPEND:
3264 case UHF_C_PORT_LINK_STATE:
3265 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3267 case UHF_C_PORT_CONNECTION:
3268 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3270 case UHF_C_PORT_ENABLE:
3271 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3273 case UHF_C_PORT_OVER_CURRENT:
3274 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3276 case UHF_C_PORT_RESET:
3277 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3279 case UHF_PORT_ENABLE:
3280 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3282 case UHF_PORT_POWER:
3283 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3285 case UHF_PORT_INDICATOR:
3286 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3288 case UHF_PORT_SUSPEND:
3292 XWRITE4(sc, oper, port, v |
3293 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3296 /* wait 20ms for resume sequence to complete */
3297 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3300 XWRITE4(sc, oper, port, v |
3301 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3304 err = USB_ERR_IOERROR;
3309 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3310 if ((value & 0xff) != 0) {
3311 err = USB_ERR_IOERROR;
3315 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3317 sc->sc_hub_desc.hubd = xhci_hubd;
3319 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3321 if (XHCI_HCS0_PPC(v))
3322 i = UHD_PWR_INDIVIDUAL;
3326 if (XHCI_HCS0_PIND(v))
3329 i |= UHD_OC_INDIVIDUAL;
3331 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3333 /* see XHCI section 5.4.9: */
3334 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3336 for (j = 1; j <= sc->sc_noport; j++) {
3338 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3339 if (v & XHCI_PS_DR) {
3340 sc->sc_hub_desc.hubd.
3341 DeviceRemovable[j / 8] |= 1U << (j % 8);
3344 len = sc->sc_hub_desc.hubd.bLength;
3347 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3349 memset(sc->sc_hub_desc.temp, 0, 16);
3352 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3353 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3356 (index > sc->sc_noport)) {
3357 err = USB_ERR_IOERROR;
3361 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3363 DPRINTFN(9, "port status=0x%08x\n", v);
3365 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3367 switch (XHCI_PS_SPEED_GET(v)) {
3369 i |= UPS_HIGH_SPEED;
3378 i |= UPS_OTHER_SPEED;
3382 if (v & XHCI_PS_CCS)
3383 i |= UPS_CURRENT_CONNECT_STATUS;
3384 if (v & XHCI_PS_PED)
3385 i |= UPS_PORT_ENABLED;
3386 if (v & XHCI_PS_OCA)
3387 i |= UPS_OVERCURRENT_INDICATOR;
3390 if (v & XHCI_PS_PP) {
3392 * The USB 3.0 RH is using the
3393 * USB 2.0's power bit
3395 i |= UPS_PORT_POWER;
3397 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3400 if (v & XHCI_PS_CSC)
3401 i |= UPS_C_CONNECT_STATUS;
3402 if (v & XHCI_PS_PEC)
3403 i |= UPS_C_PORT_ENABLED;
3404 if (v & XHCI_PS_OCC)
3405 i |= UPS_C_OVERCURRENT_INDICATOR;
3406 if (v & XHCI_PS_WRC)
3407 i |= UPS_C_BH_PORT_RESET;
3408 if (v & XHCI_PS_PRC)
3409 i |= UPS_C_PORT_RESET;
3410 if (v & XHCI_PS_PLC)
3411 i |= UPS_C_PORT_LINK_STATE;
3412 if (v & XHCI_PS_CEC)
3413 i |= UPS_C_PORT_CONFIG_ERROR;
3415 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3416 len = sizeof(sc->sc_hub_desc.ps);
3419 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3420 err = USB_ERR_IOERROR;
3423 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3426 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3432 (index > sc->sc_noport)) {
3433 err = USB_ERR_IOERROR;
3437 port = XHCI_PORTSC(index);
3438 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3441 case UHF_PORT_U1_TIMEOUT:
3442 if (XHCI_PS_SPEED_GET(v) != 4) {
3443 err = USB_ERR_IOERROR;
3446 port = XHCI_PORTPMSC(index);
3447 v = XREAD4(sc, oper, port);
3448 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3449 v |= XHCI_PM3_U1TO_SET(i);
3450 XWRITE4(sc, oper, port, v);
3452 case UHF_PORT_U2_TIMEOUT:
3453 if (XHCI_PS_SPEED_GET(v) != 4) {
3454 err = USB_ERR_IOERROR;
3457 port = XHCI_PORTPMSC(index);
3458 v = XREAD4(sc, oper, port);
3459 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3460 v |= XHCI_PM3_U2TO_SET(i);
3461 XWRITE4(sc, oper, port, v);
3463 case UHF_BH_PORT_RESET:
3464 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3466 case UHF_PORT_LINK_STATE:
3467 XWRITE4(sc, oper, port, v |
3468 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3469 /* 4ms settle time */
3470 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3472 case UHF_PORT_ENABLE:
3473 DPRINTFN(3, "set port enable %d\n", index);
3475 case UHF_PORT_SUSPEND:
3476 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3477 j = XHCI_PS_SPEED_GET(v);
3478 if ((j < 1) || (j > 3)) {
3479 /* non-supported speed */
3480 err = USB_ERR_IOERROR;
3483 XWRITE4(sc, oper, port, v |
3484 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3486 case UHF_PORT_RESET:
3487 DPRINTFN(6, "reset port %d\n", index);
3488 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3490 case UHF_PORT_POWER:
3491 DPRINTFN(3, "set port power %d\n", index);
3492 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3495 DPRINTFN(3, "set port test %d\n", index);
3497 case UHF_PORT_INDICATOR:
3498 DPRINTFN(3, "set port indicator %d\n", index);
3500 v &= ~XHCI_PS_PIC_SET(3);
3501 v |= XHCI_PS_PIC_SET(1);
3503 XWRITE4(sc, oper, port, v);
3506 err = USB_ERR_IOERROR;
3511 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3512 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3513 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3514 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3517 err = USB_ERR_IOERROR;
3527 xhci_xfer_setup(struct usb_setup_params *parm)
3529 struct usb_page_search page_info;
3530 struct usb_page_cache *pc;
3531 struct xhci_softc *sc;
3532 struct usb_xfer *xfer;
3537 sc = XHCI_BUS2SC(parm->udev->bus);
3538 xfer = parm->curr_xfer;
3541 * The proof for the "ntd" formula is illustrated like this:
3543 * +------------------------------------+
3547 * | | xxx | x | frm 0 |
3549 * | | xxx | xx | frm 1 |
3552 * +------------------------------------+
3554 * "xxx" means a completely full USB transfer descriptor
3556 * "x" and "xx" means a short USB packet
3558 * For the remainder of an USB transfer modulo
3559 * "max_data_length" we need two USB transfer descriptors.
3560 * One to transfer the remaining data and one to finalise with
3561 * a zero length packet in case the "force_short_xfer" flag is
3562 * set. We only need two USB transfer descriptors in the case
3563 * where the transfer length of the first one is a factor of
3564 * "max_frame_size". The rest of the needed USB transfer
3565 * descriptors is given by the buffer size divided by the
3566 * maximum data payload.
3568 parm->hc_max_packet_size = 0x400;
3569 parm->hc_max_packet_count = 16 * 3;
3570 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3572 xfer->flags_int.bdma_enable = 1;
3574 usbd_transfer_setup_sub(parm);
3576 if (xfer->flags_int.isochronous_xfr) {
3577 ntd = ((1 * xfer->nframes)
3578 + (xfer->max_data_length / xfer->max_hc_frame_size));
3579 } else if (xfer->flags_int.control_xfr) {
3580 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3581 + (xfer->max_data_length / xfer->max_hc_frame_size));
3583 ntd = ((2 * xfer->nframes)
3584 + (xfer->max_data_length / xfer->max_hc_frame_size));
3593 * Allocate queue heads and transfer descriptors
3597 if (usbd_transfer_setup_sub_malloc(
3598 parm, &pc, sizeof(struct xhci_td),
3599 XHCI_TD_ALIGN, ntd)) {
3600 parm->err = USB_ERR_NOMEM;
3604 for (n = 0; n != ntd; n++) {
3607 usbd_get_page(pc + n, 0, &page_info);
3609 td = page_info.buffer;
3612 td->td_self = page_info.physaddr;
3613 td->obj_next = last_obj;
3614 td->page_cache = pc + n;
3618 usb_pc_cpu_flush(pc + n);
3621 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3623 if (!xfer->flags_int.curr_dma_set) {
3624 xfer->flags_int.curr_dma_set = 1;
3630 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3632 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3633 struct usb_page_search buf_inp;
3634 struct usb_device *udev;
3635 struct xhci_endpoint_ext *pepext;
3636 struct usb_endpoint_descriptor *edesc;
3637 struct usb_page_cache *pcinp;
3639 usb_stream_t stream_id;
3643 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3644 xfer->endpoint->edesc);
3646 udev = xfer->xroot->udev;
3647 index = udev->controller_slot_id;
3649 pcinp = &sc->sc_hw.devs[index].input_pc;
3651 usbd_get_page(pcinp, 0, &buf_inp);
3653 edesc = xfer->endpoint->edesc;
3655 epno = edesc->bEndpointAddress;
3656 stream_id = xfer->stream_id;
3658 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3661 epno = XHCI_EPNO2EPID(epno);
3664 return (USB_ERR_NO_PIPE); /* invalid */
3668 /* configure endpoint */
3670 err = xhci_configure_endpoint_by_xfer(xfer);
3673 XHCI_CMD_UNLOCK(sc);
3678 * Get the endpoint into the stopped state according to the
3679 * endpoint context state diagram in the XHCI specification:
3682 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3685 DPRINTF("Could not stop endpoint %u\n", epno);
3687 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3690 DPRINTF("Could not reset endpoint %u\n", epno);
3692 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3693 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3694 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3695 stream_id, epno, index);
3698 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3701 * Get the endpoint into the running state according to the
3702 * endpoint context state diagram in the XHCI specification:
3705 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3707 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3710 DPRINTF("Could not configure endpoint %u\n", epno);
3712 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3715 DPRINTF("Could not configure endpoint %u\n", epno);
3717 XHCI_CMD_UNLOCK(sc);
3723 xhci_xfer_unsetup(struct usb_xfer *xfer)
3729 xhci_start_dma_delay(struct usb_xfer *xfer)
3731 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3733 /* put transfer on interrupt queue (again) */
3734 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3736 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3737 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3741 xhci_configure_msg(struct usb_proc_msg *pm)
3743 struct xhci_softc *sc;
3744 struct xhci_endpoint_ext *pepext;
3745 struct usb_xfer *xfer;
3747 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3750 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3752 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3753 xfer->endpoint->edesc);
3755 if ((pepext->trb_halted != 0) ||
3756 (pepext->trb_running == 0)) {
3760 /* clear halted and running */
3761 pepext->trb_halted = 0;
3762 pepext->trb_running = 0;
3764 /* nuke remaining buffered transfers */
3766 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3767 XHCI_MAX_STREAMS); i++) {
3769 * NOTE: We need to use the timeout
3770 * error code here else existing
3771 * isochronous clients can get
3774 if (pepext->xfer[i] != NULL) {
3775 xhci_device_done(pepext->xfer[i],
3781 * NOTE: The USB transfer cannot vanish in
3785 USB_BUS_UNLOCK(&sc->sc_bus);
3787 xhci_configure_reset_endpoint(xfer);
3789 USB_BUS_LOCK(&sc->sc_bus);
3791 /* check if halted is still cleared */
3792 if (pepext->trb_halted == 0) {
3793 pepext->trb_running = 1;
3794 memset(pepext->trb_index, 0,
3795 sizeof(pepext->trb_index));
3800 if (xfer->flags_int.did_dma_delay) {
3802 /* remove transfer from interrupt queue (again) */
3803 usbd_transfer_dequeue(xfer);
3805 /* we are finally done */
3806 usb_dma_delay_done_cb(xfer);
3808 /* queue changed - restart */
3813 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3815 /* try to insert xfer on HW queue */
3816 xhci_transfer_insert(xfer);
3818 /* try to multi buffer */
3819 xhci_device_generic_multi_enter(xfer->endpoint,
3820 xfer->stream_id, NULL);
3825 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3826 struct usb_endpoint *ep)
3828 struct xhci_endpoint_ext *pepext;
3830 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3831 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3833 if (udev->parent_hub == NULL) {
3834 /* root HUB has special endpoint handling */
3838 ep->methods = &xhci_device_generic_methods;
3840 pepext = xhci_get_endpoint_ext(udev, edesc);
3842 USB_BUS_LOCK(udev->bus);
3843 pepext->trb_halted = 1;
3844 pepext->trb_running = 0;
3845 USB_BUS_UNLOCK(udev->bus);
3849 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3855 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3857 struct xhci_endpoint_ext *pepext;
3861 if (udev->flags.usb_mode != USB_MODE_HOST) {
3865 if (udev->parent_hub == NULL) {
3866 /* root HUB has special endpoint handling */
3870 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3872 USB_BUS_LOCK(udev->bus);
3873 pepext->trb_halted = 1;
3874 pepext->trb_running = 0;
3875 USB_BUS_UNLOCK(udev->bus);
3879 xhci_device_init(struct usb_device *udev)
3881 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3885 /* no init for root HUB */
3886 if (udev->parent_hub == NULL)
3891 /* set invalid default */
3893 udev->controller_slot_id = sc->sc_noslot + 1;
3895 /* try to get a new slot ID from the XHCI */
3897 err = xhci_cmd_enable_slot(sc, &temp);
3900 XHCI_CMD_UNLOCK(sc);
3904 if (temp > sc->sc_noslot) {
3905 XHCI_CMD_UNLOCK(sc);
3906 return (USB_ERR_BAD_ADDRESS);
3909 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3910 DPRINTF("slot %u already allocated.\n", temp);
3911 XHCI_CMD_UNLOCK(sc);
3912 return (USB_ERR_BAD_ADDRESS);
3915 /* store slot ID for later reference */
3917 udev->controller_slot_id = temp;
3919 /* reset data structure */
3921 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3923 /* set mark slot allocated */
3925 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3927 err = xhci_alloc_device_ext(udev);
3929 XHCI_CMD_UNLOCK(sc);
3931 /* get device into default state */
3934 err = xhci_set_address(udev, NULL, 0);
3940 xhci_device_uninit(struct usb_device *udev)
3942 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3945 /* no init for root HUB */
3946 if (udev->parent_hub == NULL)
3951 index = udev->controller_slot_id;
3953 if (index <= sc->sc_noslot) {
3954 xhci_cmd_disable_slot(sc, index);
3955 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3957 /* free device extension */
3958 xhci_free_device_ext(udev);
3961 XHCI_CMD_UNLOCK(sc);
3965 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3968 * Wait until the hardware has finished any possible use of
3969 * the transfer descriptor(s)
3971 *pus = 2048; /* microseconds */
3975 xhci_device_resume(struct usb_device *udev)
3977 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3984 /* check for root HUB */
3985 if (udev->parent_hub == NULL)
3988 index = udev->controller_slot_id;
3992 /* blindly resume all endpoints */
3994 USB_BUS_LOCK(udev->bus);
3996 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
3997 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
3998 XWRITE4(sc, door, XHCI_DOORBELL(index),
3999 n | XHCI_DB_SID_SET(p));
4003 USB_BUS_UNLOCK(udev->bus);
4005 XHCI_CMD_UNLOCK(sc);
4009 xhci_device_suspend(struct usb_device *udev)
4011 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4018 /* check for root HUB */
4019 if (udev->parent_hub == NULL)
4022 index = udev->controller_slot_id;
4026 /* blindly suspend all endpoints */
4028 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4029 err = xhci_cmd_stop_ep(sc, 1, n, index);
4031 DPRINTF("Failed to suspend endpoint "
4032 "%u on slot %u (ignored).\n", n, index);
4036 XHCI_CMD_UNLOCK(sc);
4040 xhci_set_hw_power(struct usb_bus *bus)
4046 xhci_device_state_change(struct usb_device *udev)
4048 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4049 struct usb_page_search buf_inp;
4053 /* check for root HUB */
4054 if (udev->parent_hub == NULL)
4057 index = udev->controller_slot_id;
4061 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4062 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4063 &sc->sc_hw.devs[index].tt);
4065 sc->sc_hw.devs[index].nports = 0;
4070 switch (usb_get_device_state(udev)) {
4071 case USB_STATE_POWERED:
4072 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4075 /* set default state */
4076 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4078 /* reset number of contexts */
4079 sc->sc_hw.devs[index].context_num = 0;
4081 err = xhci_cmd_reset_dev(sc, index);
4084 DPRINTF("Device reset failed "
4085 "for slot %u.\n", index);
4089 case USB_STATE_ADDRESSED:
4090 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4093 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4095 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4098 DPRINTF("Failed to deconfigure "
4099 "slot %u.\n", index);
4103 case USB_STATE_CONFIGURED:
4104 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4107 /* set configured state */
4108 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4110 /* reset number of contexts */
4111 sc->sc_hw.devs[index].context_num = 0;
4113 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4115 xhci_configure_mask(udev, 3, 0);
4117 err = xhci_configure_device(udev);
4119 DPRINTF("Could not configure device "
4120 "at slot %u.\n", index);
4123 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4125 DPRINTF("Could not evaluate device "
4126 "context at slot %u.\n", index);
4133 XHCI_CMD_UNLOCK(sc);
4137 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4141 case USB_EP_MODE_DEFAULT:
4143 case USB_EP_MODE_STREAMS:
4144 if (xhcistreams == 0 ||
4145 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4146 udev->speed != USB_SPEED_SUPER)
4147 return (USB_ERR_INVAL);
4150 return (USB_ERR_INVAL);
4154 struct usb_bus_methods xhci_bus_methods = {
4155 .endpoint_init = xhci_ep_init,
4156 .endpoint_uninit = xhci_ep_uninit,
4157 .xfer_setup = xhci_xfer_setup,
4158 .xfer_unsetup = xhci_xfer_unsetup,
4159 .get_dma_delay = xhci_get_dma_delay,
4160 .device_init = xhci_device_init,
4161 .device_uninit = xhci_device_uninit,
4162 .device_resume = xhci_device_resume,
4163 .device_suspend = xhci_device_suspend,
4164 .set_hw_power = xhci_set_hw_power,
4165 .roothub_exec = xhci_roothub_exec,
4166 .xfer_poll = xhci_do_poll,
4167 .start_dma_delay = xhci_start_dma_delay,
4168 .set_address = xhci_set_address,
4169 .clear_stall = xhci_ep_clear_stall,
4170 .device_state_change = xhci_device_state_change,
4171 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4172 .set_endpoint_mode = xhci_set_endpoint_mode,