2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
92 &xhcidebug, 0, "Debug level");
93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
101 #define XHCI_INTR_ENDPT 1
103 struct xhci_std_temp {
104 struct xhci_softc *sc;
105 struct usb_page_cache *pc;
107 struct xhci_td *td_next;
110 uint32_t max_packet_size;
122 uint8_t do_isoc_sync;
125 static void xhci_do_poll(struct usb_bus *);
126 static void xhci_device_done(struct usb_xfer *, usb_error_t);
127 static void xhci_root_intr(struct xhci_softc *);
128 static void xhci_free_device_ext(struct usb_device *);
129 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
130 struct usb_endpoint_descriptor *);
131 static usb_proc_callback_t xhci_configure_msg;
132 static usb_error_t xhci_configure_device(struct usb_device *);
133 static usb_error_t xhci_configure_endpoint(struct usb_device *,
134 struct usb_endpoint_descriptor *, uint64_t, uint16_t,
135 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
136 static usb_error_t xhci_configure_mask(struct usb_device *,
138 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
140 static void xhci_endpoint_doorbell(struct usb_xfer *);
141 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
142 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
143 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
145 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
148 extern struct usb_bus_methods xhci_bus_methods;
152 xhci_dump_trb(struct xhci_trb *trb)
154 DPRINTFN(5, "trb = %p\n", trb);
155 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
156 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
157 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
161 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
163 DPRINTFN(5, "pep = %p\n", pep);
164 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
165 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
166 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
167 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
168 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
169 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
170 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
174 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
176 DPRINTFN(5, "psl = %p\n", psl);
177 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
178 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
179 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
180 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
185 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
187 struct xhci_softc *sc = XHCI_BUS2SC(bus);
190 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
191 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
193 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
194 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
196 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
197 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
198 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
203 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
205 if (sc->sc_ctx_is_64_byte) {
207 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
208 /* all contexts are initially 32-bytes */
209 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
210 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
216 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
218 if (sc->sc_ctx_is_64_byte) {
220 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
221 /* all contexts are initially 32-bytes */
222 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
223 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
225 return (le32toh(*ptr));
229 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
231 if (sc->sc_ctx_is_64_byte) {
233 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
234 /* all contexts are initially 32-bytes */
235 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
236 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
243 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
245 if (sc->sc_ctx_is_64_byte) {
247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
248 /* all contexts are initially 32-bytes */
249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
250 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
252 return (le64toh(*ptr));
257 xhci_reset_command_queue_locked(struct xhci_softc *sc)
259 struct usb_page_search buf_res;
260 struct xhci_hw_root *phwr;
266 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
267 if (temp & XHCI_CRCR_LO_CRR) {
268 DPRINTF("Command ring running\n");
269 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
272 * Try to abort the last command as per section
273 * 4.6.1.2 "Aborting a Command" of the XHCI
277 /* stop and cancel */
278 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
279 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
281 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
282 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
285 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
287 /* check if command ring is still running */
288 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
289 if (temp & XHCI_CRCR_LO_CRR) {
290 DPRINTF("Comand ring still running\n");
291 return (USB_ERR_IOERROR);
295 /* reset command ring */
296 sc->sc_command_ccs = 1;
297 sc->sc_command_idx = 0;
299 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
301 /* setup command ring control base address */
302 addr = buf_res.physaddr;
303 phwr = buf_res.buffer;
304 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
306 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
308 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
309 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
311 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
313 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
320 xhci_start_controller(struct xhci_softc *sc)
322 struct usb_page_search buf_res;
323 struct xhci_hw_root *phwr;
324 struct xhci_dev_ctx_addr *pdctxa;
332 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
333 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
334 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
336 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
337 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
338 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
340 sc->sc_event_ccs = 1;
341 sc->sc_event_idx = 0;
342 sc->sc_command_ccs = 1;
343 sc->sc_command_idx = 0;
345 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
347 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
349 DPRINTF("HCS0 = 0x%08x\n", temp);
351 if (XHCI_HCS0_CSZ(temp)) {
352 sc->sc_ctx_is_64_byte = 1;
353 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
355 sc->sc_ctx_is_64_byte = 0;
356 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
359 /* Reset controller */
360 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
362 for (i = 0; i != 100; i++) {
363 usb_pause_mtx(NULL, hz / 100);
364 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
365 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
371 device_printf(sc->sc_bus.parent, "Controller "
373 return (USB_ERR_IOERROR);
376 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
377 device_printf(sc->sc_bus.parent, "Controller does "
378 "not support 4K page size.\n");
379 return (USB_ERR_IOERROR);
382 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
384 i = XHCI_HCS1_N_PORTS(temp);
387 device_printf(sc->sc_bus.parent, "Invalid number "
388 "of ports: %u\n", i);
389 return (USB_ERR_IOERROR);
393 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
395 if (sc->sc_noslot > XHCI_MAX_DEVICES)
396 sc->sc_noslot = XHCI_MAX_DEVICES;
398 /* setup number of device slots */
400 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
401 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
403 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
405 DPRINTF("Max slots: %u\n", sc->sc_noslot);
407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
409 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
411 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
412 device_printf(sc->sc_bus.parent, "XHCI request "
413 "too many scratchpads\n");
414 return (USB_ERR_NOMEM);
417 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
419 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
421 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
422 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
424 temp = XREAD4(sc, oper, XHCI_USBSTS);
426 /* clear interrupts */
427 XWRITE4(sc, oper, XHCI_USBSTS, temp);
428 /* disable all device notifications */
429 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
431 /* setup device context base address */
432 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
433 pdctxa = buf_res.buffer;
434 memset(pdctxa, 0, sizeof(*pdctxa));
436 addr = buf_res.physaddr;
437 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
439 /* slot 0 points to the table of scratchpad pointers */
440 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
442 for (i = 0; i != sc->sc_noscratch; i++) {
443 struct usb_page_search buf_scp;
444 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
445 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
448 addr = buf_res.physaddr;
450 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
451 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
455 /* Setup event table size */
457 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
459 DPRINTF("HCS2=0x%08x\n", temp);
461 temp = XHCI_HCS2_ERST_MAX(temp);
463 if (temp > XHCI_MAX_RSEG)
464 temp = XHCI_MAX_RSEG;
466 sc->sc_erst_max = temp;
468 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
469 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
471 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
473 /* Check if we should use the default IMOD value */
474 if (sc->sc_imod_default == 0)
475 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
477 /* Setup interrupt rate */
478 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
480 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
482 phwr = buf_res.buffer;
483 addr = buf_res.physaddr;
484 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
486 /* reset hardware root structure */
487 memset(phwr, 0, sizeof(*phwr));
489 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
490 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
492 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
494 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
495 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
497 addr = (uint64_t)buf_res.physaddr;
499 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
501 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
502 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
504 /* Setup interrupter registers */
506 temp = XREAD4(sc, runt, XHCI_IMAN(0));
507 temp |= XHCI_IMAN_INTR_ENA;
508 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
510 /* setup command ring control base address */
511 addr = buf_res.physaddr;
512 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
514 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
516 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
517 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
519 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
521 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
524 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
525 XHCI_CMD_INTE | XHCI_CMD_HSEE);
527 for (i = 0; i != 100; i++) {
528 usb_pause_mtx(NULL, hz / 100);
529 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
534 XWRITE4(sc, oper, XHCI_USBCMD, 0);
535 device_printf(sc->sc_bus.parent, "Run timeout.\n");
536 return (USB_ERR_IOERROR);
539 /* catch any lost interrupts */
540 xhci_do_poll(&sc->sc_bus);
542 if (sc->sc_port_route != NULL) {
543 /* Route all ports to the XHCI by default */
544 sc->sc_port_route(sc->sc_bus.parent,
545 ~xhciroute, xhciroute);
551 xhci_halt_controller(struct xhci_softc *sc)
559 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
560 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
561 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
563 /* Halt controller */
564 XWRITE4(sc, oper, XHCI_USBCMD, 0);
566 for (i = 0; i != 100; i++) {
567 usb_pause_mtx(NULL, hz / 100);
568 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
574 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
575 return (USB_ERR_IOERROR);
581 xhci_init(struct xhci_softc *sc, device_t self)
583 /* initialise some bus fields */
584 sc->sc_bus.parent = self;
586 /* set the bus revision */
587 sc->sc_bus.usbrev = USB_REV_3_0;
589 /* set up the bus struct */
590 sc->sc_bus.methods = &xhci_bus_methods;
592 /* setup devices array */
593 sc->sc_bus.devices = sc->sc_devices;
594 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
596 /* set default cycle state in case of early interrupts */
597 sc->sc_event_ccs = 1;
598 sc->sc_command_ccs = 1;
600 /* setup command queue mutex and condition varible */
601 cv_init(&sc->sc_cmd_cv, "CMDQ");
602 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
604 /* get all DMA memory */
605 if (usb_bus_mem_alloc_all(&sc->sc_bus,
606 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
610 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
611 sc->sc_config_msg[0].bus = &sc->sc_bus;
612 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
613 sc->sc_config_msg[1].bus = &sc->sc_bus;
615 if (usb_proc_create(&sc->sc_config_proc,
616 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
617 printf("WARNING: Creation of XHCI configure "
618 "callback process failed.\n");
624 xhci_uninit(struct xhci_softc *sc)
626 usb_proc_free(&sc->sc_config_proc);
628 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
630 cv_destroy(&sc->sc_cmd_cv);
631 sx_destroy(&sc->sc_cmd_sx);
635 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
637 struct xhci_softc *sc = XHCI_BUS2SC(bus);
640 case USB_HW_POWER_SUSPEND:
641 DPRINTF("Stopping the XHCI\n");
642 xhci_halt_controller(sc);
644 case USB_HW_POWER_SHUTDOWN:
645 DPRINTF("Stopping the XHCI\n");
646 xhci_halt_controller(sc);
648 case USB_HW_POWER_RESUME:
649 DPRINTF("Starting the XHCI\n");
650 xhci_start_controller(sc);
658 xhci_generic_done_sub(struct usb_xfer *xfer)
661 struct xhci_td *td_alt_next;
665 td = xfer->td_transfer_cache;
666 td_alt_next = td->alt_next;
668 if (xfer->aframes != xfer->nframes)
669 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
673 usb_pc_cpu_invalidate(td->page_cache);
678 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
679 xfer, (unsigned int)xfer->aframes,
680 (unsigned int)xfer->nframes,
681 (unsigned int)len, (unsigned int)td->len,
682 (unsigned int)status);
685 * Verify the status length and
686 * add the length to "frlengths[]":
689 /* should not happen */
690 DPRINTF("Invalid status length, "
691 "0x%04x/0x%04x bytes\n", len, td->len);
692 status = XHCI_TRB_ERROR_LENGTH;
693 } else if (xfer->aframes != xfer->nframes) {
694 xfer->frlengths[xfer->aframes] += td->len - len;
696 /* Check for last transfer */
697 if (((void *)td) == xfer->td_transfer_last) {
701 /* Check for transfer error */
702 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
703 status != XHCI_TRB_ERROR_SUCCESS) {
704 /* the transfer is finished */
708 /* Check for short transfer */
710 if (xfer->flags_int.short_frames_ok ||
711 xfer->flags_int.isochronous_xfr ||
712 xfer->flags_int.control_xfr) {
713 /* follow alt next */
716 /* the transfer is finished */
723 if (td->alt_next != td_alt_next) {
724 /* this USB frame is complete */
729 /* update transfer cache */
731 xfer->td_transfer_cache = td;
733 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
734 (status != XHCI_TRB_ERROR_SHORT_PKT &&
735 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
736 USB_ERR_NORMAL_COMPLETION);
740 xhci_generic_done(struct usb_xfer *xfer)
744 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
745 xfer, xfer->endpoint);
749 xfer->td_transfer_cache = xfer->td_transfer_first;
751 if (xfer->flags_int.control_xfr) {
753 if (xfer->flags_int.control_hdr)
754 err = xhci_generic_done_sub(xfer);
758 if (xfer->td_transfer_cache == NULL)
762 while (xfer->aframes != xfer->nframes) {
764 err = xhci_generic_done_sub(xfer);
767 if (xfer->td_transfer_cache == NULL)
771 if (xfer->flags_int.control_xfr &&
772 !xfer->flags_int.control_act)
773 err = xhci_generic_done_sub(xfer);
775 /* transfer is complete */
776 xhci_device_done(xfer, err);
780 xhci_activate_transfer(struct usb_xfer *xfer)
784 td = xfer->td_transfer_cache;
786 usb_pc_cpu_invalidate(td->page_cache);
788 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
790 /* activate the transfer */
792 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
793 usb_pc_cpu_flush(td->page_cache);
795 xhci_endpoint_doorbell(xfer);
800 xhci_skip_transfer(struct usb_xfer *xfer)
803 struct xhci_td *td_last;
805 td = xfer->td_transfer_cache;
806 td_last = xfer->td_transfer_last;
810 usb_pc_cpu_invalidate(td->page_cache);
812 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
814 usb_pc_cpu_invalidate(td_last->page_cache);
816 /* copy LINK TRB to current waiting location */
818 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
819 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
820 usb_pc_cpu_flush(td->page_cache);
822 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
823 usb_pc_cpu_flush(td->page_cache);
825 xhci_endpoint_doorbell(xfer);
829 /*------------------------------------------------------------------------*
830 * xhci_check_transfer
831 *------------------------------------------------------------------------*/
833 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
846 td_event = le64toh(trb->qwTrb0);
847 temp = le32toh(trb->dwTrb2);
849 remainder = XHCI_TRB_2_REM_GET(temp);
850 status = XHCI_TRB_2_ERROR_GET(temp);
852 temp = le32toh(trb->dwTrb3);
853 epno = XHCI_TRB_3_EP_GET(temp);
854 index = XHCI_TRB_3_SLOT_GET(temp);
856 /* check if error means halted */
857 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
858 status != XHCI_TRB_ERROR_SUCCESS);
860 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
861 index, epno, remainder, status);
863 if (index > sc->sc_noslot) {
864 DPRINTF("Invalid slot.\n");
868 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
869 DPRINTF("Invalid endpoint.\n");
873 /* try to find the USB transfer that generated the event */
874 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
875 struct usb_xfer *xfer;
877 struct xhci_endpoint_ext *pepext;
879 pepext = &sc->sc_hw.devs[index].endp[epno];
881 xfer = pepext->xfer[i];
885 td = xfer->td_transfer_cache;
887 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
889 (long long)td->td_self,
890 (long long)td->td_self + sizeof(td->td_trb));
893 * NOTE: Some XHCI implementations might not trigger
894 * an event on the last LINK TRB so we need to
895 * consider both the last and second last event
896 * address as conditions for a successful transfer.
898 * NOTE: We assume that the XHCI will only trigger one
899 * event per chain of TRBs.
902 offset = td_event - td->td_self;
905 offset < (int64_t)sizeof(td->td_trb)) {
907 usb_pc_cpu_invalidate(td->page_cache);
909 /* compute rest of remainder, if any */
910 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
911 temp = le32toh(td->td_trb[i].dwTrb2);
912 remainder += XHCI_TRB_2_BYTES_GET(temp);
915 DPRINTFN(5, "New remainder: %u\n", remainder);
917 /* clear isochronous transfer errors */
918 if (xfer->flags_int.isochronous_xfr) {
921 status = XHCI_TRB_ERROR_SUCCESS;
926 /* "td->remainder" is verified later */
927 td->remainder = remainder;
930 usb_pc_cpu_flush(td->page_cache);
933 * 1) Last transfer descriptor makes the
936 if (((void *)td) == xfer->td_transfer_last) {
937 DPRINTF("TD is last\n");
938 xhci_generic_done(xfer);
943 * 2) Any kind of error makes the transfer
947 DPRINTF("TD has I/O error\n");
948 xhci_generic_done(xfer);
953 * 3) If there is no alternate next transfer,
954 * a short packet also makes the transfer done
956 if (td->remainder > 0) {
957 if (td->alt_next == NULL) {
959 "short TD has no alternate next\n");
960 xhci_generic_done(xfer);
963 DPRINTF("TD has short pkt\n");
964 if (xfer->flags_int.short_frames_ok ||
965 xfer->flags_int.isochronous_xfr ||
966 xfer->flags_int.control_xfr) {
967 /* follow the alt next */
968 xfer->td_transfer_cache = td->alt_next;
969 xhci_activate_transfer(xfer);
972 xhci_skip_transfer(xfer);
973 xhci_generic_done(xfer);
978 * 4) Transfer complete - go to next TD
980 DPRINTF("Following next TD\n");
981 xfer->td_transfer_cache = td->obj_next;
982 xhci_activate_transfer(xfer);
983 break; /* there should only be one match */
989 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
991 if (sc->sc_cmd_addr == trb->qwTrb0) {
992 DPRINTF("Received command event\n");
993 sc->sc_cmd_result[0] = trb->dwTrb2;
994 sc->sc_cmd_result[1] = trb->dwTrb3;
995 cv_signal(&sc->sc_cmd_cv);
996 return (1); /* command match */
1002 xhci_interrupt_poll(struct xhci_softc *sc)
1004 struct usb_page_search buf_res;
1005 struct xhci_hw_root *phwr;
1015 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1017 phwr = buf_res.buffer;
1019 /* Receive any events */
1021 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1023 i = sc->sc_event_idx;
1024 j = sc->sc_event_ccs;
1029 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1031 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1036 event = XHCI_TRB_3_TYPE_GET(temp);
1038 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1039 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1040 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1041 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1044 case XHCI_TRB_EVENT_TRANSFER:
1045 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1047 case XHCI_TRB_EVENT_CMD_COMPLETE:
1048 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1051 DPRINTF("Unhandled event = %u\n", event);
1057 if (i == XHCI_MAX_EVENTS) {
1061 /* check for timeout */
1067 sc->sc_event_idx = i;
1068 sc->sc_event_ccs = j;
1071 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1072 * latched. That means to activate the register we need to
1073 * write both the low and high double word of the 64-bit
1077 addr = (uint32_t)buf_res.physaddr;
1078 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1080 /* try to clear busy bit */
1081 addr |= XHCI_ERDP_LO_BUSY;
1083 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1084 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1090 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1091 uint16_t timeout_ms)
1093 struct usb_page_search buf_res;
1094 struct xhci_hw_root *phwr;
1099 uint8_t timeout = 0;
1102 XHCI_CMD_ASSERT_LOCKED(sc);
1104 /* get hardware root structure */
1106 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1108 phwr = buf_res.buffer;
1112 USB_BUS_LOCK(&sc->sc_bus);
1114 i = sc->sc_command_idx;
1115 j = sc->sc_command_ccs;
1117 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1118 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1119 (long long)le64toh(trb->qwTrb0),
1120 (long)le32toh(trb->dwTrb2),
1121 (long)le32toh(trb->dwTrb3));
1123 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1124 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1126 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1131 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1133 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1135 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1137 phwr->hwr_commands[i].dwTrb3 = temp;
1139 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1141 addr = buf_res.physaddr;
1142 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1144 sc->sc_cmd_addr = htole64(addr);
1148 if (i == (XHCI_MAX_COMMANDS - 1)) {
1151 temp = htole32(XHCI_TRB_3_TC_BIT |
1152 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1153 XHCI_TRB_3_CYCLE_BIT);
1155 temp = htole32(XHCI_TRB_3_TC_BIT |
1156 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1159 phwr->hwr_commands[i].dwTrb3 = temp;
1161 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1167 sc->sc_command_idx = i;
1168 sc->sc_command_ccs = j;
1170 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1172 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1173 USB_MS_TO_TICKS(timeout_ms));
1176 * In some error cases event interrupts are not generated.
1177 * Poll one time to see if the command has completed.
1179 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1180 DPRINTF("Command was completed when polling\n");
1184 DPRINTF("Command timeout!\n");
1186 * After some weeks of continuous operation, it has
1187 * been observed that the ASMedia Technology, ASM1042
1188 * SuperSpeed USB Host Controller can suddenly stop
1189 * accepting commands via the command queue. Try to
1190 * first reset the command queue. If that fails do a
1191 * host controller reset.
1194 xhci_reset_command_queue_locked(sc) == 0) {
1195 temp = le32toh(trb->dwTrb3);
1198 * Avoid infinite XHCI reset loops if the set
1199 * address command fails to respond due to a
1200 * non-enumerating device:
1202 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1203 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1204 DPRINTF("Set address timeout\n");
1210 DPRINTF("Controller reset!\n");
1211 usb_bus_reset_async_locked(&sc->sc_bus);
1213 err = USB_ERR_TIMEOUT;
1217 temp = le32toh(sc->sc_cmd_result[0]);
1218 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1219 err = USB_ERR_IOERROR;
1221 trb->dwTrb2 = sc->sc_cmd_result[0];
1222 trb->dwTrb3 = sc->sc_cmd_result[1];
1225 USB_BUS_UNLOCK(&sc->sc_bus);
1232 xhci_cmd_nop(struct xhci_softc *sc)
1234 struct xhci_trb trb;
1241 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1243 trb.dwTrb3 = htole32(temp);
1245 return (xhci_do_command(sc, &trb, 100 /* ms */));
1250 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1252 struct xhci_trb trb;
1260 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1262 err = xhci_do_command(sc, &trb, 100 /* ms */);
1266 temp = le32toh(trb.dwTrb3);
1268 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1275 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1277 struct xhci_trb trb;
1284 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1285 XHCI_TRB_3_SLOT_SET(slot_id);
1287 trb.dwTrb3 = htole32(temp);
1289 return (xhci_do_command(sc, &trb, 100 /* ms */));
1293 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1294 uint8_t bsr, uint8_t slot_id)
1296 struct xhci_trb trb;
1301 trb.qwTrb0 = htole64(input_ctx);
1303 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1304 XHCI_TRB_3_SLOT_SET(slot_id);
1307 temp |= XHCI_TRB_3_BSR_BIT;
1309 trb.dwTrb3 = htole32(temp);
1311 return (xhci_do_command(sc, &trb, 500 /* ms */));
1315 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1317 struct usb_page_search buf_inp;
1318 struct usb_page_search buf_dev;
1319 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1320 struct xhci_hw_dev *hdev;
1321 struct xhci_dev_ctx *pdev;
1322 struct xhci_endpoint_ext *pepext;
1328 /* the root HUB case is not handled here */
1329 if (udev->parent_hub == NULL)
1330 return (USB_ERR_INVAL);
1332 index = udev->controller_slot_id;
1334 hdev = &sc->sc_hw.devs[index];
1341 switch (hdev->state) {
1342 case XHCI_ST_DEFAULT:
1343 case XHCI_ST_ENABLED:
1345 hdev->state = XHCI_ST_ENABLED;
1347 /* set configure mask to slot and EP0 */
1348 xhci_configure_mask(udev, 3, 0);
1350 /* configure input slot context structure */
1351 err = xhci_configure_device(udev);
1354 DPRINTF("Could not configure device\n");
1358 /* configure input endpoint context structure */
1359 switch (udev->speed) {
1361 case USB_SPEED_FULL:
1364 case USB_SPEED_HIGH:
1372 pepext = xhci_get_endpoint_ext(udev,
1373 &udev->ctrl_ep_desc);
1374 err = xhci_configure_endpoint(udev,
1375 &udev->ctrl_ep_desc, pepext->physaddr,
1376 0, 1, 1, 0, mps, mps);
1379 DPRINTF("Could not configure default endpoint\n");
1383 /* execute set address command */
1384 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1386 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1387 (address == 0), index);
1390 temp = le32toh(sc->sc_cmd_result[0]);
1391 if (address == 0 && sc->sc_port_route != NULL &&
1392 XHCI_TRB_2_ERROR_GET(temp) ==
1393 XHCI_TRB_ERROR_PARAMETER) {
1394 /* LynxPoint XHCI - ports are not switchable */
1395 /* Un-route all ports from the XHCI */
1396 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1398 DPRINTF("Could not set address "
1399 "for slot %u.\n", index);
1404 /* update device address to new value */
1406 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1407 pdev = buf_dev.buffer;
1408 usb_pc_cpu_invalidate(&hdev->device_pc);
1410 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1411 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1413 /* update device state to new value */
1416 hdev->state = XHCI_ST_ADDRESSED;
1418 hdev->state = XHCI_ST_DEFAULT;
1422 DPRINTF("Wrong state for set address.\n");
1423 err = USB_ERR_IOERROR;
1426 XHCI_CMD_UNLOCK(sc);
1435 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1436 uint8_t deconfigure, uint8_t slot_id)
1438 struct xhci_trb trb;
1443 trb.qwTrb0 = htole64(input_ctx);
1445 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1446 XHCI_TRB_3_SLOT_SET(slot_id);
1449 temp |= XHCI_TRB_3_DCEP_BIT;
1451 trb.dwTrb3 = htole32(temp);
1453 return (xhci_do_command(sc, &trb, 100 /* ms */));
1457 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1460 struct xhci_trb trb;
1465 trb.qwTrb0 = htole64(input_ctx);
1467 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1468 XHCI_TRB_3_SLOT_SET(slot_id);
1469 trb.dwTrb3 = htole32(temp);
1471 return (xhci_do_command(sc, &trb, 100 /* ms */));
1475 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1476 uint8_t ep_id, uint8_t slot_id)
1478 struct xhci_trb trb;
1485 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1486 XHCI_TRB_3_SLOT_SET(slot_id) |
1487 XHCI_TRB_3_EP_SET(ep_id);
1490 temp |= XHCI_TRB_3_PRSV_BIT;
1492 trb.dwTrb3 = htole32(temp);
1494 return (xhci_do_command(sc, &trb, 100 /* ms */));
1498 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1499 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1501 struct xhci_trb trb;
1506 trb.qwTrb0 = htole64(dequeue_ptr);
1508 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1509 trb.dwTrb2 = htole32(temp);
1511 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1512 XHCI_TRB_3_SLOT_SET(slot_id) |
1513 XHCI_TRB_3_EP_SET(ep_id);
1514 trb.dwTrb3 = htole32(temp);
1516 return (xhci_do_command(sc, &trb, 100 /* ms */));
1520 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1521 uint8_t ep_id, uint8_t slot_id)
1523 struct xhci_trb trb;
1530 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1531 XHCI_TRB_3_SLOT_SET(slot_id) |
1532 XHCI_TRB_3_EP_SET(ep_id);
1535 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1537 trb.dwTrb3 = htole32(temp);
1539 return (xhci_do_command(sc, &trb, 100 /* ms */));
1543 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1545 struct xhci_trb trb;
1552 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1553 XHCI_TRB_3_SLOT_SET(slot_id);
1555 trb.dwTrb3 = htole32(temp);
1557 return (xhci_do_command(sc, &trb, 100 /* ms */));
1560 /*------------------------------------------------------------------------*
1561 * xhci_interrupt - XHCI interrupt handler
1562 *------------------------------------------------------------------------*/
1564 xhci_interrupt(struct xhci_softc *sc)
1569 USB_BUS_LOCK(&sc->sc_bus);
1571 status = XREAD4(sc, oper, XHCI_USBSTS);
1573 /* acknowledge interrupts, if any */
1575 XWRITE4(sc, oper, XHCI_USBSTS, status);
1576 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1579 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1581 /* force clearing of pending interrupts */
1582 if (temp & XHCI_IMAN_INTR_PEND)
1583 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1585 /* check for event(s) */
1586 xhci_interrupt_poll(sc);
1588 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1589 XHCI_STS_HSE | XHCI_STS_HCE)) {
1591 if (status & XHCI_STS_PCD) {
1595 if (status & XHCI_STS_HCH) {
1596 printf("%s: host controller halted\n",
1600 if (status & XHCI_STS_HSE) {
1601 printf("%s: host system error\n",
1605 if (status & XHCI_STS_HCE) {
1606 printf("%s: host controller error\n",
1610 USB_BUS_UNLOCK(&sc->sc_bus);
1613 /*------------------------------------------------------------------------*
1614 * xhci_timeout - XHCI timeout handler
1615 *------------------------------------------------------------------------*/
1617 xhci_timeout(void *arg)
1619 struct usb_xfer *xfer = arg;
1621 DPRINTF("xfer=%p\n", xfer);
1623 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1625 /* transfer is transferred */
1626 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1630 xhci_do_poll(struct usb_bus *bus)
1632 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1634 USB_BUS_LOCK(&sc->sc_bus);
1635 xhci_interrupt_poll(sc);
1636 USB_BUS_UNLOCK(&sc->sc_bus);
1640 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1642 struct usb_page_search buf_res;
1644 struct xhci_td *td_next;
1645 struct xhci_td *td_alt_next;
1646 struct xhci_td *td_first;
1647 uint32_t buf_offset;
1652 uint8_t shortpkt_old;
1658 shortpkt_old = temp->shortpkt;
1659 len_old = temp->len;
1666 td_next = td_first = temp->td_next;
1670 if (temp->len == 0) {
1675 /* send a Zero Length Packet, ZLP, last */
1682 average = temp->average;
1684 if (temp->len < average) {
1685 if (temp->len % temp->max_packet_size) {
1688 average = temp->len;
1692 if (td_next == NULL)
1693 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1698 td_next = td->obj_next;
1700 /* check if we are pre-computing */
1704 /* update remaining length */
1706 temp->len -= average;
1710 /* fill out current TD */
1716 /* update remaining length */
1718 temp->len -= average;
1720 /* reset TRB index */
1724 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1725 /* immediate data */
1730 td->td_trb[0].qwTrb0 = 0;
1732 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1733 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1736 dword = XHCI_TRB_2_BYTES_SET(8) |
1737 XHCI_TRB_2_TDSZ_SET(0) |
1738 XHCI_TRB_2_IRQ_SET(0);
1740 td->td_trb[0].dwTrb2 = htole32(dword);
1742 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1743 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1746 if (td->td_trb[0].qwTrb0 &
1747 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1748 if (td->td_trb[0].qwTrb0 &
1749 htole64(XHCI_TRB_0_DIR_IN_MASK))
1750 dword |= XHCI_TRB_3_TRT_IN;
1752 dword |= XHCI_TRB_3_TRT_OUT;
1755 td->td_trb[0].dwTrb3 = htole32(dword);
1757 xhci_dump_trb(&td->td_trb[x]);
1765 /* fill out buffer pointers */
1768 memset(&buf_res, 0, sizeof(buf_res));
1770 usbd_get_page(temp->pc, temp->offset +
1771 buf_offset, &buf_res);
1773 /* get length to end of page */
1774 if (buf_res.length > average)
1775 buf_res.length = average;
1777 /* check for maximum length */
1778 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1779 buf_res.length = XHCI_TD_PAGE_SIZE;
1781 npkt_off += buf_res.length;
1785 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1786 temp->max_packet_size;
1793 /* fill out TRB's */
1794 td->td_trb[x].qwTrb0 =
1795 htole64((uint64_t)buf_res.physaddr);
1798 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1799 XHCI_TRB_2_TDSZ_SET(npkt) |
1800 XHCI_TRB_2_IRQ_SET(0);
1802 td->td_trb[x].dwTrb2 = htole32(dword);
1804 switch (temp->trb_type) {
1805 case XHCI_TRB_TYPE_ISOCH:
1806 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1807 XHCI_TRB_3_TBC_SET(temp->tbc) |
1808 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1809 if (td != td_first) {
1810 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1811 } else if (temp->do_isoc_sync != 0) {
1812 temp->do_isoc_sync = 0;
1813 /* wait until "isoc_frame" */
1814 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1815 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1817 /* start data transfer at next interval */
1818 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1819 XHCI_TRB_3_ISO_SIA_BIT;
1821 if (temp->direction == UE_DIR_IN)
1822 dword |= XHCI_TRB_3_ISP_BIT;
1824 case XHCI_TRB_TYPE_DATA_STAGE:
1825 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1826 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1827 if (temp->direction == UE_DIR_IN)
1828 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1830 case XHCI_TRB_TYPE_STATUS_STAGE:
1831 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1832 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1833 if (temp->direction == UE_DIR_IN)
1834 dword |= XHCI_TRB_3_DIR_IN;
1836 default: /* XHCI_TRB_TYPE_NORMAL */
1837 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1838 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1839 if (temp->direction == UE_DIR_IN)
1840 dword |= XHCI_TRB_3_ISP_BIT;
1843 td->td_trb[x].dwTrb3 = htole32(dword);
1845 average -= buf_res.length;
1846 buf_offset += buf_res.length;
1848 xhci_dump_trb(&td->td_trb[x]);
1852 } while (average != 0);
1854 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1856 /* store number of data TRB's */
1860 DPRINTF("NTRB=%u\n", x);
1862 /* fill out link TRB */
1864 if (td_next != NULL) {
1865 /* link the current TD with the next one */
1866 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1867 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1869 /* this field will get updated later */
1870 DPRINTF("NOLINK\n");
1873 dword = XHCI_TRB_2_IRQ_SET(0);
1875 td->td_trb[x].dwTrb2 = htole32(dword);
1877 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1878 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1880 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1881 * frame only receives a single short packet event
1882 * by setting the CHAIN bit in the LINK field. In
1883 * addition some XHCI controllers have problems
1884 * sending a ZLP unless the CHAIN-BIT is set in
1887 XHCI_TRB_3_CHAIN_BIT;
1889 td->td_trb[x].dwTrb3 = htole32(dword);
1891 td->alt_next = td_alt_next;
1893 xhci_dump_trb(&td->td_trb[x]);
1895 usb_pc_cpu_flush(td->page_cache);
1901 /* setup alt next pointer, if any */
1902 if (temp->last_frame) {
1905 /* we use this field internally */
1906 td_alt_next = td_next;
1910 temp->shortpkt = shortpkt_old;
1911 temp->len = len_old;
1916 * Remove cycle bit from the first TRB if we are
1919 if (temp->step_td != 0) {
1920 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1921 usb_pc_cpu_flush(td_first->page_cache);
1924 /* clear TD SIZE to zero, hence this is the last TRB */
1925 /* remove chain bit because this is the last data TRB in the chain */
1926 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1927 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1928 /* remove CHAIN-BIT from last LINK TRB */
1929 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1931 usb_pc_cpu_flush(td->page_cache);
1934 temp->td_next = td_next;
1938 xhci_setup_generic_chain(struct usb_xfer *xfer)
1940 struct xhci_std_temp temp;
1946 temp.do_isoc_sync = 0;
1950 temp.average = xfer->max_hc_frame_size;
1951 temp.max_packet_size = xfer->max_packet_size;
1952 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1954 temp.last_frame = 0;
1956 temp.multishort = xfer->flags_int.isochronous_xfr ||
1957 xfer->flags_int.control_xfr ||
1958 xfer->flags_int.short_frames_ok;
1960 /* toggle the DMA set we are using */
1961 xfer->flags_int.curr_dma_set ^= 1;
1963 /* get next DMA set */
1964 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1969 xfer->td_transfer_first = td;
1970 xfer->td_transfer_cache = td;
1972 if (xfer->flags_int.isochronous_xfr) {
1975 /* compute multiplier for ISOCHRONOUS transfers */
1976 mult = xfer->endpoint->ecomp ?
1977 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
1978 /* check for USB 2.0 multiplier */
1980 mult = (xfer->endpoint->edesc->
1981 wMaxPacketSize[1] >> 3) & 3;
1989 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1991 DPRINTF("MFINDEX=0x%08x\n", x);
1993 switch (usbd_get_speed(xfer->xroot->udev)) {
1994 case USB_SPEED_FULL:
1996 temp.isoc_delta = 8; /* 1ms */
1997 x += temp.isoc_delta - 1;
1998 x &= ~(temp.isoc_delta - 1);
2001 shift = usbd_xfer_get_fps_shift(xfer);
2002 temp.isoc_delta = 1U << shift;
2003 x += temp.isoc_delta - 1;
2004 x &= ~(temp.isoc_delta - 1);
2005 /* simple frame load balancing */
2006 x += xfer->endpoint->usb_uframe;
2010 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2012 if ((xfer->endpoint->is_synced == 0) ||
2013 (y < (xfer->nframes << shift)) ||
2014 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2016 * If there is data underflow or the pipe
2017 * queue is empty we schedule the transfer a
2018 * few frames ahead of the current frame
2019 * position. Else two isochronous transfers
2022 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2023 xfer->endpoint->is_synced = 1;
2024 temp.do_isoc_sync = 1;
2026 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2029 /* compute isochronous completion time */
2031 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2033 xfer->isoc_time_complete =
2034 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2035 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2038 temp.isoc_frame = xfer->endpoint->isoc_next;
2039 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2041 xfer->endpoint->isoc_next += xfer->nframes << shift;
2043 } else if (xfer->flags_int.control_xfr) {
2045 /* check if we should prepend a setup message */
2047 if (xfer->flags_int.control_hdr) {
2049 temp.len = xfer->frlengths[0];
2050 temp.pc = xfer->frbuffers + 0;
2051 temp.shortpkt = temp.len ? 1 : 0;
2052 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2055 /* check for last frame */
2056 if (xfer->nframes == 1) {
2057 /* no STATUS stage yet, SETUP is last */
2058 if (xfer->flags_int.control_act)
2059 temp.last_frame = 1;
2062 xhci_setup_generic_chain_sub(&temp);
2066 temp.isoc_delta = 0;
2067 temp.isoc_frame = 0;
2068 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2072 temp.isoc_delta = 0;
2073 temp.isoc_frame = 0;
2074 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2077 if (x != xfer->nframes) {
2078 /* setup page_cache pointer */
2079 temp.pc = xfer->frbuffers + x;
2080 /* set endpoint direction */
2081 temp.direction = UE_GET_DIR(xfer->endpointno);
2084 while (x != xfer->nframes) {
2086 /* DATA0 / DATA1 message */
2088 temp.len = xfer->frlengths[x];
2089 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2090 x != 0 && temp.multishort == 0);
2094 if (x == xfer->nframes) {
2095 if (xfer->flags_int.control_xfr) {
2096 /* no STATUS stage yet, DATA is last */
2097 if (xfer->flags_int.control_act)
2098 temp.last_frame = 1;
2100 temp.last_frame = 1;
2103 if (temp.len == 0) {
2105 /* make sure that we send an USB packet */
2110 temp.tlbpc = mult - 1;
2112 } else if (xfer->flags_int.isochronous_xfr) {
2117 * Isochronous transfers don't have short
2118 * packet termination:
2123 /* isochronous transfers have a transfer limit */
2125 if (temp.len > xfer->max_frame_size)
2126 temp.len = xfer->max_frame_size;
2128 /* compute TD packet count */
2129 tdpc = (temp.len + xfer->max_packet_size - 1) /
2130 xfer->max_packet_size;
2132 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2133 temp.tlbpc = (tdpc % mult);
2135 if (temp.tlbpc == 0)
2136 temp.tlbpc = mult - 1;
2141 /* regular data transfer */
2143 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2146 xhci_setup_generic_chain_sub(&temp);
2148 if (xfer->flags_int.isochronous_xfr) {
2149 temp.offset += xfer->frlengths[x - 1];
2150 temp.isoc_frame += temp.isoc_delta;
2152 /* get next Page Cache pointer */
2153 temp.pc = xfer->frbuffers + x;
2157 /* check if we should append a status stage */
2159 if (xfer->flags_int.control_xfr &&
2160 !xfer->flags_int.control_act) {
2163 * Send a DATA1 message and invert the current
2164 * endpoint direction.
2166 temp.step_td = (xfer->nframes != 0);
2167 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2171 temp.last_frame = 1;
2172 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2174 xhci_setup_generic_chain_sub(&temp);
2179 /* must have at least one frame! */
2181 xfer->td_transfer_last = td;
2183 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2187 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2189 struct usb_page_search buf_res;
2190 struct xhci_dev_ctx_addr *pdctxa;
2192 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2194 pdctxa = buf_res.buffer;
2196 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2198 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2200 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2204 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2206 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2207 struct usb_page_search buf_inp;
2208 struct xhci_input_dev_ctx *pinp;
2213 index = udev->controller_slot_id;
2215 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2217 pinp = buf_inp.buffer;
2220 mask &= XHCI_INCTX_NON_CTRL_MASK;
2221 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2222 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2225 * Some hardware requires that we drop the endpoint
2226 * context before adding it again:
2228 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2229 mask & XHCI_INCTX_NON_CTRL_MASK);
2231 /* Add new endpoint context */
2232 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2234 /* find most significant set bit */
2235 for (x = 31; x != 1; x--) {
2236 if (mask & (1 << x))
2243 /* figure out the maximum number of contexts */
2244 if (x > sc->sc_hw.devs[index].context_num)
2245 sc->sc_hw.devs[index].context_num = x;
2247 x = sc->sc_hw.devs[index].context_num;
2249 /* update number of contexts */
2250 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2251 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2252 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2253 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2259 xhci_configure_endpoint(struct usb_device *udev,
2260 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr,
2261 uint16_t interval, uint8_t max_packet_count, uint8_t mult,
2262 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size)
2264 struct usb_page_search buf_inp;
2265 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2266 struct xhci_input_dev_ctx *pinp;
2272 index = udev->controller_slot_id;
2274 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2276 pinp = buf_inp.buffer;
2278 epno = edesc->bEndpointAddress;
2279 type = edesc->bmAttributes & UE_XFERTYPE;
2281 if (type == UE_CONTROL)
2284 epno = XHCI_EPNO2EPID(epno);
2287 return (USB_ERR_NO_PIPE); /* invalid */
2289 if (max_packet_count == 0)
2290 return (USB_ERR_BAD_BUFSIZE);
2295 return (USB_ERR_BAD_BUFSIZE);
2297 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2298 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2299 XHCI_EPCTX_0_LSA_SET(0);
2301 switch (udev->speed) {
2302 case USB_SPEED_FULL:
2315 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2317 case UE_ISOCHRONOUS:
2318 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2320 switch (udev->speed) {
2321 case USB_SPEED_SUPER:
2324 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2325 max_packet_count /= mult;
2335 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2338 XHCI_EPCTX_1_HID_SET(0) |
2339 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2340 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2342 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2343 if (type != UE_ISOCHRONOUS)
2344 temp |= XHCI_EPCTX_1_CERR_SET(3);
2349 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2351 case UE_ISOCHRONOUS:
2352 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2355 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2358 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2362 /* check for IN direction */
2364 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2366 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2368 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2370 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2372 switch (edesc->bmAttributes & UE_XFERTYPE) {
2374 case UE_ISOCHRONOUS:
2375 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2376 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2380 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2383 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2387 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2390 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2392 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2394 return (0); /* success */
2398 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2400 struct xhci_endpoint_ext *pepext;
2401 struct usb_endpoint_ss_comp_descriptor *ecomp;
2403 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2404 xfer->endpoint->edesc);
2406 ecomp = xfer->endpoint->ecomp;
2408 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2409 usb_pc_cpu_flush(pepext->page_cache);
2411 return (xhci_configure_endpoint(xfer->xroot->udev,
2412 xfer->endpoint->edesc, pepext->physaddr,
2413 xfer->interval, xfer->max_packet_count,
2414 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2415 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2416 xfer->max_frame_size));
2420 xhci_configure_device(struct usb_device *udev)
2422 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2423 struct usb_page_search buf_inp;
2424 struct usb_page_cache *pcinp;
2425 struct xhci_input_dev_ctx *pinp;
2426 struct usb_device *hubdev;
2434 index = udev->controller_slot_id;
2436 DPRINTF("index=%u\n", index);
2438 pcinp = &sc->sc_hw.devs[index].input_pc;
2440 usbd_get_page(pcinp, 0, &buf_inp);
2442 pinp = buf_inp.buffer;
2447 /* figure out route string and root HUB port number */
2449 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2451 if (hubdev->parent_hub == NULL)
2454 depth = hubdev->parent_hub->depth;
2457 * NOTE: HS/FS/LS devices and the SS root HUB can have
2458 * more than 15 ports
2461 rh_port = hubdev->port_no;
2470 route |= rh_port << (4 * (depth - 1));
2473 DPRINTF("Route=0x%08x\n", route);
2475 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2476 XHCI_SCTX_0_CTX_NUM_SET(
2477 sc->sc_hw.devs[index].context_num + 1);
2479 switch (udev->speed) {
2481 temp |= XHCI_SCTX_0_SPEED_SET(2);
2482 if (udev->parent_hs_hub != NULL &&
2483 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2485 DPRINTF("Device inherits MTT\n");
2486 temp |= XHCI_SCTX_0_MTT_SET(1);
2489 case USB_SPEED_HIGH:
2490 temp |= XHCI_SCTX_0_SPEED_SET(3);
2491 if (sc->sc_hw.devs[index].nports != 0 &&
2492 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2493 DPRINTF("HUB supports MTT\n");
2494 temp |= XHCI_SCTX_0_MTT_SET(1);
2497 case USB_SPEED_FULL:
2498 temp |= XHCI_SCTX_0_SPEED_SET(1);
2499 if (udev->parent_hs_hub != NULL &&
2500 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2502 DPRINTF("Device inherits MTT\n");
2503 temp |= XHCI_SCTX_0_MTT_SET(1);
2507 temp |= XHCI_SCTX_0_SPEED_SET(4);
2511 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2512 (udev->speed == USB_SPEED_SUPER ||
2513 udev->speed == USB_SPEED_HIGH);
2516 temp |= XHCI_SCTX_0_HUB_SET(1);
2518 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2520 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2523 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2524 sc->sc_hw.devs[index].nports);
2527 switch (udev->speed) {
2528 case USB_SPEED_SUPER:
2529 switch (sc->sc_hw.devs[index].state) {
2530 case XHCI_ST_ADDRESSED:
2531 case XHCI_ST_CONFIGURED:
2532 /* enable power save */
2533 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2536 /* disable power save */
2544 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2546 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2549 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2550 sc->sc_hw.devs[index].tt);
2553 hubdev = udev->parent_hs_hub;
2555 /* check if we should activate the transaction translator */
2556 switch (udev->speed) {
2557 case USB_SPEED_FULL:
2559 if (hubdev != NULL) {
2560 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2561 hubdev->controller_slot_id);
2562 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2570 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2573 * These fields should be initialized to zero, according to
2574 * XHCI section 6.2.2 - slot context:
2576 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2577 XHCI_SCTX_3_SLOT_STATE_SET(0);
2579 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2582 xhci_dump_device(sc, &pinp->ctx_slot);
2584 usb_pc_cpu_flush(pcinp);
2586 return (0); /* success */
2590 xhci_alloc_device_ext(struct usb_device *udev)
2592 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2593 struct usb_page_search buf_dev;
2594 struct usb_page_search buf_ep;
2595 struct xhci_trb *trb;
2596 struct usb_page_cache *pc;
2597 struct usb_page *pg;
2602 index = udev->controller_slot_id;
2604 pc = &sc->sc_hw.devs[index].device_pc;
2605 pg = &sc->sc_hw.devs[index].device_pg;
2607 /* need to initialize the page cache */
2608 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2610 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2611 (2 * sizeof(struct xhci_dev_ctx)) :
2612 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2615 usbd_get_page(pc, 0, &buf_dev);
2617 pc = &sc->sc_hw.devs[index].input_pc;
2618 pg = &sc->sc_hw.devs[index].input_pg;
2620 /* need to initialize the page cache */
2621 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2623 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2624 (2 * sizeof(struct xhci_input_dev_ctx)) :
2625 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2629 pc = &sc->sc_hw.devs[index].endpoint_pc;
2630 pg = &sc->sc_hw.devs[index].endpoint_pg;
2632 /* need to initialize the page cache */
2633 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2635 if (usb_pc_alloc_mem(pc, pg,
2636 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2640 /* initialise all endpoint LINK TRBs */
2642 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2644 /* lookup endpoint TRB ring */
2645 usbd_get_page(pc, (uintptr_t)&
2646 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2648 /* get TRB pointer */
2649 trb = buf_ep.buffer;
2650 trb += XHCI_MAX_TRANSFERS - 1;
2652 /* get TRB start address */
2653 addr = buf_ep.physaddr;
2655 /* create LINK TRB */
2656 trb->qwTrb0 = htole64(addr);
2657 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2658 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2659 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2662 usb_pc_cpu_flush(pc);
2664 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2669 xhci_free_device_ext(udev);
2671 return (USB_ERR_NOMEM);
2675 xhci_free_device_ext(struct usb_device *udev)
2677 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2680 index = udev->controller_slot_id;
2681 xhci_set_slot_pointer(sc, index, 0);
2683 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2684 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2685 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2688 static struct xhci_endpoint_ext *
2689 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2691 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2692 struct xhci_endpoint_ext *pepext;
2693 struct usb_page_cache *pc;
2694 struct usb_page_search buf_ep;
2698 epno = edesc->bEndpointAddress;
2699 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2702 epno = XHCI_EPNO2EPID(epno);
2704 index = udev->controller_slot_id;
2706 pc = &sc->sc_hw.devs[index].endpoint_pc;
2708 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2710 pepext = &sc->sc_hw.devs[index].endp[epno];
2711 pepext->page_cache = pc;
2712 pepext->trb = buf_ep.buffer;
2713 pepext->physaddr = buf_ep.physaddr;
2719 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2721 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2725 epno = xfer->endpointno;
2726 if (xfer->flags_int.control_xfr)
2729 epno = XHCI_EPNO2EPID(epno);
2730 index = xfer->xroot->udev->controller_slot_id;
2732 if (xfer->xroot->udev->flags.self_suspended == 0) {
2733 XWRITE4(sc, door, XHCI_DOORBELL(index),
2734 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2739 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2741 struct xhci_endpoint_ext *pepext;
2743 if (xfer->flags_int.bandwidth_reclaimed) {
2744 xfer->flags_int.bandwidth_reclaimed = 0;
2746 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2747 xfer->endpoint->edesc);
2751 pepext->xfer[xfer->qh_pos] = NULL;
2753 if (error && pepext->trb_running != 0) {
2754 pepext->trb_halted = 1;
2755 pepext->trb_running = 0;
2761 xhci_transfer_insert(struct usb_xfer *xfer)
2763 struct xhci_td *td_first;
2764 struct xhci_td *td_last;
2765 struct xhci_trb *trb_link;
2766 struct xhci_endpoint_ext *pepext;
2774 /* check if already inserted */
2775 if (xfer->flags_int.bandwidth_reclaimed) {
2776 DPRINTFN(8, "Already in schedule\n");
2780 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2781 xfer->endpoint->edesc);
2783 td_first = xfer->td_transfer_first;
2784 td_last = xfer->td_transfer_last;
2785 addr = pepext->physaddr;
2787 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2790 /* single buffered */
2794 /* multi buffered */
2795 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2799 if (pepext->trb_used >= trb_limit) {
2800 DPRINTFN(8, "Too many TDs queued.\n");
2801 return (USB_ERR_NOMEM);
2804 /* check for stopped condition, after putting transfer on interrupt queue */
2805 if (pepext->trb_running == 0) {
2806 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2808 DPRINTFN(8, "Not running\n");
2810 /* start configuration */
2811 (void)usb_proc_msignal(&sc->sc_config_proc,
2812 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2818 /* get current TRB index */
2819 i = pepext->trb_index;
2821 /* get next TRB index */
2824 /* the last entry of the ring is a hardcoded link TRB */
2825 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2828 /* compute terminating return address */
2829 addr += inext * sizeof(struct xhci_trb);
2831 /* compute link TRB pointer */
2832 trb_link = td_last->td_trb + td_last->ntrb;
2834 /* update next pointer of last link TRB */
2835 trb_link->qwTrb0 = htole64(addr);
2836 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2837 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2838 XHCI_TRB_3_CYCLE_BIT |
2839 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2842 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2844 usb_pc_cpu_flush(td_last->page_cache);
2846 /* write ahead chain end marker */
2848 pepext->trb[inext].qwTrb0 = 0;
2849 pepext->trb[inext].dwTrb2 = 0;
2850 pepext->trb[inext].dwTrb3 = 0;
2852 /* update next pointer of link TRB */
2854 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2855 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2858 xhci_dump_trb(&pepext->trb[i]);
2860 usb_pc_cpu_flush(pepext->page_cache);
2862 /* toggle cycle bit which activates the transfer chain */
2864 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2865 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2867 usb_pc_cpu_flush(pepext->page_cache);
2869 DPRINTF("qh_pos = %u\n", i);
2871 pepext->xfer[i] = xfer;
2875 xfer->flags_int.bandwidth_reclaimed = 1;
2877 pepext->trb_index = inext;
2879 xhci_endpoint_doorbell(xfer);
2885 xhci_root_intr(struct xhci_softc *sc)
2889 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2891 /* clear any old interrupt data */
2892 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2894 for (i = 1; i <= sc->sc_noport; i++) {
2895 /* pick out CHANGE bits from the status register */
2896 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2897 XHCI_PS_CSC | XHCI_PS_PEC |
2898 XHCI_PS_OCC | XHCI_PS_WRC |
2899 XHCI_PS_PRC | XHCI_PS_PLC |
2901 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2902 DPRINTF("port %d changed\n", i);
2905 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2906 sizeof(sc->sc_hub_idata));
2909 /*------------------------------------------------------------------------*
2910 * xhci_device_done - XHCI done handler
2912 * NOTE: This function can be called two times in a row on
2913 * the same USB transfer. From close and from interrupt.
2914 *------------------------------------------------------------------------*/
2916 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2918 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2919 xfer, xfer->endpoint, error);
2921 /* remove transfer from HW queue */
2922 xhci_transfer_remove(xfer, error);
2924 /* dequeue transfer and start next transfer */
2925 usbd_transfer_done(xfer, error);
2928 /*------------------------------------------------------------------------*
2929 * XHCI data transfer support (generic type)
2930 *------------------------------------------------------------------------*/
2932 xhci_device_generic_open(struct usb_xfer *xfer)
2934 if (xfer->flags_int.isochronous_xfr) {
2935 switch (xfer->xroot->udev->speed) {
2936 case USB_SPEED_FULL:
2939 usb_hs_bandwidth_alloc(xfer);
2946 xhci_device_generic_close(struct usb_xfer *xfer)
2950 xhci_device_done(xfer, USB_ERR_CANCELLED);
2952 if (xfer->flags_int.isochronous_xfr) {
2953 switch (xfer->xroot->udev->speed) {
2954 case USB_SPEED_FULL:
2957 usb_hs_bandwidth_free(xfer);
2964 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
2965 struct usb_xfer *enter_xfer)
2967 struct usb_xfer *xfer;
2969 /* check if there is a current transfer */
2970 xfer = ep->endpoint_q.curr;
2975 * Check if the current transfer is started and then pickup
2976 * the next one, if any. Else wait for next start event due to
2977 * block on failure feature.
2979 if (!xfer->flags_int.bandwidth_reclaimed)
2982 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
2985 * In case of enter we have to consider that the
2986 * transfer is queued by the USB core after the enter
2995 /* try to multi buffer */
2996 xhci_transfer_insert(xfer);
3000 xhci_device_generic_enter(struct usb_xfer *xfer)
3004 /* setup TD's and QH */
3005 xhci_setup_generic_chain(xfer);
3007 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3011 xhci_device_generic_start(struct usb_xfer *xfer)
3015 /* try to insert xfer on HW queue */
3016 xhci_transfer_insert(xfer);
3018 /* try to multi buffer */
3019 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3021 /* add transfer last on interrupt queue */
3022 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3024 /* start timeout, if any */
3025 if (xfer->timeout != 0)
3026 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3029 struct usb_pipe_methods xhci_device_generic_methods =
3031 .open = xhci_device_generic_open,
3032 .close = xhci_device_generic_close,
3033 .enter = xhci_device_generic_enter,
3034 .start = xhci_device_generic_start,
3037 /*------------------------------------------------------------------------*
3038 * xhci root HUB support
3039 *------------------------------------------------------------------------*
3040 * Simulate a hardware HUB by handling all the necessary requests.
3041 *------------------------------------------------------------------------*/
3043 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3046 struct usb_device_descriptor xhci_devd =
3048 .bLength = sizeof(xhci_devd),
3049 .bDescriptorType = UDESC_DEVICE, /* type */
3050 HSETW(.bcdUSB, 0x0300), /* USB version */
3051 .bDeviceClass = UDCLASS_HUB, /* class */
3052 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3053 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3054 .bMaxPacketSize = 9, /* max packet size */
3055 HSETW(.idVendor, 0x0000), /* vendor */
3056 HSETW(.idProduct, 0x0000), /* product */
3057 HSETW(.bcdDevice, 0x0100), /* device version */
3061 .bNumConfigurations = 1, /* # of configurations */
3065 struct xhci_bos_desc xhci_bosd = {
3067 .bLength = sizeof(xhci_bosd.bosd),
3068 .bDescriptorType = UDESC_BOS,
3069 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3070 .bNumDeviceCaps = 3,
3073 .bLength = sizeof(xhci_bosd.usb2extd),
3074 .bDescriptorType = 1,
3075 .bDevCapabilityType = 2,
3076 .bmAttributes[0] = 2,
3079 .bLength = sizeof(xhci_bosd.usbdcd),
3080 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3081 .bDevCapabilityType = 3,
3082 .bmAttributes = 0, /* XXX */
3083 HSETW(.wSpeedsSupported, 0x000C),
3084 .bFunctionalitySupport = 8,
3085 .bU1DevExitLat = 255, /* dummy - not used */
3086 .wU2DevExitLat = { 0x00, 0x08 },
3089 .bLength = sizeof(xhci_bosd.cidd),
3090 .bDescriptorType = 1,
3091 .bDevCapabilityType = 4,
3093 .bContainerID = 0, /* XXX */
3098 struct xhci_config_desc xhci_confd = {
3100 .bLength = sizeof(xhci_confd.confd),
3101 .bDescriptorType = UDESC_CONFIG,
3102 .wTotalLength[0] = sizeof(xhci_confd),
3104 .bConfigurationValue = 1,
3105 .iConfiguration = 0,
3106 .bmAttributes = UC_SELF_POWERED,
3107 .bMaxPower = 0 /* max power */
3110 .bLength = sizeof(xhci_confd.ifcd),
3111 .bDescriptorType = UDESC_INTERFACE,
3113 .bInterfaceClass = UICLASS_HUB,
3114 .bInterfaceSubClass = UISUBCLASS_HUB,
3115 .bInterfaceProtocol = 0,
3118 .bLength = sizeof(xhci_confd.endpd),
3119 .bDescriptorType = UDESC_ENDPOINT,
3120 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3121 .bmAttributes = UE_INTERRUPT,
3122 .wMaxPacketSize[0] = 2, /* max 15 ports */
3126 .bLength = sizeof(xhci_confd.endpcd),
3127 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3134 struct usb_hub_ss_descriptor xhci_hubd = {
3135 .bLength = sizeof(xhci_hubd),
3136 .bDescriptorType = UDESC_SS_HUB,
3140 xhci_roothub_exec(struct usb_device *udev,
3141 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3143 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3144 const char *str_ptr;
3155 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3158 ptr = (const void *)&sc->sc_hub_desc;
3162 value = UGETW(req->wValue);
3163 index = UGETW(req->wIndex);
3165 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3166 "wValue=0x%04x wIndex=0x%04x\n",
3167 req->bmRequestType, req->bRequest,
3168 UGETW(req->wLength), value, index);
3170 #define C(x,y) ((x) | ((y) << 8))
3171 switch (C(req->bRequest, req->bmRequestType)) {
3172 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3173 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3174 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3176 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3177 * for the integrated root hub.
3180 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3182 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3184 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3185 switch (value >> 8) {
3187 if ((value & 0xff) != 0) {
3188 err = USB_ERR_IOERROR;
3191 len = sizeof(xhci_devd);
3192 ptr = (const void *)&xhci_devd;
3196 if ((value & 0xff) != 0) {
3197 err = USB_ERR_IOERROR;
3200 len = sizeof(xhci_bosd);
3201 ptr = (const void *)&xhci_bosd;
3205 if ((value & 0xff) != 0) {
3206 err = USB_ERR_IOERROR;
3209 len = sizeof(xhci_confd);
3210 ptr = (const void *)&xhci_confd;
3214 switch (value & 0xff) {
3215 case 0: /* Language table */
3219 case 1: /* Vendor */
3220 str_ptr = sc->sc_vendor;
3223 case 2: /* Product */
3224 str_ptr = "XHCI root HUB";
3232 len = usb_make_str_desc(
3233 sc->sc_hub_desc.temp,
3234 sizeof(sc->sc_hub_desc.temp),
3239 err = USB_ERR_IOERROR;
3243 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3245 sc->sc_hub_desc.temp[0] = 0;
3247 case C(UR_GET_STATUS, UT_READ_DEVICE):
3249 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3251 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3252 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3254 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3256 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3257 if (value >= XHCI_MAX_DEVICES) {
3258 err = USB_ERR_IOERROR;
3262 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3263 if (value != 0 && value != 1) {
3264 err = USB_ERR_IOERROR;
3267 sc->sc_conf = value;
3269 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3271 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3272 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3273 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3274 err = USB_ERR_IOERROR;
3276 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3278 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3281 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3283 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3284 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3287 (index > sc->sc_noport)) {
3288 err = USB_ERR_IOERROR;
3291 port = XHCI_PORTSC(index);
3293 v = XREAD4(sc, oper, port);
3294 i = XHCI_PS_PLS_GET(v);
3295 v &= ~XHCI_PS_CLEAR;
3298 case UHF_C_BH_PORT_RESET:
3299 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3301 case UHF_C_PORT_CONFIG_ERROR:
3302 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3304 case UHF_C_PORT_SUSPEND:
3305 case UHF_C_PORT_LINK_STATE:
3306 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3308 case UHF_C_PORT_CONNECTION:
3309 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3311 case UHF_C_PORT_ENABLE:
3312 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3314 case UHF_C_PORT_OVER_CURRENT:
3315 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3317 case UHF_C_PORT_RESET:
3318 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3320 case UHF_PORT_ENABLE:
3321 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3323 case UHF_PORT_POWER:
3324 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3326 case UHF_PORT_INDICATOR:
3327 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3329 case UHF_PORT_SUSPEND:
3333 XWRITE4(sc, oper, port, v |
3334 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3337 /* wait 20ms for resume sequence to complete */
3338 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3341 XWRITE4(sc, oper, port, v |
3342 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3345 err = USB_ERR_IOERROR;
3350 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3351 if ((value & 0xff) != 0) {
3352 err = USB_ERR_IOERROR;
3356 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3358 sc->sc_hub_desc.hubd = xhci_hubd;
3360 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3362 if (XHCI_HCS0_PPC(v))
3363 i = UHD_PWR_INDIVIDUAL;
3367 if (XHCI_HCS0_PIND(v))
3370 i |= UHD_OC_INDIVIDUAL;
3372 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3374 /* see XHCI section 5.4.9: */
3375 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3377 for (j = 1; j <= sc->sc_noport; j++) {
3379 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3380 if (v & XHCI_PS_DR) {
3381 sc->sc_hub_desc.hubd.
3382 DeviceRemovable[j / 8] |= 1U << (j % 8);
3385 len = sc->sc_hub_desc.hubd.bLength;
3388 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3390 memset(sc->sc_hub_desc.temp, 0, 16);
3393 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3394 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3397 (index > sc->sc_noport)) {
3398 err = USB_ERR_IOERROR;
3402 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3404 DPRINTFN(9, "port status=0x%08x\n", v);
3406 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3408 switch (XHCI_PS_SPEED_GET(v)) {
3410 i |= UPS_HIGH_SPEED;
3419 i |= UPS_OTHER_SPEED;
3423 if (v & XHCI_PS_CCS)
3424 i |= UPS_CURRENT_CONNECT_STATUS;
3425 if (v & XHCI_PS_PED)
3426 i |= UPS_PORT_ENABLED;
3427 if (v & XHCI_PS_OCA)
3428 i |= UPS_OVERCURRENT_INDICATOR;
3431 if (v & XHCI_PS_PP) {
3433 * The USB 3.0 RH is using the
3434 * USB 2.0's power bit
3436 i |= UPS_PORT_POWER;
3438 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3441 if (v & XHCI_PS_CSC)
3442 i |= UPS_C_CONNECT_STATUS;
3443 if (v & XHCI_PS_PEC)
3444 i |= UPS_C_PORT_ENABLED;
3445 if (v & XHCI_PS_OCC)
3446 i |= UPS_C_OVERCURRENT_INDICATOR;
3447 if (v & XHCI_PS_WRC)
3448 i |= UPS_C_BH_PORT_RESET;
3449 if (v & XHCI_PS_PRC)
3450 i |= UPS_C_PORT_RESET;
3451 if (v & XHCI_PS_PLC)
3452 i |= UPS_C_PORT_LINK_STATE;
3453 if (v & XHCI_PS_CEC)
3454 i |= UPS_C_PORT_CONFIG_ERROR;
3456 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3457 len = sizeof(sc->sc_hub_desc.ps);
3460 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3461 err = USB_ERR_IOERROR;
3464 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3467 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3473 (index > sc->sc_noport)) {
3474 err = USB_ERR_IOERROR;
3478 port = XHCI_PORTSC(index);
3479 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3482 case UHF_PORT_U1_TIMEOUT:
3483 if (XHCI_PS_SPEED_GET(v) != 4) {
3484 err = USB_ERR_IOERROR;
3487 port = XHCI_PORTPMSC(index);
3488 v = XREAD4(sc, oper, port);
3489 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3490 v |= XHCI_PM3_U1TO_SET(i);
3491 XWRITE4(sc, oper, port, v);
3493 case UHF_PORT_U2_TIMEOUT:
3494 if (XHCI_PS_SPEED_GET(v) != 4) {
3495 err = USB_ERR_IOERROR;
3498 port = XHCI_PORTPMSC(index);
3499 v = XREAD4(sc, oper, port);
3500 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3501 v |= XHCI_PM3_U2TO_SET(i);
3502 XWRITE4(sc, oper, port, v);
3504 case UHF_BH_PORT_RESET:
3505 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3507 case UHF_PORT_LINK_STATE:
3508 XWRITE4(sc, oper, port, v |
3509 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3510 /* 4ms settle time */
3511 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3513 case UHF_PORT_ENABLE:
3514 DPRINTFN(3, "set port enable %d\n", index);
3516 case UHF_PORT_SUSPEND:
3517 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3518 j = XHCI_PS_SPEED_GET(v);
3519 if ((j < 1) || (j > 3)) {
3520 /* non-supported speed */
3521 err = USB_ERR_IOERROR;
3524 XWRITE4(sc, oper, port, v |
3525 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3527 case UHF_PORT_RESET:
3528 DPRINTFN(6, "reset port %d\n", index);
3529 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3531 case UHF_PORT_POWER:
3532 DPRINTFN(3, "set port power %d\n", index);
3533 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3536 DPRINTFN(3, "set port test %d\n", index);
3538 case UHF_PORT_INDICATOR:
3539 DPRINTFN(3, "set port indicator %d\n", index);
3541 v &= ~XHCI_PS_PIC_SET(3);
3542 v |= XHCI_PS_PIC_SET(1);
3544 XWRITE4(sc, oper, port, v);
3547 err = USB_ERR_IOERROR;
3552 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3553 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3554 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3555 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3558 err = USB_ERR_IOERROR;
3568 xhci_xfer_setup(struct usb_setup_params *parm)
3570 struct usb_page_search page_info;
3571 struct usb_page_cache *pc;
3572 struct xhci_softc *sc;
3573 struct usb_xfer *xfer;
3578 sc = XHCI_BUS2SC(parm->udev->bus);
3579 xfer = parm->curr_xfer;
3582 * The proof for the "ntd" formula is illustrated like this:
3584 * +------------------------------------+
3588 * | | xxx | x | frm 0 |
3590 * | | xxx | xx | frm 1 |
3593 * +------------------------------------+
3595 * "xxx" means a completely full USB transfer descriptor
3597 * "x" and "xx" means a short USB packet
3599 * For the remainder of an USB transfer modulo
3600 * "max_data_length" we need two USB transfer descriptors.
3601 * One to transfer the remaining data and one to finalise with
3602 * a zero length packet in case the "force_short_xfer" flag is
3603 * set. We only need two USB transfer descriptors in the case
3604 * where the transfer length of the first one is a factor of
3605 * "max_frame_size". The rest of the needed USB transfer
3606 * descriptors is given by the buffer size divided by the
3607 * maximum data payload.
3609 parm->hc_max_packet_size = 0x400;
3610 parm->hc_max_packet_count = 16 * 3;
3611 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3613 xfer->flags_int.bdma_enable = 1;
3615 usbd_transfer_setup_sub(parm);
3617 if (xfer->flags_int.isochronous_xfr) {
3618 ntd = ((1 * xfer->nframes)
3619 + (xfer->max_data_length / xfer->max_hc_frame_size));
3620 } else if (xfer->flags_int.control_xfr) {
3621 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3622 + (xfer->max_data_length / xfer->max_hc_frame_size));
3624 ntd = ((2 * xfer->nframes)
3625 + (xfer->max_data_length / xfer->max_hc_frame_size));
3634 * Allocate queue heads and transfer descriptors
3638 if (usbd_transfer_setup_sub_malloc(
3639 parm, &pc, sizeof(struct xhci_td),
3640 XHCI_TD_ALIGN, ntd)) {
3641 parm->err = USB_ERR_NOMEM;
3645 for (n = 0; n != ntd; n++) {
3648 usbd_get_page(pc + n, 0, &page_info);
3650 td = page_info.buffer;
3653 td->td_self = page_info.physaddr;
3654 td->obj_next = last_obj;
3655 td->page_cache = pc + n;
3659 usb_pc_cpu_flush(pc + n);
3662 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3664 if (!xfer->flags_int.curr_dma_set) {
3665 xfer->flags_int.curr_dma_set = 1;
3671 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3673 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3674 struct usb_page_search buf_inp;
3675 struct usb_device *udev;
3676 struct xhci_endpoint_ext *pepext;
3677 struct usb_endpoint_descriptor *edesc;
3678 struct usb_page_cache *pcinp;
3683 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3684 xfer->endpoint->edesc);
3686 udev = xfer->xroot->udev;
3687 index = udev->controller_slot_id;
3689 pcinp = &sc->sc_hw.devs[index].input_pc;
3691 usbd_get_page(pcinp, 0, &buf_inp);
3693 edesc = xfer->endpoint->edesc;
3695 epno = edesc->bEndpointAddress;
3697 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3700 epno = XHCI_EPNO2EPID(epno);
3703 return (USB_ERR_NO_PIPE); /* invalid */
3707 /* configure endpoint */
3709 err = xhci_configure_endpoint_by_xfer(xfer);
3712 XHCI_CMD_UNLOCK(sc);
3717 * Get the endpoint into the stopped state according to the
3718 * endpoint context state diagram in the XHCI specification:
3721 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3724 DPRINTF("Could not stop endpoint %u\n", epno);
3726 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3729 DPRINTF("Could not reset endpoint %u\n", epno);
3731 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3732 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3735 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3738 * Get the endpoint into the running state according to the
3739 * endpoint context state diagram in the XHCI specification:
3742 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3744 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3747 DPRINTF("Could not configure endpoint %u\n", epno);
3749 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3752 DPRINTF("Could not configure endpoint %u\n", epno);
3754 XHCI_CMD_UNLOCK(sc);
3760 xhci_xfer_unsetup(struct usb_xfer *xfer)
3766 xhci_start_dma_delay(struct usb_xfer *xfer)
3768 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3770 /* put transfer on interrupt queue (again) */
3771 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3773 (void)usb_proc_msignal(&sc->sc_config_proc,
3774 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3778 xhci_configure_msg(struct usb_proc_msg *pm)
3780 struct xhci_softc *sc;
3781 struct xhci_endpoint_ext *pepext;
3782 struct usb_xfer *xfer;
3784 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3787 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3789 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3790 xfer->endpoint->edesc);
3792 if ((pepext->trb_halted != 0) ||
3793 (pepext->trb_running == 0)) {
3797 /* clear halted and running */
3798 pepext->trb_halted = 0;
3799 pepext->trb_running = 0;
3801 /* nuke remaining buffered transfers */
3803 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3805 * NOTE: We need to use the timeout
3806 * error code here else existing
3807 * isochronous clients can get
3810 if (pepext->xfer[i] != NULL) {
3811 xhci_device_done(pepext->xfer[i],
3817 * NOTE: The USB transfer cannot vanish in
3821 USB_BUS_UNLOCK(&sc->sc_bus);
3823 xhci_configure_reset_endpoint(xfer);
3825 USB_BUS_LOCK(&sc->sc_bus);
3827 /* check if halted is still cleared */
3828 if (pepext->trb_halted == 0) {
3829 pepext->trb_running = 1;
3830 pepext->trb_index = 0;
3835 if (xfer->flags_int.did_dma_delay) {
3837 /* remove transfer from interrupt queue (again) */
3838 usbd_transfer_dequeue(xfer);
3840 /* we are finally done */
3841 usb_dma_delay_done_cb(xfer);
3843 /* queue changed - restart */
3848 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3850 /* try to insert xfer on HW queue */
3851 xhci_transfer_insert(xfer);
3853 /* try to multi buffer */
3854 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3859 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3860 struct usb_endpoint *ep)
3862 struct xhci_endpoint_ext *pepext;
3864 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3865 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3867 if (udev->parent_hub == NULL) {
3868 /* root HUB has special endpoint handling */
3872 ep->methods = &xhci_device_generic_methods;
3874 pepext = xhci_get_endpoint_ext(udev, edesc);
3876 USB_BUS_LOCK(udev->bus);
3877 pepext->trb_halted = 1;
3878 pepext->trb_running = 0;
3879 USB_BUS_UNLOCK(udev->bus);
3883 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3889 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3891 struct xhci_endpoint_ext *pepext;
3895 if (udev->flags.usb_mode != USB_MODE_HOST) {
3899 if (udev->parent_hub == NULL) {
3900 /* root HUB has special endpoint handling */
3904 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3906 USB_BUS_LOCK(udev->bus);
3907 pepext->trb_halted = 1;
3908 pepext->trb_running = 0;
3909 USB_BUS_UNLOCK(udev->bus);
3913 xhci_device_init(struct usb_device *udev)
3915 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3919 /* no init for root HUB */
3920 if (udev->parent_hub == NULL)
3925 /* set invalid default */
3927 udev->controller_slot_id = sc->sc_noslot + 1;
3929 /* try to get a new slot ID from the XHCI */
3931 err = xhci_cmd_enable_slot(sc, &temp);
3934 XHCI_CMD_UNLOCK(sc);
3938 if (temp > sc->sc_noslot) {
3939 XHCI_CMD_UNLOCK(sc);
3940 return (USB_ERR_BAD_ADDRESS);
3943 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3944 DPRINTF("slot %u already allocated.\n", temp);
3945 XHCI_CMD_UNLOCK(sc);
3946 return (USB_ERR_BAD_ADDRESS);
3949 /* store slot ID for later reference */
3951 udev->controller_slot_id = temp;
3953 /* reset data structure */
3955 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
3957 /* set mark slot allocated */
3959 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
3961 err = xhci_alloc_device_ext(udev);
3963 XHCI_CMD_UNLOCK(sc);
3965 /* get device into default state */
3968 err = xhci_set_address(udev, NULL, 0);
3974 xhci_device_uninit(struct usb_device *udev)
3976 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3979 /* no init for root HUB */
3980 if (udev->parent_hub == NULL)
3985 index = udev->controller_slot_id;
3987 if (index <= sc->sc_noslot) {
3988 xhci_cmd_disable_slot(sc, index);
3989 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
3991 /* free device extension */
3992 xhci_free_device_ext(udev);
3995 XHCI_CMD_UNLOCK(sc);
3999 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4002 * Wait until the hardware has finished any possible use of
4003 * the transfer descriptor(s)
4005 *pus = 2048; /* microseconds */
4009 xhci_device_resume(struct usb_device *udev)
4011 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4018 /* check for root HUB */
4019 if (udev->parent_hub == NULL)
4022 index = udev->controller_slot_id;
4026 /* blindly resume all endpoints */
4028 USB_BUS_LOCK(udev->bus);
4030 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4031 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4032 XWRITE4(sc, door, XHCI_DOORBELL(index),
4033 n | XHCI_DB_SID_SET(p));
4037 USB_BUS_UNLOCK(udev->bus);
4039 XHCI_CMD_UNLOCK(sc);
4043 xhci_device_suspend(struct usb_device *udev)
4045 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4052 /* check for root HUB */
4053 if (udev->parent_hub == NULL)
4056 index = udev->controller_slot_id;
4060 /* blindly suspend all endpoints */
4062 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4063 err = xhci_cmd_stop_ep(sc, 1, n, index);
4065 DPRINTF("Failed to suspend endpoint "
4066 "%u on slot %u (ignored).\n", n, index);
4070 XHCI_CMD_UNLOCK(sc);
4074 xhci_set_hw_power(struct usb_bus *bus)
4080 xhci_device_state_change(struct usb_device *udev)
4082 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4083 struct usb_page_search buf_inp;
4087 /* check for root HUB */
4088 if (udev->parent_hub == NULL)
4091 index = udev->controller_slot_id;
4095 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4096 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4097 &sc->sc_hw.devs[index].tt);
4099 sc->sc_hw.devs[index].nports = 0;
4104 switch (usb_get_device_state(udev)) {
4105 case USB_STATE_POWERED:
4106 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4109 /* set default state */
4110 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4112 /* reset number of contexts */
4113 sc->sc_hw.devs[index].context_num = 0;
4115 err = xhci_cmd_reset_dev(sc, index);
4118 DPRINTF("Device reset failed "
4119 "for slot %u.\n", index);
4123 case USB_STATE_ADDRESSED:
4124 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4127 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4129 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4132 DPRINTF("Failed to deconfigure "
4133 "slot %u.\n", index);
4137 case USB_STATE_CONFIGURED:
4138 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4141 /* set configured state */
4142 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4144 /* reset number of contexts */
4145 sc->sc_hw.devs[index].context_num = 0;
4147 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4149 xhci_configure_mask(udev, 3, 0);
4151 err = xhci_configure_device(udev);
4153 DPRINTF("Could not configure device "
4154 "at slot %u.\n", index);
4157 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4159 DPRINTF("Could not evaluate device "
4160 "context at slot %u.\n", index);
4167 XHCI_CMD_UNLOCK(sc);
4170 struct usb_bus_methods xhci_bus_methods = {
4171 .endpoint_init = xhci_ep_init,
4172 .endpoint_uninit = xhci_ep_uninit,
4173 .xfer_setup = xhci_xfer_setup,
4174 .xfer_unsetup = xhci_xfer_unsetup,
4175 .get_dma_delay = xhci_get_dma_delay,
4176 .device_init = xhci_device_init,
4177 .device_uninit = xhci_device_uninit,
4178 .device_resume = xhci_device_resume,
4179 .device_suspend = xhci_device_suspend,
4180 .set_hw_power = xhci_set_hw_power,
4181 .roothub_exec = xhci_roothub_exec,
4182 .xfer_poll = xhci_do_poll,
4183 .start_dma_delay = xhci_start_dma_delay,
4184 .set_address = xhci_set_address,
4185 .clear_stall = xhci_ep_clear_stall,
4186 .device_state_change = xhci_device_state_change,
4187 .set_hw_power_sleep = xhci_set_hw_power_sleep,