2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29 * The XHCI 1.0 spec can be found at
30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
31 * and the USB 3.0 spec at
32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 * A few words about the design implementation: This driver emulates
37 * the concept about TDs which is found in EHCI specification. This
38 * way we avoid too much diveration among USB drivers.
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR xhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #include <dev/usb/controller/xhci.h>
80 #include <dev/usb/controller/xhcireg.h>
82 #define XHCI_BUS2SC(bus) \
83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
89 static int xhcipolling;
92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
94 &xhcidebug, 0, "Debug level");
95 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
96 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
97 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
98 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
100 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
101 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
103 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
104 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
110 #define XHCI_INTR_ENDPT 1
112 struct xhci_std_temp {
113 struct xhci_softc *sc;
114 struct usb_page_cache *pc;
116 struct xhci_td *td_next;
119 uint32_t max_packet_size;
131 uint8_t do_isoc_sync;
134 static void xhci_do_poll(struct usb_bus *);
135 static void xhci_device_done(struct usb_xfer *, usb_error_t);
136 static void xhci_root_intr(struct xhci_softc *);
137 static void xhci_free_device_ext(struct usb_device *);
138 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
139 struct usb_endpoint_descriptor *);
140 static usb_proc_callback_t xhci_configure_msg;
141 static usb_error_t xhci_configure_device(struct usb_device *);
142 static usb_error_t xhci_configure_endpoint(struct usb_device *,
143 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
144 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
145 static usb_error_t xhci_configure_mask(struct usb_device *,
147 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
149 static void xhci_endpoint_doorbell(struct usb_xfer *);
150 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
151 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
152 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
154 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
157 extern struct usb_bus_methods xhci_bus_methods;
161 xhci_dump_trb(struct xhci_trb *trb)
163 DPRINTFN(5, "trb = %p\n", trb);
164 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
165 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
166 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
170 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
172 DPRINTFN(5, "pep = %p\n", pep);
173 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
174 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
175 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
176 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
177 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
178 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
179 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
183 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
185 DPRINTFN(5, "psl = %p\n", psl);
186 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
187 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
188 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
189 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
194 xhci_use_polling(void)
197 return (xhcipolling != 0);
204 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
206 struct xhci_softc *sc = XHCI_BUS2SC(bus);
209 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
210 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
212 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
213 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
215 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
216 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
217 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
222 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
224 if (sc->sc_ctx_is_64_byte) {
226 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
227 /* all contexts are initially 32-bytes */
228 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
229 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
235 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
237 if (sc->sc_ctx_is_64_byte) {
239 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
240 /* all contexts are initially 32-bytes */
241 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
242 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
244 return (le32toh(*ptr));
248 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
250 if (sc->sc_ctx_is_64_byte) {
252 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
253 /* all contexts are initially 32-bytes */
254 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
255 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
262 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
264 if (sc->sc_ctx_is_64_byte) {
266 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
267 /* all contexts are initially 32-bytes */
268 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
269 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
271 return (le64toh(*ptr));
276 xhci_reset_command_queue_locked(struct xhci_softc *sc)
278 struct usb_page_search buf_res;
279 struct xhci_hw_root *phwr;
285 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
286 if (temp & XHCI_CRCR_LO_CRR) {
287 DPRINTF("Command ring running\n");
288 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
291 * Try to abort the last command as per section
292 * 4.6.1.2 "Aborting a Command" of the XHCI
296 /* stop and cancel */
297 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
298 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
300 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
301 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
304 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
306 /* check if command ring is still running */
307 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
308 if (temp & XHCI_CRCR_LO_CRR) {
309 DPRINTF("Comand ring still running\n");
310 return (USB_ERR_IOERROR);
314 /* reset command ring */
315 sc->sc_command_ccs = 1;
316 sc->sc_command_idx = 0;
318 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
320 /* set up command ring control base address */
321 addr = buf_res.physaddr;
322 phwr = buf_res.buffer;
323 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
325 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
327 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
328 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
330 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
332 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
333 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
339 xhci_start_controller(struct xhci_softc *sc)
341 struct usb_page_search buf_res;
342 struct xhci_hw_root *phwr;
343 struct xhci_dev_ctx_addr *pdctxa;
350 sc->sc_event_ccs = 1;
351 sc->sc_event_idx = 0;
352 sc->sc_command_ccs = 1;
353 sc->sc_command_idx = 0;
355 /* Reset controller */
356 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
358 for (i = 0; i != 100; i++) {
359 usb_pause_mtx(NULL, hz / 100);
360 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
361 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
367 device_printf(sc->sc_bus.parent, "Controller "
369 return (USB_ERR_IOERROR);
372 /* set up number of device slots */
373 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
374 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
376 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
378 temp = XREAD4(sc, oper, XHCI_USBSTS);
380 /* clear interrupts */
381 XWRITE4(sc, oper, XHCI_USBSTS, temp);
382 /* disable all device notifications */
383 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
385 /* set up device context base address */
386 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
387 pdctxa = buf_res.buffer;
388 memset(pdctxa, 0, sizeof(*pdctxa));
390 addr = buf_res.physaddr;
391 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
393 /* slot 0 points to the table of scratchpad pointers */
394 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
396 for (i = 0; i != sc->sc_noscratch; i++) {
397 struct usb_page_search buf_scp;
398 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
399 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
402 addr = buf_res.physaddr;
404 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
405 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
406 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
407 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
409 /* set up event table size */
410 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
411 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
413 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
415 /* set up interrupt rate */
416 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
418 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
420 phwr = buf_res.buffer;
421 addr = buf_res.physaddr;
422 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
424 /* reset hardware root structure */
425 memset(phwr, 0, sizeof(*phwr));
427 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
428 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
430 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
432 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
433 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
435 addr = buf_res.physaddr;
437 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
439 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
440 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
442 /* set up interrupter registers */
443 temp = XREAD4(sc, runt, XHCI_IMAN(0));
444 temp |= XHCI_IMAN_INTR_ENA;
445 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
447 /* set up command ring control base address */
448 addr = buf_res.physaddr;
449 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
451 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
453 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
454 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
456 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
458 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
461 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
462 XHCI_CMD_INTE | XHCI_CMD_HSEE);
464 for (i = 0; i != 100; i++) {
465 usb_pause_mtx(NULL, hz / 100);
466 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
471 XWRITE4(sc, oper, XHCI_USBCMD, 0);
472 device_printf(sc->sc_bus.parent, "Run timeout.\n");
473 return (USB_ERR_IOERROR);
476 /* catch any lost interrupts */
477 xhci_do_poll(&sc->sc_bus);
479 if (sc->sc_port_route != NULL) {
480 /* Route all ports to the XHCI by default */
481 sc->sc_port_route(sc->sc_bus.parent,
482 ~xhciroute, xhciroute);
488 xhci_halt_controller(struct xhci_softc *sc)
496 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
497 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
498 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
500 /* Halt controller */
501 XWRITE4(sc, oper, XHCI_USBCMD, 0);
503 for (i = 0; i != 100; i++) {
504 usb_pause_mtx(NULL, hz / 100);
505 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
511 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
512 return (USB_ERR_IOERROR);
518 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
524 /* initialize some bus fields */
525 sc->sc_bus.parent = self;
527 /* set the bus revision */
528 sc->sc_bus.usbrev = USB_REV_3_0;
530 /* set up the bus struct */
531 sc->sc_bus.methods = &xhci_bus_methods;
533 /* set up devices array */
534 sc->sc_bus.devices = sc->sc_devices;
535 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
537 /* set default cycle state in case of early interrupts */
538 sc->sc_event_ccs = 1;
539 sc->sc_command_ccs = 1;
541 /* set up bus space offsets */
543 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
544 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
545 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
547 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
548 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
549 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
551 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
553 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
554 device_printf(sc->sc_bus.parent, "Controller does "
555 "not support 4K page size.\n");
559 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
561 DPRINTF("HCS0 = 0x%08x\n", temp);
563 /* set up context size */
564 if (XHCI_HCS0_CSZ(temp)) {
565 sc->sc_ctx_is_64_byte = 1;
567 sc->sc_ctx_is_64_byte = 0;
571 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
572 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
574 device_printf(self, "%d bytes context size, %d-bit DMA\n",
575 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
577 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
579 /* get number of device slots */
580 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
582 if (sc->sc_noport == 0) {
583 device_printf(sc->sc_bus.parent, "Invalid number "
584 "of ports: %u\n", sc->sc_noport);
588 sc->sc_noport = sc->sc_noport;
589 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
591 DPRINTF("Max slots: %u\n", sc->sc_noslot);
593 if (sc->sc_noslot > XHCI_MAX_DEVICES)
594 sc->sc_noslot = XHCI_MAX_DEVICES;
596 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
598 DPRINTF("HCS2=0x%08x\n", temp);
600 /* get number of scratchpads */
601 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
603 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
604 device_printf(sc->sc_bus.parent, "XHCI request "
605 "too many scratchpads\n");
609 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
611 /* get event table size */
612 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
613 if (sc->sc_erst_max > XHCI_MAX_RSEG)
614 sc->sc_erst_max = XHCI_MAX_RSEG;
616 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
618 /* get maximum exit latency */
619 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
620 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
622 /* Check if we should use the default IMOD value. */
623 if (sc->sc_imod_default == 0)
624 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
626 /* get all DMA memory */
627 if (usb_bus_mem_alloc_all(&sc->sc_bus,
628 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
632 /* set up command queue mutex and condition varible */
633 cv_init(&sc->sc_cmd_cv, "CMDQ");
634 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
636 if (usb_proc_create(&sc->sc_config_proc,
637 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
638 printf("WARNING: Creation of XHCI configure "
639 "callback process failed.\n");
641 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
642 sc->sc_config_msg[0].bus = &sc->sc_bus;
643 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
644 sc->sc_config_msg[1].bus = &sc->sc_bus;
650 xhci_uninit(struct xhci_softc *sc)
652 usb_proc_free(&sc->sc_config_proc);
654 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
656 cv_destroy(&sc->sc_cmd_cv);
657 sx_destroy(&sc->sc_cmd_sx);
661 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
663 struct xhci_softc *sc = XHCI_BUS2SC(bus);
666 case USB_HW_POWER_SUSPEND:
667 DPRINTF("Stopping the XHCI\n");
668 xhci_halt_controller(sc);
670 case USB_HW_POWER_SHUTDOWN:
671 DPRINTF("Stopping the XHCI\n");
672 xhci_halt_controller(sc);
674 case USB_HW_POWER_RESUME:
675 DPRINTF("Starting the XHCI\n");
676 xhci_start_controller(sc);
684 xhci_generic_done_sub(struct usb_xfer *xfer)
687 struct xhci_td *td_alt_next;
691 td = xfer->td_transfer_cache;
692 td_alt_next = td->alt_next;
694 if (xfer->aframes != xfer->nframes)
695 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
699 usb_pc_cpu_invalidate(td->page_cache);
704 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
705 xfer, (unsigned int)xfer->aframes,
706 (unsigned int)xfer->nframes,
707 (unsigned int)len, (unsigned int)td->len,
708 (unsigned int)status);
711 * Verify the status length and
712 * add the length to "frlengths[]":
715 /* should not happen */
716 DPRINTF("Invalid status length, "
717 "0x%04x/0x%04x bytes\n", len, td->len);
718 status = XHCI_TRB_ERROR_LENGTH;
719 } else if (xfer->aframes != xfer->nframes) {
720 xfer->frlengths[xfer->aframes] += td->len - len;
722 /* Check for last transfer */
723 if (((void *)td) == xfer->td_transfer_last) {
727 /* Check for transfer error */
728 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
729 status != XHCI_TRB_ERROR_SUCCESS) {
730 /* the transfer is finished */
734 /* Check for short transfer */
736 if (xfer->flags_int.short_frames_ok ||
737 xfer->flags_int.isochronous_xfr ||
738 xfer->flags_int.control_xfr) {
739 /* follow alt next */
742 /* the transfer is finished */
749 if (td->alt_next != td_alt_next) {
750 /* this USB frame is complete */
755 /* update transfer cache */
757 xfer->td_transfer_cache = td;
759 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
760 (status != XHCI_TRB_ERROR_SHORT_PKT &&
761 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
762 USB_ERR_NORMAL_COMPLETION);
766 xhci_generic_done(struct usb_xfer *xfer)
770 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
771 xfer, xfer->endpoint);
775 xfer->td_transfer_cache = xfer->td_transfer_first;
777 if (xfer->flags_int.control_xfr) {
779 if (xfer->flags_int.control_hdr)
780 err = xhci_generic_done_sub(xfer);
784 if (xfer->td_transfer_cache == NULL)
788 while (xfer->aframes != xfer->nframes) {
790 err = xhci_generic_done_sub(xfer);
793 if (xfer->td_transfer_cache == NULL)
797 if (xfer->flags_int.control_xfr &&
798 !xfer->flags_int.control_act)
799 err = xhci_generic_done_sub(xfer);
801 /* transfer is complete */
802 xhci_device_done(xfer, err);
806 xhci_activate_transfer(struct usb_xfer *xfer)
810 td = xfer->td_transfer_cache;
812 usb_pc_cpu_invalidate(td->page_cache);
814 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
816 /* activate the transfer */
818 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
819 usb_pc_cpu_flush(td->page_cache);
821 xhci_endpoint_doorbell(xfer);
826 xhci_skip_transfer(struct usb_xfer *xfer)
829 struct xhci_td *td_last;
831 td = xfer->td_transfer_cache;
832 td_last = xfer->td_transfer_last;
836 usb_pc_cpu_invalidate(td->page_cache);
838 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
840 usb_pc_cpu_invalidate(td_last->page_cache);
842 /* copy LINK TRB to current waiting location */
844 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
845 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
846 usb_pc_cpu_flush(td->page_cache);
848 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
849 usb_pc_cpu_flush(td->page_cache);
851 xhci_endpoint_doorbell(xfer);
855 /*------------------------------------------------------------------------*
856 * xhci_check_transfer
857 *------------------------------------------------------------------------*/
859 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
872 td_event = le64toh(trb->qwTrb0);
873 temp = le32toh(trb->dwTrb2);
875 remainder = XHCI_TRB_2_REM_GET(temp);
876 status = XHCI_TRB_2_ERROR_GET(temp);
878 temp = le32toh(trb->dwTrb3);
879 epno = XHCI_TRB_3_EP_GET(temp);
880 index = XHCI_TRB_3_SLOT_GET(temp);
882 /* check if error means halted */
883 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
884 status != XHCI_TRB_ERROR_SUCCESS);
886 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
887 index, epno, remainder, status);
889 if (index > sc->sc_noslot) {
890 DPRINTF("Invalid slot.\n");
894 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
895 DPRINTF("Invalid endpoint.\n");
899 /* try to find the USB transfer that generated the event */
900 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
901 struct usb_xfer *xfer;
903 struct xhci_endpoint_ext *pepext;
905 pepext = &sc->sc_hw.devs[index].endp[epno];
907 xfer = pepext->xfer[i];
911 td = xfer->td_transfer_cache;
913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
915 (long long)td->td_self,
916 (long long)td->td_self + sizeof(td->td_trb));
919 * NOTE: Some XHCI implementations might not trigger
920 * an event on the last LINK TRB so we need to
921 * consider both the last and second last event
922 * address as conditions for a successful transfer.
924 * NOTE: We assume that the XHCI will only trigger one
925 * event per chain of TRBs.
928 offset = td_event - td->td_self;
931 offset < (int64_t)sizeof(td->td_trb)) {
933 usb_pc_cpu_invalidate(td->page_cache);
935 /* compute rest of remainder, if any */
936 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
937 temp = le32toh(td->td_trb[i].dwTrb2);
938 remainder += XHCI_TRB_2_BYTES_GET(temp);
941 DPRINTFN(5, "New remainder: %u\n", remainder);
943 /* clear isochronous transfer errors */
944 if (xfer->flags_int.isochronous_xfr) {
947 status = XHCI_TRB_ERROR_SUCCESS;
952 /* "td->remainder" is verified later */
953 td->remainder = remainder;
956 usb_pc_cpu_flush(td->page_cache);
959 * 1) Last transfer descriptor makes the
962 if (((void *)td) == xfer->td_transfer_last) {
963 DPRINTF("TD is last\n");
964 xhci_generic_done(xfer);
969 * 2) Any kind of error makes the transfer
973 DPRINTF("TD has I/O error\n");
974 xhci_generic_done(xfer);
979 * 3) If there is no alternate next transfer,
980 * a short packet also makes the transfer done
982 if (td->remainder > 0) {
983 if (td->alt_next == NULL) {
985 "short TD has no alternate next\n");
986 xhci_generic_done(xfer);
989 DPRINTF("TD has short pkt\n");
990 if (xfer->flags_int.short_frames_ok ||
991 xfer->flags_int.isochronous_xfr ||
992 xfer->flags_int.control_xfr) {
993 /* follow the alt next */
994 xfer->td_transfer_cache = td->alt_next;
995 xhci_activate_transfer(xfer);
998 xhci_skip_transfer(xfer);
999 xhci_generic_done(xfer);
1004 * 4) Transfer complete - go to next TD
1006 DPRINTF("Following next TD\n");
1007 xfer->td_transfer_cache = td->obj_next;
1008 xhci_activate_transfer(xfer);
1009 break; /* there should only be one match */
1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1017 if (sc->sc_cmd_addr == trb->qwTrb0) {
1018 DPRINTF("Received command event\n");
1019 sc->sc_cmd_result[0] = trb->dwTrb2;
1020 sc->sc_cmd_result[1] = trb->dwTrb3;
1021 cv_signal(&sc->sc_cmd_cv);
1022 return (1); /* command match */
1028 xhci_interrupt_poll(struct xhci_softc *sc)
1030 struct usb_page_search buf_res;
1031 struct xhci_hw_root *phwr;
1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1043 phwr = buf_res.buffer;
1045 /* Receive any events */
1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1049 i = sc->sc_event_idx;
1050 j = sc->sc_event_ccs;
1055 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1062 event = XHCI_TRB_3_TYPE_GET(temp);
1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1066 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1067 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1070 case XHCI_TRB_EVENT_TRANSFER:
1071 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1073 case XHCI_TRB_EVENT_CMD_COMPLETE:
1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1077 DPRINTF("Unhandled event = %u\n", event);
1083 if (i == XHCI_MAX_EVENTS) {
1087 /* check for timeout */
1093 sc->sc_event_idx = i;
1094 sc->sc_event_ccs = j;
1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1098 * latched. That means to activate the register we need to
1099 * write both the low and high double word of the 64-bit
1103 addr = buf_res.physaddr;
1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1106 /* try to clear busy bit */
1107 addr |= XHCI_ERDP_LO_BUSY;
1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1117 uint16_t timeout_ms)
1119 struct usb_page_search buf_res;
1120 struct xhci_hw_root *phwr;
1125 uint8_t timeout = 0;
1128 XHCI_CMD_ASSERT_LOCKED(sc);
1130 /* get hardware root structure */
1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1134 phwr = buf_res.buffer;
1138 USB_BUS_LOCK(&sc->sc_bus);
1140 i = sc->sc_command_idx;
1141 j = sc->sc_command_ccs;
1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1145 (long long)le64toh(trb->qwTrb0),
1146 (long)le32toh(trb->dwTrb2),
1147 (long)le32toh(trb->dwTrb3));
1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1163 phwr->hwr_commands[i].dwTrb3 = temp;
1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1167 addr = buf_res.physaddr;
1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1170 sc->sc_cmd_addr = htole64(addr);
1174 if (i == (XHCI_MAX_COMMANDS - 1)) {
1177 temp = htole32(XHCI_TRB_3_TC_BIT |
1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1179 XHCI_TRB_3_CYCLE_BIT);
1181 temp = htole32(XHCI_TRB_3_TC_BIT |
1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1185 phwr->hwr_commands[i].dwTrb3 = temp;
1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1193 sc->sc_command_idx = i;
1194 sc->sc_command_ccs = j;
1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1199 USB_MS_TO_TICKS(timeout_ms));
1202 * In some error cases event interrupts are not generated.
1203 * Poll one time to see if the command has completed.
1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1206 DPRINTF("Command was completed when polling\n");
1210 DPRINTF("Command timeout!\n");
1212 * After some weeks of continuous operation, it has
1213 * been observed that the ASMedia Technology, ASM1042
1214 * SuperSpeed USB Host Controller can suddenly stop
1215 * accepting commands via the command queue. Try to
1216 * first reset the command queue. If that fails do a
1217 * host controller reset.
1220 xhci_reset_command_queue_locked(sc) == 0) {
1221 temp = le32toh(trb->dwTrb3);
1224 * Avoid infinite XHCI reset loops if the set
1225 * address command fails to respond due to a
1226 * non-enumerating device:
1228 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1229 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1230 DPRINTF("Set address timeout\n");
1236 DPRINTF("Controller reset!\n");
1237 usb_bus_reset_async_locked(&sc->sc_bus);
1239 err = USB_ERR_TIMEOUT;
1243 temp = le32toh(sc->sc_cmd_result[0]);
1244 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1245 err = USB_ERR_IOERROR;
1247 trb->dwTrb2 = sc->sc_cmd_result[0];
1248 trb->dwTrb3 = sc->sc_cmd_result[1];
1251 USB_BUS_UNLOCK(&sc->sc_bus);
1258 xhci_cmd_nop(struct xhci_softc *sc)
1260 struct xhci_trb trb;
1267 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1269 trb.dwTrb3 = htole32(temp);
1271 return (xhci_do_command(sc, &trb, 100 /* ms */));
1276 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1278 struct xhci_trb trb;
1286 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1288 err = xhci_do_command(sc, &trb, 100 /* ms */);
1292 temp = le32toh(trb.dwTrb3);
1294 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1301 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1303 struct xhci_trb trb;
1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1311 XHCI_TRB_3_SLOT_SET(slot_id);
1313 trb.dwTrb3 = htole32(temp);
1315 return (xhci_do_command(sc, &trb, 100 /* ms */));
1319 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1320 uint8_t bsr, uint8_t slot_id)
1322 struct xhci_trb trb;
1327 trb.qwTrb0 = htole64(input_ctx);
1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1330 XHCI_TRB_3_SLOT_SET(slot_id);
1333 temp |= XHCI_TRB_3_BSR_BIT;
1335 trb.dwTrb3 = htole32(temp);
1337 return (xhci_do_command(sc, &trb, 500 /* ms */));
1341 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1343 struct usb_page_search buf_inp;
1344 struct usb_page_search buf_dev;
1345 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1346 struct xhci_hw_dev *hdev;
1347 struct xhci_dev_ctx *pdev;
1348 struct xhci_endpoint_ext *pepext;
1354 /* the root HUB case is not handled here */
1355 if (udev->parent_hub == NULL)
1356 return (USB_ERR_INVAL);
1358 index = udev->controller_slot_id;
1360 hdev = &sc->sc_hw.devs[index];
1367 switch (hdev->state) {
1368 case XHCI_ST_DEFAULT:
1369 case XHCI_ST_ENABLED:
1371 hdev->state = XHCI_ST_ENABLED;
1373 /* set configure mask to slot and EP0 */
1374 xhci_configure_mask(udev, 3, 0);
1376 /* configure input slot context structure */
1377 err = xhci_configure_device(udev);
1380 DPRINTF("Could not configure device\n");
1384 /* configure input endpoint context structure */
1385 switch (udev->speed) {
1387 case USB_SPEED_FULL:
1390 case USB_SPEED_HIGH:
1398 pepext = xhci_get_endpoint_ext(udev,
1399 &udev->ctrl_ep_desc);
1401 /* ensure the control endpoint is setup again */
1402 USB_BUS_LOCK(udev->bus);
1403 pepext->trb_halted = 1;
1404 pepext->trb_running = 0;
1405 USB_BUS_UNLOCK(udev->bus);
1407 err = xhci_configure_endpoint(udev,
1408 &udev->ctrl_ep_desc, pepext,
1409 0, 1, 1, 0, mps, mps);
1412 DPRINTF("Could not configure default endpoint\n");
1416 /* execute set address command */
1417 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1419 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1420 (address == 0), index);
1423 temp = le32toh(sc->sc_cmd_result[0]);
1424 if (address == 0 && sc->sc_port_route != NULL &&
1425 XHCI_TRB_2_ERROR_GET(temp) ==
1426 XHCI_TRB_ERROR_PARAMETER) {
1427 /* LynxPoint XHCI - ports are not switchable */
1428 /* Un-route all ports from the XHCI */
1429 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1431 DPRINTF("Could not set address "
1432 "for slot %u.\n", index);
1437 /* update device address to new value */
1439 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1440 pdev = buf_dev.buffer;
1441 usb_pc_cpu_invalidate(&hdev->device_pc);
1443 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1444 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1446 /* update device state to new value */
1449 hdev->state = XHCI_ST_ADDRESSED;
1451 hdev->state = XHCI_ST_DEFAULT;
1455 DPRINTF("Wrong state for set address.\n");
1456 err = USB_ERR_IOERROR;
1459 XHCI_CMD_UNLOCK(sc);
1468 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1469 uint8_t deconfigure, uint8_t slot_id)
1471 struct xhci_trb trb;
1476 trb.qwTrb0 = htole64(input_ctx);
1478 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1479 XHCI_TRB_3_SLOT_SET(slot_id);
1482 temp |= XHCI_TRB_3_DCEP_BIT;
1484 trb.dwTrb3 = htole32(temp);
1486 return (xhci_do_command(sc, &trb, 100 /* ms */));
1490 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1493 struct xhci_trb trb;
1498 trb.qwTrb0 = htole64(input_ctx);
1500 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1501 XHCI_TRB_3_SLOT_SET(slot_id);
1502 trb.dwTrb3 = htole32(temp);
1504 return (xhci_do_command(sc, &trb, 100 /* ms */));
1508 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1509 uint8_t ep_id, uint8_t slot_id)
1511 struct xhci_trb trb;
1518 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1519 XHCI_TRB_3_SLOT_SET(slot_id) |
1520 XHCI_TRB_3_EP_SET(ep_id);
1523 temp |= XHCI_TRB_3_PRSV_BIT;
1525 trb.dwTrb3 = htole32(temp);
1527 return (xhci_do_command(sc, &trb, 100 /* ms */));
1531 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1532 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1534 struct xhci_trb trb;
1539 trb.qwTrb0 = htole64(dequeue_ptr);
1541 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1542 trb.dwTrb2 = htole32(temp);
1544 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1545 XHCI_TRB_3_SLOT_SET(slot_id) |
1546 XHCI_TRB_3_EP_SET(ep_id);
1547 trb.dwTrb3 = htole32(temp);
1549 return (xhci_do_command(sc, &trb, 100 /* ms */));
1553 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1554 uint8_t ep_id, uint8_t slot_id)
1556 struct xhci_trb trb;
1563 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1564 XHCI_TRB_3_SLOT_SET(slot_id) |
1565 XHCI_TRB_3_EP_SET(ep_id);
1568 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1570 trb.dwTrb3 = htole32(temp);
1572 return (xhci_do_command(sc, &trb, 100 /* ms */));
1576 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1578 struct xhci_trb trb;
1585 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1586 XHCI_TRB_3_SLOT_SET(slot_id);
1588 trb.dwTrb3 = htole32(temp);
1590 return (xhci_do_command(sc, &trb, 100 /* ms */));
1593 /*------------------------------------------------------------------------*
1594 * xhci_interrupt - XHCI interrupt handler
1595 *------------------------------------------------------------------------*/
1597 xhci_interrupt(struct xhci_softc *sc)
1602 USB_BUS_LOCK(&sc->sc_bus);
1604 status = XREAD4(sc, oper, XHCI_USBSTS);
1606 /* acknowledge interrupts, if any */
1608 XWRITE4(sc, oper, XHCI_USBSTS, status);
1609 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1612 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1614 /* force clearing of pending interrupts */
1615 if (temp & XHCI_IMAN_INTR_PEND)
1616 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1618 /* check for event(s) */
1619 xhci_interrupt_poll(sc);
1621 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1622 XHCI_STS_HSE | XHCI_STS_HCE)) {
1624 if (status & XHCI_STS_PCD) {
1628 if (status & XHCI_STS_HCH) {
1629 printf("%s: host controller halted\n",
1633 if (status & XHCI_STS_HSE) {
1634 printf("%s: host system error\n",
1638 if (status & XHCI_STS_HCE) {
1639 printf("%s: host controller error\n",
1643 USB_BUS_UNLOCK(&sc->sc_bus);
1646 /*------------------------------------------------------------------------*
1647 * xhci_timeout - XHCI timeout handler
1648 *------------------------------------------------------------------------*/
1650 xhci_timeout(void *arg)
1652 struct usb_xfer *xfer = arg;
1654 DPRINTF("xfer=%p\n", xfer);
1656 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1658 /* transfer is transferred */
1659 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1663 xhci_do_poll(struct usb_bus *bus)
1665 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1667 USB_BUS_LOCK(&sc->sc_bus);
1668 xhci_interrupt_poll(sc);
1669 USB_BUS_UNLOCK(&sc->sc_bus);
1673 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1675 struct usb_page_search buf_res;
1677 struct xhci_td *td_next;
1678 struct xhci_td *td_alt_next;
1679 struct xhci_td *td_first;
1680 uint32_t buf_offset;
1685 uint8_t shortpkt_old;
1691 shortpkt_old = temp->shortpkt;
1692 len_old = temp->len;
1699 td_next = td_first = temp->td_next;
1703 if (temp->len == 0) {
1708 /* send a Zero Length Packet, ZLP, last */
1715 average = temp->average;
1717 if (temp->len < average) {
1718 if (temp->len % temp->max_packet_size) {
1721 average = temp->len;
1725 if (td_next == NULL)
1726 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1731 td_next = td->obj_next;
1733 /* check if we are pre-computing */
1737 /* update remaining length */
1739 temp->len -= average;
1743 /* fill out current TD */
1749 /* update remaining length */
1751 temp->len -= average;
1753 /* reset TRB index */
1757 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1758 /* immediate data */
1763 td->td_trb[0].qwTrb0 = 0;
1765 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1766 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1769 dword = XHCI_TRB_2_BYTES_SET(8) |
1770 XHCI_TRB_2_TDSZ_SET(0) |
1771 XHCI_TRB_2_IRQ_SET(0);
1773 td->td_trb[0].dwTrb2 = htole32(dword);
1775 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1776 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1779 if (td->td_trb[0].qwTrb0 &
1780 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1781 if (td->td_trb[0].qwTrb0 &
1782 htole64(XHCI_TRB_0_DIR_IN_MASK))
1783 dword |= XHCI_TRB_3_TRT_IN;
1785 dword |= XHCI_TRB_3_TRT_OUT;
1788 td->td_trb[0].dwTrb3 = htole32(dword);
1790 xhci_dump_trb(&td->td_trb[x]);
1798 /* fill out buffer pointers */
1801 memset(&buf_res, 0, sizeof(buf_res));
1803 usbd_get_page(temp->pc, temp->offset +
1804 buf_offset, &buf_res);
1806 /* get length to end of page */
1807 if (buf_res.length > average)
1808 buf_res.length = average;
1810 /* check for maximum length */
1811 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1812 buf_res.length = XHCI_TD_PAGE_SIZE;
1814 npkt_off += buf_res.length;
1818 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1819 temp->max_packet_size;
1826 /* fill out TRB's */
1827 td->td_trb[x].qwTrb0 =
1828 htole64((uint64_t)buf_res.physaddr);
1831 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1832 XHCI_TRB_2_TDSZ_SET(npkt) |
1833 XHCI_TRB_2_IRQ_SET(0);
1835 td->td_trb[x].dwTrb2 = htole32(dword);
1837 switch (temp->trb_type) {
1838 case XHCI_TRB_TYPE_ISOCH:
1839 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1840 XHCI_TRB_3_TBC_SET(temp->tbc) |
1841 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1842 if (td != td_first) {
1843 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1844 } else if (temp->do_isoc_sync != 0) {
1845 temp->do_isoc_sync = 0;
1846 /* wait until "isoc_frame" */
1847 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1848 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1850 /* start data transfer at next interval */
1851 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1852 XHCI_TRB_3_ISO_SIA_BIT;
1854 if (temp->direction == UE_DIR_IN)
1855 dword |= XHCI_TRB_3_ISP_BIT;
1857 case XHCI_TRB_TYPE_DATA_STAGE:
1858 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1859 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1860 if (temp->direction == UE_DIR_IN)
1861 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1863 * Section 3.2.9 in the XHCI
1864 * specification about control
1865 * transfers says that we should use a
1866 * normal-TRB if there are more TRBs
1867 * extending the data-stage
1868 * TRB. Update the "trb_type".
1870 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1872 case XHCI_TRB_TYPE_STATUS_STAGE:
1873 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1874 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1875 if (temp->direction == UE_DIR_IN)
1876 dword |= XHCI_TRB_3_DIR_IN;
1878 default: /* XHCI_TRB_TYPE_NORMAL */
1879 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1880 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1881 if (temp->direction == UE_DIR_IN)
1882 dword |= XHCI_TRB_3_ISP_BIT;
1885 td->td_trb[x].dwTrb3 = htole32(dword);
1887 average -= buf_res.length;
1888 buf_offset += buf_res.length;
1890 xhci_dump_trb(&td->td_trb[x]);
1894 } while (average != 0);
1896 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1898 /* store number of data TRB's */
1902 DPRINTF("NTRB=%u\n", x);
1904 /* fill out link TRB */
1906 if (td_next != NULL) {
1907 /* link the current TD with the next one */
1908 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1909 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1911 /* this field will get updated later */
1912 DPRINTF("NOLINK\n");
1915 dword = XHCI_TRB_2_IRQ_SET(0);
1917 td->td_trb[x].dwTrb2 = htole32(dword);
1919 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1920 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1922 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1923 * frame only receives a single short packet event
1924 * by setting the CHAIN bit in the LINK field. In
1925 * addition some XHCI controllers have problems
1926 * sending a ZLP unless the CHAIN-BIT is set in
1929 XHCI_TRB_3_CHAIN_BIT;
1931 td->td_trb[x].dwTrb3 = htole32(dword);
1933 td->alt_next = td_alt_next;
1935 xhci_dump_trb(&td->td_trb[x]);
1937 usb_pc_cpu_flush(td->page_cache);
1943 /* set up alt next pointer, if any */
1944 if (temp->last_frame) {
1947 /* we use this field internally */
1948 td_alt_next = td_next;
1952 temp->shortpkt = shortpkt_old;
1953 temp->len = len_old;
1958 * Remove cycle bit from the first TRB if we are
1961 if (temp->step_td != 0) {
1962 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1963 usb_pc_cpu_flush(td_first->page_cache);
1966 /* clear TD SIZE to zero, hence this is the last TRB */
1967 /* remove chain bit because this is the last data TRB in the chain */
1968 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1969 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1970 /* remove CHAIN-BIT from last LINK TRB */
1971 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1973 usb_pc_cpu_flush(td->page_cache);
1976 temp->td_next = td_next;
1980 xhci_setup_generic_chain(struct usb_xfer *xfer)
1982 struct xhci_std_temp temp;
1988 temp.do_isoc_sync = 0;
1992 temp.average = xfer->max_hc_frame_size;
1993 temp.max_packet_size = xfer->max_packet_size;
1994 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1996 temp.last_frame = 0;
1998 temp.multishort = xfer->flags_int.isochronous_xfr ||
1999 xfer->flags_int.control_xfr ||
2000 xfer->flags_int.short_frames_ok;
2002 /* toggle the DMA set we are using */
2003 xfer->flags_int.curr_dma_set ^= 1;
2005 /* get next DMA set */
2006 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2011 xfer->td_transfer_first = td;
2012 xfer->td_transfer_cache = td;
2014 if (xfer->flags_int.isochronous_xfr) {
2017 /* compute multiplier for ISOCHRONOUS transfers */
2018 mult = xfer->endpoint->ecomp ?
2019 (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
2020 /* check for USB 2.0 multiplier */
2022 mult = (xfer->endpoint->edesc->
2023 wMaxPacketSize[1] >> 3) & 3;
2031 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2033 DPRINTF("MFINDEX=0x%08x\n", x);
2035 switch (usbd_get_speed(xfer->xroot->udev)) {
2036 case USB_SPEED_FULL:
2038 temp.isoc_delta = 8; /* 1ms */
2039 x += temp.isoc_delta - 1;
2040 x &= ~(temp.isoc_delta - 1);
2043 shift = usbd_xfer_get_fps_shift(xfer);
2044 temp.isoc_delta = 1U << shift;
2045 x += temp.isoc_delta - 1;
2046 x &= ~(temp.isoc_delta - 1);
2047 /* simple frame load balancing */
2048 x += xfer->endpoint->usb_uframe;
2052 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2054 if ((xfer->endpoint->is_synced == 0) ||
2055 (y < (xfer->nframes << shift)) ||
2056 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2058 * If there is data underflow or the pipe
2059 * queue is empty we schedule the transfer a
2060 * few frames ahead of the current frame
2061 * position. Else two isochronous transfers
2064 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2065 xfer->endpoint->is_synced = 1;
2066 temp.do_isoc_sync = 1;
2068 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2071 /* compute isochronous completion time */
2073 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2075 xfer->isoc_time_complete =
2076 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2077 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2080 temp.isoc_frame = xfer->endpoint->isoc_next;
2081 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2083 xfer->endpoint->isoc_next += xfer->nframes << shift;
2085 } else if (xfer->flags_int.control_xfr) {
2087 /* check if we should prepend a setup message */
2089 if (xfer->flags_int.control_hdr) {
2091 temp.len = xfer->frlengths[0];
2092 temp.pc = xfer->frbuffers + 0;
2093 temp.shortpkt = temp.len ? 1 : 0;
2094 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2097 /* check for last frame */
2098 if (xfer->nframes == 1) {
2099 /* no STATUS stage yet, SETUP is last */
2100 if (xfer->flags_int.control_act)
2101 temp.last_frame = 1;
2104 xhci_setup_generic_chain_sub(&temp);
2108 temp.isoc_delta = 0;
2109 temp.isoc_frame = 0;
2110 temp.trb_type = xfer->flags_int.control_did_data ?
2111 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2115 temp.isoc_delta = 0;
2116 temp.isoc_frame = 0;
2117 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2120 if (x != xfer->nframes) {
2121 /* set up page_cache pointer */
2122 temp.pc = xfer->frbuffers + x;
2123 /* set endpoint direction */
2124 temp.direction = UE_GET_DIR(xfer->endpointno);
2127 while (x != xfer->nframes) {
2129 /* DATA0 / DATA1 message */
2131 temp.len = xfer->frlengths[x];
2132 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2133 x != 0 && temp.multishort == 0);
2137 if (x == xfer->nframes) {
2138 if (xfer->flags_int.control_xfr) {
2139 /* no STATUS stage yet, DATA is last */
2140 if (xfer->flags_int.control_act)
2141 temp.last_frame = 1;
2143 temp.last_frame = 1;
2146 if (temp.len == 0) {
2148 /* make sure that we send an USB packet */
2153 temp.tlbpc = mult - 1;
2155 } else if (xfer->flags_int.isochronous_xfr) {
2160 * Isochronous transfers don't have short
2161 * packet termination:
2166 /* isochronous transfers have a transfer limit */
2168 if (temp.len > xfer->max_frame_size)
2169 temp.len = xfer->max_frame_size;
2171 /* compute TD packet count */
2172 tdpc = (temp.len + xfer->max_packet_size - 1) /
2173 xfer->max_packet_size;
2175 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2176 temp.tlbpc = (tdpc % mult);
2178 if (temp.tlbpc == 0)
2179 temp.tlbpc = mult - 1;
2184 /* regular data transfer */
2186 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2189 xhci_setup_generic_chain_sub(&temp);
2191 if (xfer->flags_int.isochronous_xfr) {
2192 temp.offset += xfer->frlengths[x - 1];
2193 temp.isoc_frame += temp.isoc_delta;
2195 /* get next Page Cache pointer */
2196 temp.pc = xfer->frbuffers + x;
2200 /* check if we should append a status stage */
2202 if (xfer->flags_int.control_xfr &&
2203 !xfer->flags_int.control_act) {
2206 * Send a DATA1 message and invert the current
2207 * endpoint direction.
2209 temp.step_td = (xfer->nframes != 0);
2210 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2214 temp.last_frame = 1;
2215 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2217 xhci_setup_generic_chain_sub(&temp);
2222 /* must have at least one frame! */
2224 xfer->td_transfer_last = td;
2226 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2230 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2232 struct usb_page_search buf_res;
2233 struct xhci_dev_ctx_addr *pdctxa;
2235 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2237 pdctxa = buf_res.buffer;
2239 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2241 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2243 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2247 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2249 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2250 struct usb_page_search buf_inp;
2251 struct xhci_input_dev_ctx *pinp;
2256 index = udev->controller_slot_id;
2258 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2260 pinp = buf_inp.buffer;
2263 mask &= XHCI_INCTX_NON_CTRL_MASK;
2264 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2265 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2268 * Some hardware requires that we drop the endpoint
2269 * context before adding it again:
2271 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2272 mask & XHCI_INCTX_NON_CTRL_MASK);
2274 /* Add new endpoint context */
2275 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2277 /* find most significant set bit */
2278 for (x = 31; x != 1; x--) {
2279 if (mask & (1 << x))
2286 /* figure out the maximum number of contexts */
2287 if (x > sc->sc_hw.devs[index].context_num)
2288 sc->sc_hw.devs[index].context_num = x;
2290 x = sc->sc_hw.devs[index].context_num;
2292 /* update number of contexts */
2293 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2294 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2295 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2296 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2298 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2303 xhci_configure_endpoint(struct usb_device *udev,
2304 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2305 uint16_t interval, uint8_t max_packet_count,
2306 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2307 uint16_t max_frame_size)
2309 struct usb_page_search buf_inp;
2310 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2311 struct xhci_input_dev_ctx *pinp;
2312 uint64_t ring_addr = pepext->physaddr;
2318 index = udev->controller_slot_id;
2320 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2322 pinp = buf_inp.buffer;
2324 epno = edesc->bEndpointAddress;
2325 type = edesc->bmAttributes & UE_XFERTYPE;
2327 if (type == UE_CONTROL)
2330 epno = XHCI_EPNO2EPID(epno);
2333 return (USB_ERR_NO_PIPE); /* invalid */
2335 if (max_packet_count == 0)
2336 return (USB_ERR_BAD_BUFSIZE);
2341 return (USB_ERR_BAD_BUFSIZE);
2343 /* store bMaxPacketSize for control endpoints */
2344 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2345 usb_pc_cpu_flush(pepext->page_cache);
2347 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2348 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2349 XHCI_EPCTX_0_LSA_SET(0);
2351 switch (udev->speed) {
2352 case USB_SPEED_FULL:
2365 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2367 case UE_ISOCHRONOUS:
2368 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2370 switch (udev->speed) {
2371 case USB_SPEED_SUPER:
2374 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2375 max_packet_count /= mult;
2385 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2388 XHCI_EPCTX_1_HID_SET(0) |
2389 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2390 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2393 * Always enable the "three strikes and you are gone" feature
2394 * except for ISOCHRONOUS endpoints. This is suggested by
2395 * section 4.3.3 in the XHCI specification about device slot
2398 if (type != UE_ISOCHRONOUS)
2399 temp |= XHCI_EPCTX_1_CERR_SET(3);
2403 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2405 case UE_ISOCHRONOUS:
2406 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2409 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2412 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2416 /* check for IN direction */
2418 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2420 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2422 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2424 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2426 switch (edesc->bmAttributes & UE_XFERTYPE) {
2428 case UE_ISOCHRONOUS:
2429 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2430 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2434 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2437 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2441 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2444 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2446 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2448 return (0); /* success */
2452 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2454 struct xhci_endpoint_ext *pepext;
2455 struct usb_endpoint_ss_comp_descriptor *ecomp;
2457 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2458 xfer->endpoint->edesc);
2460 ecomp = xfer->endpoint->ecomp;
2462 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */
2463 usb_pc_cpu_flush(pepext->page_cache);
2465 return (xhci_configure_endpoint(xfer->xroot->udev,
2466 xfer->endpoint->edesc, pepext,
2467 xfer->interval, xfer->max_packet_count,
2468 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2469 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2470 xfer->max_frame_size));
2474 xhci_configure_device(struct usb_device *udev)
2476 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2477 struct usb_page_search buf_inp;
2478 struct usb_page_cache *pcinp;
2479 struct xhci_input_dev_ctx *pinp;
2480 struct usb_device *hubdev;
2488 index = udev->controller_slot_id;
2490 DPRINTF("index=%u\n", index);
2492 pcinp = &sc->sc_hw.devs[index].input_pc;
2494 usbd_get_page(pcinp, 0, &buf_inp);
2496 pinp = buf_inp.buffer;
2501 /* figure out route string and root HUB port number */
2503 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2505 if (hubdev->parent_hub == NULL)
2508 depth = hubdev->parent_hub->depth;
2511 * NOTE: HS/FS/LS devices and the SS root HUB can have
2512 * more than 15 ports
2515 rh_port = hubdev->port_no;
2524 route |= rh_port << (4 * (depth - 1));
2527 DPRINTF("Route=0x%08x\n", route);
2529 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2530 XHCI_SCTX_0_CTX_NUM_SET(
2531 sc->sc_hw.devs[index].context_num + 1);
2533 switch (udev->speed) {
2535 temp |= XHCI_SCTX_0_SPEED_SET(2);
2536 if (udev->parent_hs_hub != NULL &&
2537 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2539 DPRINTF("Device inherits MTT\n");
2540 temp |= XHCI_SCTX_0_MTT_SET(1);
2543 case USB_SPEED_HIGH:
2544 temp |= XHCI_SCTX_0_SPEED_SET(3);
2545 if (sc->sc_hw.devs[index].nports != 0 &&
2546 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2547 DPRINTF("HUB supports MTT\n");
2548 temp |= XHCI_SCTX_0_MTT_SET(1);
2551 case USB_SPEED_FULL:
2552 temp |= XHCI_SCTX_0_SPEED_SET(1);
2553 if (udev->parent_hs_hub != NULL &&
2554 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2556 DPRINTF("Device inherits MTT\n");
2557 temp |= XHCI_SCTX_0_MTT_SET(1);
2561 temp |= XHCI_SCTX_0_SPEED_SET(4);
2565 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2566 (udev->speed == USB_SPEED_SUPER ||
2567 udev->speed == USB_SPEED_HIGH);
2570 temp |= XHCI_SCTX_0_HUB_SET(1);
2572 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2574 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2577 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2578 sc->sc_hw.devs[index].nports);
2581 switch (udev->speed) {
2582 case USB_SPEED_SUPER:
2583 switch (sc->sc_hw.devs[index].state) {
2584 case XHCI_ST_ADDRESSED:
2585 case XHCI_ST_CONFIGURED:
2586 /* enable power save */
2587 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2590 /* disable power save */
2598 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2600 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2603 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2604 sc->sc_hw.devs[index].tt);
2607 hubdev = udev->parent_hs_hub;
2609 /* check if we should activate the transaction translator */
2610 switch (udev->speed) {
2611 case USB_SPEED_FULL:
2613 if (hubdev != NULL) {
2614 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2615 hubdev->controller_slot_id);
2616 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2624 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2627 * These fields should be initialized to zero, according to
2628 * XHCI section 6.2.2 - slot context:
2630 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2631 XHCI_SCTX_3_SLOT_STATE_SET(0);
2633 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2636 xhci_dump_device(sc, &pinp->ctx_slot);
2638 usb_pc_cpu_flush(pcinp);
2640 return (0); /* success */
2644 xhci_alloc_device_ext(struct usb_device *udev)
2646 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2647 struct usb_page_search buf_dev;
2648 struct usb_page_search buf_ep;
2649 struct xhci_trb *trb;
2650 struct usb_page_cache *pc;
2651 struct usb_page *pg;
2656 index = udev->controller_slot_id;
2658 pc = &sc->sc_hw.devs[index].device_pc;
2659 pg = &sc->sc_hw.devs[index].device_pg;
2661 /* need to initialize the page cache */
2662 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2664 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2665 (2 * sizeof(struct xhci_dev_ctx)) :
2666 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2669 usbd_get_page(pc, 0, &buf_dev);
2671 pc = &sc->sc_hw.devs[index].input_pc;
2672 pg = &sc->sc_hw.devs[index].input_pg;
2674 /* need to initialize the page cache */
2675 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2677 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2678 (2 * sizeof(struct xhci_input_dev_ctx)) :
2679 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2683 pc = &sc->sc_hw.devs[index].endpoint_pc;
2684 pg = &sc->sc_hw.devs[index].endpoint_pg;
2686 /* need to initialize the page cache */
2687 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2689 if (usb_pc_alloc_mem(pc, pg,
2690 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2694 /* initialise all endpoint LINK TRBs */
2696 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2698 /* lookup endpoint TRB ring */
2699 usbd_get_page(pc, (uintptr_t)&
2700 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2702 /* get TRB pointer */
2703 trb = buf_ep.buffer;
2704 trb += XHCI_MAX_TRANSFERS - 1;
2706 /* get TRB start address */
2707 addr = buf_ep.physaddr;
2709 /* create LINK TRB */
2710 trb->qwTrb0 = htole64(addr);
2711 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2712 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2713 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2716 usb_pc_cpu_flush(pc);
2718 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2723 xhci_free_device_ext(udev);
2725 return (USB_ERR_NOMEM);
2729 xhci_free_device_ext(struct usb_device *udev)
2731 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734 index = udev->controller_slot_id;
2735 xhci_set_slot_pointer(sc, index, 0);
2737 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2738 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2739 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2742 static struct xhci_endpoint_ext *
2743 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2745 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2746 struct xhci_endpoint_ext *pepext;
2747 struct usb_page_cache *pc;
2748 struct usb_page_search buf_ep;
2752 epno = edesc->bEndpointAddress;
2753 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2756 epno = XHCI_EPNO2EPID(epno);
2758 index = udev->controller_slot_id;
2760 pc = &sc->sc_hw.devs[index].endpoint_pc;
2762 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2764 pepext = &sc->sc_hw.devs[index].endp[epno];
2765 pepext->page_cache = pc;
2766 pepext->trb = buf_ep.buffer;
2767 pepext->physaddr = buf_ep.physaddr;
2773 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2775 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2779 epno = xfer->endpointno;
2780 if (xfer->flags_int.control_xfr)
2783 epno = XHCI_EPNO2EPID(epno);
2784 index = xfer->xroot->udev->controller_slot_id;
2786 if (xfer->xroot->udev->flags.self_suspended == 0) {
2787 XWRITE4(sc, door, XHCI_DOORBELL(index),
2788 epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2793 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2795 struct xhci_endpoint_ext *pepext;
2797 if (xfer->flags_int.bandwidth_reclaimed) {
2798 xfer->flags_int.bandwidth_reclaimed = 0;
2800 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2801 xfer->endpoint->edesc);
2805 pepext->xfer[xfer->qh_pos] = NULL;
2807 if (error && pepext->trb_running != 0) {
2808 pepext->trb_halted = 1;
2809 pepext->trb_running = 0;
2815 xhci_transfer_insert(struct usb_xfer *xfer)
2817 struct xhci_td *td_first;
2818 struct xhci_td *td_last;
2819 struct xhci_trb *trb_link;
2820 struct xhci_endpoint_ext *pepext;
2828 /* check if already inserted */
2829 if (xfer->flags_int.bandwidth_reclaimed) {
2830 DPRINTFN(8, "Already in schedule\n");
2834 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2835 xfer->endpoint->edesc);
2837 td_first = xfer->td_transfer_first;
2838 td_last = xfer->td_transfer_last;
2839 addr = pepext->physaddr;
2841 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2844 /* single buffered */
2848 /* multi buffered */
2849 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2853 if (pepext->trb_used >= trb_limit) {
2854 DPRINTFN(8, "Too many TDs queued.\n");
2855 return (USB_ERR_NOMEM);
2858 /* check if bMaxPacketSize changed */
2859 if (xfer->flags_int.control_xfr != 0 &&
2860 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2862 DPRINTFN(8, "Reconfigure control endpoint\n");
2864 /* force driver to reconfigure endpoint */
2865 pepext->trb_halted = 1;
2866 pepext->trb_running = 0;
2869 /* check for stopped condition, after putting transfer on interrupt queue */
2870 if (pepext->trb_running == 0) {
2871 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2873 DPRINTFN(8, "Not running\n");
2875 /* start configuration */
2876 (void)usb_proc_msignal(&sc->sc_config_proc,
2877 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2883 /* get current TRB index */
2884 i = pepext->trb_index;
2886 /* get next TRB index */
2889 /* the last entry of the ring is a hardcoded link TRB */
2890 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2893 /* compute terminating return address */
2894 addr += inext * sizeof(struct xhci_trb);
2896 /* compute link TRB pointer */
2897 trb_link = td_last->td_trb + td_last->ntrb;
2899 /* update next pointer of last link TRB */
2900 trb_link->qwTrb0 = htole64(addr);
2901 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2902 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2903 XHCI_TRB_3_CYCLE_BIT |
2904 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2907 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2909 usb_pc_cpu_flush(td_last->page_cache);
2911 /* write ahead chain end marker */
2913 pepext->trb[inext].qwTrb0 = 0;
2914 pepext->trb[inext].dwTrb2 = 0;
2915 pepext->trb[inext].dwTrb3 = 0;
2917 /* update next pointer of link TRB */
2919 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2920 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2923 xhci_dump_trb(&pepext->trb[i]);
2925 usb_pc_cpu_flush(pepext->page_cache);
2927 /* toggle cycle bit which activates the transfer chain */
2929 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2930 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2932 usb_pc_cpu_flush(pepext->page_cache);
2934 DPRINTF("qh_pos = %u\n", i);
2936 pepext->xfer[i] = xfer;
2940 xfer->flags_int.bandwidth_reclaimed = 1;
2942 pepext->trb_index = inext;
2944 xhci_endpoint_doorbell(xfer);
2950 xhci_root_intr(struct xhci_softc *sc)
2954 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2956 /* clear any old interrupt data */
2957 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2959 for (i = 1; i <= sc->sc_noport; i++) {
2960 /* pick out CHANGE bits from the status register */
2961 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2962 XHCI_PS_CSC | XHCI_PS_PEC |
2963 XHCI_PS_OCC | XHCI_PS_WRC |
2964 XHCI_PS_PRC | XHCI_PS_PLC |
2966 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2967 DPRINTF("port %d changed\n", i);
2970 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2971 sizeof(sc->sc_hub_idata));
2974 /*------------------------------------------------------------------------*
2975 * xhci_device_done - XHCI done handler
2977 * NOTE: This function can be called two times in a row on
2978 * the same USB transfer. From close and from interrupt.
2979 *------------------------------------------------------------------------*/
2981 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2983 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2984 xfer, xfer->endpoint, error);
2986 /* remove transfer from HW queue */
2987 xhci_transfer_remove(xfer, error);
2989 /* dequeue transfer and start next transfer */
2990 usbd_transfer_done(xfer, error);
2993 /*------------------------------------------------------------------------*
2994 * XHCI data transfer support (generic type)
2995 *------------------------------------------------------------------------*/
2997 xhci_device_generic_open(struct usb_xfer *xfer)
2999 if (xfer->flags_int.isochronous_xfr) {
3000 switch (xfer->xroot->udev->speed) {
3001 case USB_SPEED_FULL:
3004 usb_hs_bandwidth_alloc(xfer);
3011 xhci_device_generic_close(struct usb_xfer *xfer)
3015 xhci_device_done(xfer, USB_ERR_CANCELLED);
3017 if (xfer->flags_int.isochronous_xfr) {
3018 switch (xfer->xroot->udev->speed) {
3019 case USB_SPEED_FULL:
3022 usb_hs_bandwidth_free(xfer);
3029 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3030 struct usb_xfer *enter_xfer)
3032 struct usb_xfer *xfer;
3034 /* check if there is a current transfer */
3035 xfer = ep->endpoint_q.curr;
3040 * Check if the current transfer is started and then pickup
3041 * the next one, if any. Else wait for next start event due to
3042 * block on failure feature.
3044 if (!xfer->flags_int.bandwidth_reclaimed)
3047 xfer = TAILQ_FIRST(&ep->endpoint_q.head);
3050 * In case of enter we have to consider that the
3051 * transfer is queued by the USB core after the enter
3060 /* try to multi buffer */
3061 xhci_transfer_insert(xfer);
3065 xhci_device_generic_enter(struct usb_xfer *xfer)
3069 /* set up TD's and QH */
3070 xhci_setup_generic_chain(xfer);
3072 xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3076 xhci_device_generic_start(struct usb_xfer *xfer)
3080 /* try to insert xfer on HW queue */
3081 xhci_transfer_insert(xfer);
3083 /* try to multi buffer */
3084 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3086 /* add transfer last on interrupt queue */
3087 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3089 /* start timeout, if any */
3090 if (xfer->timeout != 0)
3091 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3094 struct usb_pipe_methods xhci_device_generic_methods =
3096 .open = xhci_device_generic_open,
3097 .close = xhci_device_generic_close,
3098 .enter = xhci_device_generic_enter,
3099 .start = xhci_device_generic_start,
3102 /*------------------------------------------------------------------------*
3103 * xhci root HUB support
3104 *------------------------------------------------------------------------*
3105 * Simulate a hardware HUB by handling all the necessary requests.
3106 *------------------------------------------------------------------------*/
3108 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3111 struct usb_device_descriptor xhci_devd =
3113 .bLength = sizeof(xhci_devd),
3114 .bDescriptorType = UDESC_DEVICE, /* type */
3115 HSETW(.bcdUSB, 0x0300), /* USB version */
3116 .bDeviceClass = UDCLASS_HUB, /* class */
3117 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3118 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3119 .bMaxPacketSize = 9, /* max packet size */
3120 HSETW(.idVendor, 0x0000), /* vendor */
3121 HSETW(.idProduct, 0x0000), /* product */
3122 HSETW(.bcdDevice, 0x0100), /* device version */
3126 .bNumConfigurations = 1, /* # of configurations */
3130 struct xhci_bos_desc xhci_bosd = {
3132 .bLength = sizeof(xhci_bosd.bosd),
3133 .bDescriptorType = UDESC_BOS,
3134 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3135 .bNumDeviceCaps = 3,
3138 .bLength = sizeof(xhci_bosd.usb2extd),
3139 .bDescriptorType = 1,
3140 .bDevCapabilityType = 2,
3141 .bmAttributes[0] = 2,
3144 .bLength = sizeof(xhci_bosd.usbdcd),
3145 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3146 .bDevCapabilityType = 3,
3147 .bmAttributes = 0, /* XXX */
3148 HSETW(.wSpeedsSupported, 0x000C),
3149 .bFunctionalitySupport = 8,
3150 .bU1DevExitLat = 255, /* dummy - not used */
3151 .wU2DevExitLat = { 0x00, 0x08 },
3154 .bLength = sizeof(xhci_bosd.cidd),
3155 .bDescriptorType = 1,
3156 .bDevCapabilityType = 4,
3158 .bContainerID = 0, /* XXX */
3163 struct xhci_config_desc xhci_confd = {
3165 .bLength = sizeof(xhci_confd.confd),
3166 .bDescriptorType = UDESC_CONFIG,
3167 .wTotalLength[0] = sizeof(xhci_confd),
3169 .bConfigurationValue = 1,
3170 .iConfiguration = 0,
3171 .bmAttributes = UC_SELF_POWERED,
3172 .bMaxPower = 0 /* max power */
3175 .bLength = sizeof(xhci_confd.ifcd),
3176 .bDescriptorType = UDESC_INTERFACE,
3178 .bInterfaceClass = UICLASS_HUB,
3179 .bInterfaceSubClass = UISUBCLASS_HUB,
3180 .bInterfaceProtocol = 0,
3183 .bLength = sizeof(xhci_confd.endpd),
3184 .bDescriptorType = UDESC_ENDPOINT,
3185 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3186 .bmAttributes = UE_INTERRUPT,
3187 .wMaxPacketSize[0] = 2, /* max 15 ports */
3191 .bLength = sizeof(xhci_confd.endpcd),
3192 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3199 struct usb_hub_ss_descriptor xhci_hubd = {
3200 .bLength = sizeof(xhci_hubd),
3201 .bDescriptorType = UDESC_SS_HUB,
3205 xhci_roothub_exec(struct usb_device *udev,
3206 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3208 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3209 const char *str_ptr;
3220 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3223 ptr = (const void *)&sc->sc_hub_desc;
3227 value = UGETW(req->wValue);
3228 index = UGETW(req->wIndex);
3230 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3231 "wValue=0x%04x wIndex=0x%04x\n",
3232 req->bmRequestType, req->bRequest,
3233 UGETW(req->wLength), value, index);
3235 #define C(x,y) ((x) | ((y) << 8))
3236 switch (C(req->bRequest, req->bmRequestType)) {
3237 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3238 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3239 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3241 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3242 * for the integrated root hub.
3245 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3247 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3249 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3250 switch (value >> 8) {
3252 if ((value & 0xff) != 0) {
3253 err = USB_ERR_IOERROR;
3256 len = sizeof(xhci_devd);
3257 ptr = (const void *)&xhci_devd;
3261 if ((value & 0xff) != 0) {
3262 err = USB_ERR_IOERROR;
3265 len = sizeof(xhci_bosd);
3266 ptr = (const void *)&xhci_bosd;
3270 if ((value & 0xff) != 0) {
3271 err = USB_ERR_IOERROR;
3274 len = sizeof(xhci_confd);
3275 ptr = (const void *)&xhci_confd;
3279 switch (value & 0xff) {
3280 case 0: /* Language table */
3284 case 1: /* Vendor */
3285 str_ptr = sc->sc_vendor;
3288 case 2: /* Product */
3289 str_ptr = "XHCI root HUB";
3297 len = usb_make_str_desc(
3298 sc->sc_hub_desc.temp,
3299 sizeof(sc->sc_hub_desc.temp),
3304 err = USB_ERR_IOERROR;
3308 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3310 sc->sc_hub_desc.temp[0] = 0;
3312 case C(UR_GET_STATUS, UT_READ_DEVICE):
3314 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3316 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3317 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3319 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3321 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3322 if (value >= XHCI_MAX_DEVICES) {
3323 err = USB_ERR_IOERROR;
3327 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3328 if (value != 0 && value != 1) {
3329 err = USB_ERR_IOERROR;
3332 sc->sc_conf = value;
3334 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3336 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3337 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3338 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3339 err = USB_ERR_IOERROR;
3341 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3343 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3346 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3348 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3349 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3352 (index > sc->sc_noport)) {
3353 err = USB_ERR_IOERROR;
3356 port = XHCI_PORTSC(index);
3358 v = XREAD4(sc, oper, port);
3359 i = XHCI_PS_PLS_GET(v);
3360 v &= ~XHCI_PS_CLEAR;
3363 case UHF_C_BH_PORT_RESET:
3364 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3366 case UHF_C_PORT_CONFIG_ERROR:
3367 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3369 case UHF_C_PORT_SUSPEND:
3370 case UHF_C_PORT_LINK_STATE:
3371 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3373 case UHF_C_PORT_CONNECTION:
3374 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3376 case UHF_C_PORT_ENABLE:
3377 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3379 case UHF_C_PORT_OVER_CURRENT:
3380 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3382 case UHF_C_PORT_RESET:
3383 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3385 case UHF_PORT_ENABLE:
3386 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3388 case UHF_PORT_POWER:
3389 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3391 case UHF_PORT_INDICATOR:
3392 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3394 case UHF_PORT_SUSPEND:
3398 XWRITE4(sc, oper, port, v |
3399 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3402 /* wait 20ms for resume sequence to complete */
3403 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3406 XWRITE4(sc, oper, port, v |
3407 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3410 err = USB_ERR_IOERROR;
3415 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3416 if ((value & 0xff) != 0) {
3417 err = USB_ERR_IOERROR;
3421 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3423 sc->sc_hub_desc.hubd = xhci_hubd;
3425 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3427 if (XHCI_HCS0_PPC(v))
3428 i = UHD_PWR_INDIVIDUAL;
3432 if (XHCI_HCS0_PIND(v))
3435 i |= UHD_OC_INDIVIDUAL;
3437 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3439 /* see XHCI section 5.4.9: */
3440 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3442 for (j = 1; j <= sc->sc_noport; j++) {
3444 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3445 if (v & XHCI_PS_DR) {
3446 sc->sc_hub_desc.hubd.
3447 DeviceRemovable[j / 8] |= 1U << (j % 8);
3450 len = sc->sc_hub_desc.hubd.bLength;
3453 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3455 memset(sc->sc_hub_desc.temp, 0, 16);
3458 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3459 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3462 (index > sc->sc_noport)) {
3463 err = USB_ERR_IOERROR;
3467 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3469 DPRINTFN(9, "port status=0x%08x\n", v);
3471 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3473 switch (XHCI_PS_SPEED_GET(v)) {
3475 i |= UPS_HIGH_SPEED;
3484 i |= UPS_OTHER_SPEED;
3488 if (v & XHCI_PS_CCS)
3489 i |= UPS_CURRENT_CONNECT_STATUS;
3490 if (v & XHCI_PS_PED)
3491 i |= UPS_PORT_ENABLED;
3492 if (v & XHCI_PS_OCA)
3493 i |= UPS_OVERCURRENT_INDICATOR;
3496 if (v & XHCI_PS_PP) {
3498 * The USB 3.0 RH is using the
3499 * USB 2.0's power bit
3501 i |= UPS_PORT_POWER;
3503 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3506 if (v & XHCI_PS_CSC)
3507 i |= UPS_C_CONNECT_STATUS;
3508 if (v & XHCI_PS_PEC)
3509 i |= UPS_C_PORT_ENABLED;
3510 if (v & XHCI_PS_OCC)
3511 i |= UPS_C_OVERCURRENT_INDICATOR;
3512 if (v & XHCI_PS_WRC)
3513 i |= UPS_C_BH_PORT_RESET;
3514 if (v & XHCI_PS_PRC)
3515 i |= UPS_C_PORT_RESET;
3516 if (v & XHCI_PS_PLC)
3517 i |= UPS_C_PORT_LINK_STATE;
3518 if (v & XHCI_PS_CEC)
3519 i |= UPS_C_PORT_CONFIG_ERROR;
3521 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3522 len = sizeof(sc->sc_hub_desc.ps);
3525 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3526 err = USB_ERR_IOERROR;
3529 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3532 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3538 (index > sc->sc_noport)) {
3539 err = USB_ERR_IOERROR;
3543 port = XHCI_PORTSC(index);
3544 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3547 case UHF_PORT_U1_TIMEOUT:
3548 if (XHCI_PS_SPEED_GET(v) != 4) {
3549 err = USB_ERR_IOERROR;
3552 port = XHCI_PORTPMSC(index);
3553 v = XREAD4(sc, oper, port);
3554 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3555 v |= XHCI_PM3_U1TO_SET(i);
3556 XWRITE4(sc, oper, port, v);
3558 case UHF_PORT_U2_TIMEOUT:
3559 if (XHCI_PS_SPEED_GET(v) != 4) {
3560 err = USB_ERR_IOERROR;
3563 port = XHCI_PORTPMSC(index);
3564 v = XREAD4(sc, oper, port);
3565 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3566 v |= XHCI_PM3_U2TO_SET(i);
3567 XWRITE4(sc, oper, port, v);
3569 case UHF_BH_PORT_RESET:
3570 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3572 case UHF_PORT_LINK_STATE:
3573 XWRITE4(sc, oper, port, v |
3574 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3575 /* 4ms settle time */
3576 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3578 case UHF_PORT_ENABLE:
3579 DPRINTFN(3, "set port enable %d\n", index);
3581 case UHF_PORT_SUSPEND:
3582 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3583 j = XHCI_PS_SPEED_GET(v);
3584 if ((j < 1) || (j > 3)) {
3585 /* non-supported speed */
3586 err = USB_ERR_IOERROR;
3589 XWRITE4(sc, oper, port, v |
3590 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3592 case UHF_PORT_RESET:
3593 DPRINTFN(6, "reset port %d\n", index);
3594 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3596 case UHF_PORT_POWER:
3597 DPRINTFN(3, "set port power %d\n", index);
3598 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3601 DPRINTFN(3, "set port test %d\n", index);
3603 case UHF_PORT_INDICATOR:
3604 DPRINTFN(3, "set port indicator %d\n", index);
3606 v &= ~XHCI_PS_PIC_SET(3);
3607 v |= XHCI_PS_PIC_SET(1);
3609 XWRITE4(sc, oper, port, v);
3612 err = USB_ERR_IOERROR;
3617 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3618 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3619 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3620 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3623 err = USB_ERR_IOERROR;
3633 xhci_xfer_setup(struct usb_setup_params *parm)
3635 struct usb_page_search page_info;
3636 struct usb_page_cache *pc;
3637 struct xhci_softc *sc;
3638 struct usb_xfer *xfer;
3643 sc = XHCI_BUS2SC(parm->udev->bus);
3644 xfer = parm->curr_xfer;
3647 * The proof for the "ntd" formula is illustrated like this:
3649 * +------------------------------------+
3653 * | | xxx | x | frm 0 |
3655 * | | xxx | xx | frm 1 |
3658 * +------------------------------------+
3660 * "xxx" means a completely full USB transfer descriptor
3662 * "x" and "xx" means a short USB packet
3664 * For the remainder of an USB transfer modulo
3665 * "max_data_length" we need two USB transfer descriptors.
3666 * One to transfer the remaining data and one to finalise with
3667 * a zero length packet in case the "force_short_xfer" flag is
3668 * set. We only need two USB transfer descriptors in the case
3669 * where the transfer length of the first one is a factor of
3670 * "max_frame_size". The rest of the needed USB transfer
3671 * descriptors is given by the buffer size divided by the
3672 * maximum data payload.
3674 parm->hc_max_packet_size = 0x400;
3675 parm->hc_max_packet_count = 16 * 3;
3676 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3678 xfer->flags_int.bdma_enable = 1;
3680 usbd_transfer_setup_sub(parm);
3682 if (xfer->flags_int.isochronous_xfr) {
3683 ntd = ((1 * xfer->nframes)
3684 + (xfer->max_data_length / xfer->max_hc_frame_size));
3685 } else if (xfer->flags_int.control_xfr) {
3686 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3687 + (xfer->max_data_length / xfer->max_hc_frame_size));
3689 ntd = ((2 * xfer->nframes)
3690 + (xfer->max_data_length / xfer->max_hc_frame_size));
3699 * Allocate queue heads and transfer descriptors
3703 if (usbd_transfer_setup_sub_malloc(
3704 parm, &pc, sizeof(struct xhci_td),
3705 XHCI_TD_ALIGN, ntd)) {
3706 parm->err = USB_ERR_NOMEM;
3710 for (n = 0; n != ntd; n++) {
3713 usbd_get_page(pc + n, 0, &page_info);
3715 td = page_info.buffer;
3718 td->td_self = page_info.physaddr;
3719 td->obj_next = last_obj;
3720 td->page_cache = pc + n;
3724 usb_pc_cpu_flush(pc + n);
3727 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3729 if (!xfer->flags_int.curr_dma_set) {
3730 xfer->flags_int.curr_dma_set = 1;
3736 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3738 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3739 struct usb_page_search buf_inp;
3740 struct usb_device *udev;
3741 struct xhci_endpoint_ext *pepext;
3742 struct usb_endpoint_descriptor *edesc;
3743 struct usb_page_cache *pcinp;
3748 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3749 xfer->endpoint->edesc);
3751 udev = xfer->xroot->udev;
3752 index = udev->controller_slot_id;
3754 pcinp = &sc->sc_hw.devs[index].input_pc;
3756 usbd_get_page(pcinp, 0, &buf_inp);
3758 edesc = xfer->endpoint->edesc;
3760 epno = edesc->bEndpointAddress;
3762 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3765 epno = XHCI_EPNO2EPID(epno);
3768 return (USB_ERR_NO_PIPE); /* invalid */
3772 /* configure endpoint */
3774 err = xhci_configure_endpoint_by_xfer(xfer);
3777 XHCI_CMD_UNLOCK(sc);
3782 * Get the endpoint into the stopped state according to the
3783 * endpoint context state diagram in the XHCI specification:
3786 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3789 DPRINTF("Could not stop endpoint %u\n", epno);
3791 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3794 DPRINTF("Could not reset endpoint %u\n", epno);
3796 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3797 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3800 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3803 * Get the endpoint into the running state according to the
3804 * endpoint context state diagram in the XHCI specification:
3807 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3809 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3812 DPRINTF("Could not configure endpoint %u\n", epno);
3814 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3817 DPRINTF("Could not configure endpoint %u\n", epno);
3819 XHCI_CMD_UNLOCK(sc);
3825 xhci_xfer_unsetup(struct usb_xfer *xfer)
3831 xhci_start_dma_delay(struct usb_xfer *xfer)
3833 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3835 /* put transfer on interrupt queue (again) */
3836 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3838 (void)usb_proc_msignal(&sc->sc_config_proc,
3839 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3843 xhci_configure_msg(struct usb_proc_msg *pm)
3845 struct xhci_softc *sc;
3846 struct xhci_endpoint_ext *pepext;
3847 struct usb_xfer *xfer;
3849 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3852 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3854 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3855 xfer->endpoint->edesc);
3857 if ((pepext->trb_halted != 0) ||
3858 (pepext->trb_running == 0)) {
3862 /* clear halted and running */
3863 pepext->trb_halted = 0;
3864 pepext->trb_running = 0;
3866 /* nuke remaining buffered transfers */
3868 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3870 * NOTE: We need to use the timeout
3871 * error code here else existing
3872 * isochronous clients can get
3875 if (pepext->xfer[i] != NULL) {
3876 xhci_device_done(pepext->xfer[i],
3882 * NOTE: The USB transfer cannot vanish in
3886 USB_BUS_UNLOCK(&sc->sc_bus);
3888 xhci_configure_reset_endpoint(xfer);
3890 USB_BUS_LOCK(&sc->sc_bus);
3892 /* check if halted is still cleared */
3893 if (pepext->trb_halted == 0) {
3894 pepext->trb_running = 1;
3895 pepext->trb_index = 0;
3900 if (xfer->flags_int.did_dma_delay) {
3902 /* remove transfer from interrupt queue (again) */
3903 usbd_transfer_dequeue(xfer);
3905 /* we are finally done */
3906 usb_dma_delay_done_cb(xfer);
3908 /* queue changed - restart */
3913 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3915 /* try to insert xfer on HW queue */
3916 xhci_transfer_insert(xfer);
3918 /* try to multi buffer */
3919 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3924 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3925 struct usb_endpoint *ep)
3927 struct xhci_endpoint_ext *pepext;
3929 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3930 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3932 if (udev->parent_hub == NULL) {
3933 /* root HUB has special endpoint handling */
3937 ep->methods = &xhci_device_generic_methods;
3939 pepext = xhci_get_endpoint_ext(udev, edesc);
3941 USB_BUS_LOCK(udev->bus);
3942 pepext->trb_halted = 1;
3943 pepext->trb_running = 0;
3944 USB_BUS_UNLOCK(udev->bus);
3948 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3954 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3956 struct xhci_endpoint_ext *pepext;
3960 if (udev->flags.usb_mode != USB_MODE_HOST) {
3964 if (udev->parent_hub == NULL) {
3965 /* root HUB has special endpoint handling */
3969 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3971 USB_BUS_LOCK(udev->bus);
3972 pepext->trb_halted = 1;
3973 pepext->trb_running = 0;
3974 USB_BUS_UNLOCK(udev->bus);
3978 xhci_device_init(struct usb_device *udev)
3980 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3984 /* no init for root HUB */
3985 if (udev->parent_hub == NULL)
3990 /* set invalid default */
3992 udev->controller_slot_id = sc->sc_noslot + 1;
3994 /* try to get a new slot ID from the XHCI */
3996 err = xhci_cmd_enable_slot(sc, &temp);
3999 XHCI_CMD_UNLOCK(sc);
4003 if (temp > sc->sc_noslot) {
4004 XHCI_CMD_UNLOCK(sc);
4005 return (USB_ERR_BAD_ADDRESS);
4008 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4009 DPRINTF("slot %u already allocated.\n", temp);
4010 XHCI_CMD_UNLOCK(sc);
4011 return (USB_ERR_BAD_ADDRESS);
4014 /* store slot ID for later reference */
4016 udev->controller_slot_id = temp;
4018 /* reset data structure */
4020 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4022 /* set mark slot allocated */
4024 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4026 err = xhci_alloc_device_ext(udev);
4028 XHCI_CMD_UNLOCK(sc);
4030 /* get device into default state */
4033 err = xhci_set_address(udev, NULL, 0);
4039 xhci_device_uninit(struct usb_device *udev)
4041 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4044 /* no init for root HUB */
4045 if (udev->parent_hub == NULL)
4050 index = udev->controller_slot_id;
4052 if (index <= sc->sc_noslot) {
4053 xhci_cmd_disable_slot(sc, index);
4054 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4056 /* free device extension */
4057 xhci_free_device_ext(udev);
4060 XHCI_CMD_UNLOCK(sc);
4064 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4067 * Wait until the hardware has finished any possible use of
4068 * the transfer descriptor(s)
4070 *pus = 2048; /* microseconds */
4074 xhci_device_resume(struct usb_device *udev)
4076 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4083 /* check for root HUB */
4084 if (udev->parent_hub == NULL)
4087 index = udev->controller_slot_id;
4091 /* blindly resume all endpoints */
4093 USB_BUS_LOCK(udev->bus);
4095 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4096 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4097 XWRITE4(sc, door, XHCI_DOORBELL(index),
4098 n | XHCI_DB_SID_SET(p));
4102 USB_BUS_UNLOCK(udev->bus);
4104 XHCI_CMD_UNLOCK(sc);
4108 xhci_device_suspend(struct usb_device *udev)
4110 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4117 /* check for root HUB */
4118 if (udev->parent_hub == NULL)
4121 index = udev->controller_slot_id;
4125 /* blindly suspend all endpoints */
4127 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4128 err = xhci_cmd_stop_ep(sc, 1, n, index);
4130 DPRINTF("Failed to suspend endpoint "
4131 "%u on slot %u (ignored).\n", n, index);
4135 XHCI_CMD_UNLOCK(sc);
4139 xhci_set_hw_power(struct usb_bus *bus)
4145 xhci_device_state_change(struct usb_device *udev)
4147 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4148 struct usb_page_search buf_inp;
4152 /* check for root HUB */
4153 if (udev->parent_hub == NULL)
4156 index = udev->controller_slot_id;
4160 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4161 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4162 &sc->sc_hw.devs[index].tt);
4164 sc->sc_hw.devs[index].nports = 0;
4169 switch (usb_get_device_state(udev)) {
4170 case USB_STATE_POWERED:
4171 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4174 /* set default state */
4175 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4177 /* reset number of contexts */
4178 sc->sc_hw.devs[index].context_num = 0;
4180 err = xhci_cmd_reset_dev(sc, index);
4183 DPRINTF("Device reset failed "
4184 "for slot %u.\n", index);
4188 case USB_STATE_ADDRESSED:
4189 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4192 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4194 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4197 DPRINTF("Failed to deconfigure "
4198 "slot %u.\n", index);
4202 case USB_STATE_CONFIGURED:
4203 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4206 /* set configured state */
4207 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4209 /* reset number of contexts */
4210 sc->sc_hw.devs[index].context_num = 0;
4212 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4214 xhci_configure_mask(udev, 3, 0);
4216 err = xhci_configure_device(udev);
4218 DPRINTF("Could not configure device "
4219 "at slot %u.\n", index);
4222 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4224 DPRINTF("Could not evaluate device "
4225 "context at slot %u.\n", index);
4232 XHCI_CMD_UNLOCK(sc);
4235 struct usb_bus_methods xhci_bus_methods = {
4236 .endpoint_init = xhci_ep_init,
4237 .endpoint_uninit = xhci_ep_uninit,
4238 .xfer_setup = xhci_xfer_setup,
4239 .xfer_unsetup = xhci_xfer_unsetup,
4240 .get_dma_delay = xhci_get_dma_delay,
4241 .device_init = xhci_device_init,
4242 .device_uninit = xhci_device_uninit,
4243 .device_resume = xhci_device_resume,
4244 .device_suspend = xhci_device_suspend,
4245 .set_hw_power = xhci_set_hw_power,
4246 .roothub_exec = xhci_roothub_exec,
4247 .xfer_poll = xhci_do_poll,
4248 .start_dma_delay = xhci_start_dma_delay,
4249 .set_address = xhci_set_address,
4250 .clear_stall = xhci_ep_clear_stall,
4251 .device_state_change = xhci_device_state_change,
4252 .set_hw_power_sleep = xhci_set_hw_power_sleep,