2 * Copyright (c) 1997, 1998, 1999, 2000-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
46 * Written by Bill Paul <wpaul@windriver.com>
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manaully
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
79 #include <sys/stdint.h>
80 #include <sys/stddef.h>
81 #include <sys/param.h>
82 #include <sys/queue.h>
83 #include <sys/types.h>
84 #include <sys/systm.h>
85 #include <sys/kernel.h>
87 #include <sys/module.h>
89 #include <sys/mutex.h>
90 #include <sys/condvar.h>
91 #include <sys/sysctl.h>
93 #include <sys/unistd.h>
94 #include <sys/callout.h>
95 #include <sys/malloc.h>
98 #include <dev/usb/usb.h>
99 #include <dev/usb/usbdi.h>
100 #include <dev/usb/usbdi_util.h>
103 #define USB_DEBUG_VAR axe_debug
104 #include <dev/usb/usb_debug.h>
105 #include <dev/usb/usb_process.h>
107 #include <dev/usb/net/usb_ethernet.h>
108 #include <dev/usb/net/if_axereg.h>
111 * AXE_178_MAX_FRAME_BURST
112 * max frame burst size for Ax88178 and Ax88772
117 * use the largest your system can handle without USB stalling.
119 * NB: 88772 parts appear to generate lots of input errors with
120 * a 2K rx buffer and 8K is only slightly faster than 4K on an
121 * EHCI port on a T42 so change at your own risk.
123 #define AXE_178_MAX_FRAME_BURST 1
126 static int axe_debug = 0;
128 SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
129 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
134 * Various supported device vendors/products.
136 static const STRUCT_USB_HOST_ID axe_devs[] = {
137 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
138 AXE_DEV(ABOCOM, UF200, 0),
139 AXE_DEV(ACERCM, EP1427X2, 0),
140 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
141 AXE_DEV(ASIX, AX88172, 0),
142 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
143 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
144 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
145 AXE_DEV(ATEN, UC210T, 0),
146 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
147 AXE_DEV(BILLIONTON, USB2AR, 0),
148 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
149 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
150 AXE_DEV(DLINK, DUBE100, 0),
151 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
152 AXE_DEV(GOODWAY, GWUSB2E, 0),
153 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
154 AXE_DEV(JVC, MP_PRX1, 0),
155 AXE_DEV(LINKSYS2, USB200M, 0),
156 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
157 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
158 AXE_DEV(MELCO, LUAU2KTX, 0),
159 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
160 AXE_DEV(NETGEAR, FA120, 0),
161 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
162 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
163 AXE_DEV(SITECOM, LN029, 0),
164 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
165 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
169 static device_probe_t axe_probe;
170 static device_attach_t axe_attach;
171 static device_detach_t axe_detach;
173 static usb_callback_t axe_bulk_read_callback;
174 static usb_callback_t axe_bulk_write_callback;
176 static miibus_readreg_t axe_miibus_readreg;
177 static miibus_writereg_t axe_miibus_writereg;
178 static miibus_statchg_t axe_miibus_statchg;
180 static uether_fn_t axe_attach_post;
181 static uether_fn_t axe_init;
182 static uether_fn_t axe_stop;
183 static uether_fn_t axe_start;
184 static uether_fn_t axe_tick;
185 static uether_fn_t axe_setmulti;
186 static uether_fn_t axe_setpromisc;
188 static int axe_ifmedia_upd(struct ifnet *);
189 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190 static int axe_cmd(struct axe_softc *, int, int, int, void *);
191 static void axe_ax88178_init(struct axe_softc *);
192 static void axe_ax88772_init(struct axe_softc *);
193 static void axe_ax88772a_init(struct axe_softc *);
194 static int axe_get_phyno(struct axe_softc *, int);
196 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
200 .endpoint = UE_ADDR_ANY,
201 .direction = UE_DIR_OUT,
203 .bufsize = 16 * MCLBYTES,
204 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
205 .callback = axe_bulk_write_callback,
206 .timeout = 10000, /* 10 seconds */
211 .endpoint = UE_ADDR_ANY,
212 .direction = UE_DIR_IN,
213 .bufsize = 16384, /* bytes */
214 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
215 .callback = axe_bulk_read_callback,
216 .timeout = 0, /* no timeout */
220 static device_method_t axe_methods[] = {
221 /* Device interface */
222 DEVMETHOD(device_probe, axe_probe),
223 DEVMETHOD(device_attach, axe_attach),
224 DEVMETHOD(device_detach, axe_detach),
227 DEVMETHOD(bus_print_child, bus_generic_print_child),
228 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
231 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
232 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
233 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
238 static driver_t axe_driver = {
240 .methods = axe_methods,
241 .size = sizeof(struct axe_softc),
244 static devclass_t axe_devclass;
246 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
247 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
248 MODULE_DEPEND(axe, uether, 1, 1, 1);
249 MODULE_DEPEND(axe, usb, 1, 1, 1);
250 MODULE_DEPEND(axe, ether, 1, 1, 1);
251 MODULE_DEPEND(axe, miibus, 1, 1, 1);
252 MODULE_VERSION(axe, 1);
254 static const struct usb_ether_methods axe_ue_methods = {
255 .ue_attach_post = axe_attach_post,
256 .ue_start = axe_start,
260 .ue_setmulti = axe_setmulti,
261 .ue_setpromisc = axe_setpromisc,
262 .ue_mii_upd = axe_ifmedia_upd,
263 .ue_mii_sts = axe_ifmedia_sts,
267 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
269 struct usb_device_request req;
272 AXE_LOCK_ASSERT(sc, MA_OWNED);
274 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
275 UT_WRITE_VENDOR_DEVICE :
276 UT_READ_VENDOR_DEVICE);
277 req.bRequest = AXE_CMD_CMD(cmd);
278 USETW(req.wValue, val);
279 USETW(req.wIndex, index);
280 USETW(req.wLength, AXE_CMD_LEN(cmd));
282 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
288 axe_miibus_readreg(device_t dev, int phy, int reg)
290 struct axe_softc *sc = device_get_softc(dev);
294 if (sc->sc_phyno != phy)
297 locked = mtx_owned(&sc->sc_mtx);
301 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
302 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
303 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
306 if (AXE_IS_772(sc) && reg == MII_BMSR) {
308 * BMSR of AX88772 indicates that it supports extended
309 * capability but the extended status register is
310 * revered for embedded ethernet PHY. So clear the
311 * extended capability bit of BMSR.
322 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
324 struct axe_softc *sc = device_get_softc(dev);
329 if (sc->sc_phyno != phy)
332 locked = mtx_owned(&sc->sc_mtx);
336 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
337 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
338 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
346 axe_miibus_statchg(device_t dev)
348 struct axe_softc *sc = device_get_softc(dev);
349 struct mii_data *mii = GET_MII(sc);
354 locked = mtx_owned(&sc->sc_mtx);
358 ifp = uether_getifp(&sc->sc_ue);
359 if (mii == NULL || ifp == NULL ||
360 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
363 sc->sc_flags &= ~AXE_FLAG_LINK;
364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
365 (IFM_ACTIVE | IFM_AVALID)) {
366 switch (IFM_SUBTYPE(mii->mii_media_active)) {
369 sc->sc_flags |= AXE_FLAG_LINK;
372 if ((sc->sc_flags & AXE_FLAG_178) == 0)
374 sc->sc_flags |= AXE_FLAG_LINK;
381 /* Lost link, do nothing. */
382 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
386 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
387 val |= AXE_MEDIA_FULL_DUPLEX;
388 if (AXE_IS_178_FAMILY(sc)) {
389 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
390 if ((sc->sc_flags & AXE_FLAG_178) != 0)
391 val |= AXE_178_MEDIA_ENCK;
392 switch (IFM_SUBTYPE(mii->mii_media_active)) {
394 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
397 val |= AXE_178_MEDIA_100TX;
400 /* doesn't need to be handled */
404 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
406 device_printf(dev, "media change failed, error %d\n", err);
416 axe_ifmedia_upd(struct ifnet *ifp)
418 struct axe_softc *sc = ifp->if_softc;
419 struct mii_data *mii = GET_MII(sc);
422 AXE_LOCK_ASSERT(sc, MA_OWNED);
424 if (mii->mii_instance) {
425 struct mii_softc *miisc;
427 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
428 mii_phy_reset(miisc);
430 error = mii_mediachg(mii);
435 * Report current media status.
438 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
440 struct axe_softc *sc = ifp->if_softc;
441 struct mii_data *mii = GET_MII(sc);
446 ifmr->ifm_active = mii->mii_media_active;
447 ifmr->ifm_status = mii->mii_media_status;
451 axe_setmulti(struct usb_ether *ue)
453 struct axe_softc *sc = uether_getsc(ue);
454 struct ifnet *ifp = uether_getifp(ue);
455 struct ifmultiaddr *ifma;
458 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
460 AXE_LOCK_ASSERT(sc, MA_OWNED);
462 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
463 rxmode = le16toh(rxmode);
465 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
466 rxmode |= AXE_RXCMD_ALLMULTI;
467 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
470 rxmode &= ~AXE_RXCMD_ALLMULTI;
473 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
475 if (ifma->ifma_addr->sa_family != AF_LINK)
477 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
478 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
479 hashtbl[h / 8] |= 1 << (h % 8);
481 if_maddr_runlock(ifp);
483 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
484 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
488 axe_get_phyno(struct axe_softc *sc, int sel)
492 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
493 case PHY_TYPE_100_HOME:
495 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
497 case PHY_TYPE_SPECIAL:
501 case PHY_TYPE_NON_SUP:
511 #define AXE_GPIO_WRITE(x, y) do { \
512 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
513 uether_pause(ue, (y)); \
517 axe_ax88178_init(struct axe_softc *sc)
519 struct usb_ether *ue;
520 int gpio0, ledmode, phymode;
521 uint16_t eeprom, val;
524 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
526 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
527 eeprom = le16toh(eeprom);
528 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
530 /* if EEPROM is invalid we have to use to GPIO0 */
531 if (eeprom == 0xffff) {
532 phymode = AXE_PHY_MODE_MARVELL;
536 phymode = eeprom & 0x7f;
537 gpio0 = (eeprom & 0x80) ? 0 : 1;
538 ledmode = eeprom >> 8;
542 device_printf(sc->sc_ue.ue_dev,
543 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
545 /* Program GPIOs depending on PHY hardware. */
547 case AXE_PHY_MODE_MARVELL:
549 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
551 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
553 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
554 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
557 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
558 AXE_GPIO1_EN, hz / 3);
560 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
561 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
564 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
565 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
566 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
567 AXE_GPIO2_EN, hz / 4);
568 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
569 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
573 case AXE_PHY_MODE_CICADA:
574 case AXE_PHY_MODE_CICADA_V2:
575 case AXE_PHY_MODE_CICADA_V2_ASIX:
577 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
578 AXE_GPIO0_EN, hz / 32);
580 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
581 AXE_GPIO1_EN, hz / 32);
583 case AXE_PHY_MODE_AGERE:
584 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
585 AXE_GPIO1_EN, hz / 32);
586 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
587 AXE_GPIO2_EN, hz / 32);
588 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
589 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
590 AXE_GPIO2_EN, hz / 32);
592 case AXE_PHY_MODE_REALTEK_8211CL:
593 case AXE_PHY_MODE_REALTEK_8211BN:
594 case AXE_PHY_MODE_REALTEK_8251CL:
595 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
596 AXE_GPIO1 | AXE_GPIO1_EN;
597 AXE_GPIO_WRITE(val, hz / 32);
598 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
599 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
600 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
601 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
602 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
604 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
606 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
608 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
610 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
615 /* Unknown PHY model or no need to program GPIOs. */
620 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
621 uether_pause(ue, hz / 4);
623 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
624 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
625 uether_pause(ue, hz / 4);
626 /* Enable MII/GMII/RGMII interface to work with external PHY. */
627 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
628 uether_pause(ue, hz / 4);
630 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
634 axe_ax88772_init(struct axe_softc *sc)
636 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
637 uether_pause(&sc->sc_ue, hz / 16);
639 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
640 /* ask for the embedded PHY */
641 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
642 uether_pause(&sc->sc_ue, hz / 64);
644 /* power down and reset state, pin reset state */
645 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
646 AXE_SW_RESET_CLEAR, NULL);
647 uether_pause(&sc->sc_ue, hz / 16);
649 /* power down/reset state, pin operating state */
650 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
651 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
652 uether_pause(&sc->sc_ue, hz / 4);
654 /* power up, reset */
655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
657 /* power up, operating */
658 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
659 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
661 /* ask for external PHY */
662 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
663 uether_pause(&sc->sc_ue, hz / 64);
665 /* power down internal PHY */
666 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
667 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
670 uether_pause(&sc->sc_ue, hz / 4);
671 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
675 axe_ax88772a_init(struct axe_softc *sc)
677 struct usb_ether *ue;
681 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
682 eeprom = le16toh(eeprom);
684 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
685 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
686 /* Manually select internal(embedded) PHY - MAC mode. */
687 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
688 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
690 uether_pause(&sc->sc_ue, hz / 32);
693 * Manually select external PHY - MAC mode.
694 * Reverse MII/RMII is for AX88772A PHY mode.
696 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
697 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
698 uether_pause(&sc->sc_ue, hz / 32);
700 /* Take PHY out of power down. */
701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
702 AXE_SW_RESET_IPRL, NULL);
703 uether_pause(&sc->sc_ue, hz / 4);
704 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
705 uether_pause(&sc->sc_ue, hz);
706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
707 uether_pause(&sc->sc_ue, hz / 32);
708 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
709 uether_pause(&sc->sc_ue, hz / 32);
710 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
713 #undef AXE_GPIO_WRITE
716 axe_reset(struct axe_softc *sc)
718 struct usb_config_descriptor *cd;
721 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
723 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
724 cd->bConfigurationValue);
726 DPRINTF("reset failed (ignored)\n");
728 /* Wait a little while for the chip to get its brains in order. */
729 uether_pause(&sc->sc_ue, hz / 100);
731 /* Reinitialize controller to achieve full reset. */
732 if (sc->sc_flags & AXE_FLAG_178)
733 axe_ax88178_init(sc);
734 else if (sc->sc_flags & AXE_FLAG_772)
735 axe_ax88772_init(sc);
736 else if (sc->sc_flags & AXE_FLAG_772A)
737 axe_ax88772a_init(sc);
741 axe_attach_post(struct usb_ether *ue)
743 struct axe_softc *sc = uether_getsc(ue);
746 * Load PHY indexes first. Needed by axe_xxx_init().
748 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
750 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
751 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
752 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
753 if (sc->sc_phyno == -1)
754 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
755 if (sc->sc_phyno == -1) {
756 device_printf(sc->sc_ue.ue_dev,
757 "no valid PHY address found, assuming PHY address 0\n");
761 if (sc->sc_flags & AXE_FLAG_178) {
762 axe_ax88178_init(sc);
763 sc->sc_tx_bufsz = 16 * 1024;
764 } else if (sc->sc_flags & AXE_FLAG_772) {
765 axe_ax88772_init(sc);
766 sc->sc_tx_bufsz = 8 * 1024;
767 } else if (sc->sc_flags & AXE_FLAG_772A) {
768 axe_ax88772a_init(sc);
769 sc->sc_tx_bufsz = 8 * 1024;
773 * Get station address.
775 if (AXE_IS_178_FAMILY(sc))
776 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
778 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
783 if (sc->sc_flags & AXE_FLAG_772A) {
784 /* Set IPG values. */
785 sc->sc_ipgs[0] = 0x15;
786 sc->sc_ipgs[1] = 0x16;
787 sc->sc_ipgs[2] = 0x1A;
789 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
793 * Probe for a AX88172 chip.
796 axe_probe(device_t dev)
798 struct usb_attach_arg *uaa = device_get_ivars(dev);
800 if (uaa->usb_mode != USB_MODE_HOST)
802 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
804 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
807 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
811 * Attach the interface. Allocate softc structures, do ifmedia
812 * setup and ethernet/BPF attach.
815 axe_attach(device_t dev)
817 struct usb_attach_arg *uaa = device_get_ivars(dev);
818 struct axe_softc *sc = device_get_softc(dev);
819 struct usb_ether *ue = &sc->sc_ue;
823 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
825 device_set_usb_desc(dev);
827 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
829 iface_index = AXE_IFACE_IDX;
830 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
831 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
833 device_printf(dev, "allocating USB transfers failed\n");
839 ue->ue_udev = uaa->device;
840 ue->ue_mtx = &sc->sc_mtx;
841 ue->ue_methods = &axe_ue_methods;
843 error = uether_ifattach(ue);
845 device_printf(dev, "could not attach interface\n");
848 return (0); /* success */
852 return (ENXIO); /* failure */
856 axe_detach(device_t dev)
858 struct axe_softc *sc = device_get_softc(dev);
859 struct usb_ether *ue = &sc->sc_ue;
861 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
863 mtx_destroy(&sc->sc_mtx);
868 #if (AXE_BULK_BUF_SIZE >= 0x10000)
869 #error "Please update axe_bulk_read_callback()!"
873 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
875 struct axe_softc *sc = usbd_xfer_softc(xfer);
876 struct usb_ether *ue = &sc->sc_ue;
877 struct ifnet *ifp = uether_getifp(ue);
878 struct axe_sframe_hdr hdr;
879 struct usb_page_cache *pc;
883 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
885 switch (USB_GET_STATE(xfer)) {
886 case USB_ST_TRANSFERRED:
891 pc = usbd_xfer_get_frame(xfer, 0);
892 if (AXE_IS_178_FAMILY(sc)) {
893 while (pos < actlen) {
894 if ((pos + sizeof(hdr)) > actlen) {
895 /* too little data */
899 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
901 if ((hdr.len ^ hdr.ilen) != 0xFFFF) {
908 len = le16toh(hdr.len);
909 if ((pos + len) > actlen) {
914 uether_rxbuf(ue, pc, pos, len);
916 pos += len + (len % 2);
919 uether_rxbuf(ue, pc, 0, actlen);
927 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
928 usbd_transfer_submit(xfer);
933 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
935 if (error != USB_ERR_CANCELLED) {
936 /* try to clear stall first */
937 usbd_xfer_set_stall(xfer);
945 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
946 #error "Please update axe_bulk_write_callback()!"
950 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
952 struct axe_softc *sc = usbd_xfer_softc(xfer);
953 struct axe_sframe_hdr hdr;
954 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
955 struct usb_page_cache *pc;
959 switch (USB_GET_STATE(xfer)) {
960 case USB_ST_TRANSFERRED:
961 DPRINTFN(11, "transfer complete\n");
962 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
966 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
967 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
969 * Don't send anything if there is no link or
970 * controller is busy.
975 for (nframes = 0; nframes < 16 &&
976 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
977 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
980 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
983 pc = usbd_xfer_get_frame(xfer, nframes);
984 if (AXE_IS_178_FAMILY(sc)) {
985 hdr.len = htole16(m->m_pkthdr.len);
987 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
989 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
990 pos += m->m_pkthdr.len;
991 if ((pos % 512) == 0) {
994 usbd_copy_in(pc, pos, &hdr,
999 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1000 pos += m->m_pkthdr.len;
1005 * Update TX packet counter here. This is not
1006 * correct way but it seems that there is no way
1007 * to know how many packets are sent at the end
1008 * of transfer because controller combines
1009 * multiple writes into single one if there is
1010 * room in TX buffer of controller.
1015 * if there's a BPF listener, bounce a copy
1016 * of this frame to him:
1022 /* Set frame length. */
1023 usbd_xfer_set_frame_len(xfer, nframes, pos);
1026 usbd_xfer_set_frames(xfer, nframes);
1027 usbd_transfer_submit(xfer);
1028 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1032 default: /* Error */
1033 DPRINTFN(11, "transfer error, %s\n",
1034 usbd_errstr(error));
1037 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1039 if (error != USB_ERR_CANCELLED) {
1040 /* try to clear stall first */
1041 usbd_xfer_set_stall(xfer);
1050 axe_tick(struct usb_ether *ue)
1052 struct axe_softc *sc = uether_getsc(ue);
1053 struct mii_data *mii = GET_MII(sc);
1055 AXE_LOCK_ASSERT(sc, MA_OWNED);
1058 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1059 axe_miibus_statchg(ue->ue_dev);
1060 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1066 axe_start(struct usb_ether *ue)
1068 struct axe_softc *sc = uether_getsc(ue);
1071 * start the USB transfers, if not already started:
1073 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1074 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1078 axe_init(struct usb_ether *ue)
1080 struct axe_softc *sc = uether_getsc(ue);
1081 struct ifnet *ifp = uether_getifp(ue);
1084 AXE_LOCK_ASSERT(sc, MA_OWNED);
1086 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1089 /* Cancel pending I/O */
1094 /* Set MAC address. */
1095 if (AXE_IS_178_FAMILY(sc))
1096 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1098 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1100 /* Set transmitter IPG values */
1101 if (AXE_IS_178_FAMILY(sc))
1102 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1103 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1105 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1106 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1107 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1110 /* Enable receiver, set RX mode */
1111 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1112 if (AXE_IS_178_FAMILY(sc)) {
1114 rxmode |= AXE_178_RXCMD_MFB_2048; /* chip default */
1117 * Default Rx buffer size is too small to get
1118 * maximum performance.
1120 rxmode |= AXE_178_RXCMD_MFB_16384;
1123 rxmode |= AXE_172_RXCMD_UNICAST;
1126 /* If we want promiscuous mode, set the allframes bit. */
1127 if (ifp->if_flags & IFF_PROMISC)
1128 rxmode |= AXE_RXCMD_PROMISC;
1130 if (ifp->if_flags & IFF_BROADCAST)
1131 rxmode |= AXE_RXCMD_BROADCAST;
1133 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1135 /* Load the multicast filter. */
1138 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1140 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1141 /* Switch to selected media. */
1142 axe_ifmedia_upd(ifp);
1147 axe_setpromisc(struct usb_ether *ue)
1149 struct axe_softc *sc = uether_getsc(ue);
1150 struct ifnet *ifp = uether_getifp(ue);
1153 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1155 rxmode = le16toh(rxmode);
1157 if (ifp->if_flags & IFF_PROMISC) {
1158 rxmode |= AXE_RXCMD_PROMISC;
1160 rxmode &= ~AXE_RXCMD_PROMISC;
1163 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1169 axe_stop(struct usb_ether *ue)
1171 struct axe_softc *sc = uether_getsc(ue);
1172 struct ifnet *ifp = uether_getifp(ue);
1174 AXE_LOCK_ASSERT(sc, MA_OWNED);
1176 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1177 sc->sc_flags &= ~AXE_FLAG_LINK;
1180 * stop all the transfers, if not already stopped:
1182 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1183 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);