2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <sys/cdefs.h>
18 __FBSDID("$FreeBSD$");
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
23 #include <sys/mutex.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
31 #include <sys/endian.h>
34 #include <machine/bus.h>
35 #include <machine/resource.h>
39 #include <net/if_arp.h>
40 #include <net/ethernet.h>
41 #include <net/if_dl.h>
42 #include <net/if_media.h>
43 #include <net/if_types.h>
46 #include <netinet/in.h>
47 #include <netinet/in_systm.h>
48 #include <netinet/in_var.h>
49 #include <netinet/if_ether.h>
50 #include <netinet/ip.h>
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_regdomain.h>
55 #include <net80211/ieee80211_radiotap.h>
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
61 #include <dev/usb/wlan/if_urtwreg.h>
62 #include <dev/usb/wlan/if_urtwvar.h>
64 SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
67 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &urtw_debug, 0,
68 "control debugging printfs");
69 TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
77 URTW_DEBUG_STAT = 0x00000040, /* statistic */
78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
80 URTW_DEBUG_ANY = 0xffffffff
82 #define DPRINTF(sc, m, fmt, ...) do { \
83 if (sc->sc_debug & (m)) \
84 printf(fmt, __VA_ARGS__); \
87 #define DPRINTF(sc, m, fmt, ...) do { \
91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW | CTLFLAG_TUN,
93 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
94 TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
96 /* recognized device vendors/products */
97 #define urtw_lookup(v, p) \
98 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
99 #define URTW_DEV_B(v,p) \
100 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
101 #define URTW_DEV_L(v,p) \
102 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
103 #define URTW_REV_RTL8187B 0
104 #define URTW_REV_RTL8187L 1
105 static const STRUCT_USB_HOST_ID urtw_devs[] = {
106 URTW_DEV_B(NETGEAR, WG111V3),
107 URTW_DEV_B(REALTEK, RTL8187B_0),
108 URTW_DEV_B(REALTEK, RTL8187B_1),
109 URTW_DEV_B(REALTEK, RTL8187B_2),
110 URTW_DEV_B(SITECOMEU, WL168V4),
111 URTW_DEV_L(ASUS, P5B_WIFI),
112 URTW_DEV_L(BELKIN, F5D7050E),
113 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
114 URTW_DEV_L(NETGEAR, WG111V2),
115 URTW_DEV_L(REALTEK, RTL8187),
116 URTW_DEV_L(SITECOMEU, WL168V1),
117 URTW_DEV_L(SURECOM, EP9001G2A),
118 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
122 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
123 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
124 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
129 #define urtw_read8_m(sc, val, data) do { \
130 error = urtw_read8_c(sc, val, data); \
134 #define urtw_write8_m(sc, val, data) do { \
135 error = urtw_write8_c(sc, val, data); \
139 #define urtw_read16_m(sc, val, data) do { \
140 error = urtw_read16_c(sc, val, data); \
144 #define urtw_write16_m(sc, val, data) do { \
145 error = urtw_write16_c(sc, val, data); \
149 #define urtw_read32_m(sc, val, data) do { \
150 error = urtw_read32_c(sc, val, data); \
154 #define urtw_write32_m(sc, val, data) do { \
155 error = urtw_write32_c(sc, val, data); \
159 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
160 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
164 #define urtw_8187_write_phy_cck(sc, val, data) do { \
165 error = urtw_8187_write_phy_cck_c(sc, val, data); \
169 #define urtw_8225_write(sc, val, data) do { \
170 error = urtw_8225_write_c(sc, val, data); \
180 static uint8_t urtw_8225_agc[] = {
181 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
182 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
183 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
184 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
185 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
186 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
187 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
188 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
189 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
190 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
192 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
195 static uint8_t urtw_8225z2_agc[] = {
196 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
197 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
198 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
199 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
200 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
201 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
202 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
203 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
204 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
205 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
207 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
210 static uint32_t urtw_8225_channel[] = {
211 0x0000, /* dummy channel 0 */
228 static uint8_t urtw_8225_gain[] = {
229 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
230 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
231 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
232 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
233 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
234 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
235 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
238 static struct urtw_pair urtw_8225_rf_part1[] = {
239 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
240 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
241 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
242 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
245 static struct urtw_pair urtw_8225_rf_part2[] = {
246 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
247 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
248 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
249 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
250 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
251 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
252 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
253 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
254 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
258 static struct urtw_pair urtw_8225_rf_part3[] = {
259 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
260 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
261 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
262 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
263 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
264 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
265 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
268 static uint16_t urtw_8225_rxgain[] = {
269 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
270 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
271 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
272 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
273 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
274 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
275 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
276 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
277 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
278 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
279 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
280 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
283 static uint8_t urtw_8225_threshold[] = {
284 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
287 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
288 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
291 static uint8_t urtw_8225_txpwr_cck[] = {
292 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
293 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
294 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
295 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
296 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
297 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
300 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
301 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
302 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
303 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
304 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
305 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
306 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
309 static uint8_t urtw_8225_txpwr_ofdm[]={
310 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
313 static uint8_t urtw_8225v2_gain_bg[]={
314 0x23, 0x15, 0xa5, /* -82-1dbm */
315 0x23, 0x15, 0xb5, /* -82-2dbm */
316 0x23, 0x15, 0xc5, /* -82-3dbm */
317 0x33, 0x15, 0xc5, /* -78dbm */
318 0x43, 0x15, 0xc5, /* -74dbm */
319 0x53, 0x15, 0xc5, /* -70dbm */
320 0x63, 0x15, 0xc5, /* -66dbm */
323 static struct urtw_pair urtw_8225v2_rf_part1[] = {
324 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
325 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
326 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
327 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
330 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
331 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
332 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
333 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
334 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
337 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
338 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
339 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
340 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
341 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
342 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
343 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
344 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
345 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
346 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
347 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
348 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
349 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
350 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
351 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
352 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
353 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
354 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
355 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
356 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
357 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
358 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
359 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
360 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
361 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
362 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
363 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
364 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
365 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
366 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
367 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
368 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
371 static struct urtw_pair urtw_8225v2_rf_part2[] = {
372 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
373 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
374 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
375 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
376 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
377 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
378 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
379 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
380 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
381 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
384 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
385 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
386 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
387 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
388 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
389 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
390 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
391 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
392 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
393 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
394 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
395 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
396 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
397 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
398 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
399 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
402 static struct urtw_pair urtw_8225v2_rf_part3[] = {
403 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
404 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
405 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
406 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
407 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
408 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
409 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
410 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
413 static uint16_t urtw_8225v2_rxgain[] = {
414 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
415 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
416 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
417 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
418 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
419 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
420 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
421 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
422 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
423 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
424 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
425 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
428 static uint16_t urtw_8225v2b_rxgain[] = {
429 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
430 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
431 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
432 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
433 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
434 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
435 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
436 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
437 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
438 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
439 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
440 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
443 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
444 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
445 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
446 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
447 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
448 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
449 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
452 static uint8_t urtw_8225v2_txpwr_cck[] = {
453 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
456 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
457 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
460 static uint8_t urtw_8225v2b_txpwr_cck[] = {
461 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
462 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
463 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
464 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
467 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
468 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
474 static struct urtw_pair urtw_ratetable[] = {
475 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
476 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
477 { 96, 10 }, { 108, 11 }
481 static const uint8_t urtw_8187b_reg_table[][3] = {
482 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
483 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
484 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
485 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
486 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
487 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
488 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
489 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
490 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
491 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
492 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
493 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
494 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
495 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
496 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
497 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
498 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
499 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
500 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
501 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
502 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
503 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
504 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
505 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
506 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
507 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
508 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
509 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
510 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
511 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
512 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
516 static usb_callback_t urtw_bulk_rx_callback;
517 static usb_callback_t urtw_bulk_tx_callback;
518 static usb_callback_t urtw_bulk_tx_status_callback;
520 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
521 [URTW_8187B_BULK_RX] = {
524 .direction = UE_DIR_IN,
531 .callback = urtw_bulk_rx_callback
533 [URTW_8187B_BULK_TX_STATUS] = {
536 .direction = UE_DIR_IN,
543 .callback = urtw_bulk_tx_status_callback
545 [URTW_8187B_BULK_TX_BE] = {
547 .endpoint = URTW_8187B_TXPIPE_BE,
548 .direction = UE_DIR_OUT,
549 .bufsize = URTW_TX_MAXSIZE,
552 .force_short_xfer = 1,
555 .callback = urtw_bulk_tx_callback,
556 .timeout = URTW_DATA_TIMEOUT
558 [URTW_8187B_BULK_TX_BK] = {
560 .endpoint = URTW_8187B_TXPIPE_BK,
561 .direction = UE_DIR_OUT,
562 .bufsize = URTW_TX_MAXSIZE,
565 .force_short_xfer = 1,
568 .callback = urtw_bulk_tx_callback,
569 .timeout = URTW_DATA_TIMEOUT
571 [URTW_8187B_BULK_TX_VI] = {
573 .endpoint = URTW_8187B_TXPIPE_VI,
574 .direction = UE_DIR_OUT,
575 .bufsize = URTW_TX_MAXSIZE,
578 .force_short_xfer = 1,
581 .callback = urtw_bulk_tx_callback,
582 .timeout = URTW_DATA_TIMEOUT
584 [URTW_8187B_BULK_TX_VO] = {
586 .endpoint = URTW_8187B_TXPIPE_VO,
587 .direction = UE_DIR_OUT,
588 .bufsize = URTW_TX_MAXSIZE,
591 .force_short_xfer = 1,
594 .callback = urtw_bulk_tx_callback,
595 .timeout = URTW_DATA_TIMEOUT
597 [URTW_8187B_BULK_TX_EP12] = {
600 .direction = UE_DIR_OUT,
601 .bufsize = URTW_TX_MAXSIZE,
604 .force_short_xfer = 1,
607 .callback = urtw_bulk_tx_callback,
608 .timeout = URTW_DATA_TIMEOUT
612 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
613 [URTW_8187L_BULK_RX] = {
616 .direction = UE_DIR_IN,
623 .callback = urtw_bulk_rx_callback
625 [URTW_8187L_BULK_TX_LOW] = {
628 .direction = UE_DIR_OUT,
629 .bufsize = URTW_TX_MAXSIZE,
632 .force_short_xfer = 1,
635 .callback = urtw_bulk_tx_callback,
636 .timeout = URTW_DATA_TIMEOUT
638 [URTW_8187L_BULK_TX_NORMAL] = {
641 .direction = UE_DIR_OUT,
642 .bufsize = URTW_TX_MAXSIZE,
645 .force_short_xfer = 1,
648 .callback = urtw_bulk_tx_callback,
649 .timeout = URTW_DATA_TIMEOUT
653 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
654 const char name[IFNAMSIZ], int unit, int opmode,
655 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
656 const uint8_t mac[IEEE80211_ADDR_LEN]);
657 static void urtw_vap_delete(struct ieee80211vap *);
658 static void urtw_init(void *);
659 static void urtw_stop(struct ifnet *, int);
660 static void urtw_stop_locked(struct ifnet *, int);
661 static int urtw_ioctl(struct ifnet *, u_long, caddr_t);
662 static void urtw_start(struct ifnet *);
663 static int urtw_alloc_rx_data_list(struct urtw_softc *);
664 static int urtw_alloc_tx_data_list(struct urtw_softc *);
665 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
666 const struct ieee80211_bpf_params *);
667 static void urtw_scan_start(struct ieee80211com *);
668 static void urtw_scan_end(struct ieee80211com *);
669 static void urtw_set_channel(struct ieee80211com *);
670 static void urtw_update_mcast(struct ifnet *);
671 static int urtw_tx_start(struct urtw_softc *,
672 struct ieee80211_node *, struct mbuf *,
673 struct urtw_data *, int);
674 static int urtw_newstate(struct ieee80211vap *,
675 enum ieee80211_state, int);
676 static void urtw_led_ch(void *);
677 static void urtw_ledtask(void *, int);
678 static void urtw_watchdog(void *);
679 static void urtw_set_multi(void *);
680 static int urtw_isbmode(uint16_t);
681 static uint16_t urtw_rate2rtl(uint32_t);
682 static uint16_t urtw_rtl2rate(uint32_t);
683 static usb_error_t urtw_set_rate(struct urtw_softc *);
684 static usb_error_t urtw_update_msr(struct urtw_softc *);
685 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
686 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
687 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
688 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
689 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
690 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
691 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
692 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
693 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
695 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
697 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
698 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
699 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
700 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
701 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
702 static usb_error_t urtw_led_init(struct urtw_softc *);
703 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
704 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
705 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
707 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
709 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
711 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
712 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
713 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
715 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
717 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
719 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
720 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
721 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
722 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
723 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
724 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
725 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
726 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
727 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
728 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
729 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
730 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
731 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
732 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
733 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
734 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
735 static usb_error_t urtw_intr_enable(struct urtw_softc *);
736 static usb_error_t urtw_intr_disable(struct urtw_softc *);
737 static usb_error_t urtw_reset(struct urtw_softc *);
738 static usb_error_t urtw_led_on(struct urtw_softc *, int);
739 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
740 static usb_error_t urtw_led_blink(struct urtw_softc *);
741 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
742 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
743 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
744 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
745 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
746 static usb_error_t urtw_rx_enable(struct urtw_softc *);
747 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
748 static void urtw_free_tx_data_list(struct urtw_softc *);
749 static void urtw_free_rx_data_list(struct urtw_softc *);
750 static void urtw_free_data_list(struct urtw_softc *,
751 struct urtw_data data[], int, int);
752 static usb_error_t urtw_adapter_start(struct urtw_softc *);
753 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
754 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
755 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
756 static usb_error_t urtw_do_request(struct urtw_softc *,
757 struct usb_device_request *, void *);
758 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
759 static usb_error_t urtw_led_off(struct urtw_softc *, int);
760 static void urtw_abort_xfers(struct urtw_softc *);
761 static struct urtw_data *
762 urtw_getbuf(struct urtw_softc *sc);
763 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
765 static void urtw_updateslot(struct ifnet *);
766 static void urtw_updateslottask(void *, int);
767 static void urtw_sysctl_node(struct urtw_softc *);
770 urtw_match(device_t dev)
772 struct usb_attach_arg *uaa = device_get_ivars(dev);
774 if (uaa->usb_mode != USB_MODE_HOST)
776 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
778 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
781 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
785 urtw_attach(device_t dev)
787 const struct usb_config *setup_start;
789 struct urtw_softc *sc = device_get_softc(dev);
790 struct usb_attach_arg *uaa = device_get_ivars(dev);
791 struct ieee80211com *ic;
793 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */
798 device_set_usb_desc(dev);
801 sc->sc_udev = uaa->device;
802 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
803 sc->sc_flags |= URTW_RTL8187B;
805 sc->sc_debug = urtw_debug;
808 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
810 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
811 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
812 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
813 callout_init(&sc->sc_watchdog_ch, 0);
815 if (sc->sc_flags & URTW_RTL8187B) {
816 setup_start = urtw_8187b_usbconfig;
817 n_setup = URTW_8187B_N_XFERS;
819 setup_start = urtw_8187l_usbconfig;
820 n_setup = URTW_8187L_N_XFERS;
823 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
824 setup_start, n_setup, sc, &sc->sc_mtx);
826 device_printf(dev, "could not allocate USB transfers, "
827 "err=%s\n", usbd_errstr(error));
834 urtw_read32_m(sc, URTW_RX, &data);
835 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
838 error = urtw_get_rfchip(sc);
841 error = urtw_get_macaddr(sc);
844 error = urtw_get_txpwr(sc);
847 error = urtw_led_init(sc);
853 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
854 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
856 sc->sc_preamble_mode = urtw_preamble_mode;
858 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
860 device_printf(sc->sc_dev, "can not allocate ifnet\n");
866 if_initname(ifp, "urtw", device_get_unit(sc->sc_dev));
867 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
868 ifp->if_init = urtw_init;
869 ifp->if_ioctl = urtw_ioctl;
870 ifp->if_start = urtw_start;
871 /* XXX URTW_TX_DATA_LIST_COUNT */
872 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
873 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
874 IFQ_SET_READY(&ifp->if_snd);
878 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
879 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
881 /* set device capabilities */
883 IEEE80211_C_STA | /* station mode */
884 IEEE80211_C_MONITOR | /* monitor mode supported */
885 IEEE80211_C_TXPMGT | /* tx power management */
886 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
887 IEEE80211_C_SHSLOT | /* short slot time supported */
888 IEEE80211_C_BGSCAN | /* capable of bg scanning */
889 IEEE80211_C_WPA; /* 802.11i */
892 setbit(&bands, IEEE80211_MODE_11B);
893 setbit(&bands, IEEE80211_MODE_11G);
894 ieee80211_init_channels(ic, NULL, &bands);
896 ieee80211_ifattach(ic, sc->sc_bssid);
897 ic->ic_raw_xmit = urtw_raw_xmit;
898 ic->ic_scan_start = urtw_scan_start;
899 ic->ic_scan_end = urtw_scan_end;
900 ic->ic_set_channel = urtw_set_channel;
901 ic->ic_updateslot = urtw_updateslot;
902 ic->ic_vap_create = urtw_vap_create;
903 ic->ic_vap_delete = urtw_vap_delete;
904 ic->ic_update_mcast = urtw_update_mcast;
906 ieee80211_radiotap_attach(ic,
907 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
908 URTW_TX_RADIOTAP_PRESENT,
909 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
910 URTW_RX_RADIOTAP_PRESENT);
912 urtw_sysctl_node(sc);
915 ieee80211_announce(ic);
918 fail: URTW_UNLOCK(sc);
919 fail1: usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
920 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
926 urtw_detach(device_t dev)
928 struct urtw_softc *sc = device_get_softc(dev);
929 struct ifnet *ifp = sc->sc_ifp;
930 struct ieee80211com *ic = ifp->if_l2com;
932 if (!device_is_attached(dev))
936 ieee80211_draintask(ic, &sc->sc_updateslot_task);
937 ieee80211_draintask(ic, &sc->sc_led_task);
939 usb_callout_drain(&sc->sc_led_ch);
940 callout_drain(&sc->sc_watchdog_ch);
942 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
943 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
944 ieee80211_ifdetach(ic);
946 urtw_free_tx_data_list(sc);
947 urtw_free_rx_data_list(sc);
950 mtx_destroy(&sc->sc_mtx);
956 urtw_free_tx_data_list(struct urtw_softc *sc)
959 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
963 urtw_free_rx_data_list(struct urtw_softc *sc)
966 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
970 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
975 for (i = 0; i < ndata; i++) {
976 struct urtw_data *dp = &data[i];
985 if (dp->buf != NULL) {
986 free(dp->buf, M_USBDEV);
990 if (dp->ni != NULL) {
991 ieee80211_free_node(dp->ni);
997 static struct ieee80211vap *
998 urtw_vap_create(struct ieee80211com *ic,
999 const char name[IFNAMSIZ], int unit, int opmode, int flags,
1000 const uint8_t bssid[IEEE80211_ADDR_LEN],
1001 const uint8_t mac[IEEE80211_ADDR_LEN])
1003 struct urtw_vap *uvp;
1004 struct ieee80211vap *vap;
1006 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1008 uvp = (struct urtw_vap *) malloc(sizeof(struct urtw_vap),
1009 M_80211_VAP, M_NOWAIT | M_ZERO);
1013 /* enable s/w bmiss handling for sta mode */
1014 ieee80211_vap_setup(ic, vap, name, unit, opmode,
1015 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
1017 /* override state transition machine */
1018 uvp->newstate = vap->iv_newstate;
1019 vap->iv_newstate = urtw_newstate;
1021 /* complete setup */
1022 ieee80211_vap_attach(vap, ieee80211_media_change,
1023 ieee80211_media_status);
1024 ic->ic_opmode = opmode;
1029 urtw_vap_delete(struct ieee80211vap *vap)
1031 struct urtw_vap *uvp = URTW_VAP(vap);
1033 ieee80211_vap_detach(vap);
1034 free(uvp, M_80211_VAP);
1038 urtw_init_locked(void *arg)
1041 struct urtw_softc *sc = arg;
1042 struct ifnet *ifp = sc->sc_ifp;
1045 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1046 urtw_stop_locked(ifp, 0);
1048 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1049 urtw_adapter_start(sc);
1053 /* reset softc variables */
1056 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1057 ret = urtw_alloc_rx_data_list(sc);
1060 ret = urtw_alloc_tx_data_list(sc);
1063 sc->sc_flags |= URTW_INIT_ONCE;
1066 error = urtw_rx_enable(sc);
1069 error = urtw_tx_enable(sc);
1073 if (sc->sc_flags & URTW_RTL8187B)
1074 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1076 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1077 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1079 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1085 urtw_init(void *arg)
1087 struct urtw_softc *sc = arg;
1090 urtw_init_locked(arg);
1095 urtw_adapter_start_b(struct urtw_softc *sc)
1097 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1101 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1105 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1106 urtw_write8_m(sc, URTW_CONFIG3,
1107 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1108 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1109 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1110 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1112 urtw_write8_m(sc, 0x61, 0x10);
1113 urtw_read8_m(sc, 0x62, &data8);
1114 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1115 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1117 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1118 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1119 urtw_write8_m(sc, URTW_CONFIG3, data8);
1121 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1125 error = urtw_8187b_cmd_reset(sc);
1129 error = sc->sc_rf_init(sc);
1132 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1134 /* fix RTL8187B RX stall */
1135 error = urtw_intr_enable(sc);
1139 error = urtw_write8e(sc, 0x41, 0xf4);
1142 error = urtw_write8e(sc, 0x40, 0x00);
1145 error = urtw_write8e(sc, 0x42, 0x00);
1148 error = urtw_write8e(sc, 0x42, 0x01);
1151 error = urtw_write8e(sc, 0x40, 0x0f);
1154 error = urtw_write8e(sc, 0x42, 0x00);
1157 error = urtw_write8e(sc, 0x42, 0x01);
1161 urtw_read8_m(sc, 0xdb, &data8);
1162 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1163 urtw_write16_m(sc, 0x372, 0x59fa);
1164 urtw_write16_m(sc, 0x374, 0x59d2);
1165 urtw_write16_m(sc, 0x376, 0x59d2);
1166 urtw_write16_m(sc, 0x378, 0x19fa);
1167 urtw_write16_m(sc, 0x37a, 0x19fa);
1168 urtw_write16_m(sc, 0x37c, 0x00d0);
1169 urtw_write8_m(sc, 0x61, 0);
1171 urtw_write8_m(sc, 0x180, 0x0f);
1172 urtw_write8_m(sc, 0x183, 0x03);
1173 urtw_write8_m(sc, 0xda, 0x10);
1174 urtw_write8_m(sc, 0x24d, 0x08);
1175 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1177 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1184 urtw_adapter_start(struct urtw_softc *sc)
1188 error = urtw_reset(sc);
1192 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1193 urtw_write8_m(sc, URTW_GPIO, 0);
1196 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1197 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1201 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1204 /* applying MAC address again. */
1205 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
1206 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
1207 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1211 error = urtw_update_msr(sc);
1215 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1216 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1217 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1218 error = urtw_set_rate(sc);
1222 error = sc->sc_rf_init(sc);
1225 if (sc->sc_rf_set_sens != NULL)
1226 sc->sc_rf_set_sens(sc, sc->sc_sens);
1228 /* XXX correct? to call write16 */
1229 urtw_write16_m(sc, URTW_PSR, 1);
1230 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1231 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1232 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1233 /* XXX correct? to call write16 */
1234 urtw_write16_m(sc, URTW_PSR, 0);
1235 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1237 error = urtw_intr_enable(sc);
1246 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1251 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1252 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1253 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1254 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1260 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1266 /* XXX the code can be duplicate with urtw_reset(). */
1267 urtw_read8_m(sc, URTW_CMD, &data8);
1268 data8 = (data8 & 0x2) | URTW_CMD_RST;
1269 urtw_write8_m(sc, URTW_CMD, data8);
1271 for (i = 0; i < 20; i++) {
1272 usb_pause_mtx(&sc->sc_mtx, 2);
1273 urtw_read8_m(sc, URTW_CMD, &data8);
1274 if (!(data8 & URTW_CMD_RST))
1278 device_printf(sc->sc_dev, "reset timeout\n");
1286 urtw_do_request(struct urtw_softc *sc,
1287 struct usb_device_request *req, void *data)
1292 URTW_ASSERT_LOCKED(sc);
1295 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1296 req, data, 0, NULL, 250 /* ms */);
1300 DPRINTF(sc, URTW_DEBUG_INIT,
1301 "Control request failed, %s (retrying)\n",
1303 usb_pause_mtx(&sc->sc_mtx, hz / 100);
1309 urtw_stop_locked(struct ifnet *ifp, int disable)
1311 struct urtw_softc *sc = ifp->if_softc;
1316 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1318 error = urtw_intr_disable(sc);
1321 urtw_read8_m(sc, URTW_CMD, &data8);
1322 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1323 urtw_write8_m(sc, URTW_CMD, data8);
1325 error = sc->sc_rf_stop(sc);
1329 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1332 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1333 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1334 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1339 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1340 usbd_errstr(error));
1342 usb_callout_stop(&sc->sc_led_ch);
1343 callout_stop(&sc->sc_watchdog_ch);
1345 urtw_abort_xfers(sc);
1349 urtw_stop(struct ifnet *ifp, int disable)
1351 struct urtw_softc *sc = ifp->if_softc;
1354 urtw_stop_locked(ifp, disable);
1359 urtw_abort_xfers(struct urtw_softc *sc)
1363 URTW_ASSERT_LOCKED(sc);
1365 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1368 /* abort any pending transfers */
1369 for (i = 0; i < max; i++)
1370 usbd_transfer_stop(sc->sc_xfer[i]);
1374 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1376 struct urtw_softc *sc = ifp->if_softc;
1377 struct ieee80211com *ic = ifp->if_l2com;
1378 struct ifreq *ifr = (struct ifreq *) data;
1379 int error = 0, startall = 0;
1383 if (ifp->if_flags & IFF_UP) {
1384 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1385 if ((ifp->if_flags ^ sc->sc_if_flags) &
1386 (IFF_ALLMULTI | IFF_PROMISC))
1389 urtw_init(ifp->if_softc);
1393 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1396 sc->sc_if_flags = ifp->if_flags;
1398 ieee80211_start_all(ic);
1401 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1404 error = ether_ioctl(ifp, cmd, data);
1415 urtw_start(struct ifnet *ifp)
1417 struct urtw_data *bf;
1418 struct urtw_softc *sc = ifp->if_softc;
1419 struct ieee80211_node *ni;
1422 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1427 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1430 bf = urtw_getbuf(sc);
1432 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1436 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1437 m->m_pkthdr.rcvif = NULL;
1439 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1441 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1442 ieee80211_free_node(ni);
1447 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1453 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1454 int ndata, int maxsz, int fillmbuf)
1458 for (i = 0; i < ndata; i++) {
1459 struct urtw_data *dp = &data[i];
1463 dp->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1464 if (dp->m == NULL) {
1465 device_printf(sc->sc_dev,
1466 "could not allocate rx mbuf\n");
1470 dp->buf = mtod(dp->m, uint8_t *);
1473 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1474 if (dp->buf == NULL) {
1475 device_printf(sc->sc_dev,
1476 "could not allocate buffer\n");
1480 if (((unsigned long)dp->buf) % 4)
1481 device_printf(sc->sc_dev,
1482 "warn: unaligned buffer %p\n", dp->buf);
1489 fail: urtw_free_data_list(sc, data, ndata, fillmbuf);
1494 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1498 error = urtw_alloc_data_list(sc,
1499 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, MCLBYTES, 1 /* mbufs */);
1503 STAILQ_INIT(&sc->sc_rx_active);
1504 STAILQ_INIT(&sc->sc_rx_inactive);
1506 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1507 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1513 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1517 error = urtw_alloc_data_list(sc,
1518 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1523 STAILQ_INIT(&sc->sc_tx_active);
1524 STAILQ_INIT(&sc->sc_tx_inactive);
1525 STAILQ_INIT(&sc->sc_tx_pending);
1527 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1528 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1535 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1536 const struct ieee80211_bpf_params *params)
1538 struct ieee80211com *ic = ni->ni_ic;
1539 struct ifnet *ifp = ic->ic_ifp;
1540 struct urtw_data *bf;
1541 struct urtw_softc *sc = ifp->if_softc;
1543 /* prevent management frames from being sent if we're not ready */
1544 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1546 ieee80211_free_node(ni);
1550 bf = urtw_getbuf(sc);
1552 ieee80211_free_node(ni);
1555 return (ENOBUFS); /* XXX */
1559 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1560 ieee80211_free_node(ni);
1562 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1573 urtw_scan_start(struct ieee80211com *ic)
1576 /* XXX do nothing? */
1580 urtw_scan_end(struct ieee80211com *ic)
1583 /* XXX do nothing? */
1587 urtw_set_channel(struct ieee80211com *ic)
1589 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1590 struct ifnet *ifp = sc->sc_ifp;
1591 uint32_t data, orig;
1595 * if the user set a channel explicitly using ifconfig(8) this function
1596 * can be called earlier than we're expected that in some cases the
1597 * initialization would be failed if setting a channel is called before
1598 * the init have done.
1600 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1603 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1609 * during changing th channel we need to temporarily be disable
1612 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1613 data = orig & ~URTW_TX_LOOPBACK_MASK;
1614 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1616 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1619 usb_pause_mtx(&sc->sc_mtx, 10);
1620 urtw_write32_m(sc, URTW_TX_CONF, orig);
1622 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1623 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1624 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1625 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1630 sc->sc_curchan = ic->ic_curchan;
1633 device_printf(sc->sc_dev, "could not change the channel\n");
1637 urtw_update_mcast(struct ifnet *ifp)
1640 /* XXX do nothing? */
1644 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1645 struct urtw_data *data, int prior)
1647 struct ifnet *ifp = sc->sc_ifp;
1648 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1649 struct ieee80211_key *k;
1650 const struct ieee80211_txparam *tp;
1651 struct ieee80211com *ic = ifp->if_l2com;
1652 struct ieee80211vap *vap = ni->ni_vap;
1653 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1654 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1655 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1656 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1657 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1659 struct usb_xfer *xfer;
1660 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate,
1661 pkttime = 0, txdur = 0, isshort = 0, xferlen;
1662 uint16_t acktime, rtstime, ctstime;
1666 URTW_ASSERT_LOCKED(sc);
1671 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1672 k = ieee80211_crypto_encap(ni, m0);
1674 device_printf(sc->sc_dev,
1675 "ieee80211_crypto_encap returns NULL.\n");
1676 /* XXX we don't expect the fragmented frames */
1681 /* in case packet header moved, reset pointer */
1682 wh = mtod(m0, struct ieee80211_frame *);
1685 if (ieee80211_radiotap_active_vap(vap)) {
1686 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1688 /* XXX Are variables correct? */
1690 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1691 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1693 ieee80211_radiotap_tx(vap, m0);
1696 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT ||
1697 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) {
1698 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1699 rate = tp->mgmtrate;
1701 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1702 /* for data frames */
1703 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1704 rate = tp->mcastrate;
1705 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1706 rate = tp->ucastrate;
1708 rate = urtw_rtl2rate(sc->sc_currate);
1711 sc->sc_stats.txrates[sc->sc_currate]++;
1713 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1714 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1715 IEEE80211_CRC_LEN, rate, 0, 0);
1717 acktime = urtw_compute_txtime(14, 2,0, 0);
1718 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1721 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1722 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1723 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1724 IEEE80211_CRC_LEN, rate, 0, isshort);
1725 rtsdur = ctstime + pkttime + acktime +
1726 3 * URTW_ASIFS_TIME;
1727 txdur = rtstime + rtsdur;
1729 rtsenable = ctsenable = rtsdur = 0;
1730 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1731 IEEE80211_CRC_LEN, rate, 0, isshort);
1732 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1735 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1736 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1737 IEEE80211_CRC_LEN, rate, 0, isshort) +
1738 3 * URTW_ASIFS_TIME +
1741 dur = URTW_ASIFS_TIME + acktime;
1743 *(uint16_t *)wh->i_dur = htole16(dur);
1745 xferlen = m0->m_pkthdr.len;
1746 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1747 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1750 memset(data->buf, 0, URTW_TX_MAXSIZE);
1751 flags = m0->m_pkthdr.len & 0xfff;
1752 flags |= URTW_TX_FLAG_NO_ENC;
1753 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1754 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1755 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1756 (sc->sc_currate != 0))
1757 flags |= URTW_TX_FLAG_SPLCP;
1758 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1759 flags |= URTW_TX_FLAG_MOREFRAG;
1761 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1763 if (sc->sc_flags & URTW_RTL8187B) {
1764 struct urtw_8187b_txhdr *tx;
1766 tx = (struct urtw_8187b_txhdr *)data->buf;
1768 flags |= URTW_TX_FLAG_CTS;
1770 flags |= URTW_TX_FLAG_RTS;
1771 flags |= (urtw_rate2rtl(11) & 0xf) <<
1772 URTW_TX_FLAG_RTSRATE_SHIFT;
1773 tx->rtsdur = rtsdur;
1775 tx->flag = htole32(flags);
1777 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1778 IEEE80211_FC0_TYPE_MGT &&
1779 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1780 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1783 tx->retry = URTW_TX_MAXRETRY;
1784 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1786 struct urtw_8187l_txhdr *tx;
1788 tx = (struct urtw_8187l_txhdr *)data->buf;
1790 flags |= URTW_TX_FLAG_RTS;
1791 tx->rtsdur = rtsdur;
1793 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT;
1794 tx->flag = htole32(flags);
1795 tx->retry = 3; /* CW minimum */
1796 tx->retry = 7 << 4; /* CW maximum */
1797 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */
1798 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1801 data->buflen = xferlen;
1805 if (sc->sc_flags & URTW_RTL8187B) {
1806 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1807 case IEEE80211_FC0_TYPE_CTL:
1808 case IEEE80211_FC0_TYPE_MGT:
1809 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1812 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1813 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1814 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1818 xfer = (prior == URTW_PRIORITY_LOW) ?
1819 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1820 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1822 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1823 usbd_transfer_start(xfer);
1825 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1827 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1833 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1835 struct ieee80211com *ic = vap->iv_ic;
1836 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1837 struct urtw_vap *uvp = URTW_VAP(vap);
1838 struct ieee80211_node *ni;
1839 usb_error_t error = 0;
1841 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1842 ieee80211_state_name[vap->iv_state],
1843 ieee80211_state_name[nstate]);
1845 sc->sc_state = nstate;
1847 IEEE80211_UNLOCK(ic);
1849 usb_callout_stop(&sc->sc_led_ch);
1850 callout_stop(&sc->sc_watchdog_ch);
1853 case IEEE80211_S_INIT:
1854 case IEEE80211_S_SCAN:
1855 case IEEE80211_S_AUTH:
1856 case IEEE80211_S_ASSOC:
1858 case IEEE80211_S_RUN:
1859 ni = ieee80211_ref_node(vap->iv_bss);
1860 /* setting bssid. */
1861 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1862 urtw_write16_m(sc, URTW_BSSID + 4,
1863 ((uint16_t *)ni->ni_bssid)[2]);
1864 urtw_update_msr(sc);
1865 /* XXX maybe the below would be incorrect. */
1866 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1867 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1868 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1869 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1870 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1872 device_printf(sc->sc_dev,
1873 "could not control LED (%d)\n", error);
1874 ieee80211_free_node(ni);
1882 return (uvp->newstate(vap, nstate, arg));
1886 urtw_watchdog(void *arg)
1888 struct urtw_softc *sc = arg;
1889 struct ifnet *ifp = sc->sc_ifp;
1891 if (sc->sc_txtimer > 0) {
1892 if (--sc->sc_txtimer == 0) {
1893 device_printf(sc->sc_dev, "device timeout\n");
1897 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1902 urtw_set_multi(void *arg)
1904 struct urtw_softc *sc = arg;
1905 struct ifnet *ifp = sc->sc_ifp;
1907 if (!(ifp->if_flags & IFF_UP))
1911 * XXX don't know how to set a device. Lack of docs. Just try to set
1912 * IFF_ALLMULTI flag here.
1914 ifp->if_flags |= IFF_ALLMULTI;
1918 urtw_set_rate(struct urtw_softc *sc)
1920 int i, basic_rate, min_rr_rate, max_rr_rate;
1924 basic_rate = urtw_rate2rtl(48);
1925 min_rr_rate = urtw_rate2rtl(12);
1926 max_rr_rate = urtw_rate2rtl(48);
1928 urtw_write8_m(sc, URTW_RESP_RATE,
1929 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1930 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1932 urtw_read16_m(sc, URTW_BRSR, &data);
1933 data &= ~URTW_BRSR_MBR_8185;
1935 for (i = 0; i <= basic_rate; i++)
1938 urtw_write16_m(sc, URTW_BRSR, data);
1944 urtw_rate2rtl(uint32_t rate)
1946 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1949 for (i = 0; i < N(urtw_ratetable); i++) {
1950 if (rate == urtw_ratetable[i].reg)
1951 return urtw_ratetable[i].val;
1959 urtw_rtl2rate(uint32_t rate)
1961 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1964 for (i = 0; i < N(urtw_ratetable); i++) {
1965 if (rate == urtw_ratetable[i].val)
1966 return urtw_ratetable[i].reg;
1974 urtw_update_msr(struct urtw_softc *sc)
1976 struct ifnet *ifp = sc->sc_ifp;
1977 struct ieee80211com *ic = ifp->if_l2com;
1981 urtw_read8_m(sc, URTW_MSR, &data);
1982 data &= ~URTW_MSR_LINK_MASK;
1984 if (sc->sc_state == IEEE80211_S_RUN) {
1985 switch (ic->ic_opmode) {
1986 case IEEE80211_M_STA:
1987 case IEEE80211_M_MONITOR:
1988 data |= URTW_MSR_LINK_STA;
1989 if (sc->sc_flags & URTW_RTL8187B)
1990 data |= URTW_MSR_LINK_ENEDCA;
1992 case IEEE80211_M_IBSS:
1993 data |= URTW_MSR_LINK_ADHOC;
1995 case IEEE80211_M_HOSTAP:
1996 data |= URTW_MSR_LINK_HOSTAP;
1999 panic("unsupported operation mode 0x%x\n",
2004 data |= URTW_MSR_LINK_NONE;
2006 urtw_write8_m(sc, URTW_MSR, data);
2012 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2014 struct usb_device_request req;
2017 URTW_ASSERT_LOCKED(sc);
2019 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2020 req.bRequest = URTW_8187_GETREGS_REQ;
2021 USETW(req.wValue, (val & 0xff) | 0xff00);
2022 USETW(req.wIndex, (val >> 8) & 0x3);
2023 USETW(req.wLength, sizeof(uint8_t));
2025 error = urtw_do_request(sc, &req, data);
2030 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2032 struct usb_device_request req;
2035 URTW_ASSERT_LOCKED(sc);
2037 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2038 req.bRequest = URTW_8187_GETREGS_REQ;
2039 USETW(req.wValue, (val & 0xff) | 0xff00);
2040 USETW(req.wIndex, (val >> 8) & 0x3);
2041 USETW(req.wLength, sizeof(uint16_t));
2043 error = urtw_do_request(sc, &req, data);
2048 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2050 struct usb_device_request req;
2053 URTW_ASSERT_LOCKED(sc);
2055 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2056 req.bRequest = URTW_8187_GETREGS_REQ;
2057 USETW(req.wValue, (val & 0xff) | 0xff00);
2058 USETW(req.wIndex, (val >> 8) & 0x3);
2059 USETW(req.wLength, sizeof(uint32_t));
2061 error = urtw_do_request(sc, &req, data);
2066 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2068 struct usb_device_request req;
2070 URTW_ASSERT_LOCKED(sc);
2072 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2073 req.bRequest = URTW_8187_SETREGS_REQ;
2074 USETW(req.wValue, (val & 0xff) | 0xff00);
2075 USETW(req.wIndex, (val >> 8) & 0x3);
2076 USETW(req.wLength, sizeof(uint8_t));
2078 return (urtw_do_request(sc, &req, &data));
2082 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2084 struct usb_device_request req;
2086 URTW_ASSERT_LOCKED(sc);
2088 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2089 req.bRequest = URTW_8187_SETREGS_REQ;
2090 USETW(req.wValue, (val & 0xff) | 0xff00);
2091 USETW(req.wIndex, (val >> 8) & 0x3);
2092 USETW(req.wLength, sizeof(uint16_t));
2094 return (urtw_do_request(sc, &req, &data));
2098 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2100 struct usb_device_request req;
2102 URTW_ASSERT_LOCKED(sc);
2104 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2105 req.bRequest = URTW_8187_SETREGS_REQ;
2106 USETW(req.wValue, (val & 0xff) | 0xff00);
2107 USETW(req.wIndex, (val >> 8) & 0x3);
2108 USETW(req.wLength, sizeof(uint32_t));
2110 return (urtw_do_request(sc, &req, &data));
2114 urtw_get_macaddr(struct urtw_softc *sc)
2119 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2122 sc->sc_bssid[0] = data & 0xff;
2123 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2124 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2127 sc->sc_bssid[2] = data & 0xff;
2128 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2129 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2132 sc->sc_bssid[4] = data & 0xff;
2133 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2139 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2141 #define URTW_READCMD_LEN 3
2143 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2146 /* NB: make sure the buffer is initialized */
2149 /* enable EPROM programming */
2150 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2151 DELAY(URTW_EPROM_DELAY);
2153 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2156 error = urtw_eprom_ck(sc);
2159 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2162 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2164 addrstr[0] = addr & (1 << 7);
2165 addrstr[1] = addr & (1 << 6);
2166 addrstr[2] = addr & (1 << 5);
2167 addrstr[3] = addr & (1 << 4);
2168 addrstr[4] = addr & (1 << 3);
2169 addrstr[5] = addr & (1 << 2);
2170 addrstr[6] = addr & (1 << 1);
2171 addrstr[7] = addr & (1 << 0);
2174 addrstr[0] = addr & (1 << 5);
2175 addrstr[1] = addr & (1 << 4);
2176 addrstr[2] = addr & (1 << 3);
2177 addrstr[3] = addr & (1 << 2);
2178 addrstr[4] = addr & (1 << 1);
2179 addrstr[5] = addr & (1 << 0);
2181 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2185 error = urtw_eprom_writebit(sc, 0);
2189 for (i = 0; i < 16; i++) {
2190 error = urtw_eprom_ck(sc);
2193 error = urtw_eprom_readbit(sc, &data16);
2197 (*data) |= (data16 << (15 - i));
2200 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2203 error = urtw_eprom_ck(sc);
2207 /* now disable EPROM programming */
2208 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2211 #undef URTW_READCMD_LEN
2215 urtw_eprom_cs(struct urtw_softc *sc, int able)
2220 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2221 if (able == URTW_EPROM_ENABLE)
2222 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2224 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2225 DELAY(URTW_EPROM_DELAY);
2231 urtw_eprom_ck(struct urtw_softc *sc)
2237 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2238 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2239 DELAY(URTW_EPROM_DELAY);
2241 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2242 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2243 DELAY(URTW_EPROM_DELAY);
2249 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2254 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2255 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2256 DELAY(URTW_EPROM_DELAY);
2263 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2268 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2270 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2272 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2273 DELAY(URTW_EPROM_DELAY);
2279 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2282 usb_error_t error = 0;
2284 for (i = 0; i < buflen; i++) {
2285 error = urtw_eprom_writebit(sc, buf[i]);
2288 error = urtw_eprom_ck(sc);
2298 urtw_get_txpwr(struct urtw_softc *sc)
2304 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2307 sc->sc_txpwr_cck_base = data & 0xf;
2308 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2310 for (i = 1, j = 0; i < 6; i += 2, j++) {
2311 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2314 sc->sc_txpwr_cck[i] = data & 0xf;
2315 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2316 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2317 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2319 for (i = 1, j = 0; i < 4; i += 2, j++) {
2320 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2323 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2324 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2325 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2326 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2328 if (sc->sc_flags & URTW_RTL8187B) {
2329 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2332 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2333 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2334 error = urtw_eprom_read32(sc, 0x0a, &data);
2337 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2338 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2339 error = urtw_eprom_read32(sc, 0x1c, &data);
2342 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2343 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2344 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2345 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2347 for (i = 1, j = 0; i < 4; i += 2, j++) {
2348 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2352 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2353 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2354 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2355 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2364 urtw_get_rfchip(struct urtw_softc *sc)
2371 if (sc->sc_flags & URTW_RTL8187B) {
2372 urtw_read8_m(sc, 0xe1, &data8);
2375 sc->sc_flags |= URTW_RTL8187B_REV_B;
2378 sc->sc_flags |= URTW_RTL8187B_REV_D;
2381 sc->sc_flags |= URTW_RTL8187B_REV_E;
2384 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2385 sc->sc_flags |= URTW_RTL8187B_REV_B;
2389 urtw_read32_m(sc, URTW_TX_CONF, &data);
2390 switch (data & URTW_TX_HWMASK) {
2391 case URTW_TX_R8187vD_B:
2392 sc->sc_flags |= URTW_RTL8187B;
2394 case URTW_TX_R8187vD:
2397 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2398 data & URTW_TX_HWMASK);
2403 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2406 switch (data & 0xff) {
2407 case URTW_EPROM_RFCHIPID_RTL8225U:
2408 error = urtw_8225_isv2(sc, &ret);
2412 sc->sc_rf_init = urtw_8225_rf_init;
2413 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2414 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2415 sc->sc_rf_stop = urtw_8225_rf_stop;
2417 sc->sc_rf_init = urtw_8225v2_rf_init;
2418 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2419 sc->sc_rf_stop = urtw_8225_rf_stop;
2421 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2422 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2424 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2425 sc->sc_rf_init = urtw_8225v2b_rf_init;
2426 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2427 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2428 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2429 sc->sc_rf_stop = urtw_8225_rf_stop;
2432 panic("unsupported RF chip %d\n", data & 0xff);
2436 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2437 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2438 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2440 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2441 (data8 == 1) ? "d" : "e") : "none");
2449 urtw_led_init(struct urtw_softc *sc)
2454 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2455 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2459 switch (rev & URTW_EPROM_CID_MASK) {
2460 case URTW_EPROM_CID_ALPHA0:
2461 sc->sc_strategy = URTW_SW_LED_MODE1;
2463 case URTW_EPROM_CID_SERCOMM_PS:
2464 sc->sc_strategy = URTW_SW_LED_MODE3;
2466 case URTW_EPROM_CID_HW_LED:
2467 sc->sc_strategy = URTW_HW_LED;
2469 case URTW_EPROM_CID_RSVD0:
2470 case URTW_EPROM_CID_RSVD1:
2472 sc->sc_strategy = URTW_SW_LED_MODE0;
2476 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2484 urtw_8225_rf_init(struct urtw_softc *sc)
2486 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2491 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2495 error = urtw_8225_usb_init(sc);
2499 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2500 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2501 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2502 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2504 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2507 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2508 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2512 error = urtw_8185_rf_pins_enable(sc);
2515 usb_pause_mtx(&sc->sc_mtx, 1000);
2517 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2518 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2519 urtw_8225_rf_part1[i].val);
2520 usb_pause_mtx(&sc->sc_mtx, 1);
2522 usb_pause_mtx(&sc->sc_mtx, 100);
2524 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2525 usb_pause_mtx(&sc->sc_mtx, 200);
2527 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2528 usb_pause_mtx(&sc->sc_mtx, 200);
2530 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2532 for (i = 0; i < 95; i++) {
2533 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2534 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2538 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2540 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2542 for (i = 0; i < 128; i++) {
2543 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2544 usb_pause_mtx(&sc->sc_mtx, 1);
2545 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2546 usb_pause_mtx(&sc->sc_mtx, 1);
2549 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2550 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2551 urtw_8225_rf_part2[i].val);
2552 usb_pause_mtx(&sc->sc_mtx, 1);
2555 error = urtw_8225_setgain(sc, 4);
2559 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2560 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2561 urtw_8225_rf_part3[i].val);
2562 usb_pause_mtx(&sc->sc_mtx, 1);
2565 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2567 error = urtw_8225_set_txpwrlvl(sc, 1);
2571 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2572 usb_pause_mtx(&sc->sc_mtx, 1);
2573 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2574 usb_pause_mtx(&sc->sc_mtx, 1);
2576 /* TX ant A, 0x0 for B */
2577 error = urtw_8185_tx_antenna(sc, 0x3);
2580 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2582 error = urtw_8225_rf_set_chan(sc, 1);
2589 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2591 usb_error_t error = 0;
2593 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2599 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2603 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2604 usb_pause_mtx(&sc->sc_mtx, 1);
2610 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2614 return urtw_8187_write_phy(sc, addr, data);
2618 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2622 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2626 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2631 phyw = ((data << 8) | (addr | 0x80));
2632 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2633 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2634 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2635 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2636 usb_pause_mtx(&sc->sc_mtx, 1);
2642 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2646 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2647 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2648 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2649 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2655 urtw_8225_usb_init(struct urtw_softc *sc)
2660 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2661 urtw_write8_m(sc, URTW_GPIO, 0);
2662 error = urtw_read8e(sc, 0x53, &data);
2665 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2668 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2669 urtw_write8_m(sc, URTW_GPIO, 0x20);
2670 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2672 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2673 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2674 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2676 usb_pause_mtx(&sc->sc_mtx, 500);
2682 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2684 uint16_t d80, d82, d84;
2687 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2688 d80 &= URTW_RF_PINS_MAGIC1;
2689 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2690 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2691 d84 &= URTW_RF_PINS_MAGIC2;
2692 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2693 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2696 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2698 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2701 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2705 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2707 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2708 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2709 usb_pause_mtx(&sc->sc_mtx, 2);
2714 /* XXX why we should allocalte memory buffer instead of using memory stack? */
2716 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2721 struct usb_device_request *req;
2722 usb_error_t error = 0;
2725 req = (usb_device_request_t *)malloc(sizeof(usb_device_request_t),
2726 M_80211_VAP, M_NOWAIT | M_ZERO);
2728 device_printf(sc->sc_dev, "could not allocate a memory\n");
2731 buf = (uint8_t *)malloc(2, M_80211_VAP, M_NOWAIT | M_ZERO);
2733 device_printf(sc->sc_dev, "could not allocate a memory\n");
2737 req->bmRequestType = UT_WRITE_VENDOR_DEVICE;
2738 req->bRequest = URTW_8187_SETREGS_REQ;
2739 USETW(req->wValue, addr);
2740 USETW(req->wIndex, index);
2741 USETW(req->wLength, sizeof(uint16_t));
2742 buf[0] = (data16 & 0x00ff);
2743 buf[1] = (data16 & 0xff00) >> 8;
2745 error = urtw_do_request(sc, req, buf);
2747 free(buf, M_80211_VAP);
2748 fail1: free(req, M_80211_VAP);
2749 fail0: return (error);
2753 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2757 error = urtw_8225_set_txpwrlvl(sc, chan);
2760 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2761 usb_pause_mtx(&sc->sc_mtx, 10);
2767 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2771 if (sens < 0 || sens > 6)
2776 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2779 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2782 error = urtw_8225_setgain(sc, sens);
2786 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2793 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2796 uint8_t *cck_pwltable;
2797 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2798 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2799 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2802 cck_pwrlvl_max = 11;
2803 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2804 ofdm_pwrlvl_min = 10;
2806 /* CCK power setting */
2807 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2808 idx = cck_pwrlvl % 6;
2809 set = cck_pwrlvl / 6;
2810 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2811 urtw_8225_txpwr_cck;
2813 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2814 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2815 for (i = 0; i < 8; i++) {
2816 urtw_8187_write_phy_cck(sc, 0x44 + i,
2817 cck_pwltable[idx * 8 + i]);
2819 usb_pause_mtx(&sc->sc_mtx, 1);
2821 /* OFDM power setting */
2822 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2823 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2824 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2826 idx = ofdm_pwrlvl % 6;
2827 set = ofdm_pwrlvl / 6;
2829 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2832 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2833 urtw_8187_write_phy_ofdm(sc, 6, 0);
2834 urtw_8187_write_phy_ofdm(sc, 8, 0);
2836 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2837 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2838 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2839 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2840 usb_pause_mtx(&sc->sc_mtx, 1);
2847 urtw_8225_rf_stop(struct urtw_softc *sc)
2852 urtw_8225_write(sc, 0x4, 0x1f);
2854 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2858 urtw_read8_m(sc, URTW_CONFIG3, &data);
2859 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2860 if (sc->sc_flags & URTW_RTL8187B) {
2861 urtw_write32_m(sc, URTW_ANAPARAM2,
2862 URTW_8187B_8225_ANAPARAM2_OFF);
2863 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2864 urtw_write32_m(sc, URTW_ANAPARAM3,
2865 URTW_8187B_8225_ANAPARAM3_OFF);
2867 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2868 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2871 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2872 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2881 urtw_8225v2_rf_init(struct urtw_softc *sc)
2883 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2889 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2893 error = urtw_8225_usb_init(sc);
2897 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2898 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2899 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2900 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2902 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2905 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2906 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2910 error = urtw_8185_rf_pins_enable(sc);
2914 usb_pause_mtx(&sc->sc_mtx, 500);
2916 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2917 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2918 urtw_8225v2_rf_part1[i].val);
2920 usb_pause_mtx(&sc->sc_mtx, 50);
2923 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2925 for (i = 0; i < 95; i++) {
2926 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2927 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2928 urtw_8225v2_rxgain[i]);
2932 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2934 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2936 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2938 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2939 usb_pause_mtx(&sc->sc_mtx, 100);
2941 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2942 usb_pause_mtx(&sc->sc_mtx, 100);
2944 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2947 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2948 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2949 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2951 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2952 usb_pause_mtx(&sc->sc_mtx, 100);
2954 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2955 usb_pause_mtx(&sc->sc_mtx, 50);
2956 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2959 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2960 device_printf(sc->sc_dev, "RF calibration failed\n");
2962 usb_pause_mtx(&sc->sc_mtx, 100);
2965 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2966 for (i = 0; i < 128; i++) {
2967 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2968 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2971 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2972 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2973 urtw_8225v2_rf_part2[i].val);
2976 error = urtw_8225v2_setgain(sc, 4);
2980 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2981 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2982 urtw_8225v2_rf_part3[i].val);
2985 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2987 error = urtw_8225v2_set_txpwrlvl(sc, 1);
2991 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2992 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2994 /* TX ant A, 0x0 for B */
2995 error = urtw_8185_tx_antenna(sc, 0x3);
2998 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
3000 error = urtw_8225_rf_set_chan(sc, 1);
3007 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3011 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3015 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3016 usb_pause_mtx(&sc->sc_mtx, 10);
3022 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3026 uint8_t rlen = 12, wlen = 6;
3027 uint16_t o1, o2, o3, tmp;
3028 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3029 uint32_t mask = 0x80000000, value = 0;
3032 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3033 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3034 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3035 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3036 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3037 o1 &= ~URTW_RF_PINS_MAGIC4;
3038 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3040 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3043 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3044 bit = ((d2w & mask) != 0) ? 1 : 0;
3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3048 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3049 URTW_BB_HOST_BANG_CLK);
3051 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3052 URTW_BB_HOST_BANG_CLK);
3057 bit = ((d2w & mask) != 0) ? 1 : 0;
3058 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3059 URTW_BB_HOST_BANG_CLK);
3061 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3062 URTW_BB_HOST_BANG_CLK);
3064 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3067 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3068 URTW_BB_HOST_BANG_CLK);
3070 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3072 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3076 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3077 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3078 o1 | URTW_BB_HOST_BANG_RW);
3080 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3081 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3083 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3084 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3086 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3087 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3090 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3091 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3092 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3093 o1 | URTW_BB_HOST_BANG_RW);
3097 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3098 URTW_BB_HOST_BANG_RW);
3101 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3102 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3103 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3113 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3116 uint8_t *cck_pwrtable;
3117 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3118 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3119 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3122 /* CCK power setting */
3123 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3124 cck_pwrlvl += sc->sc_txpwr_cck_base;
3125 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3126 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3127 urtw_8225v2_txpwr_cck;
3129 for (i = 0; i < 8; i++)
3130 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3132 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3133 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3134 usb_pause_mtx(&sc->sc_mtx, 1);
3136 /* OFDM power setting */
3137 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3138 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3139 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3140 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3142 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3146 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3147 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3148 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3149 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3150 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3152 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3153 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3154 usb_pause_mtx(&sc->sc_mtx, 1);
3160 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3166 gainp = urtw_8225v2_gain_bg;
3167 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3168 usb_pause_mtx(&sc->sc_mtx, 1);
3169 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3170 usb_pause_mtx(&sc->sc_mtx, 1);
3171 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3172 usb_pause_mtx(&sc->sc_mtx, 1);
3173 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3174 usb_pause_mtx(&sc->sc_mtx, 1);
3180 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3187 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3188 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3189 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3190 usb_pause_mtx(&sc->sc_mtx, 500);
3192 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3193 URTW_8225_ADDR_0_DATA_MAGIC1);
3195 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3198 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3201 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3204 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3208 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3209 URTW_8225_ADDR_0_DATA_MAGIC2);
3215 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3217 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
3222 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3227 * initialize extra registers on 8187
3229 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3232 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3233 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3234 urtw_write8_m(sc, URTW_CW_CONF, data8);
3237 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3238 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3239 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3241 /* Auto Rate Fallback Control */
3242 #define URTW_ARFR 0x1e0
3243 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3244 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3245 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3246 data8 | URTW_RATE_FALLBACK_ENABLE);
3248 urtw_read8_m(sc, URTW_MSR, &data8);
3249 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3250 urtw_read8_m(sc, URTW_MSR, &data8);
3251 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3252 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3254 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3255 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3256 #define URTW_FEMR_FOR_8187B 0x1d4
3257 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3260 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3261 data8 = (data8 & 0x3f) | 0x80;
3262 urtw_write8_m(sc, URTW_CONFIG1, data8);
3264 /* applying MAC address again. */
3265 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
3266 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
3268 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3272 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3277 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3278 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3279 urtw_8225v2b_rf_part1[i].val);
3280 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3281 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3282 urtw_write32_m(sc, 0x1f0, 0);
3283 urtw_write32_m(sc, 0x1f4, 0);
3284 urtw_write8_m(sc, 0x1f8, 0);
3285 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3287 #define URTW_RFSW_CTRL 0x272
3288 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3293 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3296 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3297 urtw_write8_m(sc, URTW_CONFIG3,
3298 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3300 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3304 /* setup RFE initial timing */
3305 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3306 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3307 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3308 usb_pause_mtx(&sc->sc_mtx, 1100);
3310 for (i = 0; i < N(urtw_8225v2b_rf_part0); i++) {
3311 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3312 urtw_8225v2b_rf_part0[i].val);
3313 usb_pause_mtx(&sc->sc_mtx, 1);
3315 urtw_8225_write(sc, 0x00, 0x01b7);
3317 for (i = 0; i < 95; i++) {
3318 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3319 usb_pause_mtx(&sc->sc_mtx, 1);
3320 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3321 urtw_8225v2b_rxgain[i]);
3322 usb_pause_mtx(&sc->sc_mtx, 1);
3325 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3326 usb_pause_mtx(&sc->sc_mtx, 1);
3327 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3328 usb_pause_mtx(&sc->sc_mtx, 1);
3329 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3330 usb_pause_mtx(&sc->sc_mtx, 1);
3331 usb_pause_mtx(&sc->sc_mtx, 3000);
3332 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3333 usb_pause_mtx(&sc->sc_mtx, 2000);
3334 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3335 usb_pause_mtx(&sc->sc_mtx, 1);
3336 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3337 usb_pause_mtx(&sc->sc_mtx, 1);
3339 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3340 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3341 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3343 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3344 for (i = 0; i < 128; i++) {
3345 uint32_t addr, data;
3347 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3348 addr = ((i + 0x80) << 8) | 0x0000008e;
3350 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3351 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3352 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3354 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3356 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3357 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3359 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3360 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3361 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3362 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3364 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3365 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3366 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3367 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3375 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3379 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3383 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3384 usb_pause_mtx(&sc->sc_mtx, 10);
3390 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3393 uint8_t *cck_pwrtable;
3394 uint8_t cck_pwrlvl_max = 15;
3395 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3396 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3399 /* CCK power setting */
3400 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3401 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3402 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3403 cck_pwrlvl += sc->sc_txpwr_cck_base;
3404 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3405 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3406 urtw_8225v2b_txpwr_cck;
3408 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3409 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3410 ((cck_pwrlvl <= 11) ? 8 : 16);
3412 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3413 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3415 for (i = 0; i < 8; i++)
3416 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3418 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3419 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3420 usb_pause_mtx(&sc->sc_mtx, 1);
3422 /* OFDM power setting */
3423 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3424 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3425 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3426 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3427 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3429 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3430 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3432 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3433 if (ofdm_pwrlvl <= 11) {
3434 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3435 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3437 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3438 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3441 if (ofdm_pwrlvl <= 11) {
3442 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3443 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3444 } else if (ofdm_pwrlvl <= 17) {
3445 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3446 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3448 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3449 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3452 usb_pause_mtx(&sc->sc_mtx, 1);
3458 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3460 struct usb_device_request req;
3463 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3464 req.bRequest = URTW_8187_GETREGS_REQ;
3465 USETW(req.wValue, val | 0xfe00);
3466 USETW(req.wIndex, 0);
3467 USETW(req.wLength, sizeof(uint8_t));
3469 error = urtw_do_request(sc, &req, data);
3474 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3476 struct usb_device_request req;
3478 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3479 req.bRequest = URTW_8187_SETREGS_REQ;
3480 USETW(req.wValue, val | 0xfe00);
3481 USETW(req.wIndex, 0);
3482 USETW(req.wLength, sizeof(uint8_t));
3484 return (urtw_do_request(sc, &req, &data));
3488 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3493 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3497 urtw_read8_m(sc, URTW_CONFIG3, &data);
3498 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3499 urtw_write32_m(sc, URTW_ANAPARAM, val);
3500 urtw_read8_m(sc, URTW_CONFIG3, &data);
3501 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3503 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3511 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3516 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3520 urtw_read8_m(sc, URTW_CONFIG3, &data);
3521 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3522 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3523 urtw_read8_m(sc, URTW_CONFIG3, &data);
3524 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3526 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3534 urtw_intr_enable(struct urtw_softc *sc)
3538 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3544 urtw_intr_disable(struct urtw_softc *sc)
3548 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3554 urtw_reset(struct urtw_softc *sc)
3559 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3562 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3566 error = urtw_intr_disable(sc);
3569 usb_pause_mtx(&sc->sc_mtx, 100);
3571 error = urtw_write8e(sc, 0x18, 0x10);
3574 error = urtw_write8e(sc, 0x18, 0x11);
3577 error = urtw_write8e(sc, 0x18, 0x00);
3580 usb_pause_mtx(&sc->sc_mtx, 100);
3582 urtw_read8_m(sc, URTW_CMD, &data);
3583 data = (data & 0x2) | URTW_CMD_RST;
3584 urtw_write8_m(sc, URTW_CMD, data);
3585 usb_pause_mtx(&sc->sc_mtx, 100);
3587 urtw_read8_m(sc, URTW_CMD, &data);
3588 if (data & URTW_CMD_RST) {
3589 device_printf(sc->sc_dev, "reset timeout\n");
3593 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3596 usb_pause_mtx(&sc->sc_mtx, 100);
3598 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3601 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3609 urtw_led_ctl(struct urtw_softc *sc, int mode)
3611 usb_error_t error = 0;
3613 switch (sc->sc_strategy) {
3614 case URTW_SW_LED_MODE0:
3615 error = urtw_led_mode0(sc, mode);
3617 case URTW_SW_LED_MODE1:
3618 error = urtw_led_mode1(sc, mode);
3620 case URTW_SW_LED_MODE2:
3621 error = urtw_led_mode2(sc, mode);
3623 case URTW_SW_LED_MODE3:
3624 error = urtw_led_mode3(sc, mode);
3627 panic("unsupported LED mode %d\n", sc->sc_strategy);
3635 urtw_led_mode0(struct urtw_softc *sc, int mode)
3639 case URTW_LED_CTL_POWER_ON:
3640 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3642 case URTW_LED_CTL_TX:
3643 if (sc->sc_gpio_ledinprogress == 1)
3646 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3647 sc->sc_gpio_blinktime = 2;
3649 case URTW_LED_CTL_LINK:
3650 sc->sc_gpio_ledstate = URTW_LED_ON;
3653 panic("unsupported LED mode 0x%x", mode);
3657 switch (sc->sc_gpio_ledstate) {
3659 if (sc->sc_gpio_ledinprogress != 0)
3661 urtw_led_on(sc, URTW_LED_GPIO);
3663 case URTW_LED_BLINK_NORMAL:
3664 if (sc->sc_gpio_ledinprogress != 0)
3666 sc->sc_gpio_ledinprogress = 1;
3667 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3668 URTW_LED_OFF : URTW_LED_ON;
3669 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3671 case URTW_LED_POWER_ON_BLINK:
3672 urtw_led_on(sc, URTW_LED_GPIO);
3673 usb_pause_mtx(&sc->sc_mtx, 100);
3674 urtw_led_off(sc, URTW_LED_GPIO);
3677 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3684 urtw_led_mode1(struct urtw_softc *sc, int mode)
3687 return (USB_ERR_INVAL);
3691 urtw_led_mode2(struct urtw_softc *sc, int mode)
3694 return (USB_ERR_INVAL);
3698 urtw_led_mode3(struct urtw_softc *sc, int mode)
3701 return (USB_ERR_INVAL);
3705 urtw_led_on(struct urtw_softc *sc, int type)
3709 if (type == URTW_LED_GPIO) {
3710 switch (sc->sc_gpio_ledpin) {
3711 case URTW_LED_PIN_GPIO0:
3712 urtw_write8_m(sc, URTW_GPIO, 0x01);
3713 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3716 panic("unsupported LED PIN type 0x%x",
3717 sc->sc_gpio_ledpin);
3721 panic("unsupported LED type 0x%x", type);
3725 sc->sc_gpio_ledon = 1;
3731 urtw_led_off(struct urtw_softc *sc, int type)
3735 if (type == URTW_LED_GPIO) {
3736 switch (sc->sc_gpio_ledpin) {
3737 case URTW_LED_PIN_GPIO0:
3738 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3740 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3743 panic("unsupported LED PIN type 0x%x",
3744 sc->sc_gpio_ledpin);
3748 panic("unsupported LED type 0x%x", type);
3752 sc->sc_gpio_ledon = 0;
3759 urtw_led_ch(void *arg)
3761 struct urtw_softc *sc = arg;
3762 struct ifnet *ifp = sc->sc_ifp;
3763 struct ieee80211com *ic = ifp->if_l2com;
3765 ieee80211_runtask(ic, &sc->sc_led_task);
3769 urtw_ledtask(void *arg, int pending)
3771 struct urtw_softc *sc = arg;
3773 if (sc->sc_strategy != URTW_SW_LED_MODE0)
3774 panic("could not process a LED strategy 0x%x", sc->sc_strategy);
3782 urtw_led_blink(struct urtw_softc *sc)
3787 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3788 error = urtw_led_on(sc, URTW_LED_GPIO);
3790 error = urtw_led_off(sc, URTW_LED_GPIO);
3791 sc->sc_gpio_blinktime--;
3792 if (sc->sc_gpio_blinktime == 0)
3795 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3796 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3797 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3801 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3802 sc->sc_gpio_ledon == 0)
3803 error = urtw_led_on(sc, URTW_LED_GPIO);
3804 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3805 sc->sc_gpio_ledon == 1)
3806 error = urtw_led_off(sc, URTW_LED_GPIO);
3808 sc->sc_gpio_blinktime = 0;
3809 sc->sc_gpio_ledinprogress = 0;
3813 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3814 URTW_LED_ON : URTW_LED_OFF;
3816 switch (sc->sc_gpio_ledstate) {
3817 case URTW_LED_BLINK_NORMAL:
3818 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3821 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3828 urtw_rx_enable(struct urtw_softc *sc)
3833 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3834 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3836 error = urtw_rx_setconf(sc);
3840 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3841 urtw_read8_m(sc, URTW_CMD, &data);
3842 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3849 urtw_tx_enable(struct urtw_softc *sc)
3855 if (sc->sc_flags & URTW_RTL8187B) {
3856 urtw_read32_m(sc, URTW_TX_CONF, &data);
3857 data &= ~URTW_TX_LOOPBACK_MASK;
3858 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3859 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3860 data &= ~URTW_TX_SWPLCPLEN;
3861 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3862 (7 << 8) | /* short retry limit */
3863 (7 << 0) | /* long retry limit */
3864 (7 << 21); /* MAX TX DMA */
3865 urtw_write32_m(sc, URTW_TX_CONF, data);
3867 urtw_read8_m(sc, URTW_MSR, &data8);
3868 data8 |= URTW_MSR_LINK_ENEDCA;
3869 urtw_write8_m(sc, URTW_MSR, data8);
3873 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3874 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3875 urtw_write8_m(sc, URTW_CW_CONF, data8);
3877 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3878 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3879 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3880 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3881 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3883 urtw_read32_m(sc, URTW_TX_CONF, &data);
3884 data &= ~URTW_TX_LOOPBACK_MASK;
3885 data |= URTW_TX_LOOPBACK_NONE;
3886 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3887 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3888 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3889 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3890 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3891 data &= ~URTW_TX_SWPLCPLEN;
3892 data |= URTW_TX_NOICV;
3893 urtw_write32_m(sc, URTW_TX_CONF, data);
3895 urtw_read8_m(sc, URTW_CMD, &data8);
3896 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3902 urtw_rx_setconf(struct urtw_softc *sc)
3904 struct ifnet *ifp = sc->sc_ifp;
3905 struct ieee80211com *ic = ifp->if_l2com;
3909 urtw_read32_m(sc, URTW_RX, &data);
3910 data = data &~ URTW_RX_FILTER_MASK;
3911 if (sc->sc_flags & URTW_RTL8187B) {
3912 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3913 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3914 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3915 URTW_RX_FIFO_THRESHOLD_NONE |
3916 URTW_MAX_RX_DMA_2048 |
3917 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3919 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3920 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3922 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3923 data = data | URTW_RX_FILTER_ICVERR;
3924 data = data | URTW_RX_FILTER_PWR;
3926 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3927 data = data | URTW_RX_FILTER_CRCERR;
3929 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3930 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3931 data = data | URTW_RX_FILTER_ALLMAC;
3933 data = data | URTW_RX_FILTER_NICMAC;
3934 data = data | URTW_RX_CHECK_BSSID;
3937 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3938 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3939 URTW_RX_AUTORESETPHY;
3940 data = data &~ URTW_MAX_RX_DMA_MASK;
3941 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3944 urtw_write32_m(sc, URTW_RX, data);
3949 static struct mbuf *
3950 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3953 int actlen, flen, rssi;
3954 struct ieee80211_frame *wh;
3955 struct mbuf *m, *mnew;
3956 struct urtw_softc *sc = data->sc;
3957 struct ifnet *ifp = sc->sc_ifp;
3958 struct ieee80211com *ic = ifp->if_l2com;
3959 uint8_t noise = 0, rate;
3961 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3963 if (actlen < (int)URTW_MIN_RXBUFSZ) {
3968 if (sc->sc_flags & URTW_RTL8187B) {
3969 struct urtw_8187b_rxhdr *rx;
3971 rx = (struct urtw_8187b_rxhdr *)(data->buf +
3972 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
3973 flen = le32toh(rx->flag) & 0xfff;
3974 if (flen > actlen) {
3978 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3980 rssi = rx->rssi & URTW_RX_RSSI_MASK;
3983 struct urtw_8187l_rxhdr *rx;
3985 rx = (struct urtw_8187l_rxhdr *)(data->buf +
3986 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
3987 flen = le32toh(rx->flag) & 0xfff;
3988 if (flen > actlen) {
3993 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
3995 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
3999 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
4007 data->buf = mtod(mnew, uint8_t *);
4010 m->m_pkthdr.rcvif = ifp;
4011 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4013 if (ieee80211_radiotap_active(ic)) {
4014 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4016 /* XXX Are variables correct? */
4017 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4018 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4019 tap->wr_dbm_antsignal = (int8_t)rssi;
4022 wh = mtod(m, struct ieee80211_frame *);
4023 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4024 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4027 *nf_p = noise; /* XXX correct? */
4033 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4035 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4036 struct ifnet *ifp = sc->sc_ifp;
4037 struct ieee80211com *ic = ifp->if_l2com;
4038 struct ieee80211_frame *wh;
4039 struct ieee80211_node *ni;
4040 struct mbuf *m = NULL;
4041 struct urtw_data *data;
4045 URTW_ASSERT_LOCKED(sc);
4047 switch (USB_GET_STATE(xfer)) {
4048 case USB_ST_TRANSFERRED:
4049 data = STAILQ_FIRST(&sc->sc_rx_active);
4052 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4053 m = urtw_rxeof(xfer, data, &rssi, &nf);
4054 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4058 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4060 KASSERT(m == NULL, ("mbuf isn't NULL"));
4063 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4064 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4065 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4066 usbd_xfer_max_len(xfer));
4067 usbd_transfer_submit(xfer);
4070 * To avoid LOR we should unlock our private mutex here to call
4071 * ieee80211_input() because here is at the end of a USB
4072 * callback and safe to unlock.
4076 wh = mtod(m, struct ieee80211_frame *);
4077 ni = ieee80211_find_rxnode(ic,
4078 (struct ieee80211_frame_min *)wh);
4080 (void) ieee80211_input(ni, m, rssi, nf);
4081 /* node is no longer needed */
4082 ieee80211_free_node(ni);
4084 (void) ieee80211_input_all(ic, m, rssi, nf);
4090 /* needs it to the inactive queue due to a error. */
4091 data = STAILQ_FIRST(&sc->sc_rx_active);
4093 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4094 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4096 if (error != USB_ERR_CANCELLED) {
4097 usbd_xfer_set_stall(xfer);
4105 #define URTW_STATUS_TYPE_TXCLOSE 1
4106 #define URTW_STATUS_TYPE_BEACON_INTR 0
4109 urtw_txstatus_eof(struct usb_xfer *xfer)
4111 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4112 struct ifnet *ifp = sc->sc_ifp;
4113 int actlen, type, pktretry, seq;
4116 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4118 if (actlen != sizeof(uint64_t))
4121 val = le64toh(sc->sc_txstatus);
4122 type = (val >> 30) & 0x3;
4123 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4124 pktretry = val & 0xff;
4125 seq = (val >> 16) & 0xff;
4126 if (pktretry == URTW_TX_MAXRETRY)
4128 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4134 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4136 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4137 struct ifnet *ifp = sc->sc_ifp;
4139 URTW_ASSERT_LOCKED(sc);
4141 switch (USB_GET_STATE(xfer)) {
4142 case USB_ST_TRANSFERRED:
4143 urtw_txstatus_eof(xfer);
4147 usbd_xfer_set_frame_data(xfer, 0, &sc->sc_txstatus,
4149 usbd_transfer_submit(xfer);
4152 if (error != USB_ERR_CANCELLED) {
4153 usbd_xfer_set_stall(xfer);
4162 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4164 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4165 struct ifnet *ifp = sc->sc_ifp;
4168 URTW_ASSERT_LOCKED(sc);
4171 * Do any tx complete callback. Note this must be done before releasing
4172 * the node reference.
4176 if (m->m_flags & M_TXCB) {
4178 ieee80211_process_callback(data->ni, m, 0);
4184 ieee80211_free_node(data->ni);
4189 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4193 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4195 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4196 struct ifnet *ifp = sc->sc_ifp;
4197 struct urtw_data *data;
4199 URTW_ASSERT_LOCKED(sc);
4201 switch (USB_GET_STATE(xfer)) {
4202 case USB_ST_TRANSFERRED:
4203 data = STAILQ_FIRST(&sc->sc_tx_active);
4206 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4207 urtw_txeof(xfer, data);
4208 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4212 data = STAILQ_FIRST(&sc->sc_tx_pending);
4214 DPRINTF(sc, URTW_DEBUG_XMIT,
4215 "%s: empty pending queue\n", __func__);
4218 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4219 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4221 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4222 usbd_transfer_submit(xfer);
4229 data = STAILQ_FIRST(&sc->sc_tx_active);
4232 if (data->ni != NULL) {
4233 ieee80211_free_node(data->ni);
4237 if (error != USB_ERR_CANCELLED) {
4238 usbd_xfer_set_stall(xfer);
4245 static struct urtw_data *
4246 _urtw_getbuf(struct urtw_softc *sc)
4248 struct urtw_data *bf;
4250 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4252 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4256 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4257 "out of xmit buffers");
4261 static struct urtw_data *
4262 urtw_getbuf(struct urtw_softc *sc)
4264 struct urtw_data *bf;
4266 URTW_ASSERT_LOCKED(sc);
4268 bf = _urtw_getbuf(sc);
4270 struct ifnet *ifp = sc->sc_ifp;
4272 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4273 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4279 urtw_isbmode(uint16_t rate)
4282 return ((rate <= 22 && rate != 12 && rate != 18) ||
4283 rate == 44) ? (1) : (0);
4287 urtw_rate2dbps(uint16_t rate)
4307 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4308 uint8_t ismgt, uint8_t isshort)
4310 uint16_t ceiling, frametime, n_dbps;
4312 if (urtw_isbmode(rate)) {
4313 if (ismgt || !isshort || rate == 2)
4314 frametime = (uint16_t)(144 + 48 +
4315 (framelen * 8 / (rate / 2)));
4317 frametime = (uint16_t)(72 + 24 +
4318 (framelen * 8 / (rate / 2)));
4319 if ((framelen * 8 % (rate / 2)) != 0)
4322 n_dbps = urtw_rate2dbps(rate);
4323 ceiling = (16 + 8 * framelen + 6) / n_dbps
4324 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4325 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4331 * Callback from the 802.11 layer to update the
4332 * slot time based on the current setting.
4335 urtw_updateslot(struct ifnet *ifp)
4337 struct urtw_softc *sc = ifp->if_softc;
4338 struct ieee80211com *ic = ifp->if_l2com;
4340 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4344 urtw_updateslottask(void *arg, int pending)
4346 struct urtw_softc *sc = arg;
4347 struct ifnet *ifp = sc->sc_ifp;
4348 struct ieee80211com *ic = ifp->if_l2com;
4351 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4355 if (sc->sc_flags & URTW_RTL8187B) {
4356 urtw_write8_m(sc, URTW_SIFS, 0x22);
4357 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4358 urtw_write8_m(sc, URTW_SLOT, 0x9);
4360 urtw_write8_m(sc, URTW_SLOT, 0x14);
4361 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4362 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4364 urtw_write8_m(sc, URTW_SIFS, 0x22);
4365 if (sc->sc_state == IEEE80211_S_ASSOC &&
4366 ic->ic_flags & IEEE80211_F_SHSLOT)
4367 urtw_write8_m(sc, URTW_SLOT, 0x9);
4369 urtw_write8_m(sc, URTW_SLOT, 0x14);
4370 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4371 urtw_write8_m(sc, URTW_DIFS, 0x14);
4372 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4373 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4375 urtw_write8_m(sc, URTW_DIFS, 0x24);
4376 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4377 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4385 urtw_sysctl_node(struct urtw_softc *sc)
4387 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4388 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4389 struct sysctl_ctx_list *ctx;
4390 struct sysctl_oid_list *child, *parent;
4391 struct sysctl_oid *tree;
4392 struct urtw_stats *stats = &sc->sc_stats;
4394 ctx = device_get_sysctl_ctx(sc->sc_dev);
4395 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4397 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4398 NULL, "URTW statistics");
4399 parent = SYSCTL_CHILDREN(tree);
4401 /* Tx statistics. */
4402 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
4403 NULL, "Tx MAC statistics");
4404 child = SYSCTL_CHILDREN(tree);
4405 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4407 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4409 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4411 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4413 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4415 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4417 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4419 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4421 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4423 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4425 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4427 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4429 #undef URTW_SYSCTL_STAT_ADD32
4432 static device_method_t urtw_methods[] = {
4433 DEVMETHOD(device_probe, urtw_match),
4434 DEVMETHOD(device_attach, urtw_attach),
4435 DEVMETHOD(device_detach, urtw_detach),
4438 static driver_t urtw_driver = {
4440 .methods = urtw_methods,
4441 .size = sizeof(struct urtw_softc)
4443 static devclass_t urtw_devclass;
4445 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0);
4446 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4447 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4448 MODULE_VERSION(urtw, 1);