3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
35 #define VGE_JUMBO_MTU 9000
37 #define VGE_TX_DESC_CNT 256
38 #define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */
39 #define VGE_TX_RING_ALIGN 64
40 #define VGE_RX_RING_ALIGN 64
41 #define VGE_MAXTXSEGS 6
42 #define VGE_RX_BUF_ALIGN sizeof(uint64_t)
45 * VIA Velocity allows 64bit DMA addressing but high 16bits
46 * of the DMA address should be the same for Tx/Rx buffers.
47 * Because this condition can't be guaranteed vge(4) limit
48 * DMA address space to 48bits.
50 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
51 #define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR
53 #define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF
56 #define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
57 #define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
58 #define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT)
59 #define VGE_TX_DESC_DEC(x) \
60 ((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT))
61 #define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT)
62 #define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
63 #define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
64 #define VGE_BUFLEN(y) ((y) & 0x3FFF)
65 #define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16)
66 #define VGE_MIN_FRAMELEN 60
68 #define VGE_INT_HOLDOFF_TICK 20
69 #define VGE_INT_HOLDOFF_USEC(x) ((x) / VGE_INT_HOLDOFF_TICK)
70 #define VGE_INT_HOLDOFF_MIN 0
71 #define VGE_INT_HOLDOFF_MAX (255 * VGE_INT_HOLDOFF_TICK)
72 #define VGE_INT_HOLDOFF_DEFAULT 150
74 #define VGE_RX_COAL_PKT_MIN 1
75 #define VGE_RX_COAL_PKT_MAX VGE_RX_DESC_CNT
76 #define VGE_RX_COAL_PKT_DEFAULT 64
78 #define VGE_TX_COAL_PKT_MIN 1
79 #define VGE_TX_COAL_PKT_MAX VGE_TX_DESC_CNT
80 #define VGE_TX_COAL_PKT_DEFAULT 128
90 bus_dmamap_t tx_dmamap;
91 struct vge_tx_desc *tx_desc;
92 struct vge_txdesc *txd_prev;
97 bus_dmamap_t rx_dmamap;
98 struct vge_rx_desc *rx_desc;
99 struct vge_rxdesc *rxd_prev;
102 struct vge_chain_data{
103 bus_dma_tag_t vge_ring_tag;
104 bus_dma_tag_t vge_buffer_tag;
105 bus_dma_tag_t vge_tx_tag;
106 struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT];
107 bus_dma_tag_t vge_rx_tag;
108 struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT];
109 bus_dma_tag_t vge_tx_ring_tag;
110 bus_dmamap_t vge_tx_ring_map;
111 bus_dma_tag_t vge_rx_ring_tag;
112 bus_dmamap_t vge_rx_ring_map;
113 bus_dmamap_t vge_rx_sparemap;
121 struct mbuf *vge_head;
122 struct mbuf *vge_tail;
125 #define VGE_CHAIN_RESET(_sc) \
127 if ((_sc)->vge_cdata.vge_head != NULL) { \
128 m_freem((_sc)->vge_cdata.vge_head); \
129 (_sc)->vge_cdata.vge_head = NULL; \
130 (_sc)->vge_cdata.vge_tail = NULL; \
134 struct vge_ring_data {
135 struct vge_tx_desc *vge_tx_ring;
136 bus_addr_t vge_tx_ring_paddr;
137 struct vge_rx_desc *vge_rx_ring;
138 bus_addr_t vge_rx_ring_paddr;
141 struct vge_hw_stats {
143 uint32_t rx_good_frames;
144 uint32_t rx_fifo_oflows;
146 uint32_t rx_runts_errs;
148 uint32_t rx_pkts_65_127;
149 uint32_t rx_pkts_128_255;
150 uint32_t rx_pkts_256_511;
151 uint32_t rx_pkts_512_1023;
152 uint32_t rx_pkts_1024_1518;
153 uint32_t rx_pkts_1519_max;
154 uint32_t rx_pkts_1519_max_errs;
157 uint32_t rx_pause_frames;
158 uint32_t rx_alignerrs;
163 uint32_t tx_good_frames;
165 uint32_t tx_pkts_65_127;
166 uint32_t tx_pkts_128_255;
167 uint32_t tx_pkts_256_511;
168 uint32_t tx_pkts_512_1023;
169 uint32_t tx_pkts_1024_1518;
174 uint32_t tx_latecolls;
178 struct ifnet *vge_ifp; /* interface info */
180 struct resource *vge_res;
181 struct resource *vge_irq;
187 #define VGE_FLAG_PCIE 0x0001
188 #define VGE_FLAG_MSI 0x0002
189 #define VGE_FLAG_PMCAP 0x0004
190 #define VGE_FLAG_JUMBO 0x0008
191 #define VGE_FLAG_SUSPENDED 0x4000
192 #define VGE_FLAG_LINK 0x8000
200 struct callout vge_watchdog;
203 struct vge_chain_data vge_cdata;
204 struct vge_ring_data vge_rdata;
205 struct vge_hw_stats vge_stats;
208 #define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
209 #define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx)
210 #define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED)
213 * register space access macros
215 #define CSR_WRITE_STREAM_4(sc, reg, val) \
216 bus_write_stream_4(sc->vge_res, reg, val)
217 #define CSR_WRITE_4(sc, reg, val) \
218 bus_write_4(sc->vge_res, reg, val)
219 #define CSR_WRITE_2(sc, reg, val) \
220 bus_write_2(sc->vge_res, reg, val)
221 #define CSR_WRITE_1(sc, reg, val) \
222 bus_write_1(sc->vge_res, reg, val)
224 #define CSR_READ_4(sc, reg) \
225 bus_read_4(sc->vge_res, reg)
226 #define CSR_READ_2(sc, reg) \
227 bus_read_2(sc->vge_res, reg)
228 #define CSR_READ_1(sc, reg) \
229 bus_read_1(sc->vge_res, reg)
231 #define CSR_SETBIT_1(sc, reg, x) \
232 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
233 #define CSR_SETBIT_2(sc, reg, x) \
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
235 #define CSR_SETBIT_4(sc, reg, x) \
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
238 #define CSR_CLRBIT_1(sc, reg, x) \
239 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
240 #define CSR_CLRBIT_2(sc, reg, x) \
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
242 #define CSR_CLRBIT_4(sc, reg, x) \
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
245 #define VGE_RXCHUNK 4
246 #define VGE_TIMEOUT 10000