2 * Copyright (c) 2013 Tsubai Masanari
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 * $OpenBSD: src/sys/dev/pci/if_vmxreg.h,v 1.2 2013/06/12 01:07:33 uebayasi Exp $
27 uint64_t ucast_packets;
29 uint64_t mcast_packets;
31 uint64_t bcast_packets;
40 uint64_t ucast_packets;
42 uint64_t mcast_packets;
44 uint64_t bcast_packets;
50 /* Interrupt moderation levels */
51 #define UPT1_IMOD_NONE 0 /* No moderation */
52 #define UPT1_IMOD_HIGHEST 7 /* Least interrupts */
53 #define UPT1_IMOD_ADAPTIVE 8 /* Adaptive interrupt moderation */
55 /* Hardware features */
56 #define UPT1_F_CSUM 0x0001 /* Rx checksum verification */
57 #define UPT1_F_RSS 0x0002 /* Receive side scaling */
58 #define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */
59 #define UPT1_F_LRO 0x0008 /* Large receive offloading */
61 #define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* Interrupt mask */
62 #define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */
63 #define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* Ring1 Rx head */
64 #define VMXNET3_BAR0_RXH2(q) (0xA00 + (q) * 8) /* Ring2 Rx head */
65 #define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */
66 #define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */
67 #define VMXNET3_BAR1_DSL 0x010 /* Driver shared address low */
68 #define VMXNET3_BAR1_DSH 0x018 /* Driver shared address high */
69 #define VMXNET3_BAR1_CMD 0x020 /* Command */
70 #define VMXNET3_BAR1_MACL 0x028 /* MAC address low */
71 #define VMXNET3_BAR1_MACH 0x030 /* MAC address high */
72 #define VMXNET3_BAR1_INTR 0x038 /* Interrupt status */
73 #define VMXNET3_BAR1_EVENT 0x040 /* Event status */
75 #define VMXNET3_CMD_ENABLE 0xCAFE0000 /* Enable VMXNET3 */
76 #define VMXNET3_CMD_DISABLE 0xCAFE0001 /* Disable VMXNET3 */
77 #define VMXNET3_CMD_RESET 0xCAFE0002 /* Reset device */
78 #define VMXNET3_CMD_SET_RXMODE 0xCAFE0003 /* Set interface flags */
79 #define VMXNET3_CMD_SET_FILTER 0xCAFE0004 /* Set address filter */
80 #define VMXNET3_CMD_VLAN_FILTER 0xCAFE0005 /* Set VLAN filter */
81 #define VMXNET3_CMD_GET_STATUS 0xF00D0000 /* Get queue errors */
82 #define VMXNET3_CMD_GET_STATS 0xF00D0001 /* Get queue statistics */
83 #define VMXNET3_CMD_GET_LINK 0xF00D0002 /* Get link status */
84 #define VMXNET3_CMD_GET_MACL 0xF00D0003 /* Get MAC address low */
85 #define VMXNET3_CMD_GET_MACH 0xF00D0004 /* Get MAC address high */
86 #define VMXNET3_CMD_GET_INTRCFG 0xF00D0008 /* Get interrupt config */
88 #define VMXNET3_DMADESC_ALIGN 128
89 #define VMXNET3_INIT_GEN 1
91 struct vmxnet3_txdesc {
95 uint32_t gen:1; /* Generation */
97 uint32_t dtype:1; /* Descriptor type */
99 uint32_t offload_pos:14; /* Offloading position */
101 uint32_t hlen:10; /* Header len */
102 uint32_t offload_mode:2; /* Offloading mode */
103 uint32_t eop:1; /* End of packet */
104 uint32_t compreq:1; /* Completion request */
106 uint32_t vtag_mode:1; /* VLAN tag insertion mode */
107 uint32_t vtag:16; /* VLAN tag */
110 /* Offloading modes */
111 #define VMXNET3_OM_NONE 0
112 #define VMXNET3_OM_CSUM 2
113 #define VMXNET3_OM_TSO 3
115 struct vmxnet3_txcompdesc {
116 uint32_t eop_idx:12; /* EOP index in Tx ring */
127 struct vmxnet3_rxdesc {
131 uint32_t btype:1; /* Buffer type */
132 uint32_t dtype:1; /* Descriptor type */
140 #define VMXNET3_BTYPE_HEAD 0 /* Head only */
141 #define VMXNET3_BTYPE_BODY 1 /* Body only */
143 struct vmxnet3_rxcompdesc {
144 uint32_t rxd_idx:12; /* Rx descriptor index */
146 uint32_t eop:1; /* End of packet */
147 uint32_t sop:1; /* Start of packet */
150 uint32_t no_csum:1; /* No checksum calculated */
153 uint32_t rss_hash:32; /* RSS hash value */
157 uint32_t vlan:1; /* 802.1Q VLAN frame */
158 uint32_t vtag:16; /* VLAN tag */
161 uint32_t csum_ok:1; /* TCP/UDP checksum ok */
164 uint32_t ipcsum_ok:1; /* IP checksum OK */
167 uint32_t fragment:1; /* IP fragment */
168 uint32_t fcs:1; /* Frame CRC correct */
173 #define VMXNET3_REV1_MAGIC 0XBABEFEE1
175 #define VMXNET3_GOS_UNKNOWN 0x00
176 #define VMXNET3_GOS_LINUX 0x04
177 #define VMXNET3_GOS_WINDOWS 0x08
178 #define VMXNET3_GOS_SOLARIS 0x0C
179 #define VMXNET3_GOS_FREEBSD 0x10
180 #define VMXNET3_GOS_PXE 0x14
182 #define VMXNET3_GOS_32BIT 0x01
183 #define VMXNET3_GOS_64BIT 0x02
185 #define VMXNET3_MAX_TX_QUEUES 8
186 #define VMXNET3_MAX_RX_QUEUES 16
187 #define VMXNET3_MAX_INTRS \
188 (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
190 #define VMXNET3_ICTRL_DISABLE_ALL 0x01
192 #define VMXNET3_RXMODE_UCAST 0x01
193 #define VMXNET3_RXMODE_MCAST 0x02
194 #define VMXNET3_RXMODE_BCAST 0x04
195 #define VMXNET3_RXMODE_ALLMULTI 0x08
196 #define VMXNET3_RXMODE_PROMISC 0x10
198 #define VMXNET3_EVENT_RQERROR 0x01
199 #define VMXNET3_EVENT_TQERROR 0x02
200 #define VMXNET3_EVENT_LINK 0x04
201 #define VMXNET3_EVENT_DIC 0x08
202 #define VMXNET3_EVENT_DEBUG 0x10
204 #define VMXNET3_MIN_MTU 60
205 #define VMXNET3_MAX_MTU 9000
207 /* Interrupt mask mode. */
208 #define VMXNET3_IMM_AUTO 0x00
209 #define VMXNET3_IMM_ACTIVE 0x01
210 #define VMXNET3_IMM_LAZY 0x02
212 /* Interrupt type. */
213 #define VMXNET3_IT_AUTO 0x00
214 #define VMXNET3_IT_LEGACY 0x01
215 #define VMXNET3_IT_MSI 0x02
216 #define VMXNET3_IT_MSIX 0x03
218 struct vmxnet3_driver_shared {
223 uint32_t version; /* Driver version */
224 uint32_t guest; /* Guest OS */
225 uint32_t vmxnet3_revision; /* Supported VMXNET3 revision */
226 uint32_t upt_version; /* Supported UPT version */
227 uint64_t upt_features;
228 uint64_t driver_data;
229 uint64_t queue_shared;
230 uint32_t driver_data_len;
231 uint32_t queue_shared_len;
236 uint32_t reserved1[4];
238 /* Interrupt control */
242 uint8_t modlevel[VMXNET3_MAX_INTRS];
244 uint32_t reserved2[2];
246 /* Receive filter parameters */
248 uint16_t mcast_tablelen;
250 uint64_t mcast_table;
251 uint32_t vlan_filter[4096 / 32];
260 uint32_t reserved3[5];
263 struct vmxnet3_txq_shared {
266 uint32_t intr_threshold;
273 uint64_t driver_data;
275 uint32_t cmd_ring_len;
276 uint32_t data_ring_len;
277 uint32_t comp_ring_len;
278 uint32_t driver_data_len;
287 struct UPT1_TxStats stats;
292 struct vmxnet3_rxq_shared {
293 uint8_t update_rxhead;
297 uint64_t cmd_ring[2];
299 uint64_t driver_data;
301 uint32_t cmd_ring_len[2];
302 uint32_t comp_ring_len;
303 uint32_t driver_data_len;
311 struct UPT1_RxStats stats;
316 #endif /* _IF_VMXREG_H */