2 * Copyright (c) 2005 Marcel Moolenaar
5 * Copyright (c) 2009 The FreeBSD Foundation
8 * Portions of this software were developed by Ed Schouten
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/systm.h>
40 #include <dev/vt/vt.h>
41 #include <dev/vt/hw/vga/vga_reg.h>
43 #include <machine/bus.h>
45 #if defined(__amd64__) || defined(__i386__)
48 #include <machine/pmap.h>
49 #include <machine/vmparam.h>
50 #endif /* __amd64__ || __i386__ */
53 bus_space_tag_t vga_fb_tag;
54 bus_space_handle_t vga_fb_handle;
55 bus_space_tag_t vga_reg_tag;
56 bus_space_handle_t vga_reg_handle;
60 /* Convenience macros. */
61 #define MEM_READ1(sc, ofs) \
62 bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs)
63 #define MEM_WRITE1(sc, ofs, val) \
64 bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val)
65 #define REG_READ1(sc, reg) \
66 bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg)
67 #define REG_WRITE1(sc, reg, val) \
68 bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val)
70 #define VT_VGA_WIDTH 640
71 #define VT_VGA_HEIGHT 480
72 #define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8)
74 static vd_init_t vga_init;
75 static vd_blank_t vga_blank;
76 static vd_bitbltchr_t vga_bitbltchr;
77 static vd_maskbitbltchr_t vga_maskbitbltchr;
78 static vd_drawrect_t vga_drawrect;
79 static vd_setpixel_t vga_setpixel;
80 static vd_putchar_t vga_putchar;
81 static vd_postswitch_t vga_postswitch;
83 static const struct vt_driver vt_vga_driver = {
85 .vd_blank = vga_blank,
86 .vd_bitbltchr = vga_bitbltchr,
87 .vd_maskbitbltchr = vga_maskbitbltchr,
88 .vd_drawrect = vga_drawrect,
89 .vd_setpixel = vga_setpixel,
90 .vd_putchar = vga_putchar,
91 .vd_postswitch = vga_postswitch,
92 .vd_priority = VD_PRIORITY_GENERIC,
96 * Driver supports both text mode and graphics mode. Make sure the
97 * buffer is always big enough to support both.
99 static struct vga_softc vga_conssoftc;
100 VT_CONSDEV_DECLARE(vt_vga_driver, MAX(80, PIXEL_WIDTH(VT_VGA_WIDTH)),
101 MAX(25, PIXEL_HEIGHT(VT_VGA_HEIGHT)), &vga_conssoftc);
104 vga_setcolor(struct vt_device *vd, term_color_t color)
106 struct vga_softc *sc = vd->vd_softc;
108 if (sc->vga_curcolor != color) {
109 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
110 REG_WRITE1(sc, VGA_GC_DATA, color);
111 sc->vga_curcolor = color;
116 vga_blank(struct vt_device *vd, term_color_t color)
118 struct vga_softc *sc = vd->vd_softc;
121 vga_setcolor(vd, color);
122 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++)
123 MEM_WRITE1(sc, ofs, 0xff);
127 vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color,
130 struct vga_softc *sc = vd->vd_softc;
132 /* Skip empty writes, in order to avoid palette changes. */
134 vga_setcolor(vd, color);
136 * When this MEM_READ1() gets disabled, all sorts of
137 * artifacts occur. This is because this read loads the
138 * set of 8 pixels that are about to be changed. There
139 * is one scenario where we can avoid the read, namely
140 * if all pixels are about to be overwritten anyway.
144 MEM_WRITE1(sc, dst, v);
149 vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color)
152 vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color,
157 vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill,
162 for (y = y1; y <= y2; y++) {
163 if (fill || (y == y1) || (y == y2)) {
164 for (x = x1; x <= x2; x++)
165 vga_setpixel(vd, x, y, color);
167 vga_setpixel(vd, x1, y, color);
168 vga_setpixel(vd, x2, y, color);
174 vga_bitblt_draw(struct vt_device *vd, const uint8_t *src,
175 u_long ldst, uint8_t shift, unsigned int width, unsigned int height,
176 term_color_t color, int negate)
182 for (; height > 0; height--) {
184 ldst += VT_VGA_WIDTH / 8;
186 for (w = width; w > 0; w -= 8) {
190 /* Don't go too far. */
192 b &= 0xff << (8 - w);
194 /* Reintroduce bits from previous column. */
195 out = (b >> shift) | r;
196 r = b << (8 - shift);
197 vga_bitblt_put(vd, dst++, color, out);
199 /* Print the remainder. */
200 vga_bitblt_put(vd, dst, color, r);
205 vga_bitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask,
206 int bpl, vt_axis_t top, vt_axis_t left, unsigned int width,
207 unsigned int height, term_color_t fg, term_color_t bg)
212 /* Don't try to put off screen pixels */
213 if (((left + width) > VT_VGA_WIDTH) || ((top + height) >
217 dst = (VT_VGA_WIDTH * top + left) / 8;
219 for (; height > 0; height--) {
221 for (w = width; w > 0; w -= 8) {
222 vga_bitblt_put(vd, ldst, fg, *src);
223 vga_bitblt_put(vd, ldst, bg, ~*src);
227 dst += VT_VGA_WIDTH / 8;
231 /* Bitblt with mask support. Slow. */
233 vga_maskbitbltchr(struct vt_device *vd, const uint8_t *src, const uint8_t *mask,
234 int bpl, vt_axis_t top, vt_axis_t left, unsigned int width,
235 unsigned int height, term_color_t fg, term_color_t bg)
237 struct vga_softc *sc = vd->vd_softc;
241 dst = (VT_VGA_WIDTH * top + left) / 8;
244 /* Don't try to put off screen pixels */
245 if (((left + width) > VT_VGA_WIDTH) || ((top + height) >
249 if (sc->vga_curcolor == fg) {
250 vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0);
251 vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1);
253 vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1);
254 vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0);
259 * Binary searchable table for Unicode to CP437 conversion.
263 uint16_t unicode_base;
268 static const struct unicp437 cp437table[] = {
269 { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 },
270 { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 },
271 { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 },
272 { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 },
273 { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 },
274 { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 },
275 { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 },
276 { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 },
277 { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 },
278 { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 },
279 { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 },
280 { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 },
281 { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 },
282 { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 },
283 { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 },
284 { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 },
285 { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 },
286 { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 },
287 { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 },
288 { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 },
289 { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 },
290 { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 },
291 { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 },
292 { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 },
293 { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 },
294 { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 },
295 { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 },
296 { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 },
297 { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 },
298 { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 },
299 { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 },
300 { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 },
301 { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 },
302 { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 },
303 { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 },
304 { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 },
305 { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 },
306 { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 },
307 { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 },
308 { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 },
309 { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 },
310 { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 },
311 { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 },
312 { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 },
313 { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 },
314 { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 },
315 { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 },
316 { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 },
317 { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 },
318 { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 },
319 { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 },
320 { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 },
321 { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 },
322 { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 },
323 { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 },
324 { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 },
325 { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 },
326 { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 },
327 { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 },
328 { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 },
329 { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 },
330 { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 },
331 { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 },
332 { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 },
333 { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 },
334 { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 },
335 { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 },
336 { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 },
337 { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 },
338 { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 },
339 { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 },
340 { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 },
341 { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 },
342 { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 },
343 { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 },
344 { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 },
345 { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 },
346 { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 },
347 { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 },
348 { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 },
349 { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 },
350 { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 },
351 { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 },
352 { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x01 },
356 vga_get_cp437(term_char_t c)
361 max = (sizeof(cp437table) / sizeof(struct unicp437)) - 1;
363 if (c < cp437table[0].unicode_base ||
364 c > cp437table[max].unicode_base + cp437table[max].length)
368 mid = (min + max) / 2;
369 if (c < cp437table[mid].unicode_base)
371 else if (c > cp437table[mid].unicode_base +
372 cp437table[mid].length)
375 return (c - cp437table[mid].unicode_base +
376 cp437table[mid].cp437_base);
383 vga_putchar(struct vt_device *vd, term_char_t c,
384 vt_axis_t top, vt_axis_t left, term_color_t fg, term_color_t bg)
386 struct vga_softc *sc = vd->vd_softc;
390 * Convert character to CP437, which is the character set used
391 * by the VGA hardware by default.
393 ch = vga_get_cp437(c);
396 * Convert colors to VGA attributes.
400 MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 0, ch);
401 MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 1, attr);
405 vga_initialize_graphics(struct vt_device *vd)
407 struct vga_softc *sc = vd->vd_softc;
410 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP |
411 VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA);
412 /* Set sequencer clocking and memory mode. */
413 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE);
414 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89);
415 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE);
416 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM);
418 /* Set the graphics controller in graphics mode. */
419 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS);
420 REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA);
421 /* Program the CRT controller. */
422 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL);
423 REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */
424 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END);
425 REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */
426 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK);
427 REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */
428 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK);
429 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2);
430 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE);
431 REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */
432 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE);
433 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0);
434 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL);
435 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */
436 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW);
437 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 |
438 VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8);
439 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE);
440 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9);
441 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START);
442 REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */
443 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
444 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c);
445 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END);
446 REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/
447 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET);
448 REG_WRITE1(sc, VGA_CRTC_DATA, 0x28);
449 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK);
450 REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */
451 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK);
452 REG_WRITE1(sc, VGA_CRTC_DATA, 0x04);
453 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
454 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW |
455 VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS);
456 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE);
457 REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */
459 REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0);
461 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
462 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
463 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
464 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT);
465 REG_WRITE1(sc, VGA_SEQ_DATA, 0);
467 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
468 REG_WRITE1(sc, VGA_GC_DATA, 0);
469 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
470 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
471 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE);
472 REG_WRITE1(sc, VGA_GC_DATA, 0);
473 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE);
474 REG_WRITE1(sc, VGA_GC_DATA, 0);
475 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT);
476 REG_WRITE1(sc, VGA_GC_DATA, 0);
477 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
478 REG_WRITE1(sc, VGA_GC_DATA, 0);
479 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE);
480 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
481 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK);
482 REG_WRITE1(sc, VGA_GC_DATA, 0xff);
486 vga_initialize(struct vt_device *vd, int textmode)
488 struct vga_softc *sc = vd->vd_softc;
491 /* Make sure the VGA adapter is not in monochrome emulation mode. */
492 x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R);
493 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA);
495 /* Unprotect CRTC registers 0-7. */
496 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
497 x = REG_READ1(sc, VGA_CRTC_DATA);
498 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR);
501 * Wait for the vertical retrace.
502 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has
503 * the side-effect of clearing the internal flip-flip of the attribute
504 * controller's write register. This means that because this code is
505 * here, we know for sure that the first write to the attribute
506 * controller will be a write to the address register. Removing this
507 * code therefore also removes that guarantee and appropriate measures
511 x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1);
512 x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE;
513 } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE));
515 /* Now, disable the sync. signals. */
516 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
517 x = REG_READ1(sc, VGA_CRTC_DATA);
518 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR);
520 /* Asynchronous sequencer reset. */
521 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
522 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR);
525 vga_initialize_graphics(vd);
527 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN);
528 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
529 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START);
530 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO);
531 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END);
532 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
533 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH);
534 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
535 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW);
536 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
537 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH);
538 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
539 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW);
540 REG_WRITE1(sc, VGA_CRTC_DATA, 0x59);
541 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC);
542 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL);
545 /* Set the attribute controller to blink disable. */
546 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
547 REG_WRITE1(sc, VGA_AC_WRITE, 0);
549 /* Set the attribute controller in graphics mode. */
550 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
551 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA);
552 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING);
553 REG_WRITE1(sc, VGA_AC_WRITE, 0);
555 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0));
556 REG_WRITE1(sc, VGA_AC_WRITE, 0);
557 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1));
558 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R);
559 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2));
560 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G);
561 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3));
562 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R);
563 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4));
564 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B);
565 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5));
566 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B);
567 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6));
568 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B);
569 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7));
570 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
571 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8));
572 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
574 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9));
575 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
576 VGA_AC_PAL_SB | VGA_AC_PAL_R);
577 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10));
578 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
579 VGA_AC_PAL_SB | VGA_AC_PAL_G);
580 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11));
581 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
582 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G);
583 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12));
584 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
585 VGA_AC_PAL_SB | VGA_AC_PAL_B);
586 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13));
587 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
588 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B);
589 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14));
590 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
591 VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B);
592 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15));
593 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
594 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
595 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR);
596 REG_WRITE1(sc, VGA_AC_WRITE, 0);
597 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE);
598 REG_WRITE1(sc, VGA_AC_WRITE, 0x0f);
599 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT);
600 REG_WRITE1(sc, VGA_AC_WRITE, 0);
606 * Done. Clear the frame buffer. All bit planes are
607 * enabled, so a single-paged loop should clear all
610 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) {
612 MEM_WRITE1(sc, ofs, 0);
616 /* Re-enable the sequencer. */
617 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
618 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
619 /* Re-enable the sync signals. */
620 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
621 x = REG_READ1(sc, VGA_CRTC_DATA);
622 REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR);
625 /* Switch to write mode 3, because we'll mainly do bitblt. */
626 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
627 REG_WRITE1(sc, VGA_GC_DATA, 3);
628 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
629 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
634 vga_init(struct vt_device *vd)
636 struct vga_softc *sc = vd->vd_softc;
639 #if defined(__amd64__) || defined(__i386__)
640 sc->vga_fb_tag = X86_BUS_SPACE_MEM;
641 sc->vga_fb_handle = KERNBASE + VGA_MEM_BASE;
642 sc->vga_reg_tag = X86_BUS_SPACE_IO;
643 sc->vga_reg_handle = VGA_REG_BASE;
644 #elif defined(__ia64__)
645 sc->vga_fb_tag = IA64_BUS_SPACE_MEM;
646 sc->vga_fb_handle = IA64_PHYS_TO_RR6(VGA_MEM_BASE);
647 sc->vga_reg_tag = IA64_BUS_SPACE_IO;
648 sc->vga_reg_handle = VGA_REG_BASE;
650 # error "Architecture not yet supported!"
653 TUNABLE_INT_FETCH("hw.vga.textmode", &textmode);
655 vd->vd_flags |= VDF_TEXTMODE;
659 vd->vd_width = VT_VGA_WIDTH;
660 vd->vd_height = VT_VGA_HEIGHT;
662 vga_initialize(vd, textmode);
664 return (CN_INTERNAL);
668 vga_postswitch(struct vt_device *vd)
671 /* Reinit VGA mode, to restore view after app which change mode. */
672 vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE));
673 /* Ask vt(9) to update chars on visible area. */
674 vd->vd_flags |= VDF_INVALID;