2 * Copyright(c) 2002-2011 Exar Corp.
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33 #ifndef VXGE_HAL_DEVICE_H
34 #define VXGE_HAL_DEVICE_H
38 struct __hal_mrpcim_t;
39 struct __hal_srpcim_t;
44 * Represents vpd capabilty structure
46 typedef struct vxge_hal_vpd_data_t {
47 u8 product_name[VXGE_HAL_VPD_LEN];
48 u8 serial_num[VXGE_HAL_VPD_LEN];
49 } vxge_hal_vpd_data_t;
51 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
55 * HAL trace buffer object.
57 typedef struct __hal_tracebuf_t {
68 * HAL msix to vpath map.
70 typedef struct __hal_msix_map_t {
78 * HAL device object. Represents X3100.
80 typedef struct __hal_device_t {
81 vxge_hal_device_t header;
87 #define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1
88 #define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
89 #define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
92 vxge_hal_pci_config_t pci_config_space;
93 vxge_hal_pci_config_t pci_config_space_bios;
94 vxge_hal_pci_caps_offset_t pci_caps;
95 vxge_hal_pci_e_caps_offset_t pci_e_caps;
96 vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps;
97 vxge_hal_legacy_reg_t *legacy_reg;
98 vxge_hal_toc_reg_t *toc_reg;
99 vxge_hal_common_reg_t *common_reg;
100 vxge_hal_memrepair_reg_t *memrepair_reg;
101 vxge_hal_pcicfgmgmt_reg_t
102 *pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES];
103 vxge_hal_mrpcim_reg_t *mrpcim_reg;
104 vxge_hal_srpcim_reg_t
105 *srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES];
106 vxge_hal_vpmgmt_reg_t
107 *vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES];
109 *vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES];
113 virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS];
114 u64 vpath_assignments;
117 u64 tim_int_mask0[4];
118 u32 tim_int_mask1[4];
120 msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX];
121 struct __hal_srpcim_t *srpcim;
122 struct __hal_mrpcim_t *mrpcim;
123 __hal_blockpool_t block_pool;
124 vxge_list_t pending_channel_list;
125 spinlock_t pending_channel_lock;
126 vxge_hal_device_stats_t stats;
127 volatile u32 msix_enabled;
128 volatile u32 hw_is_initialized;
129 volatile int device_resetting;
130 volatile int is_promisc;
132 spinlock_t titan_post_lock;
133 u32 mtu_first_time_set;
135 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
136 __hal_tracebuf_t trace_buf;
138 volatile u32 in_poll;
145 * I2C device id. Used in I2C control register for accessing EEPROM device
148 #define VXGE_DEV_ID 5
150 #define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \
151 ((__hal_device_t *)hldev)->manager_up = \
152 __hal_ifmsg_is_manager_up(wmsg); \
155 #define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \
156 ((vxge_hal_device_t *)hldev)->link_state = ls; \
159 #define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \
160 ((vxge_hal_device_t *)hldev)->data_rate = dr; \
163 #define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \
165 ((__hal_device_t *)hldev)->tim_int_mask0[0] |= \
166 vBIT(0x8, (i*4), 4); \
167 ((__hal_device_t *)hldev)->tim_int_mask0[1] |= \
168 vBIT(0x4, (i*4), 4); \
169 ((__hal_device_t *)hldev)->tim_int_mask0[3] |= \
170 vBIT(0x1, (i*4), 4); \
172 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \
173 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \
174 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \
178 #define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \
180 ((__hal_device_t *)hldev)->tim_int_mask0[0] &= \
181 ~vBIT(0x8, (i*4), 4); \
182 ((__hal_device_t *)hldev)->tim_int_mask0[1] &= \
183 ~vBIT(0x4, (i*4), 4); \
184 ((__hal_device_t *)hldev)->tim_int_mask0[3] &= \
185 ~vBIT(0x1, (i*4), 4); \
187 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \
188 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \
189 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \
193 /* ========================== PRIVATE API ================================= */
196 vxge_hal_pio_mem_write32_upper(pci_dev_h pdev,
202 vxge_hal_pio_mem_write32_lower(pci_dev_h pdev,
208 __hal_device_event_queued(void *data,
212 __hal_device_pci_caps_list_process(__hal_device_t *hldev);
215 __hal_device_pci_e_init(__hal_device_t *hldev);
218 vxge_hal_device_register_poll(pci_dev_h pdev,
226 __hal_device_register_stall(pci_dev_h pdev,
234 __hal_device_reg_addr_get(__hal_device_t *hldev);
237 __hal_device_id_get(__hal_device_t *hldev);
240 __hal_device_access_rights_get(u32 host_type, u32 func_id);
243 __hal_device_host_info_get(__hal_device_t *hldev);
246 __hal_device_hw_initialize(__hal_device_t *hldev);
249 __hal_device_reset(__hal_device_t *hldev);
252 __hal_device_handle_link_up_ind(__hal_device_t *hldev);
255 __hal_device_handle_link_down_ind(__hal_device_t *hldev);
258 __hal_device_handle_error(
259 __hal_device_t *hldev,
261 vxge_hal_event_e type);
265 #endif /* VXGE_HAL_DEVICE_H */