2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/bus.h>
108 #include <machine/resource.h>
110 #include <sys/rman.h>
112 #include <dev/pci/pcireg.h>
113 #include <dev/pci/pcivar.h>
115 #include <dev/mii/mii.h>
116 #include <dev/mii/mii_bitbang.h>
117 #include <dev/mii/miivar.h>
119 /* "device miibus" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
122 #define WB_USEIOSPACE
124 #include <dev/wb/if_wbreg.h>
126 MODULE_DEPEND(wb, pci, 1, 1, 1);
127 MODULE_DEPEND(wb, ether, 1, 1, 1);
128 MODULE_DEPEND(wb, miibus, 1, 1, 1);
131 * Various supported device vendors/types and their names.
133 static const struct wb_type wb_devs[] = {
134 { WB_VENDORID, WB_DEVICEID_840F,
135 "Winbond W89C840F 10/100BaseTX" },
136 { CP_VENDORID, CP_DEVICEID_RL100,
137 "Compex RL100-ATX 10/100baseTX" },
141 static int wb_probe(device_t);
142 static int wb_attach(device_t);
143 static int wb_detach(device_t);
145 static int wb_bfree(struct mbuf *, void *addr, void *args);
146 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
148 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
150 static void wb_rxeof(struct wb_softc *);
151 static void wb_rxeoc(struct wb_softc *);
152 static void wb_txeof(struct wb_softc *);
153 static void wb_txeoc(struct wb_softc *);
154 static void wb_intr(void *);
155 static void wb_tick(void *);
156 static void wb_start(struct ifnet *);
157 static void wb_start_locked(struct ifnet *);
158 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
159 static void wb_init(void *);
160 static void wb_init_locked(struct wb_softc *);
161 static void wb_stop(struct wb_softc *);
162 static void wb_watchdog(struct wb_softc *);
163 static int wb_shutdown(device_t);
164 static int wb_ifmedia_upd(struct ifnet *);
165 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
167 static void wb_eeprom_putbyte(struct wb_softc *, int);
168 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
169 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
171 static void wb_setcfg(struct wb_softc *, u_int32_t);
172 static void wb_setmulti(struct wb_softc *);
173 static void wb_reset(struct wb_softc *);
174 static void wb_fixmedia(struct wb_softc *);
175 static int wb_list_rx_init(struct wb_softc *);
176 static int wb_list_tx_init(struct wb_softc *);
178 static int wb_miibus_readreg(device_t, int, int);
179 static int wb_miibus_writereg(device_t, int, int, int);
180 static void wb_miibus_statchg(device_t);
185 static uint32_t wb_mii_bitbang_read(device_t);
186 static void wb_mii_bitbang_write(device_t, uint32_t);
188 static const struct mii_bitbang_ops wb_mii_bitbang_ops = {
190 wb_mii_bitbang_write,
192 WB_SIO_MII_DATAOUT, /* MII_BIT_MDO */
193 WB_SIO_MII_DATAIN, /* MII_BIT_MDI */
194 WB_SIO_MII_CLK, /* MII_BIT_MDC */
195 WB_SIO_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
196 0, /* MII_BIT_DIR_PHY_HOST */
201 #define WB_RES SYS_RES_IOPORT
202 #define WB_RID WB_PCI_LOIO
204 #define WB_RES SYS_RES_MEMORY
205 #define WB_RID WB_PCI_LOMEM
208 static device_method_t wb_methods[] = {
209 /* Device interface */
210 DEVMETHOD(device_probe, wb_probe),
211 DEVMETHOD(device_attach, wb_attach),
212 DEVMETHOD(device_detach, wb_detach),
213 DEVMETHOD(device_shutdown, wb_shutdown),
216 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
217 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
218 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
223 static driver_t wb_driver = {
226 sizeof(struct wb_softc)
229 static devclass_t wb_devclass;
231 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
232 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
234 #define WB_SETBIT(sc, reg, x) \
235 CSR_WRITE_4(sc, reg, \
236 CSR_READ_4(sc, reg) | (x))
238 #define WB_CLRBIT(sc, reg, x) \
239 CSR_WRITE_4(sc, reg, \
240 CSR_READ_4(sc, reg) & ~(x))
243 CSR_WRITE_4(sc, WB_SIO, \
244 CSR_READ_4(sc, WB_SIO) | (x))
247 CSR_WRITE_4(sc, WB_SIO, \
248 CSR_READ_4(sc, WB_SIO) & ~(x))
251 * Send a read command and address to the EEPROM, check for ACK.
254 wb_eeprom_putbyte(sc, addr)
260 d = addr | WB_EECMD_READ;
263 * Feed in each bit and stobe the clock.
265 for (i = 0x400; i; i >>= 1) {
267 SIO_SET(WB_SIO_EE_DATAIN);
269 SIO_CLR(WB_SIO_EE_DATAIN);
272 SIO_SET(WB_SIO_EE_CLK);
274 SIO_CLR(WB_SIO_EE_CLK);
280 * Read a word of data stored in the EEPROM at address 'addr.'
283 wb_eeprom_getword(sc, addr, dest)
291 /* Enter EEPROM access mode. */
292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
295 * Send address of word we want to read.
297 wb_eeprom_putbyte(sc, addr);
299 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
302 * Start reading bits from EEPROM.
304 for (i = 0x8000; i; i >>= 1) {
305 SIO_SET(WB_SIO_EE_CLK);
307 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
309 SIO_CLR(WB_SIO_EE_CLK);
313 /* Turn off EEPROM access mode. */
314 CSR_WRITE_4(sc, WB_SIO, 0);
320 * Read a sequence of words from the EEPROM.
323 wb_read_eeprom(sc, dest, off, cnt, swap)
331 u_int16_t word = 0, *ptr;
333 for (i = 0; i < cnt; i++) {
334 wb_eeprom_getword(sc, off + i, &word);
335 ptr = (u_int16_t *)(dest + (i * 2));
344 * Read the MII serial port for the MII bit-bang module.
347 wb_mii_bitbang_read(device_t dev)
352 sc = device_get_softc(dev);
354 val = CSR_READ_4(sc, WB_SIO);
355 CSR_BARRIER(sc, WB_SIO, 4,
356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
362 * Write the MII serial port for the MII bit-bang module.
365 wb_mii_bitbang_write(device_t dev, uint32_t val)
369 sc = device_get_softc(dev);
371 CSR_WRITE_4(sc, WB_SIO, val);
372 CSR_BARRIER(sc, WB_SIO, 4,
373 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
377 wb_miibus_readreg(dev, phy, reg)
382 return (mii_bitbang_readreg(dev, &wb_mii_bitbang_ops, phy, reg));
386 wb_miibus_writereg(dev, phy, reg, data)
391 mii_bitbang_writereg(dev, &wb_mii_bitbang_ops, phy, reg, data);
397 wb_miibus_statchg(dev)
401 struct mii_data *mii;
403 sc = device_get_softc(dev);
404 mii = device_get_softc(sc->wb_miibus);
405 wb_setcfg(sc, mii->mii_media_active);
409 * Program the 64-bit multicast hash filter.
417 u_int32_t hashes[2] = { 0, 0 };
418 struct ifmultiaddr *ifma;
424 rxfilt = CSR_READ_4(sc, WB_NETCFG);
426 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
427 rxfilt |= WB_NETCFG_RX_MULTI;
428 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
429 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
430 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
434 /* first, zot all the existing hash bits */
435 CSR_WRITE_4(sc, WB_MAR0, 0);
436 CSR_WRITE_4(sc, WB_MAR1, 0);
438 /* now program new ones */
440 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
441 if (ifma->ifma_addr->sa_family != AF_LINK)
443 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
444 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
446 hashes[0] |= (1 << h);
448 hashes[1] |= (1 << (h - 32));
451 if_maddr_runlock(ifp);
454 rxfilt |= WB_NETCFG_RX_MULTI;
456 rxfilt &= ~WB_NETCFG_RX_MULTI;
458 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
459 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
460 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
464 * The Winbond manual states that in order to fiddle with the
465 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
466 * first have to put the transmit and/or receive logic in the idle state.
475 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
477 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
479 for (i = 0; i < WB_TIMEOUT; i++) {
481 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
482 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
487 device_printf(sc->wb_dev,
488 "failed to force tx and rx to idle state\n");
491 if (IFM_SUBTYPE(media) == IFM_10_T)
492 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
494 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
496 if ((media & IFM_GMASK) == IFM_FDX)
497 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
499 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
502 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
510 struct mii_data *mii;
511 struct mii_softc *miisc;
513 CSR_WRITE_4(sc, WB_NETCFG, 0);
514 CSR_WRITE_4(sc, WB_BUSCTL, 0);
515 CSR_WRITE_4(sc, WB_TXADDR, 0);
516 CSR_WRITE_4(sc, WB_RXADDR, 0);
518 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
519 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
521 for (i = 0; i < WB_TIMEOUT; i++) {
523 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
527 device_printf(sc->wb_dev, "reset never completed!\n");
529 /* Wait a little while for the chip to get its brains in order. */
532 if (sc->wb_miibus == NULL)
535 mii = device_get_softc(sc->wb_miibus);
536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
544 struct mii_data *mii = NULL;
548 mii = device_get_softc(sc->wb_miibus);
552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
553 media = mii->mii_media_active & ~IFM_10_T;
555 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
556 media = mii->mii_media_active & ~IFM_100_TX;
561 ifmedia_set(&mii->mii_media, media);
565 * Probe for a Winbond chip. Check the PCI vendor and device
566 * IDs against our list and return a device name if we find a match.
572 const struct wb_type *t;
576 while(t->wb_name != NULL) {
577 if ((pci_get_vendor(dev) == t->wb_vid) &&
578 (pci_get_device(dev) == t->wb_did)) {
579 device_set_desc(dev, t->wb_name);
580 return (BUS_PROBE_DEFAULT);
589 * Attach the interface. Allocate softc structures, do ifmedia
590 * setup and ethernet/BPF attach.
596 u_char eaddr[ETHER_ADDR_LEN];
601 sc = device_get_softc(dev);
604 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
606 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
609 * Map control/status registers.
611 pci_enable_busmaster(dev);
614 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
616 if (sc->wb_res == NULL) {
617 device_printf(dev, "couldn't map ports/memory\n");
622 /* Allocate interrupt */
624 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
625 RF_SHAREABLE | RF_ACTIVE);
627 if (sc->wb_irq == NULL) {
628 device_printf(dev, "couldn't map interrupt\n");
633 /* Save the cache line size. */
634 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
636 /* Reset the adapter. */
640 * Get station address from the EEPROM.
642 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
644 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
645 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
647 if (sc->wb_ldata == NULL) {
648 device_printf(dev, "no memory for list buffers!\n");
653 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
655 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
657 device_printf(dev, "can not if_alloc()\n");
662 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
663 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
664 ifp->if_ioctl = wb_ioctl;
665 ifp->if_start = wb_start;
666 ifp->if_init = wb_init;
667 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
672 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd,
673 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
675 device_printf(dev, "attaching PHYs failed\n");
680 * Call MI attach routine.
682 ether_ifattach(ifp, eaddr);
684 /* Hook interrupt last to avoid having to lock softc */
685 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
686 NULL, wb_intr, sc, &sc->wb_intrhand);
689 device_printf(dev, "couldn't set up irq\n");
702 * Shutdown hardware and free up resources. This can be called any
703 * time after the mutex has been initialized. It is called in both
704 * the error case in attach and the normal detach case so it needs
705 * to be careful about only freeing resources that have actually been
715 sc = device_get_softc(dev);
716 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
720 * Delete any miibus and phy devices attached to this interface.
721 * This should only be done if attach succeeded.
723 if (device_is_attached(dev)) {
728 callout_drain(&sc->wb_stat_callout);
731 device_delete_child(dev, sc->wb_miibus);
732 bus_generic_detach(dev);
735 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
737 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
739 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
745 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
749 mtx_destroy(&sc->wb_mtx);
755 * Initialize the transmit descriptors.
761 struct wb_chain_data *cd;
762 struct wb_list_data *ld;
768 for (i = 0; i < WB_TX_LIST_CNT; i++) {
769 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
770 if (i == (WB_TX_LIST_CNT - 1)) {
771 cd->wb_tx_chain[i].wb_nextdesc =
774 cd->wb_tx_chain[i].wb_nextdesc =
775 &cd->wb_tx_chain[i + 1];
779 cd->wb_tx_free = &cd->wb_tx_chain[0];
780 cd->wb_tx_tail = cd->wb_tx_head = NULL;
787 * Initialize the RX descriptors and allocate mbufs for them. Note that
788 * we arrange the descriptors in a closed ring, so that the last descriptor
789 * points back to the first.
795 struct wb_chain_data *cd;
796 struct wb_list_data *ld;
802 for (i = 0; i < WB_RX_LIST_CNT; i++) {
803 cd->wb_rx_chain[i].wb_ptr =
804 (struct wb_desc *)&ld->wb_rx_list[i];
805 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
806 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
808 if (i == (WB_RX_LIST_CNT - 1)) {
809 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
810 ld->wb_rx_list[i].wb_next =
811 vtophys(&ld->wb_rx_list[0]);
813 cd->wb_rx_chain[i].wb_nextdesc =
814 &cd->wb_rx_chain[i + 1];
815 ld->wb_rx_list[i].wb_next =
816 vtophys(&ld->wb_rx_list[i + 1]);
820 cd->wb_rx_head = &cd->wb_rx_chain[0];
826 wb_bfree(struct mbuf *m, void *buf, void *args)
829 return (EXT_FREE_OK);
833 * Initialize an RX descriptor and attach an MBUF cluster.
838 struct wb_chain_onefrag *c;
841 struct mbuf *m_new = NULL;
844 MGETHDR(m_new, M_NOWAIT, MT_DATA);
847 m_new->m_data = c->wb_buf;
848 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
849 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf,
850 NULL, 0, EXT_NET_DRV);
853 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
854 m_new->m_data = m_new->m_ext.ext_buf;
857 m_adj(m_new, sizeof(u_int64_t));
860 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
861 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
862 c->wb_ptr->wb_status = WB_RXSTAT;
868 * A frame has been uploaded: pass the resulting mbuf chain up to
869 * the higher level protocols.
875 struct mbuf *m = NULL;
877 struct wb_chain_onefrag *cur_rx;
885 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
887 struct mbuf *m0 = NULL;
889 cur_rx = sc->wb_cdata.wb_rx_head;
890 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
894 if ((rxstat & WB_RXSTAT_MIIERR) ||
895 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
896 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
897 !(rxstat & WB_RXSTAT_LASTFRAG) ||
898 !(rxstat & WB_RXSTAT_RXCMP)) {
900 wb_newbuf(sc, cur_rx, m);
901 device_printf(sc->wb_dev,
902 "receiver babbling: possible chip bug,"
910 if (rxstat & WB_RXSTAT_RXERR) {
912 wb_newbuf(sc, cur_rx, m);
916 /* No errors; receive the packet. */
917 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
920 * XXX The Winbond chip includes the CRC with every
921 * received frame, and there's no way to turn this
922 * behavior off (at least, I can't find anything in
923 * the manual that explains how to do it) so we have
924 * to trim off the CRC manually.
926 total_len -= ETHER_CRC_LEN;
928 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
930 wb_newbuf(sc, cur_rx, m);
939 (*ifp->if_input)(ifp, m);
950 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
951 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
952 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
953 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
954 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
958 * A frame was downloaded to the chip. It's safe for us to clean up
965 struct wb_chain *cur_tx;
970 /* Clear the timeout timer. */
973 if (sc->wb_cdata.wb_tx_head == NULL)
977 * Go through our tx list and free mbufs for those
978 * frames that have been transmitted.
980 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
983 cur_tx = sc->wb_cdata.wb_tx_head;
984 txstat = WB_TXSTATUS(cur_tx);
986 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
989 if (txstat & WB_TXSTAT_TXERR) {
991 if (txstat & WB_TXSTAT_ABORT)
992 ifp->if_collisions++;
993 if (txstat & WB_TXSTAT_LATECOLL)
994 ifp->if_collisions++;
997 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1000 m_freem(cur_tx->wb_mbuf);
1001 cur_tx->wb_mbuf = NULL;
1003 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1004 sc->wb_cdata.wb_tx_head = NULL;
1005 sc->wb_cdata.wb_tx_tail = NULL;
1009 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1014 * TX 'end of channel' interrupt handler.
1018 struct wb_softc *sc;
1026 if (sc->wb_cdata.wb_tx_head == NULL) {
1027 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1028 sc->wb_cdata.wb_tx_tail = NULL;
1030 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1031 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1033 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1042 struct wb_softc *sc;
1050 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1055 /* Disable interrupts. */
1056 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1060 status = CSR_READ_4(sc, WB_ISR);
1062 CSR_WRITE_4(sc, WB_ISR, status);
1064 if ((status & WB_INTRS) == 0)
1067 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1070 if (status & WB_ISR_RX_ERR)
1076 if (status & WB_ISR_RX_OK)
1079 if (status & WB_ISR_RX_IDLE)
1082 if (status & WB_ISR_TX_OK)
1085 if (status & WB_ISR_TX_NOBUF)
1088 if (status & WB_ISR_TX_IDLE) {
1090 if (sc->wb_cdata.wb_tx_head != NULL) {
1091 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1092 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1096 if (status & WB_ISR_TX_UNDERRUN) {
1099 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1100 /* Jack up TX threshold */
1101 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1102 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1103 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1104 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1107 if (status & WB_ISR_BUS_ERR) {
1114 /* Re-enable interrupts. */
1115 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1117 if (ifp->if_snd.ifq_head != NULL) {
1118 wb_start_locked(ifp);
1128 struct wb_softc *sc;
1129 struct mii_data *mii;
1133 mii = device_get_softc(sc->wb_miibus);
1137 if (sc->wb_timer > 0 && --sc->wb_timer == 0)
1139 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1143 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1144 * pointers to the fragment pointers.
1147 wb_encap(sc, c, m_head)
1148 struct wb_softc *sc;
1150 struct mbuf *m_head;
1153 struct wb_desc *f = NULL;
1158 * Start packing the mbufs in this chain into
1159 * the fragment pointers. Stop when we run out
1160 * of fragments or hit the end of the mbuf chain.
1165 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1166 if (m->m_len != 0) {
1167 if (frag == WB_MAXFRAGS)
1169 total_len += m->m_len;
1170 f = &c->wb_ptr->wb_frag[frag];
1171 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1173 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1176 f->wb_status = WB_TXSTAT_OWN;
1177 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1178 f->wb_data = vtophys(mtod(m, vm_offset_t));
1184 * Handle special case: we used up all 16 fragments,
1185 * but we have more mbufs left in the chain. Copy the
1186 * data into an mbuf cluster. Note that we don't
1187 * bother clearing the values in the other fragment
1188 * pointers/counters; it wouldn't gain us anything,
1189 * and would waste cycles.
1192 struct mbuf *m_new = NULL;
1194 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1197 if (m_head->m_pkthdr.len > MHLEN) {
1198 MCLGET(m_new, M_NOWAIT);
1199 if (!(m_new->m_flags & M_EXT)) {
1204 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1205 mtod(m_new, caddr_t));
1206 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1209 f = &c->wb_ptr->wb_frag[0];
1211 f->wb_data = vtophys(mtod(m_new, caddr_t));
1212 f->wb_ctl = total_len = m_new->m_len;
1213 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1217 if (total_len < WB_MIN_FRAMELEN) {
1218 f = &c->wb_ptr->wb_frag[frag];
1219 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1220 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1221 f->wb_ctl |= WB_TXCTL_TLINK;
1222 f->wb_status = WB_TXSTAT_OWN;
1226 c->wb_mbuf = m_head;
1227 c->wb_lastdesc = frag - 1;
1228 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1229 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1235 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1236 * to the mbuf data regions directly in the transmit lists. We also save a
1237 * copy of the pointers since the transmit list fragment pointers are
1238 * physical addresses.
1245 struct wb_softc *sc;
1249 wb_start_locked(ifp);
1254 wb_start_locked(ifp)
1257 struct wb_softc *sc;
1258 struct mbuf *m_head = NULL;
1259 struct wb_chain *cur_tx = NULL, *start_tx;
1265 * Check for an available queue slot. If there are none,
1268 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1269 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1273 start_tx = sc->wb_cdata.wb_tx_free;
1275 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1276 IF_DEQUEUE(&ifp->if_snd, m_head);
1280 /* Pick a descriptor off the free list. */
1281 cur_tx = sc->wb_cdata.wb_tx_free;
1282 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1284 /* Pack the data into the descriptor. */
1285 wb_encap(sc, cur_tx, m_head);
1287 if (cur_tx != start_tx)
1288 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1291 * If there's a BPF listener, bounce a copy of this frame
1294 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1298 * If there are no packets queued, bail.
1304 * Place the request for the upload interrupt
1305 * in the last descriptor in the chain. This way, if
1306 * we're chaining several packets at once, we'll only
1307 * get an interrupt once for the whole chain rather than
1308 * once for each packet.
1310 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1311 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1312 sc->wb_cdata.wb_tx_tail = cur_tx;
1314 if (sc->wb_cdata.wb_tx_head == NULL) {
1315 sc->wb_cdata.wb_tx_head = start_tx;
1316 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1317 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1320 * We need to distinguish between the case where
1321 * the own bit is clear because the chip cleared it
1322 * and where the own bit is clear because we haven't
1323 * set it yet. The magic value WB_UNSET is just some
1324 * ramdomly chosen number which doesn't have the own
1325 * bit set. When we actually transmit the frame, the
1326 * status word will have _only_ the own bit set, so
1327 * the txeoc handler will be able to tell if it needs
1328 * to initiate another transmission to flush out pending
1331 WB_TXOWN(start_tx) = WB_UNSENT;
1335 * Set a timeout in case the chip goes out to lunch.
1344 struct wb_softc *sc = xsc;
1353 struct wb_softc *sc;
1355 struct ifnet *ifp = sc->wb_ifp;
1357 struct mii_data *mii;
1360 mii = device_get_softc(sc->wb_miibus);
1363 * Cancel pending I/O and free all RX/TX buffers.
1368 sc->wb_txthresh = WB_TXTHRESH_INIT;
1371 * Set cache alignment and burst length.
1374 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1375 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1376 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1379 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1380 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1381 switch(sc->wb_cachesize) {
1383 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1386 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1389 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1393 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1397 /* This doesn't tend to work too well at 100Mbps. */
1398 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1400 /* Init our MAC address */
1401 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1402 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
1405 /* Init circular RX list. */
1406 if (wb_list_rx_init(sc) == ENOBUFS) {
1407 device_printf(sc->wb_dev,
1408 "initialization failed: no memory for rx buffers\n");
1413 /* Init TX descriptors. */
1414 wb_list_tx_init(sc);
1416 /* If we want promiscuous mode, set the allframes bit. */
1417 if (ifp->if_flags & IFF_PROMISC) {
1418 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1420 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1424 * Set capture broadcast bit to capture broadcast frames.
1426 if (ifp->if_flags & IFF_BROADCAST) {
1427 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1429 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1433 * Program the multicast filter, if necessary.
1438 * Load the address of the RX list.
1440 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1441 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1444 * Enable interrupts.
1446 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1447 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1449 /* Enable receiver and transmitter. */
1450 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1451 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1453 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1454 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1455 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1459 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1462 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1466 * Set media options.
1472 struct wb_softc *sc;
1477 if (ifp->if_flags & IFF_UP)
1485 * Report current media status.
1488 wb_ifmedia_sts(ifp, ifmr)
1490 struct ifmediareq *ifmr;
1492 struct wb_softc *sc;
1493 struct mii_data *mii;
1498 mii = device_get_softc(sc->wb_miibus);
1501 ifmr->ifm_active = mii->mii_media_active;
1502 ifmr->ifm_status = mii->mii_media_status;
1507 wb_ioctl(ifp, command, data)
1512 struct wb_softc *sc = ifp->if_softc;
1513 struct mii_data *mii;
1514 struct ifreq *ifr = (struct ifreq *) data;
1520 if (ifp->if_flags & IFF_UP) {
1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1538 mii = device_get_softc(sc->wb_miibus);
1539 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1542 error = ether_ioctl(ifp, command, data);
1551 struct wb_softc *sc;
1558 if_printf(ifp, "watchdog timeout\n");
1560 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1561 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1567 if (ifp->if_snd.ifq_head != NULL)
1568 wb_start_locked(ifp);
1572 * Stop the adapter and free any mbufs allocated to the
1577 struct wb_softc *sc;
1586 callout_stop(&sc->wb_stat_callout);
1588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1589 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1590 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1591 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1594 * Free data in the RX lists.
1596 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1597 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1598 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1599 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1602 bzero((char *)&sc->wb_ldata->wb_rx_list,
1603 sizeof(sc->wb_ldata->wb_rx_list));
1606 * Free the TX list buffers.
1608 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1609 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1610 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1611 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1615 bzero((char *)&sc->wb_ldata->wb_tx_list,
1616 sizeof(sc->wb_ldata->wb_tx_list));
1618 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1622 * Stop all chip I/O so that the kernel's probe routines don't
1623 * get confused by errant DMAs when rebooting.
1629 struct wb_softc *sc;
1631 sc = device_get_softc(dev);