2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
101 #ifdef HAVE_KERNEL_OPTION_HEADERS
102 #include "opt_device_polling.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/taskqueue.h>
116 #include <net/if_arp.h>
117 #include <net/ethernet.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_types.h>
124 #include <machine/bus.h>
125 #include <machine/resource.h>
127 #include <sys/rman.h>
129 #include <dev/mii/mii.h>
130 #include <dev/mii/miivar.h>
132 #include <dev/pci/pcireg.h>
133 #include <dev/pci/pcivar.h>
135 MODULE_DEPEND(xl, pci, 1, 1, 1);
136 MODULE_DEPEND(xl, ether, 1, 1, 1);
137 MODULE_DEPEND(xl, miibus, 1, 1, 1);
139 /* "device miibus" required. See GENERIC if you get errors here. */
140 #include "miibus_if.h"
142 #include <dev/xl/if_xlreg.h>
145 * TX Checksumming is disabled by default for two reasons:
146 * - TX Checksumming will occasionally produce corrupt packets
147 * - TX Checksumming seems to reduce performance
149 * Only 905B/C cards were reported to have this problem, it is possible
150 * that later chips _may_ be immune.
152 #define XL905B_TXCSUM_BROKEN 1
154 #ifdef XL905B_TXCSUM_BROKEN
155 #define XL905B_CSUM_FEATURES 0
157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct xl_type xl_devs[] = {
164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
165 "3Com 3c900-TPO Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
167 "3Com 3c900-COMBO Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
169 "3Com 3c905-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
171 "3Com 3c905-T4 Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
173 "3Com 3c900B-TPO Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
175 "3Com 3c900B-COMBO Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
177 "3Com 3c900B-TPC Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
179 "3Com 3c900B-FL Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
181 "3Com 3c905B-TX Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
183 "3Com 3c905B-T4 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
185 "3Com 3c905B-FX/SC Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
187 "3Com 3c905B-COMBO Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
189 "3Com 3c905C-TX Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
195 "3Com 3c980 Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
197 "3Com 3c980C Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
199 "3Com 3cSOHO100-TX OfficeConnect" },
200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
201 "3Com 3c450-TX HomeConnect" },
202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
203 "3Com 3c555 Fast Etherlink XL" },
204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
205 "3Com 3c556 Fast Etherlink XL" },
206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
207 "3Com 3c556B Fast Etherlink XL" },
208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
209 "3Com 3c575TX Fast Etherlink XL" },
210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
211 "3Com 3c575B Fast Etherlink XL" },
212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
213 "3Com 3c575C Fast Etherlink XL" },
214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
215 "3Com 3c656 Fast Etherlink XL" },
216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
217 "3Com 3c656B Fast Etherlink XL" },
218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
219 "3Com 3c656C Fast Etherlink XL" },
223 static int xl_probe(device_t);
224 static int xl_attach(device_t);
225 static int xl_detach(device_t);
227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
228 static void xl_stats_update(void *);
229 static void xl_stats_update_locked(struct xl_softc *);
230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
231 static int xl_rxeof(struct xl_softc *);
232 static void xl_rxeof_task(void *, int);
233 static int xl_rx_resync(struct xl_softc *);
234 static void xl_txeof(struct xl_softc *);
235 static void xl_txeof_90xB(struct xl_softc *);
236 static void xl_txeoc(struct xl_softc *);
237 static void xl_intr(void *);
238 static void xl_start(struct ifnet *);
239 static void xl_start_locked(struct ifnet *);
240 static void xl_start_90xB_locked(struct ifnet *);
241 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
242 static void xl_init(void *);
243 static void xl_init_locked(struct xl_softc *);
244 static void xl_stop(struct xl_softc *);
245 static int xl_watchdog(struct xl_softc *);
246 static int xl_shutdown(device_t);
247 static int xl_suspend(device_t);
248 static int xl_resume(device_t);
249 static void xl_setwol(struct xl_softc *);
251 #ifdef DEVICE_POLLING
252 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
253 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
256 static int xl_ifmedia_upd(struct ifnet *);
257 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
259 static int xl_eeprom_wait(struct xl_softc *);
260 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
261 static void xl_mii_sync(struct xl_softc *);
262 static void xl_mii_send(struct xl_softc *, u_int32_t, int);
263 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
264 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
266 static void xl_setcfg(struct xl_softc *);
267 static void xl_setmode(struct xl_softc *, int);
268 static void xl_setmulti(struct xl_softc *);
269 static void xl_setmulti_hash(struct xl_softc *);
270 static void xl_reset(struct xl_softc *);
271 static int xl_list_rx_init(struct xl_softc *);
272 static int xl_list_tx_init(struct xl_softc *);
273 static int xl_list_tx_init_90xB(struct xl_softc *);
274 static void xl_wait(struct xl_softc *);
275 static void xl_mediacheck(struct xl_softc *);
276 static void xl_choose_media(struct xl_softc *sc, int *media);
277 static void xl_choose_xcvr(struct xl_softc *, int);
278 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
280 static void xl_testpacket(struct xl_softc *);
283 static int xl_miibus_readreg(device_t, int, int);
284 static int xl_miibus_writereg(device_t, int, int, int);
285 static void xl_miibus_statchg(device_t);
286 static void xl_miibus_mediainit(device_t);
288 static device_method_t xl_methods[] = {
289 /* Device interface */
290 DEVMETHOD(device_probe, xl_probe),
291 DEVMETHOD(device_attach, xl_attach),
292 DEVMETHOD(device_detach, xl_detach),
293 DEVMETHOD(device_shutdown, xl_shutdown),
294 DEVMETHOD(device_suspend, xl_suspend),
295 DEVMETHOD(device_resume, xl_resume),
298 DEVMETHOD(bus_print_child, bus_generic_print_child),
299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
302 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
303 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
304 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
305 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
310 static driver_t xl_driver = {
313 sizeof(struct xl_softc)
316 static devclass_t xl_devclass;
318 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0);
319 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
322 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
327 *paddr = segs->ds_addr;
331 * Murphy's law says that it's possible the chip can wedge and
332 * the 'command in progress' bit may never clear. Hence, we wait
333 * only a finite amount of time to avoid getting caught in an
334 * infinite loop. Normally this delay routine would be a macro,
335 * but it isn't called during normal operation so we can afford
336 * to make it a function.
339 xl_wait(struct xl_softc *sc)
343 for (i = 0; i < XL_TIMEOUT; i++) {
344 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
349 device_printf(sc->xl_dev, "command never completed!\n");
353 * MII access routines are provided for adapters with external
354 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
355 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
356 * Note: if you don't perform the MDIO operations just right,
357 * it's possible to end up with code that works correctly with
358 * some chips/CPUs/processor speeds/bus speeds/etc but not
362 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
363 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
366 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
367 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
370 * Sync the PHYs by setting data bit and strobing the clock 32 times.
373 xl_mii_sync(struct xl_softc *sc)
378 MII_SET(XL_MII_DIR|XL_MII_DATA);
380 for (i = 0; i < 32; i++) {
382 MII_SET(XL_MII_DATA);
383 MII_SET(XL_MII_DATA);
385 MII_SET(XL_MII_DATA);
386 MII_SET(XL_MII_DATA);
391 * Clock a series of bits through the MII.
394 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
403 MII_SET(XL_MII_DATA);
405 MII_CLR(XL_MII_DATA);
413 * Read an PHY register through the MII.
416 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
420 /* Set up frame for RX. */
421 frame->mii_stdelim = XL_MII_STARTDELIM;
422 frame->mii_opcode = XL_MII_READOP;
423 frame->mii_turnaround = 0;
426 /* Select register window 4. */
429 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
430 /* Turn on data xmit. */
435 /* Send command/address info. */
436 xl_mii_send(sc, frame->mii_stdelim, 2);
437 xl_mii_send(sc, frame->mii_opcode, 2);
438 xl_mii_send(sc, frame->mii_phyaddr, 5);
439 xl_mii_send(sc, frame->mii_regaddr, 5);
442 MII_CLR((XL_MII_CLK|XL_MII_DATA));
450 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
454 * Now try reading data bits. If the ack failed, we still
455 * need to clock through 16 cycles to keep the PHY(s) in sync.
458 for (i = 0; i < 16; i++) {
465 for (i = 0x8000; i; i >>= 1) {
468 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
469 frame->mii_data |= i;
478 return (ack ? 1 : 0);
482 * Write to a PHY register through the MII.
485 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
488 /* Set up frame for TX. */
489 frame->mii_stdelim = XL_MII_STARTDELIM;
490 frame->mii_opcode = XL_MII_WRITEOP;
491 frame->mii_turnaround = XL_MII_TURNAROUND;
493 /* Select the window 4. */
496 /* Turn on data output. */
501 xl_mii_send(sc, frame->mii_stdelim, 2);
502 xl_mii_send(sc, frame->mii_opcode, 2);
503 xl_mii_send(sc, frame->mii_phyaddr, 5);
504 xl_mii_send(sc, frame->mii_regaddr, 5);
505 xl_mii_send(sc, frame->mii_turnaround, 2);
506 xl_mii_send(sc, frame->mii_data, 16);
519 xl_miibus_readreg(device_t dev, int phy, int reg)
522 struct xl_mii_frame frame;
524 sc = device_get_softc(dev);
527 * Pretend that PHYs are only available at MII address 24.
528 * This is to guard against problems with certain 3Com ASIC
529 * revisions that incorrectly map the internal transceiver
530 * control registers at all MII addresses. This can cause
531 * the miibus code to attach the same PHY several times over.
533 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
536 bzero((char *)&frame, sizeof(frame));
537 frame.mii_phyaddr = phy;
538 frame.mii_regaddr = reg;
540 xl_mii_readreg(sc, &frame);
542 return (frame.mii_data);
546 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
549 struct xl_mii_frame frame;
551 sc = device_get_softc(dev);
553 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24)
556 bzero((char *)&frame, sizeof(frame));
557 frame.mii_phyaddr = phy;
558 frame.mii_regaddr = reg;
559 frame.mii_data = data;
561 xl_mii_writereg(sc, &frame);
567 xl_miibus_statchg(device_t dev)
570 struct mii_data *mii;
572 sc = device_get_softc(dev);
573 mii = device_get_softc(sc->xl_miibus);
577 /* Set ASIC's duplex mode to match the PHY. */
579 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
580 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
582 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
583 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
587 * Special support for the 3c905B-COMBO. This card has 10/100 support
588 * plus BNC and AUI ports. This means we will have both an miibus attached
589 * plus some non-MII media settings. In order to allow this, we have to
590 * add the extra media to the miibus's ifmedia struct, but we can't do
591 * that during xl_attach() because the miibus hasn't been attached yet.
592 * So instead, we wait until the miibus probe/attach is done, at which
593 * point we will get a callback telling is that it's safe to add our
597 xl_miibus_mediainit(device_t dev)
600 struct mii_data *mii;
603 sc = device_get_softc(dev);
604 mii = device_get_softc(sc->xl_miibus);
605 ifm = &mii->mii_media;
607 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
609 * Check for a 10baseFL board in disguise.
611 if (sc->xl_type == XL_TYPE_905B &&
612 sc->xl_media == XL_MEDIAOPT_10FL) {
614 device_printf(sc->xl_dev, "found 10baseFL\n");
615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
616 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
618 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
620 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
623 device_printf(sc->xl_dev, "found AUI\n");
624 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
628 if (sc->xl_media & XL_MEDIAOPT_BNC) {
630 device_printf(sc->xl_dev, "found BNC\n");
631 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
636 * The EEPROM is slow: give it time to come ready after issuing
640 xl_eeprom_wait(struct xl_softc *sc)
644 for (i = 0; i < 100; i++) {
645 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
652 device_printf(sc->xl_dev, "eeprom failed to come ready\n");
660 * Read a sequence of words from the EEPROM. Note that ethernet address
661 * data is stored in the EEPROM in network byte order.
664 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
667 u_int16_t word = 0, *ptr;
669 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
670 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
672 * XXX: WARNING! DANGER!
673 * It's easy to accidentally overwrite the rom content!
674 * Note: the 3c575 uses 8bit EEPROM offsets.
678 if (xl_eeprom_wait(sc))
681 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
684 for (i = 0; i < cnt; i++) {
685 if (sc->xl_flags & XL_FLAG_8BITROM)
686 CSR_WRITE_2(sc, XL_W0_EE_CMD,
687 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
689 CSR_WRITE_2(sc, XL_W0_EE_CMD,
690 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
691 err = xl_eeprom_wait(sc);
694 word = CSR_READ_2(sc, XL_W0_EE_DATA);
695 ptr = (u_int16_t *)(dest + (i * 2));
702 return (err ? 1 : 0);
706 * NICs older than the 3c905B have only one multicast option, which
707 * is to enable reception of all multicast frames.
710 xl_setmulti(struct xl_softc *sc)
712 struct ifnet *ifp = sc->xl_ifp;
713 struct ifmultiaddr *ifma;
720 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
722 if (ifp->if_flags & IFF_ALLMULTI) {
723 rxfilt |= XL_RXFILTER_ALLMULTI;
724 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
729 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
731 if_maddr_runlock(ifp);
734 rxfilt |= XL_RXFILTER_ALLMULTI;
736 rxfilt &= ~XL_RXFILTER_ALLMULTI;
738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
742 * 3c905B adapters have a hash filter that we can program.
745 xl_setmulti_hash(struct xl_softc *sc)
747 struct ifnet *ifp = sc->xl_ifp;
749 struct ifmultiaddr *ifma;
756 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
758 if (ifp->if_flags & IFF_ALLMULTI) {
759 rxfilt |= XL_RXFILTER_ALLMULTI;
760 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
763 rxfilt &= ~XL_RXFILTER_ALLMULTI;
765 /* first, zot all the existing hash bits */
766 for (i = 0; i < XL_HASHFILT_SIZE; i++)
767 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
769 /* now program new ones */
771 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
772 if (ifma->ifma_addr->sa_family != AF_LINK)
775 * Note: the 3c905B currently only supports a 64-bit hash
776 * table, which means we really only need 6 bits, but the
777 * manual indicates that future chip revisions will have a
778 * 256-bit hash table, hence the routine is set up to
779 * calculate 8 bits of position info in case we need it some
781 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have
782 * a 256 bit hash table. This means we have to use all 8 bits
783 * regardless. On older cards, the upper 2 bits will be
786 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
787 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
788 CSR_WRITE_2(sc, XL_COMMAND,
789 h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
792 if_maddr_runlock(ifp);
795 rxfilt |= XL_RXFILTER_MULTIHASH;
797 rxfilt &= ~XL_RXFILTER_MULTIHASH;
799 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
803 xl_setcfg(struct xl_softc *sc)
807 /*XL_LOCK_ASSERT(sc);*/
810 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
811 icfg &= ~XL_ICFG_CONNECTOR_MASK;
812 if (sc->xl_media & XL_MEDIAOPT_MII ||
813 sc->xl_media & XL_MEDIAOPT_BT4)
814 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
815 if (sc->xl_media & XL_MEDIAOPT_BTX)
816 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
818 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
819 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
823 xl_setmode(struct xl_softc *sc, int media)
827 char *pmsg = "", *dmsg = "";
832 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
834 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
836 if (sc->xl_media & XL_MEDIAOPT_BT) {
837 if (IFM_SUBTYPE(media) == IFM_10_T) {
838 pmsg = "10baseT transceiver";
839 sc->xl_xcvr = XL_XCVR_10BT;
840 icfg &= ~XL_ICFG_CONNECTOR_MASK;
841 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
842 mediastat |= XL_MEDIASTAT_LINKBEAT |
843 XL_MEDIASTAT_JABGUARD;
844 mediastat &= ~XL_MEDIASTAT_SQEENB;
848 if (sc->xl_media & XL_MEDIAOPT_BFX) {
849 if (IFM_SUBTYPE(media) == IFM_100_FX) {
850 pmsg = "100baseFX port";
851 sc->xl_xcvr = XL_XCVR_100BFX;
852 icfg &= ~XL_ICFG_CONNECTOR_MASK;
853 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
854 mediastat |= XL_MEDIASTAT_LINKBEAT;
855 mediastat &= ~XL_MEDIASTAT_SQEENB;
859 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
860 if (IFM_SUBTYPE(media) == IFM_10_5) {
862 sc->xl_xcvr = XL_XCVR_AUI;
863 icfg &= ~XL_ICFG_CONNECTOR_MASK;
864 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
865 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
866 XL_MEDIASTAT_JABGUARD);
867 mediastat |= ~XL_MEDIASTAT_SQEENB;
869 if (IFM_SUBTYPE(media) == IFM_10_FL) {
870 pmsg = "10baseFL transceiver";
871 sc->xl_xcvr = XL_XCVR_AUI;
872 icfg &= ~XL_ICFG_CONNECTOR_MASK;
873 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
874 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
875 XL_MEDIASTAT_JABGUARD);
876 mediastat |= ~XL_MEDIASTAT_SQEENB;
880 if (sc->xl_media & XL_MEDIAOPT_BNC) {
881 if (IFM_SUBTYPE(media) == IFM_10_2) {
883 sc->xl_xcvr = XL_XCVR_COAX;
884 icfg &= ~XL_ICFG_CONNECTOR_MASK;
885 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
886 mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
887 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
891 if ((media & IFM_GMASK) == IFM_FDX ||
892 IFM_SUBTYPE(media) == IFM_100_FX) {
895 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
899 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
900 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
903 if (IFM_SUBTYPE(media) == IFM_10_2)
904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
906 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
908 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
910 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
915 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
919 xl_reset(struct xl_softc *sc)
926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
927 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
928 XL_RESETOPT_DISADVFD:0));
931 * If we're using memory mapped register mode, pause briefly
932 * after issuing the reset command before trying to access any
933 * other registers. With my 3c575C cardbus card, failing to do
934 * this results in the system locking up while trying to poll
935 * the command busy bit in the status register.
937 if (sc->xl_flags & XL_FLAG_USE_MMIO)
940 for (i = 0; i < XL_TIMEOUT; i++) {
942 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
947 device_printf(sc->xl_dev, "reset didn't complete\n");
949 /* Reset TX and RX. */
950 /* Note: the RX reset takes an absurd amount of time
951 * on newer versions of the Tornado chips such as those
952 * on the 3c905CX and newer 3c908C cards. We wait an
953 * extra amount of time so that xl_wait() doesn't complain
954 * and annoy the users.
956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
962 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
963 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
965 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
966 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
967 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
968 XL_RESETOPT_INVERT_LED : 0) |
969 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
970 XL_RESETOPT_INVERT_MII : 0));
973 /* Wait a little while for the chip to get its brains in order. */
978 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
979 * IDs against our list and return a device name if we find a match.
982 xl_probe(device_t dev)
984 const struct xl_type *t;
988 while (t->xl_name != NULL) {
989 if ((pci_get_vendor(dev) == t->xl_vid) &&
990 (pci_get_device(dev) == t->xl_did)) {
991 device_set_desc(dev, t->xl_name);
992 return (BUS_PROBE_DEFAULT);
1001 * This routine is a kludge to work around possible hardware faults
1002 * or manufacturing defects that can cause the media options register
1003 * (or reset options register, as it's called for the first generation
1004 * 3c90x adapters) to return an incorrect result. I have encountered
1005 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1006 * which doesn't have any of the 'mediaopt' bits set. This screws up
1007 * the attach routine pretty badly because it doesn't know what media
1008 * to look for. If we find ourselves in this predicament, this routine
1009 * will try to guess the media options values and warn the user of a
1010 * possible manufacturing defect with his adapter/system/whatever.
1013 xl_mediacheck(struct xl_softc *sc)
1017 * If some of the media options bits are set, assume they are
1018 * correct. If not, try to figure it out down below.
1019 * XXX I should check for 10baseFL, but I don't have an adapter
1022 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1024 * Check the XCVR value. If it's not in the normal range
1025 * of values, we need to fake it up here.
1027 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1030 device_printf(sc->xl_dev,
1031 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
1032 device_printf(sc->xl_dev,
1033 "choosing new default based on card type\n");
1036 if (sc->xl_type == XL_TYPE_905B &&
1037 sc->xl_media & XL_MEDIAOPT_10FL)
1039 device_printf(sc->xl_dev,
1040 "WARNING: no media options bits set in the media options register!!\n");
1041 device_printf(sc->xl_dev,
1042 "this could be a manufacturing defect in your adapter or system\n");
1043 device_printf(sc->xl_dev,
1044 "attempting to guess media type; you should probably consult your vendor\n");
1047 xl_choose_xcvr(sc, 1);
1051 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1056 * Read the device ID from the EEPROM.
1057 * This is what's loaded into the PCI device ID register, so it has
1058 * to be correct otherwise we wouldn't have gotten this far.
1060 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1063 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1064 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1065 sc->xl_media = XL_MEDIAOPT_BT;
1066 sc->xl_xcvr = XL_XCVR_10BT;
1068 device_printf(sc->xl_dev,
1069 "guessing 10BaseT transceiver\n");
1071 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1072 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1073 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1074 sc->xl_xcvr = XL_XCVR_10BT;
1076 device_printf(sc->xl_dev,
1077 "guessing COMBO (AUI/BNC/TP)\n");
1079 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1080 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1081 sc->xl_xcvr = XL_XCVR_10BT;
1083 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1085 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1086 sc->xl_media = XL_MEDIAOPT_10FL;
1087 sc->xl_xcvr = XL_XCVR_AUI;
1089 device_printf(sc->xl_dev, "guessing 10baseFL\n");
1091 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1092 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1093 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1094 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1095 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1096 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1097 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1098 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1099 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1100 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1101 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1102 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */
1103 sc->xl_media = XL_MEDIAOPT_MII;
1104 sc->xl_xcvr = XL_XCVR_MII;
1106 device_printf(sc->xl_dev, "guessing MII\n");
1108 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1109 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1110 sc->xl_media = XL_MEDIAOPT_BT4;
1111 sc->xl_xcvr = XL_XCVR_MII;
1113 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1115 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1116 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1117 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1118 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1119 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1120 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1121 sc->xl_media = XL_MEDIAOPT_BTX;
1122 sc->xl_xcvr = XL_XCVR_AUTO;
1124 device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1126 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1127 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1128 sc->xl_xcvr = XL_XCVR_AUTO;
1130 device_printf(sc->xl_dev,
1131 "guessing 10/100 plus BNC/AUI\n");
1134 device_printf(sc->xl_dev,
1135 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1136 sc->xl_media = XL_MEDIAOPT_BT;
1142 * Attach the interface. Allocate softc structures, do ifmedia
1143 * setup and ethernet/BPF attach.
1146 xl_attach(device_t dev)
1148 u_char eaddr[ETHER_ADDR_LEN];
1149 u_int16_t sinfo2, xcvr[2];
1150 struct xl_softc *sc;
1153 int unit, error = 0, rid, res;
1156 sc = device_get_softc(dev);
1159 unit = device_get_unit(dev);
1161 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1163 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1165 did = pci_get_device(dev);
1168 if (did == TC_DEVICEID_HURRICANE_555)
1169 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1170 if (did == TC_DEVICEID_HURRICANE_556 ||
1171 did == TC_DEVICEID_HURRICANE_556B)
1172 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1173 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1174 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1175 if (did == TC_DEVICEID_HURRICANE_555 ||
1176 did == TC_DEVICEID_HURRICANE_556)
1177 sc->xl_flags |= XL_FLAG_8BITROM;
1178 if (did == TC_DEVICEID_HURRICANE_556B)
1179 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1181 if (did == TC_DEVICEID_HURRICANE_575B ||
1182 did == TC_DEVICEID_HURRICANE_575C ||
1183 did == TC_DEVICEID_HURRICANE_656B ||
1184 did == TC_DEVICEID_TORNADO_656C)
1185 sc->xl_flags |= XL_FLAG_FUNCREG;
1186 if (did == TC_DEVICEID_HURRICANE_575A ||
1187 did == TC_DEVICEID_HURRICANE_575B ||
1188 did == TC_DEVICEID_HURRICANE_575C ||
1189 did == TC_DEVICEID_HURRICANE_656B ||
1190 did == TC_DEVICEID_TORNADO_656C)
1191 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1193 if (did == TC_DEVICEID_HURRICANE_656)
1194 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1195 if (did == TC_DEVICEID_HURRICANE_575B)
1196 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1197 if (did == TC_DEVICEID_HURRICANE_575C)
1198 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1199 if (did == TC_DEVICEID_TORNADO_656C)
1200 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1201 if (did == TC_DEVICEID_HURRICANE_656 ||
1202 did == TC_DEVICEID_HURRICANE_656B)
1203 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1204 XL_FLAG_INVERT_LED_PWR;
1205 if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1206 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1207 sc->xl_flags |= XL_FLAG_PHYOK;
1210 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1211 case TC_DEVICEID_HURRICANE_575A:
1212 case TC_DEVICEID_HURRICANE_575B:
1213 case TC_DEVICEID_HURRICANE_575C:
1214 sc->xl_flags |= XL_FLAG_NO_MMIO;
1221 * Map control/status registers.
1223 pci_enable_busmaster(dev);
1225 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1227 res = SYS_RES_MEMORY;
1229 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1232 if (sc->xl_res != NULL) {
1233 sc->xl_flags |= XL_FLAG_USE_MMIO;
1235 device_printf(dev, "using memory mapped I/O\n");
1238 res = SYS_RES_IOPORT;
1239 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1240 if (sc->xl_res == NULL) {
1241 device_printf(dev, "couldn't map ports/memory\n");
1246 device_printf(dev, "using port I/O\n");
1249 sc->xl_btag = rman_get_bustag(sc->xl_res);
1250 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1252 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1253 rid = XL_PCI_FUNCMEM;
1254 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1257 if (sc->xl_fres == NULL) {
1258 device_printf(dev, "couldn't map funcreg memory\n");
1263 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1264 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1267 /* Allocate interrupt */
1269 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1270 RF_SHAREABLE | RF_ACTIVE);
1271 if (sc->xl_irq == NULL) {
1272 device_printf(dev, "couldn't map interrupt\n");
1277 /* Initialize interface name. */
1278 ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1280 device_printf(dev, "can not if_alloc()\n");
1285 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1287 /* Reset the adapter. */
1293 * Get station address from the EEPROM.
1295 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1296 device_printf(dev, "failed to read station address\n");
1301 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0);
1302 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1305 * Now allocate a tag for the DMA descriptor lists and a chunk
1306 * of DMA-able memory based on the tag. Also obtain the DMA
1307 * addresses of the RX and TX ring, which we'll need later.
1308 * All of our lists are allocated as a contiguous block
1311 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1312 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1313 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1314 &sc->xl_ldata.xl_rx_tag);
1316 device_printf(dev, "failed to allocate rx dma tag\n");
1320 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1321 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1322 &sc->xl_ldata.xl_rx_dmamap);
1324 device_printf(dev, "no memory for rx list buffers!\n");
1325 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1326 sc->xl_ldata.xl_rx_tag = NULL;
1330 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1331 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1332 XL_RX_LIST_SZ, xl_dma_map_addr,
1333 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1335 device_printf(dev, "cannot get dma address of the rx ring!\n");
1336 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1337 sc->xl_ldata.xl_rx_dmamap);
1338 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1339 sc->xl_ldata.xl_rx_tag = NULL;
1343 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1344 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1345 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1346 &sc->xl_ldata.xl_tx_tag);
1348 device_printf(dev, "failed to allocate tx dma tag\n");
1352 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1353 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1354 &sc->xl_ldata.xl_tx_dmamap);
1356 device_printf(dev, "no memory for list buffers!\n");
1357 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1358 sc->xl_ldata.xl_tx_tag = NULL;
1362 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1363 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1364 XL_TX_LIST_SZ, xl_dma_map_addr,
1365 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1367 device_printf(dev, "cannot get dma address of the tx ring!\n");
1368 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1369 sc->xl_ldata.xl_tx_dmamap);
1370 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1371 sc->xl_ldata.xl_tx_tag = NULL;
1376 * Allocate a DMA tag for the mapping of mbufs.
1378 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1379 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1380 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1381 NULL, &sc->xl_mtag);
1383 device_printf(dev, "failed to allocate mbuf dma tag\n");
1387 /* We need a spare DMA map for the RX ring. */
1388 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1393 * Figure out the card type. 3c905B adapters have the
1394 * 'supportsNoTxLength' bit set in the capabilities
1395 * word in the EEPROM.
1396 * Note: my 3c575C cardbus card lies. It returns a value
1397 * of 0x1578 for its capabilities word, which is somewhat
1398 * nonsensical. Another way to distinguish a 3c90x chip
1399 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1400 * bit. This will only be set for 3c90x boomerage chips.
1402 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1403 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1404 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1405 sc->xl_type = XL_TYPE_905B;
1407 sc->xl_type = XL_TYPE_90X;
1409 /* Check availability of WOL. */
1410 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1411 pci_find_extcap(dev, PCIY_PMG, &pmcap) == 0) {
1412 sc->xl_pmcap = pmcap;
1413 sc->xl_flags |= XL_FLAG_WOL;
1415 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1416 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1418 "No auxiliary remote wakeup connector!\n");
1421 /* Set the TX start threshold for best performance. */
1422 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1424 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1425 ifp->if_ioctl = xl_ioctl;
1426 ifp->if_capabilities = IFCAP_VLAN_MTU;
1427 if (sc->xl_type == XL_TYPE_905B) {
1428 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1429 #ifdef XL905B_TXCSUM_BROKEN
1430 ifp->if_capabilities |= IFCAP_RXCSUM;
1432 ifp->if_capabilities |= IFCAP_HWCSUM;
1435 if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1436 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1437 ifp->if_capenable = ifp->if_capabilities;
1438 #ifdef DEVICE_POLLING
1439 ifp->if_capabilities |= IFCAP_POLLING;
1441 ifp->if_start = xl_start;
1442 ifp->if_init = xl_init;
1443 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1444 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1445 IFQ_SET_READY(&ifp->if_snd);
1448 * Now we have to see what sort of media we have.
1449 * This includes probing for an MII interace and a
1453 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1455 device_printf(dev, "media options word: %x\n", sc->xl_media);
1457 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1458 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1459 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1460 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1464 if (sc->xl_media & XL_MEDIAOPT_MII ||
1465 sc->xl_media & XL_MEDIAOPT_BTX ||
1466 sc->xl_media & XL_MEDIAOPT_BT4) {
1468 device_printf(dev, "found MII/AUTO\n");
1470 if (mii_phy_probe(dev, &sc->xl_miibus,
1471 xl_ifmedia_upd, xl_ifmedia_sts)) {
1472 device_printf(dev, "no PHY found!\n");
1480 * Sanity check. If the user has selected "auto" and this isn't
1481 * a 10/100 card of some kind, we need to force the transceiver
1482 * type to something sane.
1484 if (sc->xl_xcvr == XL_XCVR_AUTO)
1485 xl_choose_xcvr(sc, bootverbose);
1490 if (sc->xl_media & XL_MEDIAOPT_BT) {
1492 device_printf(dev, "found 10baseT\n");
1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1495 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1496 ifmedia_add(&sc->ifmedia,
1497 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1500 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1502 * Check for a 10baseFL board in disguise.
1504 if (sc->xl_type == XL_TYPE_905B &&
1505 sc->xl_media == XL_MEDIAOPT_10FL) {
1507 device_printf(dev, "found 10baseFL\n");
1508 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1511 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1512 ifmedia_add(&sc->ifmedia,
1513 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1516 device_printf(dev, "found AUI\n");
1517 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1521 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1523 device_printf(dev, "found BNC\n");
1524 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1527 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1529 device_printf(dev, "found 100baseFX\n");
1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1533 media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1534 xl_choose_media(sc, &media);
1536 if (sc->xl_miibus == NULL)
1537 ifmedia_set(&sc->ifmedia, media);
1540 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1542 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1546 * Call MI attach routine.
1548 ether_ifattach(ifp, eaddr);
1550 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1551 NULL, xl_intr, sc, &sc->xl_intrhand);
1553 device_printf(dev, "couldn't set up irq\n");
1554 ether_ifdetach(ifp);
1566 * Choose a default media.
1567 * XXX This is a leaf function only called by xl_attach() and
1568 * acquires/releases the non-recursible driver mutex to
1569 * satisfy lock assertions.
1572 xl_choose_media(struct xl_softc *sc, int *media)
1577 switch (sc->xl_xcvr) {
1579 *media = IFM_ETHER|IFM_10_T;
1580 xl_setmode(sc, *media);
1583 if (sc->xl_type == XL_TYPE_905B &&
1584 sc->xl_media == XL_MEDIAOPT_10FL) {
1585 *media = IFM_ETHER|IFM_10_FL;
1586 xl_setmode(sc, *media);
1588 *media = IFM_ETHER|IFM_10_5;
1589 xl_setmode(sc, *media);
1593 *media = IFM_ETHER|IFM_10_2;
1594 xl_setmode(sc, *media);
1597 case XL_XCVR_100BTX:
1599 /* Chosen by miibus */
1601 case XL_XCVR_100BFX:
1602 *media = IFM_ETHER|IFM_100_FX;
1605 device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1608 * This will probably be wrong, but it prevents
1609 * the ifmedia code from panicking.
1611 *media = IFM_ETHER|IFM_10_T;
1619 * Shutdown hardware and free up resources. This can be called any
1620 * time after the mutex has been initialized. It is called in both
1621 * the error case in attach and the normal detach case so it needs
1622 * to be careful about only freeing resources that have actually been
1626 xl_detach(device_t dev)
1628 struct xl_softc *sc;
1632 sc = device_get_softc(dev);
1635 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1637 #ifdef DEVICE_POLLING
1638 if (ifp && ifp->if_capenable & IFCAP_POLLING)
1639 ether_poll_deregister(ifp);
1642 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1644 res = SYS_RES_MEMORY;
1647 res = SYS_RES_IOPORT;
1650 /* These should only be active if attach succeeded */
1651 if (device_is_attached(dev)) {
1655 taskqueue_drain(taskqueue_swi, &sc->xl_task);
1656 callout_drain(&sc->xl_stat_callout);
1657 ether_ifdetach(ifp);
1660 device_delete_child(dev, sc->xl_miibus);
1661 bus_generic_detach(dev);
1662 ifmedia_removeall(&sc->ifmedia);
1664 if (sc->xl_intrhand)
1665 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1667 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1668 if (sc->xl_fres != NULL)
1669 bus_release_resource(dev, SYS_RES_MEMORY,
1670 XL_PCI_FUNCMEM, sc->xl_fres);
1672 bus_release_resource(dev, res, rid, sc->xl_res);
1678 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1679 bus_dma_tag_destroy(sc->xl_mtag);
1681 if (sc->xl_ldata.xl_rx_tag) {
1682 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1683 sc->xl_ldata.xl_rx_dmamap);
1684 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1685 sc->xl_ldata.xl_rx_dmamap);
1686 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1688 if (sc->xl_ldata.xl_tx_tag) {
1689 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1690 sc->xl_ldata.xl_tx_dmamap);
1691 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1692 sc->xl_ldata.xl_tx_dmamap);
1693 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1696 mtx_destroy(&sc->xl_mtx);
1702 * Initialize the transmit descriptors.
1705 xl_list_tx_init(struct xl_softc *sc)
1707 struct xl_chain_data *cd;
1708 struct xl_list_data *ld;
1715 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1716 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1717 error = bus_dmamap_create(sc->xl_mtag, 0,
1718 &cd->xl_tx_chain[i].xl_map);
1721 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1722 i * sizeof(struct xl_list);
1723 if (i == (XL_TX_LIST_CNT - 1))
1724 cd->xl_tx_chain[i].xl_next = NULL;
1726 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1729 cd->xl_tx_free = &cd->xl_tx_chain[0];
1730 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1732 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1737 * Initialize the transmit descriptors.
1740 xl_list_tx_init_90xB(struct xl_softc *sc)
1742 struct xl_chain_data *cd;
1743 struct xl_list_data *ld;
1750 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1751 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1752 error = bus_dmamap_create(sc->xl_mtag, 0,
1753 &cd->xl_tx_chain[i].xl_map);
1756 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1757 i * sizeof(struct xl_list);
1758 if (i == (XL_TX_LIST_CNT - 1))
1759 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1761 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1763 cd->xl_tx_chain[i].xl_prev =
1764 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1766 cd->xl_tx_chain[i].xl_prev =
1767 &cd->xl_tx_chain[i - 1];
1770 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1771 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1777 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1782 * Initialize the RX descriptors and allocate mbufs for them. Note that
1783 * we arrange the descriptors in a closed ring, so that the last descriptor
1784 * points back to the first.
1787 xl_list_rx_init(struct xl_softc *sc)
1789 struct xl_chain_data *cd;
1790 struct xl_list_data *ld;
1799 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1800 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1801 error = bus_dmamap_create(sc->xl_mtag, 0,
1802 &cd->xl_rx_chain[i].xl_map);
1805 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1808 if (i == (XL_RX_LIST_CNT - 1))
1812 nextptr = ld->xl_rx_dmaaddr +
1813 next * sizeof(struct xl_list_onefrag);
1814 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1815 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1818 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1819 cd->xl_rx_head = &cd->xl_rx_chain[0];
1825 * Initialize an RX descriptor and attach an MBUF cluster.
1826 * If we fail to do so, we need to leave the old mbuf and
1827 * the old DMA map untouched so that it can be reused.
1830 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1832 struct mbuf *m_new = NULL;
1834 bus_dma_segment_t segs[1];
1839 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1843 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1845 /* Force longword alignment for packet payload. */
1846 m_adj(m_new, ETHER_ALIGN);
1848 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1849 segs, &nseg, BUS_DMA_NOWAIT);
1852 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1857 ("%s: too many DMA segments (%d)", __func__, nseg));
1859 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1861 c->xl_map = sc->xl_tmpmap;
1862 sc->xl_tmpmap = map;
1864 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1865 c->xl_ptr->xl_status = 0;
1866 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1867 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1872 xl_rx_resync(struct xl_softc *sc)
1874 struct xl_chain_onefrag *pos;
1879 pos = sc->xl_cdata.xl_rx_head;
1881 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1882 if (pos->xl_ptr->xl_status)
1887 if (i == XL_RX_LIST_CNT)
1890 sc->xl_cdata.xl_rx_head = pos;
1896 * A frame has been uploaded: pass the resulting mbuf chain up to
1897 * the higher level protocols.
1900 xl_rxeof(struct xl_softc *sc)
1903 struct ifnet *ifp = sc->xl_ifp;
1904 struct xl_chain_onefrag *cur_rx;
1911 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1912 BUS_DMASYNC_POSTREAD);
1913 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1914 #ifdef DEVICE_POLLING
1915 if (ifp->if_capenable & IFCAP_POLLING) {
1916 if (sc->rxcycles <= 0)
1921 cur_rx = sc->xl_cdata.xl_rx_head;
1922 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1923 total_len = rxstat & XL_RXSTAT_LENMASK;
1926 * Since we have told the chip to allow large frames,
1927 * we need to trap giant frame errors in software. We allow
1928 * a little more than the normal frame size to account for
1929 * frames with VLAN tags.
1931 if (total_len > XL_MAX_FRAMELEN)
1932 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1935 * If an error occurs, update stats, clear the
1936 * status word and leave the mbuf cluster in place:
1937 * it should simply get re-used next time this descriptor
1938 * comes up in the ring.
1940 if (rxstat & XL_RXSTAT_UP_ERROR) {
1942 cur_rx->xl_ptr->xl_status = 0;
1943 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1944 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1949 * If the error bit was not set, the upload complete
1950 * bit should be set which means we have a valid packet.
1951 * If not, something truly strange has happened.
1953 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1954 device_printf(sc->xl_dev,
1955 "bad receive status -- packet dropped\n");
1957 cur_rx->xl_ptr->xl_status = 0;
1958 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1959 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1963 /* No errors; receive the packet. */
1964 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1965 BUS_DMASYNC_POSTREAD);
1966 m = cur_rx->xl_mbuf;
1969 * Try to conjure up a new mbuf cluster. If that
1970 * fails, it means we have an out of memory condition and
1971 * should leave the buffer in place and continue. This will
1972 * result in a lost packet, but there's little else we
1973 * can do in this situation.
1975 if (xl_newbuf(sc, cur_rx)) {
1977 cur_rx->xl_ptr->xl_status = 0;
1978 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1979 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1982 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1983 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1986 m->m_pkthdr.rcvif = ifp;
1987 m->m_pkthdr.len = m->m_len = total_len;
1989 if (ifp->if_capenable & IFCAP_RXCSUM) {
1990 /* Do IP checksum checking. */
1991 if (rxstat & XL_RXSTAT_IPCKOK)
1992 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1993 if (!(rxstat & XL_RXSTAT_IPCKERR))
1994 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1995 if ((rxstat & XL_RXSTAT_TCPCOK &&
1996 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1997 (rxstat & XL_RXSTAT_UDPCKOK &&
1998 !(rxstat & XL_RXSTAT_UDPCKERR))) {
1999 m->m_pkthdr.csum_flags |=
2000 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2001 m->m_pkthdr.csum_data = 0xffff;
2006 (*ifp->if_input)(ifp, m);
2011 * If we are running from the taskqueue, the interface
2012 * might have been stopped while we were passing the last
2013 * packet up the network stack.
2015 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
2020 * Handle the 'end of channel' condition. When the upload
2021 * engine hits the end of the RX ring, it will stall. This
2022 * is our cue to flush the RX ring, reload the uplist pointer
2023 * register and unstall the engine.
2024 * XXX This is actually a little goofy. With the ThunderLAN
2025 * chip, you get an interrupt when the receiver hits the end
2026 * of the receive ring, which tells you exactly when you
2027 * you need to reload the ring pointer. Here we have to
2028 * fake it. I'm mad at myself for not being clever enough
2029 * to avoid the use of a goto here.
2031 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2032 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2033 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2035 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2036 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2037 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2044 * Taskqueue wrapper for xl_rxeof().
2047 xl_rxeof_task(void *arg, int pending)
2049 struct xl_softc *sc = (struct xl_softc *)arg;
2052 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
2058 * A frame was downloaded to the chip. It's safe for us to clean up
2062 xl_txeof(struct xl_softc *sc)
2064 struct xl_chain *cur_tx;
2065 struct ifnet *ifp = sc->xl_ifp;
2070 * Go through our tx list and free mbufs for those
2071 * frames that have been uploaded. Note: the 3c905B
2072 * sets a special bit in the status word to let us
2073 * know that a frame has been downloaded, but the
2074 * original 3c900/3c905 adapters don't do that.
2075 * Consequently, we have to use a different test if
2076 * xl_type != XL_TYPE_905B.
2078 while (sc->xl_cdata.xl_tx_head != NULL) {
2079 cur_tx = sc->xl_cdata.xl_tx_head;
2081 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2084 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2085 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2086 BUS_DMASYNC_POSTWRITE);
2087 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2088 m_freem(cur_tx->xl_mbuf);
2089 cur_tx->xl_mbuf = NULL;
2091 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2093 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2094 sc->xl_cdata.xl_tx_free = cur_tx;
2097 if (sc->xl_cdata.xl_tx_head == NULL) {
2098 sc->xl_wdog_timer = 0;
2099 sc->xl_cdata.xl_tx_tail = NULL;
2101 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2102 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2103 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2104 sc->xl_cdata.xl_tx_head->xl_phys);
2105 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2111 xl_txeof_90xB(struct xl_softc *sc)
2113 struct xl_chain *cur_tx = NULL;
2114 struct ifnet *ifp = sc->xl_ifp;
2119 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2120 BUS_DMASYNC_POSTREAD);
2121 idx = sc->xl_cdata.xl_tx_cons;
2122 while (idx != sc->xl_cdata.xl_tx_prod) {
2123 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2125 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2126 XL_TXSTAT_DL_COMPLETE))
2129 if (cur_tx->xl_mbuf != NULL) {
2130 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2131 BUS_DMASYNC_POSTWRITE);
2132 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2133 m_freem(cur_tx->xl_mbuf);
2134 cur_tx->xl_mbuf = NULL;
2139 sc->xl_cdata.xl_tx_cnt--;
2140 XL_INC(idx, XL_TX_LIST_CNT);
2143 if (sc->xl_cdata.xl_tx_cnt == 0)
2144 sc->xl_wdog_timer = 0;
2145 sc->xl_cdata.xl_tx_cons = idx;
2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2152 * TX 'end of channel' interrupt handler. Actually, we should
2153 * only get a 'TX complete' interrupt if there's a transmit error,
2154 * so this is really TX error handler.
2157 xl_txeoc(struct xl_softc *sc)
2163 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2164 if (txstat & XL_TXSTATUS_UNDERRUN ||
2165 txstat & XL_TXSTATUS_JABBER ||
2166 txstat & XL_TXSTATUS_RECLAIM) {
2167 device_printf(sc->xl_dev,
2168 "transmission error: %x\n", txstat);
2169 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2171 if (sc->xl_type == XL_TYPE_905B) {
2172 if (sc->xl_cdata.xl_tx_cnt) {
2176 i = sc->xl_cdata.xl_tx_cons;
2177 c = &sc->xl_cdata.xl_tx_chain[i];
2178 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2180 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2183 if (sc->xl_cdata.xl_tx_head != NULL)
2184 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2185 sc->xl_cdata.xl_tx_head->xl_phys);
2188 * Remember to set this for the
2189 * first generation 3c90X chips.
2191 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2192 if (txstat & XL_TXSTATUS_UNDERRUN &&
2193 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2194 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2195 device_printf(sc->xl_dev,
2196 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2198 CSR_WRITE_2(sc, XL_COMMAND,
2199 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2200 if (sc->xl_type == XL_TYPE_905B) {
2201 CSR_WRITE_2(sc, XL_COMMAND,
2202 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2207 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2208 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2211 * Write an arbitrary byte to the TX_STATUS register
2212 * to clear this interrupt/error and advance to the next.
2214 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2221 struct xl_softc *sc = arg;
2222 struct ifnet *ifp = sc->xl_ifp;
2227 #ifdef DEVICE_POLLING
2228 if (ifp->if_capenable & IFCAP_POLLING) {
2234 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS &&
2236 CSR_WRITE_2(sc, XL_COMMAND,
2237 XL_CMD_INTR_ACK|(status & XL_INTRS));
2239 if (status & XL_STAT_UP_COMPLETE) {
2242 curpkts = ifp->if_ipackets;
2244 if (curpkts == ifp->if_ipackets) {
2245 while (xl_rx_resync(sc))
2250 if (status & XL_STAT_DOWN_COMPLETE) {
2251 if (sc->xl_type == XL_TYPE_905B)
2257 if (status & XL_STAT_TX_COMPLETE) {
2262 if (status & XL_STAT_ADFAIL) {
2263 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2267 if (status & XL_STAT_STATSOFLOW) {
2268 sc->xl_stats_no_timeout = 1;
2269 xl_stats_update_locked(sc);
2270 sc->xl_stats_no_timeout = 0;
2274 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2275 if (sc->xl_type == XL_TYPE_905B)
2276 xl_start_90xB_locked(ifp);
2278 xl_start_locked(ifp);
2284 #ifdef DEVICE_POLLING
2286 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2288 struct xl_softc *sc = ifp->if_softc;
2292 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2293 rx_npkts = xl_poll_locked(ifp, cmd, count);
2299 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2301 struct xl_softc *sc = ifp->if_softc;
2306 sc->rxcycles = count;
2307 rx_npkts = xl_rxeof(sc);
2308 if (sc->xl_type == XL_TYPE_905B)
2313 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2314 if (sc->xl_type == XL_TYPE_905B)
2315 xl_start_90xB_locked(ifp);
2317 xl_start_locked(ifp);
2320 if (cmd == POLL_AND_CHECK_STATUS) {
2323 status = CSR_READ_2(sc, XL_STATUS);
2324 if (status & XL_INTRS && status != 0xFFFF) {
2325 CSR_WRITE_2(sc, XL_COMMAND,
2326 XL_CMD_INTR_ACK|(status & XL_INTRS));
2328 if (status & XL_STAT_TX_COMPLETE) {
2333 if (status & XL_STAT_ADFAIL) {
2334 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2338 if (status & XL_STAT_STATSOFLOW) {
2339 sc->xl_stats_no_timeout = 1;
2340 xl_stats_update_locked(sc);
2341 sc->xl_stats_no_timeout = 0;
2347 #endif /* DEVICE_POLLING */
2350 * XXX: This is an entry point for callout which needs to take the lock.
2353 xl_stats_update(void *xsc)
2355 struct xl_softc *sc = xsc;
2359 if (xl_watchdog(sc) == EJUSTRETURN)
2362 xl_stats_update_locked(sc);
2366 xl_stats_update_locked(struct xl_softc *sc)
2368 struct ifnet *ifp = sc->xl_ifp;
2369 struct xl_stats xl_stats;
2372 struct mii_data *mii = NULL;
2376 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2378 if (sc->xl_miibus != NULL)
2379 mii = device_get_softc(sc->xl_miibus);
2381 p = (u_int8_t *)&xl_stats;
2383 /* Read all the stats registers. */
2386 for (i = 0; i < 16; i++)
2387 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2389 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2391 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2392 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision;
2395 * Boomerang and cyclone chips have an extra stats counter
2396 * in window 4 (BadSSD). We have to read this too in order
2397 * to clear out all the stats registers and avoid a statsoflow
2401 CSR_READ_1(sc, XL_W4_BADSSD);
2403 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2408 if (!sc->xl_stats_no_timeout)
2409 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2413 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2414 * pointers to the fragment pointers.
2417 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2420 struct ifnet *ifp = sc->xl_ifp;
2421 int error, i, nseg, total_len;
2426 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2427 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2429 if (error && error != EFBIG) {
2430 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2435 * Handle special case: we used up all 63 fragments,
2436 * but we have more mbufs left in the chain. Copy the
2437 * data into an mbuf cluster. Note that we don't
2438 * bother clearing the values in the other fragment
2439 * pointers/counters; it wouldn't gain us anything,
2440 * and would waste cycles.
2443 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS);
2444 if (m_new == NULL) {
2451 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2452 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2456 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2461 KASSERT(nseg <= XL_MAXFRAGS,
2462 ("%s: too many DMA segments (%d)", __func__, nseg));
2470 for (i = 0; i < nseg; i++) {
2471 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2472 ("segment size too large"));
2473 c->xl_ptr->xl_frag[i].xl_addr =
2474 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2475 c->xl_ptr->xl_frag[i].xl_len =
2476 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2477 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2479 c->xl_ptr->xl_frag[nseg - 1].xl_len =
2480 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG);
2481 c->xl_ptr->xl_status = htole32(total_len);
2482 c->xl_ptr->xl_next = 0;
2484 if (sc->xl_type == XL_TYPE_905B) {
2485 status = XL_TXSTAT_RND_DEFEAT;
2487 #ifndef XL905B_TXCSUM_BROKEN
2488 if ((*m_head)->m_pkthdr.csum_flags) {
2489 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2490 status |= XL_TXSTAT_IPCKSUM;
2491 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2492 status |= XL_TXSTAT_TCPCKSUM;
2493 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2494 status |= XL_TXSTAT_UDPCKSUM;
2497 c->xl_ptr->xl_status = htole32(status);
2500 c->xl_mbuf = *m_head;
2501 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2506 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2507 * to the mbuf data regions directly in the transmit lists. We also save a
2508 * copy of the pointers since the transmit list fragment pointers are
2509 * physical addresses.
2513 xl_start(struct ifnet *ifp)
2515 struct xl_softc *sc = ifp->if_softc;
2519 if (sc->xl_type == XL_TYPE_905B)
2520 xl_start_90xB_locked(ifp);
2522 xl_start_locked(ifp);
2528 xl_start_locked(struct ifnet *ifp)
2530 struct xl_softc *sc = ifp->if_softc;
2531 struct mbuf *m_head = NULL;
2532 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2538 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2542 * Check for an available queue slot. If there are none,
2545 if (sc->xl_cdata.xl_tx_free == NULL) {
2548 if (sc->xl_cdata.xl_tx_free == NULL) {
2549 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2554 start_tx = sc->xl_cdata.xl_tx_free;
2556 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2557 sc->xl_cdata.xl_tx_free != NULL;) {
2558 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2562 /* Pick a descriptor off the free list. */
2563 cur_tx = sc->xl_cdata.xl_tx_free;
2565 /* Pack the data into the descriptor. */
2566 error = xl_encap(sc, cur_tx, &m_head);
2570 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2571 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2575 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2576 cur_tx->xl_next = NULL;
2578 /* Chain it together. */
2580 prev->xl_next = cur_tx;
2581 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2586 * If there's a BPF listener, bounce a copy of this frame
2589 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2593 * If there are no packets queued, bail.
2599 * Place the request for the upload interrupt
2600 * in the last descriptor in the chain. This way, if
2601 * we're chaining several packets at once, we'll only
2602 * get an interrupt once for the whole chain rather than
2603 * once for each packet.
2605 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2607 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2608 BUS_DMASYNC_PREWRITE);
2611 * Queue the packets. If the TX channel is clear, update
2612 * the downlist pointer register.
2614 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2617 if (sc->xl_cdata.xl_tx_head != NULL) {
2618 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2619 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2620 htole32(start_tx->xl_phys);
2621 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2622 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2623 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2624 sc->xl_cdata.xl_tx_tail = cur_tx;
2626 sc->xl_cdata.xl_tx_head = start_tx;
2627 sc->xl_cdata.xl_tx_tail = cur_tx;
2629 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2630 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2632 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2637 * Set a timeout in case the chip goes out to lunch.
2639 sc->xl_wdog_timer = 5;
2642 * XXX Under certain conditions, usually on slower machines
2643 * where interrupts may be dropped, it's possible for the
2644 * adapter to chew up all the buffers in the receive ring
2645 * and stall, without us being able to do anything about it.
2646 * To guard against this, we need to make a pass over the
2647 * RX queue to make sure there aren't any packets pending.
2648 * Doing it here means we can flush the receive ring at the
2649 * same time the chip is DMAing the transmit descriptors we
2652 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2653 * nature of their chips in all their marketing literature;
2654 * we may as well take advantage of it. :)
2656 taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2660 xl_start_90xB_locked(struct ifnet *ifp)
2662 struct xl_softc *sc = ifp->if_softc;
2663 struct mbuf *m_head = NULL;
2664 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2669 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2673 idx = sc->xl_cdata.xl_tx_prod;
2674 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2676 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2677 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2678 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2679 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2683 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2687 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2689 /* Pack the data into the descriptor. */
2690 error = xl_encap(sc, cur_tx, &m_head);
2694 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2695 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2699 /* Chain it together. */
2701 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2705 * If there's a BPF listener, bounce a copy of this frame
2708 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2710 XL_INC(idx, XL_TX_LIST_CNT);
2711 sc->xl_cdata.xl_tx_cnt++;
2715 * If there are no packets queued, bail.
2721 * Place the request for the upload interrupt
2722 * in the last descriptor in the chain. This way, if
2723 * we're chaining several packets at once, we'll only
2724 * get an interrupt once for the whole chain rather than
2725 * once for each packet.
2727 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2729 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2730 BUS_DMASYNC_PREWRITE);
2732 /* Start transmission */
2733 sc->xl_cdata.xl_tx_prod = idx;
2734 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2737 * Set a timeout in case the chip goes out to lunch.
2739 sc->xl_wdog_timer = 5;
2745 struct xl_softc *sc = xsc;
2753 xl_init_locked(struct xl_softc *sc)
2755 struct ifnet *ifp = sc->xl_ifp;
2757 u_int16_t rxfilt = 0;
2758 struct mii_data *mii = NULL;
2762 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2765 * Cancel pending I/O and free all RX/TX buffers.
2769 /* Reset the chip to a known state. */
2772 if (sc->xl_miibus == NULL) {
2773 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2780 if (sc->xl_miibus != NULL)
2781 mii = device_get_softc(sc->xl_miibus);
2784 * Clear WOL status and disable all WOL feature as WOL
2785 * would interfere Rx operation under normal environments.
2787 if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2789 CSR_READ_2(sc, XL_W7_BM_PME);
2790 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2792 /* Init our MAC address */
2794 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2795 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2796 IF_LLADDR(sc->xl_ifp)[i]);
2799 /* Clear the station mask. */
2800 for (i = 0; i < 3; i++)
2801 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2803 /* Reset TX and RX. */
2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2809 /* Init circular RX list. */
2810 error = xl_list_rx_init(sc);
2812 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2818 /* Init TX descriptors. */
2819 if (sc->xl_type == XL_TYPE_905B)
2820 error = xl_list_tx_init_90xB(sc);
2822 error = xl_list_tx_init(sc);
2824 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2831 * Set the TX freethresh value.
2832 * Note that this has no effect on 3c905B "cyclone"
2833 * cards but is required for 3c900/3c905 "boomerang"
2834 * cards in order to enable the download engine.
2836 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2838 /* Set the TX start threshold for best performance. */
2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2842 * If this is a 3c905B, also set the tx reclaim threshold.
2843 * This helps cut down on the number of tx reclaim errors
2844 * that could happen on a busy network. The chip multiplies
2845 * the register value by 16 to obtain the actual threshold
2846 * in bytes, so we divide by 16 when setting the value here.
2847 * The existing threshold value can be examined by reading
2848 * the register at offset 9 in window 5.
2850 if (sc->xl_type == XL_TYPE_905B) {
2851 CSR_WRITE_2(sc, XL_COMMAND,
2852 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2855 /* Set RX filter bits. */
2857 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2859 /* Set the individual bit to receive frames for this host only. */
2860 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2862 /* If we want promiscuous mode, set the allframes bit. */
2863 if (ifp->if_flags & IFF_PROMISC) {
2864 rxfilt |= XL_RXFILTER_ALLFRAMES;
2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2867 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2872 * Set capture broadcast bit to capture broadcast frames.
2874 if (ifp->if_flags & IFF_BROADCAST) {
2875 rxfilt |= XL_RXFILTER_BROADCAST;
2876 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2878 rxfilt &= ~XL_RXFILTER_BROADCAST;
2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2883 * Program the multicast filter, if necessary.
2885 if (sc->xl_type == XL_TYPE_905B)
2886 xl_setmulti_hash(sc);
2891 * Load the address of the RX list. We have to
2892 * stall the upload engine before we can manipulate
2893 * the uplist pointer register, then unstall it when
2894 * we're finished. We also have to wait for the
2895 * stall command to complete before proceeding.
2896 * Note that we have to do this after any RX resets
2897 * have completed since the uplist register is cleared
2900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2902 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2906 if (sc->xl_type == XL_TYPE_905B) {
2907 /* Set polling interval */
2908 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2909 /* Load the address of the TX list */
2910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2912 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2913 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2914 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2919 * If the coax transceiver is on, make sure to enable
2920 * the DC-DC converter.
2923 if (sc->xl_xcvr == XL_XCVR_COAX)
2924 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2929 * increase packet size to allow reception of 802.1q or ISL packets.
2930 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2931 * control register. For 3c90xB/C chips, use the RX packet size
2935 if (sc->xl_type == XL_TYPE_905B)
2936 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2939 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2940 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2941 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2944 /* Clear out the stats counters. */
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2946 sc->xl_stats_no_timeout = 1;
2947 xl_stats_update_locked(sc);
2948 sc->xl_stats_no_timeout = 0;
2950 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2954 * Enable interrupts.
2956 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2958 #ifdef DEVICE_POLLING
2959 /* Disable interrupts if we are polling. */
2960 if (ifp->if_capenable & IFCAP_POLLING)
2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2965 if (sc->xl_flags & XL_FLAG_FUNCREG)
2966 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2968 /* Set the RX early threshold */
2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2970 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2972 /* Enable receiver and transmitter. */
2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2975 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2978 /* XXX Downcall to miibus. */
2982 /* Select window 7 for normal operations. */
2985 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2986 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2988 sc->xl_wdog_timer = 0;
2989 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc);
2993 * Set media options.
2996 xl_ifmedia_upd(struct ifnet *ifp)
2998 struct xl_softc *sc = ifp->if_softc;
2999 struct ifmedia *ifm = NULL;
3000 struct mii_data *mii = NULL;
3004 if (sc->xl_miibus != NULL)
3005 mii = device_get_softc(sc->xl_miibus);
3009 ifm = &mii->mii_media;
3011 switch (IFM_SUBTYPE(ifm->ifm_media)) {
3016 xl_setmode(sc, ifm->ifm_media);
3021 if (sc->xl_media & XL_MEDIAOPT_MII ||
3022 sc->xl_media & XL_MEDIAOPT_BTX ||
3023 sc->xl_media & XL_MEDIAOPT_BT4) {
3024 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3027 xl_setmode(sc, ifm->ifm_media);
3036 * Report current media status.
3039 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3041 struct xl_softc *sc = ifp->if_softc;
3043 u_int16_t status = 0;
3044 struct mii_data *mii = NULL;
3048 if (sc->xl_miibus != NULL)
3049 mii = device_get_softc(sc->xl_miibus);
3052 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3055 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3056 icfg >>= XL_ICFG_CONNECTOR_BITS;
3058 ifmr->ifm_active = IFM_ETHER;
3059 ifmr->ifm_status = IFM_AVALID;
3061 if ((status & XL_MEDIASTAT_CARRIER) == 0)
3062 ifmr->ifm_status |= IFM_ACTIVE;
3066 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3067 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3068 ifmr->ifm_active |= IFM_FDX;
3070 ifmr->ifm_active |= IFM_HDX;
3073 if (sc->xl_type == XL_TYPE_905B &&
3074 sc->xl_media == XL_MEDIAOPT_10FL) {
3075 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3076 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3077 ifmr->ifm_active |= IFM_FDX;
3079 ifmr->ifm_active |= IFM_HDX;
3081 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3084 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3087 * XXX MII and BTX/AUTO should be separate cases.
3090 case XL_XCVR_100BTX:
3095 ifmr->ifm_active = mii->mii_media_active;
3096 ifmr->ifm_status = mii->mii_media_status;
3099 case XL_XCVR_100BFX:
3100 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3103 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3111 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3113 struct xl_softc *sc = ifp->if_softc;
3114 struct ifreq *ifr = (struct ifreq *) data;
3115 int error = 0, mask;
3116 struct mii_data *mii = NULL;
3124 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3125 if (ifp->if_flags & IFF_UP) {
3126 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3127 ifp->if_flags & IFF_PROMISC &&
3128 !(sc->xl_if_flags & IFF_PROMISC)) {
3129 rxfilt |= XL_RXFILTER_ALLFRAMES;
3130 CSR_WRITE_2(sc, XL_COMMAND,
3131 XL_CMD_RX_SET_FILT|rxfilt);
3133 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3134 !(ifp->if_flags & IFF_PROMISC) &&
3135 sc->xl_if_flags & IFF_PROMISC) {
3136 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3137 CSR_WRITE_2(sc, XL_COMMAND,
3138 XL_CMD_RX_SET_FILT|rxfilt);
3143 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3146 sc->xl_if_flags = ifp->if_flags;
3152 /* XXX Downcall from if_addmulti() possibly with locks held. */
3154 if (sc->xl_type == XL_TYPE_905B)
3155 xl_setmulti_hash(sc);
3163 if (sc->xl_miibus != NULL)
3164 mii = device_get_softc(sc->xl_miibus);
3166 error = ifmedia_ioctl(ifp, ifr,
3167 &sc->ifmedia, command);
3169 error = ifmedia_ioctl(ifp, ifr,
3170 &mii->mii_media, command);
3173 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3174 #ifdef DEVICE_POLLING
3175 if ((mask & IFCAP_POLLING) != 0 &&
3176 (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3177 ifp->if_capenable ^= IFCAP_POLLING;
3178 if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3179 error = ether_poll_register(xl_poll, ifp);
3183 /* Disable interrupts */
3184 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3185 ifp->if_capenable |= IFCAP_POLLING;
3188 error = ether_poll_deregister(ifp);
3189 /* Enable interrupts. */
3191 CSR_WRITE_2(sc, XL_COMMAND,
3192 XL_CMD_INTR_ACK | 0xFF);
3193 CSR_WRITE_2(sc, XL_COMMAND,
3194 XL_CMD_INTR_ENB | XL_INTRS);
3195 if (sc->xl_flags & XL_FLAG_FUNCREG)
3196 bus_space_write_4(sc->xl_ftag,
3197 sc->xl_fhandle, 4, 0x8000);
3201 #endif /* DEVICE_POLLING */
3203 if ((mask & IFCAP_TXCSUM) != 0 &&
3204 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3205 ifp->if_capenable ^= IFCAP_TXCSUM;
3206 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3207 ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3209 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3211 if ((mask & IFCAP_RXCSUM) != 0 &&
3212 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3213 ifp->if_capenable ^= IFCAP_RXCSUM;
3214 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3215 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3216 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3220 error = ether_ioctl(ifp, command, data);
3228 xl_watchdog(struct xl_softc *sc)
3230 struct ifnet *ifp = sc->xl_ifp;
3231 u_int16_t status = 0;
3236 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3242 if (sc->xl_type == XL_TYPE_905B) {
3244 if (sc->xl_cdata.xl_tx_cnt == 0)
3248 if (sc->xl_cdata.xl_tx_head == NULL)
3252 device_printf(sc->xl_dev,
3253 "watchdog timeout (missed Tx interrupts) -- recovering\n");
3259 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3260 device_printf(sc->xl_dev, "watchdog timeout\n");
3262 if (status & XL_MEDIASTAT_CARRIER)
3263 device_printf(sc->xl_dev,
3264 "no carrier - transceiver cable problem?\n");
3266 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3269 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3270 if (sc->xl_type == XL_TYPE_905B)
3271 xl_start_90xB_locked(ifp);
3273 xl_start_locked(ifp);
3276 return (EJUSTRETURN);
3280 * Stop the adapter and free any mbufs allocated to the
3284 xl_stop(struct xl_softc *sc)
3287 struct ifnet *ifp = sc->xl_ifp;
3291 sc->xl_wdog_timer = 0;
3293 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3298 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3299 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3303 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3305 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3310 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3312 if (sc->xl_flags & XL_FLAG_FUNCREG)
3313 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3315 /* Stop the stats updater. */
3316 callout_stop(&sc->xl_stat_callout);
3319 * Free data in the RX lists.
3321 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3322 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3323 bus_dmamap_unload(sc->xl_mtag,
3324 sc->xl_cdata.xl_rx_chain[i].xl_map);
3325 bus_dmamap_destroy(sc->xl_mtag,
3326 sc->xl_cdata.xl_rx_chain[i].xl_map);
3327 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3328 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3331 if (sc->xl_ldata.xl_rx_list != NULL)
3332 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3334 * Free the TX list buffers.
3336 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3337 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3338 bus_dmamap_unload(sc->xl_mtag,
3339 sc->xl_cdata.xl_tx_chain[i].xl_map);
3340 bus_dmamap_destroy(sc->xl_mtag,
3341 sc->xl_cdata.xl_tx_chain[i].xl_map);
3342 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3343 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3346 if (sc->xl_ldata.xl_tx_list != NULL)
3347 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3349 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3353 * Stop all chip I/O so that the kernel's probe routines don't
3354 * get confused by errant DMAs when rebooting.
3357 xl_shutdown(device_t dev)
3360 return (xl_suspend(dev));
3364 xl_suspend(device_t dev)
3366 struct xl_softc *sc;
3368 sc = device_get_softc(dev);
3379 xl_resume(device_t dev)
3381 struct xl_softc *sc;
3384 sc = device_get_softc(dev);
3389 if (ifp->if_flags & IFF_UP) {
3390 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3400 xl_setwol(struct xl_softc *sc)
3403 u_int16_t cfg, pmstat;
3405 if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3410 /* Clear any pending PME events. */
3411 CSR_READ_2(sc, XL_W7_BM_PME);
3413 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3414 cfg |= XL_BM_PME_MAGIC;
3415 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3417 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3418 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3420 pmstat = pci_read_config(sc->xl_dev,
3421 sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3422 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3423 pmstat |= PCIM_PSTAT_PMEENABLE;
3425 pmstat &= ~PCIM_PSTAT_PMEENABLE;
3426 pci_write_config(sc->xl_dev,
3427 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);