2 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2012 Joachim Eastwood <manabian@gmail.com>
8 * Based on at91sam9260.dtsi
10 * Licensed under GPLv2 or later.
13 #include "skeleton.dtsi"
14 #include <dt-bindings/pinctrl/at91.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/clock/at91.h>
20 model = "Atmel AT91RM9200 family SoC";
21 compatible = "atmel,at91rm9200";
22 interrupt-parent = <&aic>;
46 compatible = "arm,arm920t";
52 reg = <0x20000000 0x04000000>;
56 slow_xtal: slow_xtal {
57 compatible = "fixed-clock";
59 clock-frequency = <0>;
62 main_xtal: main_xtal {
63 compatible = "fixed-clock";
65 clock-frequency = <0>;
70 compatible = "mmio-sram";
71 reg = <0x00200000 0x4000>;
75 compatible = "simple-bus";
81 compatible = "simple-bus";
86 aic: interrupt-controller@fffff000 {
87 #interrupt-cells = <3>;
88 compatible = "atmel,at91rm9200-aic";
90 reg = <0xfffff000 0x200>;
91 atmel,external-irqs = <25 26 27 28 29 30 31>;
94 ramc0: ramc@ffffff00 {
95 compatible = "atmel,at91rm9200-sdramc";
96 reg = <0xffffff00 0x100>;
100 compatible = "atmel,at91rm9200-pmc";
101 reg = <0xfffffc00 0x100>;
102 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
103 interrupt-controller;
104 #address-cells = <1>;
106 #interrupt-cells = <1>;
109 compatible = "atmel,at91rm9200-clk-main-osc";
111 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
112 clocks = <&main_xtal>;
116 compatible = "atmel,at91rm9200-clk-main";
118 clocks = <&main_osc>;
122 compatible = "atmel,at91rm9200-clk-pll";
124 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
127 atmel,clk-input-range = <1000000 32000000>;
128 #atmel,pll-clk-output-range-cells = <3>;
129 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
130 <150000000 180000000 2>;
134 compatible = "atmel,at91rm9200-clk-pll";
136 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
139 atmel,clk-input-range = <1000000 32000000>;
140 #atmel,pll-clk-output-range-cells = <3>;
141 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
142 <150000000 180000000 2>;
146 compatible = "atmel,at91rm9200-clk-master";
148 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
149 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
150 atmel,clk-output-range = <0 80000000>;
151 atmel,clk-divisors = <1 2 3 4>;
155 compatible = "atmel,at91rm9200-clk-usb";
157 atmel,clk-divisors = <1 2 0 0>;
162 compatible = "atmel,at91rm9200-clk-programmable";
163 #address-cells = <1>;
165 interrupt-parent = <&pmc>;
166 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
171 interrupts = <AT91_PMC_PCKRDY(0)>;
177 interrupts = <AT91_PMC_PCKRDY(1)>;
183 interrupts = <AT91_PMC_PCKRDY(2)>;
189 interrupts = <AT91_PMC_PCKRDY(3)>;
194 compatible = "atmel,at91rm9200-clk-system";
195 #address-cells = <1>;
236 compatible = "atmel,at91rm9200-clk-peripheral";
237 #address-cells = <1>;
261 usart0_clk: usart0_clk {
266 usart1_clk: usart1_clk {
271 usart2_clk: usart2_clk {
276 usart3_clk: usart3_clk {
351 macb0_clk: macb0_clk {
359 compatible = "atmel,at91rm9200-st";
360 reg = <0xfffffd00 0x100>;
361 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
365 compatible = "atmel,at91rm9200-rtc";
366 reg = <0xfffffe00 0x40>;
367 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
371 tcb0: timer@fffa0000 {
372 compatible = "atmel,at91rm9200-tcb";
373 reg = <0xfffa0000 0x100>;
374 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
375 18 IRQ_TYPE_LEVEL_HIGH 0
376 19 IRQ_TYPE_LEVEL_HIGH 0>;
377 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
378 clock-names = "t0_clk", "t1_clk", "t2_clk";
381 tcb1: timer@fffa4000 {
382 compatible = "atmel,at91rm9200-tcb";
383 reg = <0xfffa4000 0x100>;
384 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
385 21 IRQ_TYPE_LEVEL_HIGH 0
386 22 IRQ_TYPE_LEVEL_HIGH 0>;
387 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
388 clock-names = "t0_clk", "t1_clk", "t2_clk";
392 compatible = "atmel,at91rm9200-i2c";
393 reg = <0xfffb8000 0x4000>;
394 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_twi>;
397 clocks = <&twi0_clk>;
398 #address-cells = <1>;
404 compatible = "atmel,hsmci";
405 reg = <0xfffb4000 0x4000>;
406 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
407 clocks = <&mci0_clk>;
408 clock-names = "mci_clk";
409 #address-cells = <1>;
411 pinctrl-names = "default";
416 compatible = "atmel,at91rm9200-ssc";
417 reg = <0xfffd0000 0x4000>;
418 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
421 clocks = <&ssc0_clk>;
422 clock-names = "pclk";
427 compatible = "atmel,at91rm9200-ssc";
428 reg = <0xfffd4000 0x4000>;
429 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
432 clocks = <&ssc1_clk>;
433 clock-names = "pclk";
438 compatible = "atmel,at91rm9200-ssc";
439 reg = <0xfffd8000 0x4000>;
440 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
443 clocks = <&ssc2_clk>;
444 clock-names = "pclk";
448 macb0: ethernet@fffbc000 {
449 compatible = "cdns,at91rm9200-emac", "cdns,emac";
450 reg = <0xfffbc000 0x4000>;
451 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_macb_rmii>;
455 clocks = <&macb0_clk>;
456 clock-names = "ether_clk";
461 #address-cells = <1>;
463 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
464 ranges = <0xfffff400 0xfffff400 0x800>;
468 0xffffffff 0xffffffff /* pioA */
469 0xffffffff 0x083fffff /* pioB */
470 0xffff3fff 0x00000000 /* pioC */
471 0x03ff87ff 0x0fffff80 /* pioD */
474 /* shared pinctrl settings */
476 pinctrl_dbgu: dbgu-0 {
478 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A */
479 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA31 periph with pullup */
484 pinctrl_uart0: uart0-0 {
486 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
487 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
490 pinctrl_uart0_cts: uart0_cts-0 {
492 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
495 pinctrl_uart0_rts: uart0_rts-0 {
497 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
502 pinctrl_uart1: uart1-0 {
504 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB20 periph A with pullup */
505 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
508 pinctrl_uart1_rts: uart1_rts-0 {
510 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
513 pinctrl_uart1_cts: uart1_cts-0 {
515 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
518 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
520 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
521 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
524 pinctrl_uart1_dcd: uart1_dcd-0 {
526 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
529 pinctrl_uart1_ri: uart1_ri-0 {
531 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
536 pinctrl_uart2: uart2-0 {
538 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA22 periph A */
539 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
542 pinctrl_uart2_rts: uart2_rts-0 {
544 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
547 pinctrl_uart2_cts: uart2_cts-0 {
549 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
554 pinctrl_uart3: uart3-0 {
556 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
557 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA6 periph B */
560 pinctrl_uart3_rts: uart3_rts-0 {
562 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
565 pinctrl_uart3_cts: uart3_cts-0 {
567 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
572 pinctrl_nand: nand-0 {
574 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */
575 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */
580 pinctrl_macb_rmii: macb_rmii-0 {
582 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */
583 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */
584 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
585 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
586 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
587 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
588 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
589 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
590 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
591 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
594 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
596 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */
597 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */
598 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */
599 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */
600 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */
601 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */
602 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */
603 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
608 pinctrl_mmc0_clk: mmc0_clk-0 {
610 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
613 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
615 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
616 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */
619 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
621 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
622 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
623 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */
626 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
628 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
629 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */
632 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
634 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */
635 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
636 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */
641 pinctrl_ssc0_tx: ssc0_tx-0 {
643 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
644 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
645 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */
648 pinctrl_ssc0_rx: ssc0_rx-0 {
650 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
651 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
652 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
657 pinctrl_ssc1_tx: ssc1_tx-0 {
659 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
660 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
661 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
664 pinctrl_ssc1_rx: ssc1_rx-0 {
666 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
667 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
668 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
673 pinctrl_ssc2_tx: ssc2_tx-0 {
675 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
676 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
677 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
680 pinctrl_ssc2_rx: ssc2_rx-0 {
682 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
683 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
684 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
691 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */
692 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */
695 pinctrl_twi_gpio: twi_gpio-0 {
697 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
698 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */
703 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
704 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
707 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
708 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
711 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
712 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
715 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
716 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
719 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
720 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
723 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
724 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
727 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
728 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
731 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
732 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
735 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
736 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
741 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
742 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
745 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
746 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
749 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
750 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
753 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
754 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
757 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
758 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
761 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
762 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
765 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
766 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
769 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
770 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
773 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
774 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
779 pinctrl_spi0: spi0-0 {
781 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
782 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
783 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
787 pioA: gpio@fffff400 {
788 compatible = "atmel,at91rm9200-gpio";
789 reg = <0xfffff400 0x200>;
790 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
793 interrupt-controller;
794 #interrupt-cells = <2>;
795 clocks = <&pioA_clk>;
798 pioB: gpio@fffff600 {
799 compatible = "atmel,at91rm9200-gpio";
800 reg = <0xfffff600 0x200>;
801 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
804 interrupt-controller;
805 #interrupt-cells = <2>;
806 clocks = <&pioB_clk>;
809 pioC: gpio@fffff800 {
810 compatible = "atmel,at91rm9200-gpio";
811 reg = <0xfffff800 0x200>;
812 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
815 interrupt-controller;
816 #interrupt-cells = <2>;
817 clocks = <&pioC_clk>;
820 pioD: gpio@fffffa00 {
821 compatible = "atmel,at91rm9200-gpio";
822 reg = <0xfffffa00 0x200>;
823 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
826 interrupt-controller;
827 #interrupt-cells = <2>;
828 clocks = <&pioD_clk>;
832 dbgu: serial@fffff200 {
833 compatible = "atmel,at91rm9200-usart";
834 reg = <0xfffff200 0x200>;
835 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
836 pinctrl-names = "default";
837 pinctrl-0 = <&pinctrl_dbgu>;
839 clock-names = "usart";
843 usart0: serial@fffc0000 {
844 compatible = "atmel,at91rm9200-usart";
845 reg = <0xfffc0000 0x200>;
846 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
849 pinctrl-names = "default";
850 pinctrl-0 = <&pinctrl_uart0>;
851 clocks = <&usart0_clk>;
852 clock-names = "usart";
856 usart1: serial@fffc4000 {
857 compatible = "atmel,at91rm9200-usart";
858 reg = <0xfffc4000 0x200>;
859 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
862 pinctrl-names = "default";
863 pinctrl-0 = <&pinctrl_uart1>;
864 clocks = <&usart1_clk>;
865 clock-names = "usart";
869 usart2: serial@fffc8000 {
870 compatible = "atmel,at91rm9200-usart";
871 reg = <0xfffc8000 0x200>;
872 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
875 pinctrl-names = "default";
876 pinctrl-0 = <&pinctrl_uart2>;
877 clocks = <&usart2_clk>;
878 clock-names = "usart";
882 usart3: serial@fffcc000 {
883 compatible = "atmel,at91rm9200-usart";
884 reg = <0xfffcc000 0x200>;
885 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
888 pinctrl-names = "default";
889 pinctrl-0 = <&pinctrl_uart3>;
890 clocks = <&usart3_clk>;
891 clock-names = "usart";
895 usb1: gadget@fffb0000 {
896 compatible = "atmel,at91rm9200-udc";
897 reg = <0xfffb0000 0x4000>;
898 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
899 clocks = <&udc_clk>, <&udpck>;
900 clock-names = "pclk", "hclk";
905 #address-cells = <1>;
907 compatible = "atmel,at91rm9200-spi";
908 reg = <0xfffe0000 0x200>;
909 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
910 pinctrl-names = "default";
911 pinctrl-0 = <&pinctrl_spi0>;
912 clocks = <&spi0_clk>;
913 clock-names = "spi_clk";
918 nand0: nand@40000000 {
919 compatible = "atmel,at91rm9200-nand";
920 #address-cells = <1>;
922 reg = <0x40000000 0x10000000>;
923 atmel,nand-addr-offset = <21>;
924 atmel,nand-cmd-offset = <22>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&pinctrl_nand>;
927 nand-ecc-mode = "soft";
928 gpios = <&pioC 2 GPIO_ACTIVE_HIGH
930 &pioB 1 GPIO_ACTIVE_HIGH
935 usb0: ohci@00300000 {
936 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
937 reg = <0x00300000 0x100000>;
938 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
939 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
940 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
946 compatible = "i2c-gpio";
947 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
948 &pioA 26 GPIO_ACTIVE_HIGH /* scl */
950 i2c-gpio,sda-open-drain;
951 i2c-gpio,scl-open-drain;
952 i2c-gpio,delay-us = <2>; /* ~100 kHz */
953 pinctrl-names = "default";
954 pinctrl-0 = <&pinctrl_twi_gpio>;
955 #address-cells = <1>;