2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
48 #define CPU_ENABLE_SSE
51 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
52 void enable_K5_wt_alloc(void);
53 void enable_K6_wt_alloc(void);
54 void enable_K6_2_wt_alloc(void);
58 static void init_5x86(void);
59 static void init_bluelightning(void);
60 static void init_486dlc(void);
61 static void init_cy486dx(void);
62 #ifdef CPU_I486_ON_386
63 static void init_i486_on_386(void);
65 static void init_6x86(void);
69 static void init_6x86MX(void);
70 static void init_ppro(void);
71 static void init_mendocino(void);
74 static int hw_instruction_sse;
75 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
78 * -1: automatic (default)
79 * 0: keep enable CLFLUSH
80 * 1: force disable CLFLUSH
82 static int hw_clflush_disable = -1;
84 /* Must *NOT* be BSS or locore will bzero these after setting them */
85 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
86 u_int cpu_feature = 0; /* Feature flags */
87 u_int cpu_feature2 = 0; /* Feature flags */
88 u_int amd_feature = 0; /* AMD feature flags */
89 u_int amd_feature2 = 0; /* AMD feature flags */
90 u_int amd_pminfo = 0; /* AMD advanced power management info */
91 u_int via_feature_rng = 0; /* VIA RNG features */
92 u_int via_feature_xcrypt = 0; /* VIA ACE features */
93 u_int cpu_high = 0; /* Highest arg to CPUID */
94 u_int cpu_id = 0; /* Stepping ID */
95 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
96 u_int cpu_procinfo2 = 0; /* Multicore info */
97 char cpu_vendor[20] = ""; /* CPU Origin code */
98 u_int cpu_vendor_id = 0; /* CPU vendor ID */
99 u_int cpu_clflush_line_size = 32;
101 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
102 &via_feature_rng, 0, "VIA RNG feature available in CPU");
103 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
104 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
106 #ifdef CPU_ENABLE_SSE
107 u_int cpu_fxsr; /* SSE enabled */
108 u_int cpu_mxcsr_mask; /* valid bits in mxcsr */
116 init_bluelightning(void)
120 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
121 need_post_dma_flush = 1;
124 saveintr = intr_disable();
126 load_cr0(rcr0() | CR0_CD | CR0_NW);
129 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
130 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
132 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
134 /* Enables 13MB and 0-640KB cache. */
135 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
136 #ifdef CPU_BLUELIGHTNING_3X
137 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
139 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
142 /* Enable caching in CR0. */
143 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
145 intr_restore(saveintr);
149 * Cyrix 486SLC/DLC/SR/DR series
157 saveintr = intr_disable();
160 ccr0 = read_cyrix_reg(CCR0);
161 #ifndef CYRIX_CACHE_WORKS
162 ccr0 |= CCR0_NC1 | CCR0_BARB;
163 write_cyrix_reg(CCR0, ccr0);
167 #ifndef CYRIX_CACHE_REALLY_WORKS
168 ccr0 |= CCR0_NC1 | CCR0_BARB;
172 #ifdef CPU_DIRECT_MAPPED_CACHE
173 ccr0 |= CCR0_CO; /* Direct mapped mode. */
175 write_cyrix_reg(CCR0, ccr0);
177 /* Clear non-cacheable region. */
178 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
179 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
180 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
181 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
183 write_cyrix_reg(0, 0); /* dummy write */
185 /* Enable caching in CR0. */
186 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
188 #endif /* !CYRIX_CACHE_WORKS */
189 intr_restore(saveintr);
194 * Cyrix 486S/DX series
202 saveintr = intr_disable();
205 ccr2 = read_cyrix_reg(CCR2);
207 ccr2 |= CCR2_SUSP_HLT;
211 /* Enables WB cache interface pin and Lock NW bit in CR0. */
212 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
213 /* Unlock NW bit in CR0. */
214 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
215 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
218 write_cyrix_reg(CCR2, ccr2);
219 intr_restore(saveintr);
230 u_char ccr2, ccr3, ccr4, pcr0;
232 saveintr = intr_disable();
234 load_cr0(rcr0() | CR0_CD | CR0_NW);
237 (void)read_cyrix_reg(CCR3); /* dummy */
239 /* Initialize CCR2. */
240 ccr2 = read_cyrix_reg(CCR2);
243 ccr2 |= CCR2_SUSP_HLT;
245 ccr2 &= ~CCR2_SUSP_HLT;
248 write_cyrix_reg(CCR2, ccr2);
250 /* Initialize CCR4. */
251 ccr3 = read_cyrix_reg(CCR3);
252 write_cyrix_reg(CCR3, CCR3_MAPEN0);
254 ccr4 = read_cyrix_reg(CCR4);
257 #ifdef CPU_FASTER_5X86_FPU
258 ccr4 |= CCR4_FASTFPE;
260 ccr4 &= ~CCR4_FASTFPE;
262 ccr4 &= ~CCR4_IOMASK;
263 /********************************************************************
264 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
265 * should be 0 for errata fix.
266 ********************************************************************/
268 ccr4 |= CPU_IORT & CCR4_IOMASK;
270 write_cyrix_reg(CCR4, ccr4);
272 /* Initialize PCR0. */
273 /****************************************************************
274 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
275 * BTB_EN might make your system unstable.
276 ****************************************************************/
277 pcr0 = read_cyrix_reg(PCR0);
294 /****************************************************************
295 * WARNING: if you use a memory mapped I/O device, don't use
296 * DISABLE_5X86_LSSER option, which may reorder memory mapped
298 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
299 ****************************************************************/
300 #ifdef CPU_DISABLE_5X86_LSSER
305 write_cyrix_reg(PCR0, pcr0);
308 write_cyrix_reg(CCR3, ccr3);
310 (void)read_cyrix_reg(0x80); /* dummy */
312 /* Unlock NW bit in CR0. */
313 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
314 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
315 /* Lock NW bit in CR0. */
316 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
318 intr_restore(saveintr);
321 #ifdef CPU_I486_ON_386
323 * There are i486 based upgrade products for i386 machines.
324 * In this case, BIOS doesn't enable CPU cache.
327 init_i486_on_386(void)
331 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
332 need_post_dma_flush = 1;
335 saveintr = intr_disable();
337 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
339 intr_restore(saveintr);
346 * XXX - What should I do here? Please let me know.
354 saveintr = intr_disable();
356 load_cr0(rcr0() | CR0_CD | CR0_NW);
359 /* Initialize CCR0. */
360 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
362 /* Initialize CCR1. */
363 #ifdef CPU_CYRIX_NO_LOCK
364 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
366 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
369 /* Initialize CCR2. */
371 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
373 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
376 ccr3 = read_cyrix_reg(CCR3);
377 write_cyrix_reg(CCR3, CCR3_MAPEN0);
379 /* Initialize CCR4. */
380 ccr4 = read_cyrix_reg(CCR4);
382 ccr4 &= ~CCR4_IOMASK;
384 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
386 write_cyrix_reg(CCR4, ccr4 | 7);
389 /* Initialize CCR5. */
391 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
395 write_cyrix_reg(CCR3, ccr3);
397 /* Unlock NW bit in CR0. */
398 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
401 * Earlier revision of the 6x86 CPU could crash the system if
402 * L1 cache is in write-back mode.
404 if ((cyrix_did & 0xff00) > 0x1600)
405 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
407 /* Revision 2.6 and lower. */
408 #ifdef CYRIX_CACHE_REALLY_WORKS
409 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
411 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
415 /* Lock NW bit in CR0. */
416 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
418 intr_restore(saveintr);
420 #endif /* I486_CPU */
424 * IDT WinChip C6/2/2A/2B/3
426 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
437 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
439 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
440 fcr &= ~(1ULL << 11);
443 * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
445 if (CPUID_TO_MODEL(cpu_id) >= 8)
446 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
450 cpu_feature = regs[3];
456 * Cyrix 6x86MX (code-named M2)
458 * XXX - What should I do here? Please let me know.
466 saveintr = intr_disable();
468 load_cr0(rcr0() | CR0_CD | CR0_NW);
471 /* Initialize CCR0. */
472 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
474 /* Initialize CCR1. */
475 #ifdef CPU_CYRIX_NO_LOCK
476 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
478 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
481 /* Initialize CCR2. */
483 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
485 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
488 ccr3 = read_cyrix_reg(CCR3);
489 write_cyrix_reg(CCR3, CCR3_MAPEN0);
491 /* Initialize CCR4. */
492 ccr4 = read_cyrix_reg(CCR4);
493 ccr4 &= ~CCR4_IOMASK;
495 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
497 write_cyrix_reg(CCR4, ccr4 | 7);
500 /* Initialize CCR5. */
502 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
506 write_cyrix_reg(CCR3, ccr3);
508 /* Unlock NW bit in CR0. */
509 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
511 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
513 /* Lock NW bit in CR0. */
514 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
516 intr_restore(saveintr);
525 * Local APIC should be disabled if it is not going to be used.
527 apicbase = rdmsr(MSR_APICBASE);
528 apicbase &= ~APICBASE_ENABLED;
529 wrmsr(MSR_APICBASE, apicbase);
533 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
539 #ifdef CPU_PPRO2CELERON
541 u_int64_t bbl_cr_ctl3;
543 saveintr = intr_disable();
545 load_cr0(rcr0() | CR0_CD | CR0_NW);
548 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
550 /* If the L2 cache is configured, do nothing. */
551 if (!(bbl_cr_ctl3 & 1)) {
552 bbl_cr_ctl3 = 0x134052bLL;
554 /* Set L2 Cache Latency (Default: 5). */
555 #ifdef CPU_CELERON_L2_LATENCY
556 #if CPU_L2_LATENCY > 15
557 #error invalid CPU_L2_LATENCY.
559 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
561 bbl_cr_ctl3 |= 5 << 1;
563 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
566 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
567 intr_restore(saveintr);
568 #endif /* CPU_PPRO2CELERON */
572 * Initialize special VIA features
581 * Explicitly enable CX8 and PGE on C3.
583 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
585 if (CPUID_TO_MODEL(cpu_id) <= 9)
586 fcr = (1 << 1) | (1 << 7);
591 * Check extended CPUID for PadLock features.
593 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
595 do_cpuid(0xc0000000, regs);
596 if (regs[0] >= 0xc0000001) {
597 do_cpuid(0xc0000001, regs);
602 /* Enable RNG if present. */
603 if ((val & VIA_CPUID_HAS_RNG) != 0) {
604 via_feature_rng = VIA_HAS_RNG;
605 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
608 /* Enable PadLock if present. */
609 if ((val & VIA_CPUID_HAS_ACE) != 0)
610 via_feature_xcrypt |= VIA_HAS_AES;
611 if ((val & VIA_CPUID_HAS_ACE2) != 0)
612 via_feature_xcrypt |= VIA_HAS_AESCTR;
613 if ((val & VIA_CPUID_HAS_PHE) != 0)
614 via_feature_xcrypt |= VIA_HAS_SHA;
615 if ((val & VIA_CPUID_HAS_PMM) != 0)
616 via_feature_xcrypt |= VIA_HAS_MM;
617 if (via_feature_xcrypt != 0)
620 wrmsr(0x1107, rdmsr(0x1107) | fcr);
623 #endif /* I686_CPU */
625 #if defined(I586_CPU) || defined(I686_CPU)
631 /* Expose all hidden features. */
632 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
634 cpu_feature = regs[3];
639 * Initialize CR4 (Control register 4) to enable SSE instructions.
644 #if defined(CPU_ENABLE_SSE)
645 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
646 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
647 cpu_fxsr = hw_instruction_sse = 1;
652 extern int elf32_nxstack;
661 init_bluelightning();
672 #ifdef CPU_I486_ON_386
680 #endif /* I486_CPU */
683 switch (cpu_vendor_id) {
684 case CPU_VENDOR_CENTAUR:
687 case CPU_VENDOR_TRANSMETA:
698 switch (cpu_vendor_id) {
699 case CPU_VENDOR_INTEL:
700 switch (cpu_id & 0xff0) {
709 #ifdef CPU_ATHLON_SSE_HACK
712 * Sometimes the BIOS doesn't enable SSE instructions.
713 * According to AMD document 20734, the mobile
714 * Duron, the (mobile) Athlon 4 and the Athlon MP
715 * support SSE. These correspond to cpu_id 0x66X
718 if ((cpu_feature & CPUID_XMM) == 0 &&
719 ((cpu_id & ~0xf) == 0x660 ||
720 (cpu_id & ~0xf) == 0x670 ||
721 (cpu_id & ~0xf) == 0x680)) {
723 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
725 cpu_feature = regs[3];
729 case CPU_VENDOR_CENTAUR:
732 case CPU_VENDOR_TRANSMETA:
737 if ((amd_feature & AMDID_NX) != 0) {
740 msr = rdmsr(MSR_EFER) | EFER_NXE;
741 wrmsr(MSR_EFER, msr);
754 * CPUID with %eax = 1, %ebx returns
755 * Bits 15-8: CLFLUSH line size
756 * (Value * 8 = cache line size in bytes)
758 if ((cpu_feature & CPUID_CLFSH) != 0)
759 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
761 * XXXKIB: (temporary) hack to work around traps generated
762 * when CLFLUSHing APIC register window under virtualization
763 * environments. These environments tend to disable the
764 * CPUID_SS feature even though the native CPU supports it.
766 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
767 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
768 cpu_feature &= ~CPUID_CLFSH;
770 * Allow to disable CLFLUSH feature manually by
771 * hw.clflush_disable tunable.
773 if (hw_clflush_disable == 1)
774 cpu_feature &= ~CPUID_CLFSH;
776 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
778 * OS should flush L1 cache by itself because no PC-98 supports
779 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
780 * when need_pre_dma_flush = 1, use invd instruction after DMA
781 * transfer when need_post_dma_flush = 1. If your CPU upgrade
782 * product supports hardware cache control, you can add the
783 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
784 * This option eliminates unneeded cache flush instruction(s).
786 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
790 need_post_dma_flush = 1;
793 need_pre_dma_flush = 1;
796 need_pre_dma_flush = 1;
797 #ifdef CPU_I486_ON_386
798 need_post_dma_flush = 1;
805 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
806 switch (cpu_id & 0xFF0) {
807 case 0x470: /* Enhanced Am486DX2 WB */
808 case 0x490: /* Enhanced Am486DX4 WB */
809 case 0x4F0: /* Am5x86 WB */
810 need_pre_dma_flush = 1;
813 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
814 need_post_dma_flush = 1;
816 #ifdef CPU_I486_ON_386
817 need_pre_dma_flush = 1;
820 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
823 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
825 * Enable write allocate feature of AMD processors.
826 * Following two functions require the Maxmem variable being set.
829 enable_K5_wt_alloc(void)
835 * Write allocate is supported only on models 1, 2, and 3, with
836 * a stepping of 4 or greater.
838 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
839 saveintr = intr_disable();
840 msr = rdmsr(0x83); /* HWCR */
841 wrmsr(0x83, msr & !(0x10));
844 * We have to tell the chip where the top of memory is,
845 * since video cards could have frame bufferes there,
846 * memory-mapped I/O could be there, etc.
852 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
854 if (!(inb(0x43b) & 4)) {
855 wrmsr(0x86, 0x0ff00f0);
856 msr |= AMD_WT_ALLOC_PRE;
860 * There is no way to know wheter 15-16M hole exists or not.
861 * Therefore, we disable write allocate for this range.
863 wrmsr(0x86, 0x0ff00f0);
864 msr |= AMD_WT_ALLOC_PRE;
869 wrmsr(0x83, msr|0x10); /* enable write allocate */
870 intr_restore(saveintr);
875 enable_K6_wt_alloc(void)
881 saveintr = intr_disable();
884 #ifdef CPU_DISABLE_CACHE
886 * Certain K6-2 box becomes unstable when write allocation is
890 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
891 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
892 * All other bits in TR12 have no effect on the processer's operation.
893 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
896 wrmsr(0x0000000e, (u_int64_t)0x0008);
898 /* Don't assume that memory size is aligned with 4M. */
900 size = ((Maxmem >> 8) + 3) >> 2;
904 /* Limit is 508M bytes. */
907 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
909 #if defined(PC98) || defined(NO_MEMORY_HOLE)
910 if (whcr & (0x7fLL << 1)) {
913 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
916 if (!(inb(0x43b) & 4))
924 * There is no way to know wheter 15-16M hole exists or not.
925 * Therefore, we disable write allocate for this range.
929 wrmsr(0x0c0000082, whcr);
931 intr_restore(saveintr);
935 enable_K6_2_wt_alloc(void)
941 saveintr = intr_disable();
944 #ifdef CPU_DISABLE_CACHE
946 * Certain K6-2 box becomes unstable when write allocation is
950 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
951 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
952 * All other bits in TR12 have no effect on the processer's operation.
953 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
956 wrmsr(0x0000000e, (u_int64_t)0x0008);
958 /* Don't assume that memory size is aligned with 4M. */
960 size = ((Maxmem >> 8) + 3) >> 2;
964 /* Limit is 4092M bytes. */
967 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
969 #if defined(PC98) || defined(NO_MEMORY_HOLE)
970 if (whcr & (0x3ffLL << 22)) {
973 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
976 if (!(inb(0x43b) & 4))
977 whcr &= ~(1LL << 16);
984 * There is no way to know wheter 15-16M hole exists or not.
985 * Therefore, we disable write allocate for this range.
987 whcr &= ~(1LL << 16);
989 wrmsr(0x0c0000082, whcr);
991 intr_restore(saveintr);
993 #endif /* I585_CPU && CPU_WT_ALLOC */
999 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1001 register_t saveintr;
1003 u_char ccr1, ccr2, ccr3;
1004 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1007 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1008 saveintr = intr_disable();
1011 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1012 ccr0 = read_cyrix_reg(CCR0);
1014 ccr1 = read_cyrix_reg(CCR1);
1015 ccr2 = read_cyrix_reg(CCR2);
1016 ccr3 = read_cyrix_reg(CCR3);
1017 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1018 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1019 ccr4 = read_cyrix_reg(CCR4);
1020 if ((cpu == CPU_M1) || (cpu == CPU_M2))
1021 ccr5 = read_cyrix_reg(CCR5);
1023 pcr0 = read_cyrix_reg(PCR0);
1024 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
1026 intr_restore(saveintr);
1028 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1029 printf("CCR0=%x, ", (u_int)ccr0);
1031 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1032 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1033 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1034 printf(", CCR4=%x, ", (u_int)ccr4);
1035 if (cpu == CPU_M1SC)
1036 printf("PCR0=%x\n", pcr0);
1038 printf("CCR5=%x\n", ccr5);
1041 printf("CR0=%x\n", cr0);