2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
6 * This code is derived from software contributed to Berkeley by
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
44 #include "opt_atalk.h"
45 #include "opt_atpic.h"
46 #include "opt_compat.h"
52 #include "opt_kstack_pages.h"
53 #include "opt_maxmem.h"
54 #include "opt_mp_watchdog.h"
56 #include "opt_perfmon.h"
57 #include "opt_platform.h"
59 #include "opt_kdtrace.h"
61 #include <sys/param.h>
63 #include <sys/systm.h>
67 #include <sys/callout.h>
70 #include <sys/eventhandler.h>
72 #include <sys/imgact.h>
74 #include <sys/kernel.h>
76 #include <sys/linker.h>
78 #include <sys/malloc.h>
79 #include <sys/memrange.h>
80 #include <sys/msgbuf.h>
81 #include <sys/mutex.h>
83 #include <sys/ptrace.h>
84 #include <sys/reboot.h>
85 #include <sys/rwlock.h>
86 #include <sys/sched.h>
87 #include <sys/signalvar.h>
91 #include <sys/syscallsubr.h>
92 #include <sys/sysctl.h>
93 #include <sys/sysent.h>
94 #include <sys/sysproto.h>
95 #include <sys/ucontext.h>
96 #include <sys/vmmeter.h>
99 #include <vm/vm_extern.h>
100 #include <vm/vm_kern.h>
101 #include <vm/vm_page.h>
102 #include <vm/vm_map.h>
103 #include <vm/vm_object.h>
104 #include <vm/vm_pager.h>
105 #include <vm/vm_param.h>
109 #error KDB must be enabled in order for DDB to work!
112 #include <ddb/db_sym.h>
116 #include <pc98/pc98/pc98_machdep.h>
121 #include <net/netisr.h>
123 #include <machine/bootinfo.h>
124 #include <machine/clock.h>
125 #include <machine/cpu.h>
126 #include <machine/cputypes.h>
127 #include <machine/intr_machdep.h>
129 #include <machine/md_var.h>
130 #include <machine/metadata.h>
131 #include <machine/mp_watchdog.h>
132 #include <machine/pc/bios.h>
133 #include <machine/pcb.h>
134 #include <machine/pcb_ext.h>
135 #include <machine/proc.h>
136 #include <machine/reg.h>
137 #include <machine/sigframe.h>
138 #include <machine/specialreg.h>
139 #include <machine/vm86.h>
141 #include <machine/perfmon.h>
144 #include <machine/smp.h>
151 #include <machine/apicvar.h>
155 #include <x86/isa/icu.h>
159 #include <machine/xbox.h>
161 int arch_i386_is_xbox = 0;
162 uint32_t arch_i386_xbox_memsize = 0;
167 #include <xen/xen-os.h>
168 #include <xen/hypervisor.h>
169 #include <machine/xen/xenvar.h>
170 #include <machine/xen/xenfunc.h>
171 #include <xen/xen_intr.h>
173 void Xhypervisor_callback(void);
174 void failsafe_callback(void);
176 extern trap_info_t trap_table[];
177 struct proc_ldt default_proc_ldt;
178 extern int init_first;
180 extern unsigned long physfree;
183 /* Sanity check for __curthread() */
184 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
186 extern register_t init386(int first);
187 extern void dblfault_handler(void);
189 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
190 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
192 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
193 #define CPU_ENABLE_SSE
196 static void cpu_startup(void *);
197 static void fpstate_drop(struct thread *td);
198 static void get_fpcontext(struct thread *td, mcontext_t *mcp,
199 char *xfpusave, size_t xfpusave_len);
200 static int set_fpcontext(struct thread *td, mcontext_t *mcp,
201 char *xfpustate, size_t xfpustate_len);
202 #ifdef CPU_ENABLE_SSE
203 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
204 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
205 #endif /* CPU_ENABLE_SSE */
206 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
209 extern vm_offset_t ksym_start, ksym_end;
212 /* Intel ICH registers */
213 #define ICH_PMBASE 0x400
214 #define ICH_SMI_EN ICH_PMBASE + 0x30
216 int _udatasel, _ucodesel;
220 int need_pre_dma_flush; /* If 1, use wbinvd befor DMA transfer. */
221 int need_post_dma_flush; /* If 1, use invd after DMA transfer. */
223 static int ispc98 = 1;
224 SYSCTL_INT(_machdep, OID_AUTO, ispc98, CTLFLAG_RD, &ispc98, 0, "");
230 static void osendsig(sig_t catcher, ksiginfo_t *, sigset_t *mask);
232 #ifdef COMPAT_FREEBSD4
233 static void freebsd4_sendsig(sig_t catcher, ksiginfo_t *, sigset_t *mask);
240 FEATURE(pae, "Physical Address Extensions");
244 * The number of PHYSMAP entries must be one less than the number of
245 * PHYSSEG entries because the PHYSMAP entry that spans the largest
246 * physical address that is accessible by ISA DMA is split into two
249 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
251 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
252 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
254 /* must be 2 less so 0 0 can signal end of chunks */
255 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2)
256 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2)
258 struct kva_md_info kmi;
260 static struct trapframe proc0_tf;
261 struct pcpu __pcpu[MAXCPU];
265 struct mem_range_softc mem_range_softc;
276 * On MacBooks, we need to disallow the legacy USB circuit to
277 * generate an SMI# because this can cause several problems,
278 * namely: incorrect CPU frequency detection and failure to
280 * We do this by disabling a bit in the SMI_EN (SMI Control and
281 * Enable register) of the Intel ICH LPC Interface Bridge.
283 sysenv = getenv("smbios.system.product");
284 if (sysenv != NULL) {
285 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
286 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
287 strncmp(sysenv, "MacBook4,1", 10) == 0 ||
288 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
289 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
290 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
291 strncmp(sysenv, "MacBookPro4,1", 13) == 0 ||
292 strncmp(sysenv, "Macmini1,1", 10) == 0) {
294 printf("Disabling LEGACY_USB_EN bit on "
296 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
303 * Good {morning,afternoon,evening,night}.
307 panicifcpuunsupported();
313 * Display physical memory if SMBIOS reports reasonable amount.
316 sysenv = getenv("smbios.memory.enabled");
317 if (sysenv != NULL) {
318 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
321 if (memsize < ptoa((uintmax_t)cnt.v_free_count))
322 memsize = ptoa((uintmax_t)Maxmem);
323 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
324 realmem = atop(memsize);
327 * Display any holes after the first chunk of extended memory.
332 printf("Physical memory chunk(s):\n");
333 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
336 size = phys_avail[indx + 1] - phys_avail[indx];
338 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
339 (uintmax_t)phys_avail[indx],
340 (uintmax_t)phys_avail[indx + 1] - 1,
341 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
345 vm_ksubmap_init(&kmi);
347 printf("avail memory = %ju (%ju MB)\n",
348 ptoa((uintmax_t)cnt.v_free_count),
349 ptoa((uintmax_t)cnt.v_free_count) / 1048576);
352 * Set up buffers, so they can be used to read disk labels.
355 vm_pager_bufferinit();
362 * Send an interrupt to process.
364 * Stack is set up to allow sigcode stored
365 * at top to call routine, followed by call
366 * to sigreturn routine below. After sigreturn
367 * resets the signal mask, the stack, and the
368 * frame pointer, it returns to the user
373 osendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
375 struct osigframe sf, *fp;
379 struct trapframe *regs;
385 PROC_LOCK_ASSERT(p, MA_OWNED);
386 sig = ksi->ksi_signo;
388 mtx_assert(&psp->ps_mtx, MA_OWNED);
390 oonstack = sigonstack(regs->tf_esp);
392 /* Allocate space for the signal handler context. */
393 if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
394 SIGISMEMBER(psp->ps_sigonstack, sig)) {
395 fp = (struct osigframe *)(td->td_sigstk.ss_sp +
396 td->td_sigstk.ss_size - sizeof(struct osigframe));
397 #if defined(COMPAT_43)
398 td->td_sigstk.ss_flags |= SS_ONSTACK;
401 fp = (struct osigframe *)regs->tf_esp - 1;
403 /* Translate the signal if appropriate. */
404 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
405 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
407 /* Build the argument list for the signal handler. */
409 sf.sf_scp = (register_t)&fp->sf_siginfo.si_sc;
410 bzero(&sf.sf_siginfo, sizeof(sf.sf_siginfo));
411 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
412 /* Signal handler installed with SA_SIGINFO. */
413 sf.sf_arg2 = (register_t)&fp->sf_siginfo;
414 sf.sf_siginfo.si_signo = sig;
415 sf.sf_siginfo.si_code = ksi->ksi_code;
416 sf.sf_ahu.sf_action = (__osiginfohandler_t *)catcher;
419 /* Old FreeBSD-style arguments. */
420 sf.sf_arg2 = ksi->ksi_code;
421 sf.sf_addr = (register_t)ksi->ksi_addr;
422 sf.sf_ahu.sf_handler = catcher;
424 mtx_unlock(&psp->ps_mtx);
427 /* Save most if not all of trap frame. */
428 sf.sf_siginfo.si_sc.sc_eax = regs->tf_eax;
429 sf.sf_siginfo.si_sc.sc_ebx = regs->tf_ebx;
430 sf.sf_siginfo.si_sc.sc_ecx = regs->tf_ecx;
431 sf.sf_siginfo.si_sc.sc_edx = regs->tf_edx;
432 sf.sf_siginfo.si_sc.sc_esi = regs->tf_esi;
433 sf.sf_siginfo.si_sc.sc_edi = regs->tf_edi;
434 sf.sf_siginfo.si_sc.sc_cs = regs->tf_cs;
435 sf.sf_siginfo.si_sc.sc_ds = regs->tf_ds;
436 sf.sf_siginfo.si_sc.sc_ss = regs->tf_ss;
437 sf.sf_siginfo.si_sc.sc_es = regs->tf_es;
438 sf.sf_siginfo.si_sc.sc_fs = regs->tf_fs;
439 sf.sf_siginfo.si_sc.sc_gs = rgs();
440 sf.sf_siginfo.si_sc.sc_isp = regs->tf_isp;
442 /* Build the signal context to be used by osigreturn(). */
443 sf.sf_siginfo.si_sc.sc_onstack = (oonstack) ? 1 : 0;
444 SIG2OSIG(*mask, sf.sf_siginfo.si_sc.sc_mask);
445 sf.sf_siginfo.si_sc.sc_sp = regs->tf_esp;
446 sf.sf_siginfo.si_sc.sc_fp = regs->tf_ebp;
447 sf.sf_siginfo.si_sc.sc_pc = regs->tf_eip;
448 sf.sf_siginfo.si_sc.sc_ps = regs->tf_eflags;
449 sf.sf_siginfo.si_sc.sc_trapno = regs->tf_trapno;
450 sf.sf_siginfo.si_sc.sc_err = regs->tf_err;
453 * If we're a vm86 process, we want to save the segment registers.
454 * We also change eflags to be our emulated eflags, not the actual
457 if (regs->tf_eflags & PSL_VM) {
458 /* XXX confusing names: `tf' isn't a trapframe; `regs' is. */
459 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
460 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
462 sf.sf_siginfo.si_sc.sc_gs = tf->tf_vm86_gs;
463 sf.sf_siginfo.si_sc.sc_fs = tf->tf_vm86_fs;
464 sf.sf_siginfo.si_sc.sc_es = tf->tf_vm86_es;
465 sf.sf_siginfo.si_sc.sc_ds = tf->tf_vm86_ds;
467 if (vm86->vm86_has_vme == 0)
468 sf.sf_siginfo.si_sc.sc_ps =
469 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
470 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
472 /* See sendsig() for comments. */
473 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
477 * Copy the sigframe out to the user's stack.
479 if (copyout(&sf, fp, sizeof(*fp)) != 0) {
481 printf("process %ld has trashed its stack\n", (long)p->p_pid);
487 regs->tf_esp = (int)fp;
488 if (p->p_sysent->sv_sigcode_base != 0) {
489 regs->tf_eip = p->p_sysent->sv_sigcode_base + szsigcode -
492 /* a.out sysentvec does not use shared page */
493 regs->tf_eip = p->p_sysent->sv_psstrings - szosigcode;
495 regs->tf_eflags &= ~(PSL_T | PSL_D);
496 regs->tf_cs = _ucodesel;
497 regs->tf_ds = _udatasel;
498 regs->tf_es = _udatasel;
499 regs->tf_fs = _udatasel;
501 regs->tf_ss = _udatasel;
503 mtx_lock(&psp->ps_mtx);
505 #endif /* COMPAT_43 */
507 #ifdef COMPAT_FREEBSD4
509 freebsd4_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
511 struct sigframe4 sf, *sfp;
515 struct trapframe *regs;
521 PROC_LOCK_ASSERT(p, MA_OWNED);
522 sig = ksi->ksi_signo;
524 mtx_assert(&psp->ps_mtx, MA_OWNED);
526 oonstack = sigonstack(regs->tf_esp);
528 /* Save user context. */
529 bzero(&sf, sizeof(sf));
530 sf.sf_uc.uc_sigmask = *mask;
531 sf.sf_uc.uc_stack = td->td_sigstk;
532 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
533 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
534 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
535 sf.sf_uc.uc_mcontext.mc_gs = rgs();
536 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(*regs));
537 bzero(sf.sf_uc.uc_mcontext.mc_fpregs,
538 sizeof(sf.sf_uc.uc_mcontext.mc_fpregs));
539 bzero(sf.sf_uc.uc_mcontext.__spare__,
540 sizeof(sf.sf_uc.uc_mcontext.__spare__));
541 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__));
543 /* Allocate space for the signal handler context. */
544 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
545 SIGISMEMBER(psp->ps_sigonstack, sig)) {
546 sfp = (struct sigframe4 *)(td->td_sigstk.ss_sp +
547 td->td_sigstk.ss_size - sizeof(struct sigframe4));
548 #if defined(COMPAT_43)
549 td->td_sigstk.ss_flags |= SS_ONSTACK;
552 sfp = (struct sigframe4 *)regs->tf_esp - 1;
554 /* Translate the signal if appropriate. */
555 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
556 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
558 /* Build the argument list for the signal handler. */
560 sf.sf_ucontext = (register_t)&sfp->sf_uc;
561 bzero(&sf.sf_si, sizeof(sf.sf_si));
562 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
563 /* Signal handler installed with SA_SIGINFO. */
564 sf.sf_siginfo = (register_t)&sfp->sf_si;
565 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
567 /* Fill in POSIX parts */
568 sf.sf_si.si_signo = sig;
569 sf.sf_si.si_code = ksi->ksi_code;
570 sf.sf_si.si_addr = ksi->ksi_addr;
572 /* Old FreeBSD-style arguments. */
573 sf.sf_siginfo = ksi->ksi_code;
574 sf.sf_addr = (register_t)ksi->ksi_addr;
575 sf.sf_ahu.sf_handler = catcher;
577 mtx_unlock(&psp->ps_mtx);
581 * If we're a vm86 process, we want to save the segment registers.
582 * We also change eflags to be our emulated eflags, not the actual
585 if (regs->tf_eflags & PSL_VM) {
586 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
587 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
589 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
590 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
591 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
592 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
594 if (vm86->vm86_has_vme == 0)
595 sf.sf_uc.uc_mcontext.mc_eflags =
596 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
597 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
600 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
601 * syscalls made by the signal handler. This just avoids
602 * wasting time for our lazy fixup of such faults. PSL_NT
603 * does nothing in vm86 mode, but vm86 programs can set it
604 * almost legitimately in probes for old cpu types.
606 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
610 * Copy the sigframe out to the user's stack.
612 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) {
614 printf("process %ld has trashed its stack\n", (long)p->p_pid);
620 regs->tf_esp = (int)sfp;
621 regs->tf_eip = p->p_sysent->sv_sigcode_base + szsigcode -
623 regs->tf_eflags &= ~(PSL_T | PSL_D);
624 regs->tf_cs = _ucodesel;
625 regs->tf_ds = _udatasel;
626 regs->tf_es = _udatasel;
627 regs->tf_fs = _udatasel;
628 regs->tf_ss = _udatasel;
630 mtx_lock(&psp->ps_mtx);
632 #endif /* COMPAT_FREEBSD4 */
635 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
637 struct sigframe sf, *sfp;
642 struct trapframe *regs;
643 struct segment_descriptor *sdp;
651 PROC_LOCK_ASSERT(p, MA_OWNED);
652 sig = ksi->ksi_signo;
654 mtx_assert(&psp->ps_mtx, MA_OWNED);
655 #ifdef COMPAT_FREEBSD4
656 if (SIGISMEMBER(psp->ps_freebsd4, sig)) {
657 freebsd4_sendsig(catcher, ksi, mask);
662 if (SIGISMEMBER(psp->ps_osigset, sig)) {
663 osendsig(catcher, ksi, mask);
668 oonstack = sigonstack(regs->tf_esp);
670 #ifdef CPU_ENABLE_SSE
671 if (cpu_max_ext_state_size > sizeof(union savefpu) && use_xsave) {
672 xfpusave_len = cpu_max_ext_state_size - sizeof(union savefpu);
673 xfpusave = __builtin_alloca(xfpusave_len);
682 /* Save user context. */
683 bzero(&sf, sizeof(sf));
684 sf.sf_uc.uc_sigmask = *mask;
685 sf.sf_uc.uc_stack = td->td_sigstk;
686 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
687 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
688 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
689 sf.sf_uc.uc_mcontext.mc_gs = rgs();
690 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(*regs));
691 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */
692 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len);
695 * Unconditionally fill the fsbase and gsbase into the mcontext.
697 sdp = &td->td_pcb->pcb_fsd;
698 sf.sf_uc.uc_mcontext.mc_fsbase = sdp->sd_hibase << 24 |
700 sdp = &td->td_pcb->pcb_gsd;
701 sf.sf_uc.uc_mcontext.mc_gsbase = sdp->sd_hibase << 24 |
703 bzero(sf.sf_uc.uc_mcontext.mc_spare2,
704 sizeof(sf.sf_uc.uc_mcontext.mc_spare2));
705 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__));
707 /* Allocate space for the signal handler context. */
708 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
709 SIGISMEMBER(psp->ps_sigonstack, sig)) {
710 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
711 #if defined(COMPAT_43)
712 td->td_sigstk.ss_flags |= SS_ONSTACK;
715 sp = (char *)regs->tf_esp - 128;
716 if (xfpusave != NULL) {
718 sp = (char *)((unsigned int)sp & ~0x3F);
719 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp;
721 sp -= sizeof(struct sigframe);
723 /* Align to 16 bytes. */
724 sfp = (struct sigframe *)((unsigned int)sp & ~0xF);
726 /* Translate the signal if appropriate. */
727 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
728 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
730 /* Build the argument list for the signal handler. */
732 sf.sf_ucontext = (register_t)&sfp->sf_uc;
733 bzero(&sf.sf_si, sizeof(sf.sf_si));
734 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
735 /* Signal handler installed with SA_SIGINFO. */
736 sf.sf_siginfo = (register_t)&sfp->sf_si;
737 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
739 /* Fill in POSIX parts */
740 sf.sf_si = ksi->ksi_info;
741 sf.sf_si.si_signo = sig; /* maybe a translated signal */
743 /* Old FreeBSD-style arguments. */
744 sf.sf_siginfo = ksi->ksi_code;
745 sf.sf_addr = (register_t)ksi->ksi_addr;
746 sf.sf_ahu.sf_handler = catcher;
748 mtx_unlock(&psp->ps_mtx);
752 * If we're a vm86 process, we want to save the segment registers.
753 * We also change eflags to be our emulated eflags, not the actual
756 if (regs->tf_eflags & PSL_VM) {
757 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
758 struct vm86_kernel *vm86 = &td->td_pcb->pcb_ext->ext_vm86;
760 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
761 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
762 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
763 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
765 if (vm86->vm86_has_vme == 0)
766 sf.sf_uc.uc_mcontext.mc_eflags =
767 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
768 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
771 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
772 * syscalls made by the signal handler. This just avoids
773 * wasting time for our lazy fixup of such faults. PSL_NT
774 * does nothing in vm86 mode, but vm86 programs can set it
775 * almost legitimately in probes for old cpu types.
777 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
781 * Copy the sigframe out to the user's stack.
783 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 ||
784 (xfpusave != NULL && copyout(xfpusave,
785 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len)
788 printf("process %ld has trashed its stack\n", (long)p->p_pid);
794 regs->tf_esp = (int)sfp;
795 regs->tf_eip = p->p_sysent->sv_sigcode_base;
796 if (regs->tf_eip == 0)
797 regs->tf_eip = p->p_sysent->sv_psstrings - szsigcode;
798 regs->tf_eflags &= ~(PSL_T | PSL_D);
799 regs->tf_cs = _ucodesel;
800 regs->tf_ds = _udatasel;
801 regs->tf_es = _udatasel;
802 regs->tf_fs = _udatasel;
803 regs->tf_ss = _udatasel;
805 mtx_lock(&psp->ps_mtx);
809 * System call to cleanup state after a signal
810 * has been taken. Reset signal mask and
811 * stack state from context left by sendsig (above).
812 * Return to previous pc and psl as specified by
813 * context left by sendsig. Check carefully to
814 * make sure that the user has not modified the
815 * state to gain improper privileges.
823 struct osigreturn_args /* {
824 struct osigcontext *sigcntxp;
827 struct osigcontext sc;
828 struct trapframe *regs;
829 struct osigcontext *scp;
834 error = copyin(uap->sigcntxp, &sc, sizeof(sc));
839 if (eflags & PSL_VM) {
840 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
841 struct vm86_kernel *vm86;
844 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
845 * set up the vm86 area, and we can't enter vm86 mode.
847 if (td->td_pcb->pcb_ext == 0)
849 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
850 if (vm86->vm86_inited == 0)
853 /* Go back to user mode if both flags are set. */
854 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
855 ksiginfo_init_trap(&ksi);
856 ksi.ksi_signo = SIGBUS;
857 ksi.ksi_code = BUS_OBJERR;
858 ksi.ksi_addr = (void *)regs->tf_eip;
859 trapsignal(td, &ksi);
862 if (vm86->vm86_has_vme) {
863 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
864 (eflags & VME_USERCHANGE) | PSL_VM;
866 vm86->vm86_eflags = eflags; /* save VIF, VIP */
867 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
868 (eflags & VM_USERCHANGE) | PSL_VM;
870 tf->tf_vm86_ds = scp->sc_ds;
871 tf->tf_vm86_es = scp->sc_es;
872 tf->tf_vm86_fs = scp->sc_fs;
873 tf->tf_vm86_gs = scp->sc_gs;
874 tf->tf_ds = _udatasel;
875 tf->tf_es = _udatasel;
876 tf->tf_fs = _udatasel;
879 * Don't allow users to change privileged or reserved flags.
881 if (!EFL_SECURE(eflags, regs->tf_eflags)) {
886 * Don't allow users to load a valid privileged %cs. Let the
887 * hardware check for invalid selectors, excess privilege in
888 * other selectors, invalid %eip's and invalid %esp's.
890 if (!CS_SECURE(scp->sc_cs)) {
891 ksiginfo_init_trap(&ksi);
892 ksi.ksi_signo = SIGBUS;
893 ksi.ksi_code = BUS_OBJERR;
894 ksi.ksi_trapno = T_PROTFLT;
895 ksi.ksi_addr = (void *)regs->tf_eip;
896 trapsignal(td, &ksi);
899 regs->tf_ds = scp->sc_ds;
900 regs->tf_es = scp->sc_es;
901 regs->tf_fs = scp->sc_fs;
904 /* Restore remaining registers. */
905 regs->tf_eax = scp->sc_eax;
906 regs->tf_ebx = scp->sc_ebx;
907 regs->tf_ecx = scp->sc_ecx;
908 regs->tf_edx = scp->sc_edx;
909 regs->tf_esi = scp->sc_esi;
910 regs->tf_edi = scp->sc_edi;
911 regs->tf_cs = scp->sc_cs;
912 regs->tf_ss = scp->sc_ss;
913 regs->tf_isp = scp->sc_isp;
914 regs->tf_ebp = scp->sc_fp;
915 regs->tf_esp = scp->sc_sp;
916 regs->tf_eip = scp->sc_pc;
917 regs->tf_eflags = eflags;
919 #if defined(COMPAT_43)
920 if (scp->sc_onstack & 1)
921 td->td_sigstk.ss_flags |= SS_ONSTACK;
923 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
925 kern_sigprocmask(td, SIG_SETMASK, (sigset_t *)&scp->sc_mask, NULL,
927 return (EJUSTRETURN);
929 #endif /* COMPAT_43 */
931 #ifdef COMPAT_FREEBSD4
936 freebsd4_sigreturn(td, uap)
938 struct freebsd4_sigreturn_args /* {
939 const ucontext4 *sigcntxp;
943 struct trapframe *regs;
944 struct ucontext4 *ucp;
945 int cs, eflags, error;
948 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
953 eflags = ucp->uc_mcontext.mc_eflags;
954 if (eflags & PSL_VM) {
955 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
956 struct vm86_kernel *vm86;
959 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
960 * set up the vm86 area, and we can't enter vm86 mode.
962 if (td->td_pcb->pcb_ext == 0)
964 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
965 if (vm86->vm86_inited == 0)
968 /* Go back to user mode if both flags are set. */
969 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
970 ksiginfo_init_trap(&ksi);
971 ksi.ksi_signo = SIGBUS;
972 ksi.ksi_code = BUS_OBJERR;
973 ksi.ksi_addr = (void *)regs->tf_eip;
974 trapsignal(td, &ksi);
976 if (vm86->vm86_has_vme) {
977 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
978 (eflags & VME_USERCHANGE) | PSL_VM;
980 vm86->vm86_eflags = eflags; /* save VIF, VIP */
981 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
982 (eflags & VM_USERCHANGE) | PSL_VM;
984 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
985 tf->tf_eflags = eflags;
986 tf->tf_vm86_ds = tf->tf_ds;
987 tf->tf_vm86_es = tf->tf_es;
988 tf->tf_vm86_fs = tf->tf_fs;
989 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
990 tf->tf_ds = _udatasel;
991 tf->tf_es = _udatasel;
992 tf->tf_fs = _udatasel;
995 * Don't allow users to change privileged or reserved flags.
997 if (!EFL_SECURE(eflags, regs->tf_eflags)) {
998 uprintf("pid %d (%s): freebsd4_sigreturn eflags = 0x%x\n",
999 td->td_proc->p_pid, td->td_name, eflags);
1004 * Don't allow users to load a valid privileged %cs. Let the
1005 * hardware check for invalid selectors, excess privilege in
1006 * other selectors, invalid %eip's and invalid %esp's.
1008 cs = ucp->uc_mcontext.mc_cs;
1009 if (!CS_SECURE(cs)) {
1010 uprintf("pid %d (%s): freebsd4_sigreturn cs = 0x%x\n",
1011 td->td_proc->p_pid, td->td_name, cs);
1012 ksiginfo_init_trap(&ksi);
1013 ksi.ksi_signo = SIGBUS;
1014 ksi.ksi_code = BUS_OBJERR;
1015 ksi.ksi_trapno = T_PROTFLT;
1016 ksi.ksi_addr = (void *)regs->tf_eip;
1017 trapsignal(td, &ksi);
1021 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(*regs));
1024 #if defined(COMPAT_43)
1025 if (ucp->uc_mcontext.mc_onstack & 1)
1026 td->td_sigstk.ss_flags |= SS_ONSTACK;
1028 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
1030 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
1031 return (EJUSTRETURN);
1033 #endif /* COMPAT_FREEBSD4 */
1039 sys_sigreturn(td, uap)
1041 struct sigreturn_args /* {
1042 const struct __ucontext *sigcntxp;
1047 struct trapframe *regs;
1050 size_t xfpustate_len;
1051 int cs, eflags, error, ret;
1056 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
1060 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) {
1061 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid,
1062 td->td_name, ucp->uc_mcontext.mc_flags);
1065 regs = td->td_frame;
1066 eflags = ucp->uc_mcontext.mc_eflags;
1067 if (eflags & PSL_VM) {
1068 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
1069 struct vm86_kernel *vm86;
1072 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
1073 * set up the vm86 area, and we can't enter vm86 mode.
1075 if (td->td_pcb->pcb_ext == 0)
1077 vm86 = &td->td_pcb->pcb_ext->ext_vm86;
1078 if (vm86->vm86_inited == 0)
1081 /* Go back to user mode if both flags are set. */
1082 if ((eflags & PSL_VIP) && (eflags & PSL_VIF)) {
1083 ksiginfo_init_trap(&ksi);
1084 ksi.ksi_signo = SIGBUS;
1085 ksi.ksi_code = BUS_OBJERR;
1086 ksi.ksi_addr = (void *)regs->tf_eip;
1087 trapsignal(td, &ksi);
1090 if (vm86->vm86_has_vme) {
1091 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
1092 (eflags & VME_USERCHANGE) | PSL_VM;
1094 vm86->vm86_eflags = eflags; /* save VIF, VIP */
1095 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
1096 (eflags & VM_USERCHANGE) | PSL_VM;
1098 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
1099 tf->tf_eflags = eflags;
1100 tf->tf_vm86_ds = tf->tf_ds;
1101 tf->tf_vm86_es = tf->tf_es;
1102 tf->tf_vm86_fs = tf->tf_fs;
1103 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
1104 tf->tf_ds = _udatasel;
1105 tf->tf_es = _udatasel;
1106 tf->tf_fs = _udatasel;
1109 * Don't allow users to change privileged or reserved flags.
1111 if (!EFL_SECURE(eflags, regs->tf_eflags)) {
1112 uprintf("pid %d (%s): sigreturn eflags = 0x%x\n",
1113 td->td_proc->p_pid, td->td_name, eflags);
1118 * Don't allow users to load a valid privileged %cs. Let the
1119 * hardware check for invalid selectors, excess privilege in
1120 * other selectors, invalid %eip's and invalid %esp's.
1122 cs = ucp->uc_mcontext.mc_cs;
1123 if (!CS_SECURE(cs)) {
1124 uprintf("pid %d (%s): sigreturn cs = 0x%x\n",
1125 td->td_proc->p_pid, td->td_name, cs);
1126 ksiginfo_init_trap(&ksi);
1127 ksi.ksi_signo = SIGBUS;
1128 ksi.ksi_code = BUS_OBJERR;
1129 ksi.ksi_trapno = T_PROTFLT;
1130 ksi.ksi_addr = (void *)regs->tf_eip;
1131 trapsignal(td, &ksi);
1135 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) {
1136 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len;
1137 if (xfpustate_len > cpu_max_ext_state_size -
1138 sizeof(union savefpu)) {
1140 "pid %d (%s): sigreturn xfpusave_len = 0x%zx\n",
1141 p->p_pid, td->td_name, xfpustate_len);
1144 xfpustate = __builtin_alloca(xfpustate_len);
1145 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate,
1146 xfpustate, xfpustate_len);
1149 "pid %d (%s): sigreturn copying xfpustate failed\n",
1150 p->p_pid, td->td_name);
1157 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate,
1161 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(*regs));
1164 #if defined(COMPAT_43)
1165 if (ucp->uc_mcontext.mc_onstack & 1)
1166 td->td_sigstk.ss_flags |= SS_ONSTACK;
1168 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
1171 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
1172 return (EJUSTRETURN);
1176 * Machine dependent boot() routine
1178 * I haven't seen anything to put here yet
1179 * Possibly some stuff might be grafted back here from boot()
1187 * Flush the D-cache for non-DMA I/O so that the I-cache can
1188 * be made coherent later.
1191 cpu_flush_dcache(void *ptr, size_t len)
1193 /* Not applicable */
1196 /* Get current clock frequency for the given cpu id. */
1198 cpu_est_clockrate(int cpu_id, uint64_t *rate)
1200 uint64_t tsc1, tsc2;
1201 uint64_t acnt, mcnt, perf;
1204 if (pcpu_find(cpu_id) == NULL || rate == NULL)
1206 if ((cpu_feature & CPUID_TSC) == 0)
1207 return (EOPNOTSUPP);
1210 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
1211 * DELAY(9) based logic fails.
1213 if (tsc_is_invariant && !tsc_perf_stat)
1214 return (EOPNOTSUPP);
1218 /* Schedule ourselves on the indicated cpu. */
1219 thread_lock(curthread);
1220 sched_bind(curthread, cpu_id);
1221 thread_unlock(curthread);
1225 /* Calibrate by measuring a short delay. */
1226 reg = intr_disable();
1227 if (tsc_is_invariant) {
1228 wrmsr(MSR_MPERF, 0);
1229 wrmsr(MSR_APERF, 0);
1232 mcnt = rdmsr(MSR_MPERF);
1233 acnt = rdmsr(MSR_APERF);
1236 perf = 1000 * acnt / mcnt;
1237 *rate = (tsc2 - tsc1) * perf;
1243 *rate = (tsc2 - tsc1) * 1000;
1248 thread_lock(curthread);
1249 sched_unbind(curthread);
1250 thread_unlock(curthread);
1263 HYPERVISOR_sched_op(SCHEDOP_block, 0);
1269 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
1272 int scheduler_running;
1275 cpu_idle_hlt(sbintime_t sbt)
1278 scheduler_running = 1;
1285 * Shutdown the CPU as much as possible
1296 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */
1297 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
1298 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
1299 TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
1300 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
1301 0, "Use MONITOR/MWAIT for short idle");
1303 #define STATE_RUNNING 0x0
1304 #define STATE_MWAIT 0x1
1305 #define STATE_SLEEPING 0x2
1309 cpu_idle_acpi(sbintime_t sbt)
1313 state = (int *)PCPU_PTR(monitorbuf);
1314 *state = STATE_SLEEPING;
1316 /* See comments in cpu_idle_hlt(). */
1318 if (sched_runnable())
1320 else if (cpu_idle_hook)
1323 __asm __volatile("sti; hlt");
1324 *state = STATE_RUNNING;
1330 cpu_idle_hlt(sbintime_t sbt)
1334 state = (int *)PCPU_PTR(monitorbuf);
1335 *state = STATE_SLEEPING;
1338 * Since we may be in a critical section from cpu_idle(), if
1339 * an interrupt fires during that critical section we may have
1340 * a pending preemption. If the CPU halts, then that thread
1341 * may not execute until a later interrupt awakens the CPU.
1342 * To handle this race, check for a runnable thread after
1343 * disabling interrupts and immediately return if one is
1344 * found. Also, we must absolutely guarentee that hlt is
1345 * the next instruction after sti. This ensures that any
1346 * interrupt that fires after the call to disable_intr() will
1347 * immediately awaken the CPU from hlt. Finally, please note
1348 * that on x86 this works fine because of interrupts enabled only
1349 * after the instruction following sti takes place, while IF is set
1350 * to 1 immediately, allowing hlt instruction to acknowledge the
1354 if (sched_runnable())
1357 __asm __volatile("sti; hlt");
1358 *state = STATE_RUNNING;
1363 * MWAIT cpu power states. Lower 4 bits are sub-states.
1365 #define MWAIT_C0 0xf0
1366 #define MWAIT_C1 0x00
1367 #define MWAIT_C2 0x10
1368 #define MWAIT_C3 0x20
1369 #define MWAIT_C4 0x30
1372 cpu_idle_mwait(sbintime_t sbt)
1376 state = (int *)PCPU_PTR(monitorbuf);
1377 *state = STATE_MWAIT;
1379 /* See comments in cpu_idle_hlt(). */
1381 if (sched_runnable()) {
1383 *state = STATE_RUNNING;
1386 cpu_monitor(state, 0, 0);
1387 if (*state == STATE_MWAIT)
1388 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0));
1391 *state = STATE_RUNNING;
1395 cpu_idle_spin(sbintime_t sbt)
1400 state = (int *)PCPU_PTR(monitorbuf);
1401 *state = STATE_RUNNING;
1404 * The sched_runnable() call is racy but as long as there is
1405 * a loop missing it one time will have just a little impact if any
1406 * (and it is much better than missing the check at all).
1408 for (i = 0; i < 1000; i++) {
1409 if (sched_runnable())
1416 * C1E renders the local APIC timer dead, so we disable it by
1417 * reading the Interrupt Pending Message register and clearing
1418 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
1421 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
1422 * #32559 revision 3.00+
1424 #define MSR_AMDK8_IPM 0xc0010055
1425 #define AMDK8_SMIONCMPHALT (1ULL << 27)
1426 #define AMDK8_C1EONCMPHALT (1ULL << 28)
1427 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
1430 cpu_probe_amdc1e(void)
1434 * Detect the presence of C1E capability mostly on latest
1435 * dual-cores (or future) k8 family.
1437 if (cpu_vendor_id == CPU_VENDOR_AMD &&
1438 (cpu_id & 0x00000f00) == 0x00000f00 &&
1439 (cpu_id & 0x0fff0000) >= 0x00040000) {
1440 cpu_ident_amdc1e = 1;
1444 #if defined(PC98) || defined(XEN)
1445 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_hlt;
1447 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi;
1456 sbintime_t sbt = -1;
1458 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
1460 #if defined(MP_WATCHDOG) && !defined(XEN)
1461 ap_watchdog(PCPU_GET(cpuid));
1464 /* If we are busy - try to use fast methods. */
1466 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
1467 cpu_idle_mwait(busy);
1473 /* If we have time - switch timers into idle mode. */
1476 sbt = cpu_idleclock();
1480 /* Apply AMD APIC timer C1E workaround. */
1481 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) {
1482 msr = rdmsr(MSR_AMDK8_IPM);
1483 if (msr & AMDK8_CMPHALT)
1484 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
1488 /* Call main idle method. */
1491 /* Switch timers mack into active mode. */
1499 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
1504 cpu_idle_wakeup(int cpu)
1509 pcpu = pcpu_find(cpu);
1510 state = (int *)pcpu->pc_monitorbuf;
1512 * This doesn't need to be atomic since missing the race will
1513 * simply result in unnecessary IPIs.
1515 if (*state == STATE_SLEEPING)
1517 if (*state == STATE_MWAIT)
1518 *state = STATE_RUNNING;
1523 * Ordered by speed/power consumption.
1529 { cpu_idle_spin, "spin" },
1530 { cpu_idle_mwait, "mwait" },
1531 { cpu_idle_hlt, "hlt" },
1533 { cpu_idle_acpi, "acpi" },
1539 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
1545 avail = malloc(256, M_TEMP, M_WAITOK);
1547 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1548 if (strstr(idle_tbl[i].id_name, "mwait") &&
1549 (cpu_feature2 & CPUID2_MON) == 0)
1552 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
1553 cpu_idle_hook == NULL)
1556 p += sprintf(p, "%s%s", p != avail ? ", " : "",
1557 idle_tbl[i].id_name);
1559 error = sysctl_handle_string(oidp, avail, 0, req);
1560 free(avail, M_TEMP);
1564 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
1565 0, 0, idle_sysctl_available, "A", "list of available idle functions");
1568 idle_sysctl(SYSCTL_HANDLER_ARGS)
1576 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1577 if (idle_tbl[i].id_fn == cpu_idle_fn) {
1578 p = idle_tbl[i].id_name;
1582 strncpy(buf, p, sizeof(buf));
1583 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
1584 if (error != 0 || req->newptr == NULL)
1586 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
1587 if (strstr(idle_tbl[i].id_name, "mwait") &&
1588 (cpu_feature2 & CPUID2_MON) == 0)
1591 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
1592 cpu_idle_hook == NULL)
1595 if (strcmp(idle_tbl[i].id_name, buf))
1597 cpu_idle_fn = idle_tbl[i].id_fn;
1603 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
1604 idle_sysctl, "A", "currently selected idle function");
1607 * Reset registers to default values on exec.
1610 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
1612 struct trapframe *regs = td->td_frame;
1613 struct pcb *pcb = td->td_pcb;
1615 /* Reset pc->pcb_gs and %gs before possibly invalidating it. */
1616 pcb->pcb_gs = _udatasel;
1619 mtx_lock_spin(&dt_lock);
1620 if (td->td_proc->p_md.md_ldt)
1623 mtx_unlock_spin(&dt_lock);
1625 bzero((char *)regs, sizeof(struct trapframe));
1626 regs->tf_eip = imgp->entry_addr;
1627 regs->tf_esp = stack;
1628 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1629 regs->tf_ss = _udatasel;
1630 regs->tf_ds = _udatasel;
1631 regs->tf_es = _udatasel;
1632 regs->tf_fs = _udatasel;
1633 regs->tf_cs = _ucodesel;
1635 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1636 regs->tf_ebx = imgp->ps_strings;
1639 * Reset the hardware debug registers if they were in use.
1640 * They won't have any meaning for the newly exec'd process.
1642 if (pcb->pcb_flags & PCB_DBREGS) {
1649 if (pcb == curpcb) {
1651 * Clear the debug registers on the running
1652 * CPU, otherwise they will end up affecting
1653 * the next process we switch to.
1657 pcb->pcb_flags &= ~PCB_DBREGS;
1660 pcb->pcb_initial_npxcw = __INITIAL_NPXCW__;
1663 * Drop the FP state if we hold it, so that the process gets a
1664 * clean FP state if it uses the FPU again.
1669 * XXX - Linux emulator
1670 * Make sure sure edx is 0x0 on entry. Linux binaries depend
1673 td->td_retval[1] = 0;
1684 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support:
1686 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
1687 * instructions. We must set the CR0_MP bit and use the CR0_TS
1688 * bit to control the trap, because setting the CR0_EM bit does
1689 * not cause WAIT instructions to trap. It's important to trap
1690 * WAIT instructions - otherwise the "wait" variants of no-wait
1691 * control instructions would degenerate to the "no-wait" variants
1692 * after FP context switches but work correctly otherwise. It's
1693 * particularly important to trap WAITs when there is no NPX -
1694 * otherwise the "wait" variants would always degenerate.
1696 * Try setting CR0_NE to get correct error reporting on 486DX's.
1697 * Setting it should fail or do nothing on lesser processors.
1699 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
1704 u_long bootdev; /* not a struct cdev *- encoding is different */
1705 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1706 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)");
1708 static char bootmethod[16] = "BIOS";
1709 SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0,
1710 "System firmware boot method");
1713 * Initialize 386 and configure to run kernel
1717 * Initialize segments & interrupt table
1723 union descriptor *gdt;
1724 union descriptor *ldt;
1726 union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1727 union descriptor ldt[NLDT]; /* local descriptor table */
1729 static struct gate_descriptor idt0[NIDT];
1730 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1731 struct region_descriptor r_gdt, r_idt; /* table descriptors */
1732 struct mtx dt_lock; /* lock for GDT and LDT */
1734 static struct i386tss dblfault_tss;
1735 static char dblfault_stack[PAGE_SIZE];
1737 extern vm_offset_t proc0kstack;
1741 * software prototypes -- in more palatable form.
1743 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret
1744 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it)
1746 struct soft_segment_descriptor gdt_segs[] = {
1747 /* GNULL_SEL 0 Null Descriptor */
1753 .ssd_xx = 0, .ssd_xx1 = 0,
1756 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */
1758 .ssd_limit = 0xfffff,
1759 .ssd_type = SDT_MEMRWA,
1762 .ssd_xx = 0, .ssd_xx1 = 0,
1765 /* GUFS_SEL 2 %fs Descriptor for user */
1767 .ssd_limit = 0xfffff,
1768 .ssd_type = SDT_MEMRWA,
1771 .ssd_xx = 0, .ssd_xx1 = 0,
1774 /* GUGS_SEL 3 %gs Descriptor for user */
1776 .ssd_limit = 0xfffff,
1777 .ssd_type = SDT_MEMRWA,
1780 .ssd_xx = 0, .ssd_xx1 = 0,
1783 /* GCODE_SEL 4 Code Descriptor for kernel */
1785 .ssd_limit = 0xfffff,
1786 .ssd_type = SDT_MEMERA,
1789 .ssd_xx = 0, .ssd_xx1 = 0,
1792 /* GDATA_SEL 5 Data Descriptor for kernel */
1794 .ssd_limit = 0xfffff,
1795 .ssd_type = SDT_MEMRWA,
1798 .ssd_xx = 0, .ssd_xx1 = 0,
1801 /* GUCODE_SEL 6 Code Descriptor for user */
1803 .ssd_limit = 0xfffff,
1804 .ssd_type = SDT_MEMERA,
1807 .ssd_xx = 0, .ssd_xx1 = 0,
1810 /* GUDATA_SEL 7 Data Descriptor for user */
1812 .ssd_limit = 0xfffff,
1813 .ssd_type = SDT_MEMRWA,
1816 .ssd_xx = 0, .ssd_xx1 = 0,
1819 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1820 { .ssd_base = 0x400,
1821 .ssd_limit = 0xfffff,
1822 .ssd_type = SDT_MEMRWA,
1825 .ssd_xx = 0, .ssd_xx1 = 0,
1829 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
1832 .ssd_limit = sizeof(struct i386tss)-1,
1833 .ssd_type = SDT_SYS386TSS,
1836 .ssd_xx = 0, .ssd_xx1 = 0,
1839 /* GLDT_SEL 10 LDT Descriptor */
1840 { .ssd_base = (int) ldt,
1841 .ssd_limit = sizeof(ldt)-1,
1842 .ssd_type = SDT_SYSLDT,
1845 .ssd_xx = 0, .ssd_xx1 = 0,
1848 /* GUSERLDT_SEL 11 User LDT Descriptor per process */
1849 { .ssd_base = (int) ldt,
1850 .ssd_limit = (512 * sizeof(union descriptor)-1),
1851 .ssd_type = SDT_SYSLDT,
1854 .ssd_xx = 0, .ssd_xx1 = 0,
1857 /* GPANIC_SEL 12 Panic Tss Descriptor */
1858 { .ssd_base = (int) &dblfault_tss,
1859 .ssd_limit = sizeof(struct i386tss)-1,
1860 .ssd_type = SDT_SYS386TSS,
1863 .ssd_xx = 0, .ssd_xx1 = 0,
1866 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */
1868 .ssd_limit = 0xfffff,
1869 .ssd_type = SDT_MEMERA,
1872 .ssd_xx = 0, .ssd_xx1 = 0,
1875 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */
1877 .ssd_limit = 0xfffff,
1878 .ssd_type = SDT_MEMERA,
1881 .ssd_xx = 0, .ssd_xx1 = 0,
1884 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */
1886 .ssd_limit = 0xfffff,
1887 .ssd_type = SDT_MEMRWA,
1890 .ssd_xx = 0, .ssd_xx1 = 0,
1893 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */
1895 .ssd_limit = 0xfffff,
1896 .ssd_type = SDT_MEMRWA,
1899 .ssd_xx = 0, .ssd_xx1 = 0,
1902 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */
1904 .ssd_limit = 0xfffff,
1905 .ssd_type = SDT_MEMRWA,
1908 .ssd_xx = 0, .ssd_xx1 = 0,
1911 /* GNDIS_SEL 18 NDIS Descriptor */
1917 .ssd_xx = 0, .ssd_xx1 = 0,
1923 static struct soft_segment_descriptor ldt_segs[] = {
1924 /* Null Descriptor - overwritten by call gate */
1930 .ssd_xx = 0, .ssd_xx1 = 0,
1933 /* Null Descriptor - overwritten by call gate */
1939 .ssd_xx = 0, .ssd_xx1 = 0,
1942 /* Null Descriptor - overwritten by call gate */
1948 .ssd_xx = 0, .ssd_xx1 = 0,
1951 /* Code Descriptor for user */
1953 .ssd_limit = 0xfffff,
1954 .ssd_type = SDT_MEMERA,
1957 .ssd_xx = 0, .ssd_xx1 = 0,
1960 /* Null Descriptor - overwritten by call gate */
1966 .ssd_xx = 0, .ssd_xx1 = 0,
1969 /* Data Descriptor for user */
1971 .ssd_limit = 0xfffff,
1972 .ssd_type = SDT_MEMRWA,
1975 .ssd_xx = 0, .ssd_xx1 = 0,
1981 setidt(idx, func, typ, dpl, selec)
1988 struct gate_descriptor *ip;
1991 ip->gd_looffset = (int)func;
1992 ip->gd_selector = selec;
1998 ip->gd_hioffset = ((int)func)>>16 ;
2002 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
2003 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
2004 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
2005 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
2007 #ifdef KDTRACE_HOOKS
2011 IDTVEC(xen_intr_upcall),
2013 IDTVEC(lcall_syscall), IDTVEC(int0x80_syscall);
2017 * Display the index and function name of any IDT entries that don't use
2018 * the default 'rsvd' entry point.
2020 DB_SHOW_COMMAND(idt, db_show_idt)
2022 struct gate_descriptor *ip;
2027 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
2028 func = (ip->gd_hioffset << 16 | ip->gd_looffset);
2029 if (func != (uintptr_t)&IDTVEC(rsvd)) {
2030 db_printf("%3d\t", idx);
2031 db_printsym(func, DB_STGY_PROC);
2038 /* Show privileged registers. */
2039 DB_SHOW_COMMAND(sysregs, db_show_sysregs)
2041 uint64_t idtr, gdtr;
2044 db_printf("idtr\t0x%08x/%04x\n",
2045 (u_int)(idtr >> 16), (u_int)idtr & 0xffff);
2047 db_printf("gdtr\t0x%08x/%04x\n",
2048 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff);
2049 db_printf("ldtr\t0x%04x\n", rldt());
2050 db_printf("tr\t0x%04x\n", rtr());
2051 db_printf("cr0\t0x%08x\n", rcr0());
2052 db_printf("cr2\t0x%08x\n", rcr2());
2053 db_printf("cr3\t0x%08x\n", rcr3());
2054 db_printf("cr4\t0x%08x\n", rcr4());
2060 struct segment_descriptor *sd;
2061 struct soft_segment_descriptor *ssd;
2063 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
2064 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
2065 ssd->ssd_type = sd->sd_type;
2066 ssd->ssd_dpl = sd->sd_dpl;
2067 ssd->ssd_p = sd->sd_p;
2068 ssd->ssd_def32 = sd->sd_def32;
2069 ssd->ssd_gran = sd->sd_gran;
2072 #if !defined(PC98) && !defined(XEN)
2074 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
2076 int i, insert_idx, physmap_idx;
2078 physmap_idx = *physmap_idxp;
2080 if (boothowto & RB_VERBOSE)
2081 printf("SMAP type=%02x base=%016llx len=%016llx\n",
2082 smap->type, smap->base, smap->length);
2084 if (smap->type != SMAP_TYPE_MEMORY)
2087 if (smap->length == 0)
2091 if (smap->base > 0xffffffff) {
2092 printf("%uK of memory above 4GB ignored\n",
2093 (u_int)(smap->length / 1024));
2099 * Find insertion point while checking for overlap. Start off by
2100 * assuming the new entry will be added to the end.
2102 insert_idx = physmap_idx + 2;
2103 for (i = 0; i <= physmap_idx; i += 2) {
2104 if (smap->base < physmap[i + 1]) {
2105 if (smap->base + smap->length <= physmap[i]) {
2109 if (boothowto & RB_VERBOSE)
2111 "Overlapping memory regions, ignoring second region\n");
2116 /* See if we can prepend to the next entry. */
2117 if (insert_idx <= physmap_idx &&
2118 smap->base + smap->length == physmap[insert_idx]) {
2119 physmap[insert_idx] = smap->base;
2123 /* See if we can append to the previous entry. */
2124 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) {
2125 physmap[insert_idx - 1] += smap->length;
2130 *physmap_idxp = physmap_idx;
2131 if (physmap_idx == PHYSMAP_SIZE) {
2133 "Too many segments in the physical address map, giving up\n");
2138 * Move the last 'N' entries down to make room for the new
2141 for (i = physmap_idx; i > insert_idx; i -= 2) {
2142 physmap[i] = physmap[i - 2];
2143 physmap[i + 1] = physmap[i - 1];
2146 /* Insert the new entry. */
2147 physmap[insert_idx] = smap->base;
2148 physmap[insert_idx + 1] = smap->base + smap->length;
2151 #endif /* !PC98 && !XEN */
2161 if (basemem > 640) {
2162 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
2168 * XXX if biosbasemem is now < 640, there is a `hole'
2169 * between the end of base memory and the start of
2170 * ISA memory. The hole may be empty or it may
2171 * contain BIOS code or data. Map it read/write so
2172 * that the BIOS can write to it. (Memory from 0 to
2173 * the physical end of the kernel is mapped read-only
2174 * to begin with and then parts of it are remapped.
2175 * The parts that aren't remapped form holes that
2176 * remain read-only and are unused by the kernel.
2177 * The base memory area is below the physical end of
2178 * the kernel and right now forms a read-only hole.
2179 * The part of it from PAGE_SIZE to
2180 * (trunc_page(biosbasemem * 1024) - 1) will be
2181 * remapped and used by the kernel later.)
2183 * This code is similar to the code used in
2184 * pmap_mapdev, but since no memory needs to be
2185 * allocated we simply change the mapping.
2187 for (pa = trunc_page(basemem * 1024);
2188 pa < ISA_HOLE_START; pa += PAGE_SIZE)
2189 pmap_kenter(KERNBASE + pa, pa);
2192 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
2193 * the vm86 page table so that vm86 can scribble on them using
2194 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
2195 * page 0, at least as initialized here?
2197 pte = (pt_entry_t *)vm86paddr;
2198 for (i = basemem / 4; i < 160; i++)
2199 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
2204 * Populate the (physmap) array with base/bound pairs describing the
2205 * available physical memory in the system, then test this memory and
2206 * build the phys_avail array describing the actually-available memory.
2208 * If we cannot accurately determine the physical memory map, then use
2209 * value from the 0xE801 call, and failing that, the RTC.
2211 * Total memory size may be set by the kernel environment variable
2212 * hw.physmem or the compile-time define MAXMEM.
2214 * XXX first should be vm_paddr_t.
2218 getmemsize(int first)
2220 int off, physmap_idx, pa_indx, da_indx;
2221 u_long physmem_tunable, memtest;
2222 vm_paddr_t physmap[PHYSMAP_SIZE];
2224 quad_t dcons_addr, dcons_size;
2231 bzero(physmap, sizeof(physmap));
2233 /* XXX - some of EPSON machines can't use PG_N */
2235 if (pc98_machine_type & M_EPSON_PC98) {
2236 switch (epson_machine_id) {
2240 case EPSON_PC486_HX:
2241 case EPSON_PC486_HG:
2242 case EPSON_PC486_HA:
2248 under16 = pc98_getmemsize(&basemem, &extmem);
2252 physmap[1] = basemem * 1024;
2254 physmap[physmap_idx] = 0x100000;
2255 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
2258 * Now, physmap contains a map of physical memory.
2262 /* make hole for AP bootstrap code */
2263 physmap[1] = mp_bootaddress(physmap[1]);
2267 * Maxmem isn't the "maximum memory", it's one larger than the
2268 * highest page of the physical address space. It should be
2269 * called something like "Maxphyspage". We may adjust this
2270 * based on ``hw.physmem'' and the results of the memory test.
2272 Maxmem = atop(physmap[physmap_idx + 1]);
2275 Maxmem = MAXMEM / 4;
2278 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
2279 Maxmem = atop(physmem_tunable);
2282 * By default keep the memtest enabled. Use a general name so that
2283 * one could eventually do more with the code than just disable it.
2286 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
2288 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
2289 (boothowto & RB_VERBOSE))
2290 printf("Physical memory use set to %ldK\n", Maxmem * 4);
2293 * If Maxmem has been increased beyond what the system has detected,
2294 * extend the last memory segment to the new limit.
2296 if (atop(physmap[physmap_idx + 1]) < Maxmem)
2297 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
2300 * We need to divide chunk if Maxmem is larger than 16MB and
2301 * under 16MB area is not full of memory.
2302 * (1) system area (15-16MB region) is cut off
2303 * (2) extended memory is only over 16MB area (ex. Melco "HYPERMEMORY")
2305 if ((under16 != 16 * 1024) && (extmem > 15 * 1024)) {
2306 /* 15M - 16M region is cut off, so need to divide chunk */
2307 physmap[physmap_idx + 1] = under16 * 1024;
2309 physmap[physmap_idx] = 0x1000000;
2310 physmap[physmap_idx + 1] = physmap[2] + extmem * 1024;
2313 /* call pmap initialization to make new kernel address space */
2314 pmap_bootstrap(first);
2317 * Size up each available chunk of physical memory.
2319 physmap[0] = PAGE_SIZE; /* mask off page 0 */
2322 phys_avail[pa_indx++] = physmap[0];
2323 phys_avail[pa_indx] = physmap[0];
2324 dump_avail[da_indx] = physmap[0];
2328 * Get dcons buffer address
2330 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
2331 getenv_quad("dcons.size", &dcons_size) == 0)
2335 * physmap is in bytes, so when converting to page boundaries,
2336 * round up the start address and round down the end address.
2338 for (i = 0; i <= physmap_idx; i += 2) {
2341 end = ptoa((vm_paddr_t)Maxmem);
2342 if (physmap[i + 1] < end)
2343 end = trunc_page(physmap[i + 1]);
2344 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
2345 int tmp, page_bad, full;
2346 int *ptr = (int *)CADDR3;
2350 * block out kernel memory as not available.
2352 if (pa >= KERNLOAD && pa < first)
2356 * block out dcons buffer
2359 && pa >= trunc_page(dcons_addr)
2360 && pa < dcons_addr + dcons_size)
2368 * map page into kernel: valid, read/write,non-cacheable
2370 *pte = pa | PG_V | PG_RW | pg_n;
2375 * Test for alternating 1's and 0's
2377 *(volatile int *)ptr = 0xaaaaaaaa;
2378 if (*(volatile int *)ptr != 0xaaaaaaaa)
2381 * Test for alternating 0's and 1's
2383 *(volatile int *)ptr = 0x55555555;
2384 if (*(volatile int *)ptr != 0x55555555)
2389 *(volatile int *)ptr = 0xffffffff;
2390 if (*(volatile int *)ptr != 0xffffffff)
2395 *(volatile int *)ptr = 0x0;
2396 if (*(volatile int *)ptr != 0x0)
2399 * Restore original value.
2405 * Adjust array of valid/good pages.
2407 if (page_bad == TRUE)
2410 * If this good page is a continuation of the
2411 * previous set of good pages, then just increase
2412 * the end pointer. Otherwise start a new chunk.
2413 * Note that "end" points one higher than end,
2414 * making the range >= start and < end.
2415 * If we're also doing a speculative memory
2416 * test and we at or past the end, bump up Maxmem
2417 * so that we keep going. The first bad page
2418 * will terminate the loop.
2420 if (phys_avail[pa_indx] == pa) {
2421 phys_avail[pa_indx] += PAGE_SIZE;
2424 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2426 "Too many holes in the physical address space, giving up\n");
2431 phys_avail[pa_indx++] = pa; /* start */
2432 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
2436 if (dump_avail[da_indx] == pa) {
2437 dump_avail[da_indx] += PAGE_SIZE;
2440 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2444 dump_avail[da_indx++] = pa; /* start */
2445 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
2457 * The last chunk must contain at least one page plus the message
2458 * buffer to avoid complicating other code (message buffer address
2459 * calculation, etc.).
2461 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
2462 round_page(msgbufsize) >= phys_avail[pa_indx]) {
2463 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
2464 phys_avail[pa_indx--] = 0;
2465 phys_avail[pa_indx--] = 0;
2468 Maxmem = atop(phys_avail[pa_indx]);
2470 /* Trim off space for the message buffer. */
2471 phys_avail[pa_indx] -= round_page(msgbufsize);
2473 /* Map the message buffer. */
2474 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE)
2475 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
2482 getmemsize(int first)
2484 int has_smap, off, physmap_idx, pa_indx, da_indx;
2485 u_long physmem_tunable, memtest;
2486 vm_paddr_t physmap[PHYSMAP_SIZE];
2488 quad_t dcons_addr, dcons_size;
2490 int hasbrokenint12, i, res;
2492 struct vm86frame vmf;
2493 struct vm86context vmc;
2495 struct bios_smap *smap, *smapbase, *smapend;
2502 Maxmem = xen_start_info->nr_pages - init_first;
2505 physmap[0] = init_first << PAGE_SHIFT;
2506 physmap[1] = ptoa(Maxmem) - round_page(msgbufsize);
2510 if (arch_i386_is_xbox) {
2512 * We queried the memory size before, so chop off 4MB for
2513 * the framebuffer and inform the OS of this.
2516 physmap[1] = (arch_i386_xbox_memsize * 1024 * 1024) - XBOX_FB_SIZE;
2521 bzero(&vmf, sizeof(vmf));
2522 bzero(physmap, sizeof(physmap));
2526 * Check if the loader supplied an SMAP memory map. If so,
2527 * use that and do not make any VM86 calls.
2531 kmdp = preload_search_by_type("elf kernel");
2533 kmdp = preload_search_by_type("elf32 kernel");
2535 smapbase = (struct bios_smap *)preload_search_info(kmdp,
2536 MODINFO_METADATA | MODINFOMD_SMAP);
2537 if (smapbase != NULL) {
2539 * subr_module.c says:
2540 * "Consumer may safely assume that size value precedes data."
2541 * ie: an int32_t immediately precedes SMAP.
2543 smapsize = *((u_int32_t *)smapbase - 1);
2544 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
2547 for (smap = smapbase; smap < smapend; smap++)
2548 if (!add_smap_entry(smap, physmap, &physmap_idx))
2554 * Some newer BIOSes have a broken INT 12H implementation
2555 * which causes a kernel panic immediately. In this case, we
2556 * need use the SMAP to determine the base memory size.
2559 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
2560 if (hasbrokenint12 == 0) {
2561 /* Use INT12 to determine base memory size. */
2562 vm86_intcall(0x12, &vmf);
2563 basemem = vmf.vmf_ax;
2568 * Fetch the memory map with INT 15:E820. Map page 1 R/W into
2569 * the kernel page table so we can use it as a buffer. The
2570 * kernel will unmap this page later.
2572 pmap_kenter(KERNBASE + (1 << PAGE_SHIFT), 1 << PAGE_SHIFT);
2574 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
2575 res = vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
2576 KASSERT(res != 0, ("vm86_getptr() failed: address not found"));
2580 vmf.vmf_eax = 0xE820;
2581 vmf.vmf_edx = SMAP_SIG;
2582 vmf.vmf_ecx = sizeof(struct bios_smap);
2583 i = vm86_datacall(0x15, &vmf, &vmc);
2584 if (i || vmf.vmf_eax != SMAP_SIG)
2587 if (!add_smap_entry(smap, physmap, &physmap_idx))
2589 } while (vmf.vmf_ebx != 0);
2593 * If we didn't fetch the "base memory" size from INT12,
2594 * figure it out from the SMAP (or just guess).
2597 for (i = 0; i <= physmap_idx; i += 2) {
2598 if (physmap[i] == 0x00000000) {
2599 basemem = physmap[i + 1] / 1024;
2604 /* XXX: If we couldn't find basemem from SMAP, just guess. */
2610 if (physmap[1] != 0)
2614 * If we failed to find an SMAP, figure out the extended
2615 * memory size. We will then build a simple memory map with
2616 * two segments, one for "base memory" and the second for
2617 * "extended memory". Note that "extended memory" starts at a
2618 * physical address of 1MB and that both basemem and extmem
2619 * are in units of 1KB.
2621 * First, try to fetch the extended memory size via INT 15:E801.
2623 vmf.vmf_ax = 0xE801;
2624 if (vm86_intcall(0x15, &vmf) == 0) {
2625 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
2628 * If INT15:E801 fails, this is our last ditch effort
2629 * to determine the extended memory size. Currently
2630 * we prefer the RTC value over INT15:88.
2634 vm86_intcall(0x15, &vmf);
2635 extmem = vmf.vmf_ax;
2637 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
2642 * Special hack for chipsets that still remap the 384k hole when
2643 * there's 16MB of memory - this really confuses people that
2644 * are trying to use bus mastering ISA controllers with the
2645 * "16MB limit"; they only have 16MB, but the remapping puts
2646 * them beyond the limit.
2648 * If extended memory is between 15-16MB (16-17MB phys address range),
2651 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
2655 physmap[1] = basemem * 1024;
2657 physmap[physmap_idx] = 0x100000;
2658 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
2663 * Now, physmap contains a map of physical memory.
2667 /* make hole for AP bootstrap code */
2668 physmap[1] = mp_bootaddress(physmap[1]);
2672 * Maxmem isn't the "maximum memory", it's one larger than the
2673 * highest page of the physical address space. It should be
2674 * called something like "Maxphyspage". We may adjust this
2675 * based on ``hw.physmem'' and the results of the memory test.
2677 Maxmem = atop(physmap[physmap_idx + 1]);
2680 Maxmem = MAXMEM / 4;
2683 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
2684 Maxmem = atop(physmem_tunable);
2687 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend
2688 * the amount of memory in the system.
2690 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1]))
2691 Maxmem = atop(physmap[physmap_idx + 1]);
2694 * By default enable the memory test on real hardware, and disable
2695 * it if we appear to be running in a VM. This avoids touching all
2696 * pages unnecessarily, which doesn't matter on real hardware but is
2697 * bad for shared VM hosts. Use a general name so that
2698 * one could eventually do more with the code than just disable it.
2700 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1;
2701 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
2703 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
2704 (boothowto & RB_VERBOSE))
2705 printf("Physical memory use set to %ldK\n", Maxmem * 4);
2708 * If Maxmem has been increased beyond what the system has detected,
2709 * extend the last memory segment to the new limit.
2711 if (atop(physmap[physmap_idx + 1]) < Maxmem)
2712 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
2714 /* call pmap initialization to make new kernel address space */
2715 pmap_bootstrap(first);
2718 * Size up each available chunk of physical memory.
2720 physmap[0] = PAGE_SIZE; /* mask off page 0 */
2723 phys_avail[pa_indx++] = physmap[0];
2724 phys_avail[pa_indx] = physmap[0];
2725 dump_avail[da_indx] = physmap[0];
2729 * Get dcons buffer address
2731 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
2732 getenv_quad("dcons.size", &dcons_size) == 0)
2737 * physmap is in bytes, so when converting to page boundaries,
2738 * round up the start address and round down the end address.
2740 for (i = 0; i <= physmap_idx; i += 2) {
2743 end = ptoa((vm_paddr_t)Maxmem);
2744 if (physmap[i + 1] < end)
2745 end = trunc_page(physmap[i + 1]);
2746 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
2747 int tmp, page_bad, full;
2748 int *ptr = (int *)CADDR3;
2752 * block out kernel memory as not available.
2754 if (pa >= KERNLOAD && pa < first)
2758 * block out dcons buffer
2761 && pa >= trunc_page(dcons_addr)
2762 && pa < dcons_addr + dcons_size)
2770 * map page into kernel: valid, read/write,non-cacheable
2772 *pte = pa | PG_V | PG_RW | PG_N;
2777 * Test for alternating 1's and 0's
2779 *(volatile int *)ptr = 0xaaaaaaaa;
2780 if (*(volatile int *)ptr != 0xaaaaaaaa)
2783 * Test for alternating 0's and 1's
2785 *(volatile int *)ptr = 0x55555555;
2786 if (*(volatile int *)ptr != 0x55555555)
2791 *(volatile int *)ptr = 0xffffffff;
2792 if (*(volatile int *)ptr != 0xffffffff)
2797 *(volatile int *)ptr = 0x0;
2798 if (*(volatile int *)ptr != 0x0)
2801 * Restore original value.
2807 * Adjust array of valid/good pages.
2809 if (page_bad == TRUE)
2812 * If this good page is a continuation of the
2813 * previous set of good pages, then just increase
2814 * the end pointer. Otherwise start a new chunk.
2815 * Note that "end" points one higher than end,
2816 * making the range >= start and < end.
2817 * If we're also doing a speculative memory
2818 * test and we at or past the end, bump up Maxmem
2819 * so that we keep going. The first bad page
2820 * will terminate the loop.
2822 if (phys_avail[pa_indx] == pa) {
2823 phys_avail[pa_indx] += PAGE_SIZE;
2826 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
2828 "Too many holes in the physical address space, giving up\n");
2833 phys_avail[pa_indx++] = pa; /* start */
2834 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
2838 if (dump_avail[da_indx] == pa) {
2839 dump_avail[da_indx] += PAGE_SIZE;
2842 if (da_indx == DUMP_AVAIL_ARRAY_END) {
2846 dump_avail[da_indx++] = pa; /* start */
2847 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
2857 phys_avail[0] = physfree;
2858 phys_avail[1] = xen_start_info->nr_pages*PAGE_SIZE;
2860 dump_avail[1] = xen_start_info->nr_pages*PAGE_SIZE;
2866 * The last chunk must contain at least one page plus the message
2867 * buffer to avoid complicating other code (message buffer address
2868 * calculation, etc.).
2870 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
2871 round_page(msgbufsize) >= phys_avail[pa_indx]) {
2872 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
2873 phys_avail[pa_indx--] = 0;
2874 phys_avail[pa_indx--] = 0;
2877 Maxmem = atop(phys_avail[pa_indx]);
2879 /* Trim off space for the message buffer. */
2880 phys_avail[pa_indx] -= round_page(msgbufsize);
2882 /* Map the message buffer. */
2883 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE)
2884 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
2892 #define MTOPSIZE (1<<(14 + PAGE_SHIFT))
2898 unsigned long gdtmachpfn;
2899 int error, gsel_tss, metadata_missing, x, pa;
2901 #ifdef CPU_ENABLE_SSE
2902 struct xstate_hdr *xhdr;
2904 struct callback_register event = {
2905 .type = CALLBACKTYPE_event,
2906 .address = {GSEL(GCODE_SEL, SEL_KPL), (unsigned long)Xhypervisor_callback },
2908 struct callback_register failsafe = {
2909 .type = CALLBACKTYPE_failsafe,
2910 .address = {GSEL(GCODE_SEL, SEL_KPL), (unsigned long)failsafe_callback },
2913 thread0.td_kstack = proc0kstack;
2914 thread0.td_kstack_pages = KSTACK_PAGES;
2917 * This may be done better later if it gets more high level
2918 * components in it. If so just link td->td_proc here.
2920 proc_linkup0(&proc0, &thread0);
2922 metadata_missing = 0;
2923 if (xen_start_info->mod_start) {
2924 preload_metadata = (caddr_t)xen_start_info->mod_start;
2925 preload_bootstrap_relocate(KERNBASE);
2927 metadata_missing = 1;
2930 kern_envp = static_env;
2931 else if ((caddr_t)xen_start_info->cmd_line)
2932 kern_envp = xen_setbootenv((caddr_t)xen_start_info->cmd_line);
2934 boothowto |= xen_boothowto(kern_envp);
2936 /* Init basic tunables, hz etc */
2940 * XEN occupies a portion of the upper virtual address space
2941 * At its base it manages an array mapping machine page frames
2942 * to physical page frames - hence we need to be able to
2943 * access 4GB - (64MB - 4MB + 64k)
2945 gdt_segs[GPRIV_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2946 gdt_segs[GUFS_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2947 gdt_segs[GUGS_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2948 gdt_segs[GCODE_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2949 gdt_segs[GDATA_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2950 gdt_segs[GUCODE_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2951 gdt_segs[GUDATA_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2952 gdt_segs[GBIOSLOWMEM_SEL].ssd_limit = atop(HYPERVISOR_VIRT_START + MTOPSIZE);
2955 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
2956 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
2958 PT_SET_MA(gdt, xpmap_ptom(VTOP(gdt)) | PG_V | PG_RW);
2959 bzero(gdt, PAGE_SIZE);
2960 for (x = 0; x < NGDT; x++)
2961 ssdtosd(&gdt_segs[x], &gdt[x].sd);
2963 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
2965 gdtmachpfn = vtomach(gdt) >> PAGE_SHIFT;
2966 PT_SET_MA(gdt, xpmap_ptom(VTOP(gdt)) | PG_V);
2967 PANIC_IF(HYPERVISOR_set_gdt(&gdtmachpfn, 512) != 0);
2971 if ((error = HYPERVISOR_set_trap_table(trap_table)) != 0) {
2972 panic("set_trap_table failed - error %d\n", error);
2975 error = HYPERVISOR_callback_op(CALLBACKOP_register, &event);
2977 error = HYPERVISOR_callback_op(CALLBACKOP_register, &failsafe);
2978 #if CONFIG_XEN_COMPAT <= 0x030002
2979 if (error == -ENOXENSYS)
2980 HYPERVISOR_set_callbacks(GSEL(GCODE_SEL, SEL_KPL),
2981 (unsigned long)Xhypervisor_callback,
2982 GSEL(GCODE_SEL, SEL_KPL), (unsigned long)failsafe_callback);
2984 pcpu_init(pc, 0, sizeof(struct pcpu));
2985 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
2986 pmap_kenter(pa + KERNBASE, pa);
2987 dpcpu_init((void *)(first + KERNBASE), 0);
2988 first += DPCPU_SIZE;
2989 physfree += DPCPU_SIZE;
2990 init_first += DPCPU_SIZE / PAGE_SIZE;
2992 PCPU_SET(prvspace, pc);
2993 PCPU_SET(curthread, &thread0);
2996 * Initialize mutexes.
2998 * icu_lock: in order to allow an interrupt to occur in a critical
2999 * section, to set pcpu->ipending (etc...) properly, we
3000 * must be able to get the icu lock, so it can't be
3004 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
3006 /* make ldt memory segments */
3007 PT_SET_MA(ldt, xpmap_ptom(VTOP(ldt)) | PG_V | PG_RW);
3008 bzero(ldt, PAGE_SIZE);
3009 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
3010 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
3011 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
3012 ssdtosd(&ldt_segs[x], &ldt[x].sd);
3014 default_proc_ldt.ldt_base = (caddr_t)ldt;
3015 default_proc_ldt.ldt_len = 6;
3016 _default_ldt = (int)&default_proc_ldt;
3017 PCPU_SET(currentldt, _default_ldt);
3018 PT_SET_MA(ldt, *vtopte((unsigned long)ldt) & ~PG_RW);
3019 xen_set_ldt((unsigned long) ldt, (sizeof ldt_segs / sizeof ldt_segs[0]));
3021 #if defined(XEN_PRIVILEGED)
3023 * Initialize the i8254 before the console so that console
3024 * initialization can use DELAY().
3030 * Initialize the console before we print anything out.
3034 if (metadata_missing)
3035 printf("WARNING: loader(8) metadata is missing!\n");
3042 /* Reset and mask the atpics and leave them shut down. */
3046 * Point the ICU spurious interrupt vectors at the APIC spurious
3047 * interrupt handler.
3049 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
3050 GSEL(GCODE_SEL, SEL_KPL));
3051 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
3052 GSEL(GCODE_SEL, SEL_KPL));
3057 ksym_start = bootinfo.bi_symtab;
3058 ksym_end = bootinfo.bi_esymtab;
3064 if (boothowto & RB_KDB)
3065 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
3068 finishidentcpu(); /* Final stage of CPU initialization */
3069 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
3070 GSEL(GCODE_SEL, SEL_KPL));
3071 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
3072 GSEL(GCODE_SEL, SEL_KPL));
3073 initializecpu(); /* Initialize CPU registers */
3074 initializecpucache();
3076 /* pointer to selector slot for %fs/%gs */
3077 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
3079 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
3080 dblfault_tss.tss_esp2 = (int)&dblfault_stack[sizeof(dblfault_stack)];
3081 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
3082 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
3084 dblfault_tss.tss_cr3 = (int)IdlePDPT;
3086 dblfault_tss.tss_cr3 = (int)IdlePTD;
3088 dblfault_tss.tss_eip = (int)dblfault_handler;
3089 dblfault_tss.tss_eflags = PSL_KERNEL;
3090 dblfault_tss.tss_ds = dblfault_tss.tss_es =
3091 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
3092 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
3093 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
3094 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
3098 init_param2(physmem);
3100 /* now running on new page tables, configured,and u/iom is accessible */
3102 msgbufinit(msgbufp, msgbufsize);
3107 * Set up thread0 pcb after npxinit calculated pcb + fpu save
3108 * area size. Zero out the extended state header in fpu save
3111 thread0.td_pcb = get_pcb_td(&thread0);
3112 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
3113 #ifdef CPU_ENABLE_SSE
3115 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
3117 xhdr->xstate_bv = xsave_mask;
3120 PCPU_SET(curpcb, thread0.td_pcb);
3121 /* make an initial tss so cpu can get interrupt stack on syscall! */
3122 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
3123 PCPU_SET(common_tss.tss_esp0, (vm_offset_t)thread0.td_pcb - 16);
3124 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
3125 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
3126 HYPERVISOR_stack_switch(GSEL(GDATA_SEL, SEL_KPL),
3127 PCPU_GET(common_tss.tss_esp0));
3129 /* transfer to user mode */
3131 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
3132 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
3134 /* setup proc 0's pcb */
3135 thread0.td_pcb->pcb_flags = 0;
3137 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
3139 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
3141 thread0.td_pcb->pcb_ext = 0;
3142 thread0.td_frame = &proc0_tf;
3143 thread0.td_pcb->pcb_fsd = PCPU_GET(fsgs_gdt)[0];
3144 thread0.td_pcb->pcb_gsd = PCPU_GET(fsgs_gdt)[1];
3148 /* Location of kernel stack for locore */
3149 return ((register_t)thread0.td_pcb);
3157 struct gate_descriptor *gdp;
3158 int gsel_tss, metadata_missing, x, pa;
3160 #ifdef CPU_ENABLE_SSE
3161 struct xstate_hdr *xhdr;
3164 thread0.td_kstack = proc0kstack;
3165 thread0.td_kstack_pages = KSTACK_PAGES;
3168 * This may be done better later if it gets more high level
3169 * components in it. If so just link td->td_proc here.
3171 proc_linkup0(&proc0, &thread0);
3180 metadata_missing = 0;
3181 if (bootinfo.bi_modulep) {
3182 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
3183 preload_bootstrap_relocate(KERNBASE);
3185 metadata_missing = 1;
3188 kern_envp = static_env;
3189 else if (bootinfo.bi_envp)
3190 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
3192 /* Init basic tunables, hz etc */
3196 * Make gdt memory segments. All segments cover the full 4GB
3197 * of address space and permissions are enforced at page level.
3199 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
3200 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
3201 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1);
3202 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1);
3203 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1);
3204 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1);
3207 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1);
3208 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
3209 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
3211 for (x = 0; x < NGDT; x++)
3212 ssdtosd(&gdt_segs[x], &gdt[x].sd);
3214 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
3215 r_gdt.rd_base = (int) gdt;
3216 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
3219 pcpu_init(pc, 0, sizeof(struct pcpu));
3220 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
3221 pmap_kenter(pa + KERNBASE, pa);
3222 dpcpu_init((void *)(first + KERNBASE), 0);
3223 first += DPCPU_SIZE;
3224 PCPU_SET(prvspace, pc);
3225 PCPU_SET(curthread, &thread0);
3228 * Initialize mutexes.
3230 * icu_lock: in order to allow an interrupt to occur in a critical
3231 * section, to set pcpu->ipending (etc...) properly, we
3232 * must be able to get the icu lock, so it can't be
3236 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
3238 /* make ldt memory segments */
3239 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
3240 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
3241 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
3242 ssdtosd(&ldt_segs[x], &ldt[x].sd);
3244 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
3246 PCPU_SET(currentldt, _default_ldt);
3249 for (x = 0; x < NIDT; x++)
3250 setidt(x, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL,
3251 GSEL(GCODE_SEL, SEL_KPL));
3252 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL,
3253 GSEL(GCODE_SEL, SEL_KPL));
3254 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL,
3255 GSEL(GCODE_SEL, SEL_KPL));
3256 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL,
3257 GSEL(GCODE_SEL, SEL_KPL));
3258 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL,
3259 GSEL(GCODE_SEL, SEL_KPL));
3260 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL,
3261 GSEL(GCODE_SEL, SEL_KPL));
3262 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL,
3263 GSEL(GCODE_SEL, SEL_KPL));
3264 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
3265 GSEL(GCODE_SEL, SEL_KPL));
3266 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL
3267 , GSEL(GCODE_SEL, SEL_KPL));
3268 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
3269 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL,
3270 GSEL(GCODE_SEL, SEL_KPL));
3271 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL,
3272 GSEL(GCODE_SEL, SEL_KPL));
3273 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL,
3274 GSEL(GCODE_SEL, SEL_KPL));
3275 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL,
3276 GSEL(GCODE_SEL, SEL_KPL));
3277 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
3278 GSEL(GCODE_SEL, SEL_KPL));
3279 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL,
3280 GSEL(GCODE_SEL, SEL_KPL));
3281 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL,
3282 GSEL(GCODE_SEL, SEL_KPL));
3283 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL,
3284 GSEL(GCODE_SEL, SEL_KPL));
3285 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL,
3286 GSEL(GCODE_SEL, SEL_KPL));
3287 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL,
3288 GSEL(GCODE_SEL, SEL_KPL));
3289 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall), SDT_SYS386TGT, SEL_UPL,
3290 GSEL(GCODE_SEL, SEL_KPL));
3291 #ifdef KDTRACE_HOOKS
3292 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYS386TGT, SEL_UPL,
3293 GSEL(GCODE_SEL, SEL_KPL));
3296 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYS386IGT, SEL_UPL,
3297 GSEL(GCODE_SEL, SEL_KPL));
3300 r_idt.rd_limit = sizeof(idt0) - 1;
3301 r_idt.rd_base = (int) idt;
3306 * The following code queries the PCI ID of 0:0:0. For the XBOX,
3307 * This should be 0x10de / 0x02a5.
3309 * This is exactly what Linux does.
3311 outl(0xcf8, 0x80000000);
3312 if (inl(0xcfc) == 0x02a510de) {
3313 arch_i386_is_xbox = 1;
3314 pic16l_setled(XBOX_LED_GREEN);
3317 * We are an XBOX, but we may have either 64MB or 128MB of
3318 * memory. The PCI host bridge should be programmed for this,
3319 * so we just query it.
3321 outl(0xcf8, 0x80000084);
3322 arch_i386_xbox_memsize = (inl(0xcfc) == 0x7FFFFFF) ? 128 : 64;
3327 * Initialize the i8254 before the console so that console
3328 * initialization can use DELAY().
3333 * Initialize the console before we print anything out.
3337 if (metadata_missing)
3338 printf("WARNING: loader(8) metadata is missing!\n");
3347 /* Reset and mask the atpics and leave them shut down. */
3351 * Point the ICU spurious interrupt vectors at the APIC spurious
3352 * interrupt handler.
3354 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
3355 GSEL(GCODE_SEL, SEL_KPL));
3356 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL,
3357 GSEL(GCODE_SEL, SEL_KPL));
3362 ksym_start = bootinfo.bi_symtab;
3363 ksym_end = bootinfo.bi_esymtab;
3369 if (boothowto & RB_KDB)
3370 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
3373 finishidentcpu(); /* Final stage of CPU initialization */
3374 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL,
3375 GSEL(GCODE_SEL, SEL_KPL));
3376 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL,
3377 GSEL(GCODE_SEL, SEL_KPL));
3378 initializecpu(); /* Initialize CPU registers */
3379 initializecpucache();
3381 /* pointer to selector slot for %fs/%gs */
3382 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
3384 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
3385 dblfault_tss.tss_esp2 = (int)&dblfault_stack[sizeof(dblfault_stack)];
3386 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
3387 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
3389 dblfault_tss.tss_cr3 = (int)IdlePDPT;
3391 dblfault_tss.tss_cr3 = (int)IdlePTD;
3393 dblfault_tss.tss_eip = (int)dblfault_handler;
3394 dblfault_tss.tss_eflags = PSL_KERNEL;
3395 dblfault_tss.tss_ds = dblfault_tss.tss_es =
3396 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
3397 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
3398 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
3399 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
3403 init_param2(physmem);
3405 /* now running on new page tables, configured,and u/iom is accessible */
3407 msgbufinit(msgbufp, msgbufsize);
3412 * Set up thread0 pcb after npxinit calculated pcb + fpu save
3413 * area size. Zero out the extended state header in fpu save
3416 thread0.td_pcb = get_pcb_td(&thread0);
3417 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
3418 #ifdef CPU_ENABLE_SSE
3420 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
3422 xhdr->xstate_bv = xsave_mask;
3425 PCPU_SET(curpcb, thread0.td_pcb);
3426 /* make an initial tss so cpu can get interrupt stack on syscall! */
3427 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
3428 PCPU_SET(common_tss.tss_esp0, (vm_offset_t)thread0.td_pcb - 16);
3429 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
3430 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
3431 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
3432 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
3433 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
3436 /* make a call gate to reenter kernel with */
3437 gdp = &ldt[LSYS5CALLS_SEL].gd;
3439 x = (int) &IDTVEC(lcall_syscall);
3440 gdp->gd_looffset = x;
3441 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
3443 gdp->gd_type = SDT_SYS386CGT;
3444 gdp->gd_dpl = SEL_UPL;
3446 gdp->gd_hioffset = x >> 16;
3448 /* XXX does this work? */
3450 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
3451 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
3453 /* transfer to user mode */
3455 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
3456 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
3458 /* setup proc 0's pcb */
3459 thread0.td_pcb->pcb_flags = 0;
3461 thread0.td_pcb->pcb_cr3 = (int)IdlePDPT;
3463 thread0.td_pcb->pcb_cr3 = (int)IdlePTD;
3465 thread0.td_pcb->pcb_ext = 0;
3466 thread0.td_frame = &proc0_tf;
3474 /* Location of kernel stack for locore */
3475 return ((register_t)thread0.td_pcb);
3480 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
3483 pcpu->pc_acpi_id = 0xffffffff;
3488 smap_sysctl_handler(SYSCTL_HANDLER_ARGS)
3490 struct bios_smap *smapbase;
3491 struct bios_smap_xattr smap;
3494 int count, error, i;
3496 /* Retrieve the system memory map from the loader. */
3497 kmdp = preload_search_by_type("elf kernel");
3499 kmdp = preload_search_by_type("elf32 kernel");
3502 smapbase = (struct bios_smap *)preload_search_info(kmdp,
3503 MODINFO_METADATA | MODINFOMD_SMAP);
3504 if (smapbase == NULL)
3506 smapattr = (uint32_t *)preload_search_info(kmdp,
3507 MODINFO_METADATA | MODINFOMD_SMAP_XATTR);
3508 count = *((u_int32_t *)smapbase - 1) / sizeof(*smapbase);
3510 for (i = 0; i < count; i++) {
3511 smap.base = smapbase[i].base;
3512 smap.length = smapbase[i].length;
3513 smap.type = smapbase[i].type;
3514 if (smapattr != NULL)
3515 smap.xattr = smapattr[i];
3518 error = SYSCTL_OUT(req, &smap, sizeof(smap));
3522 SYSCTL_PROC(_machdep, OID_AUTO, smap, CTLTYPE_OPAQUE|CTLFLAG_RD, NULL, 0,
3523 smap_sysctl_handler, "S,bios_smap_xattr", "Raw BIOS SMAP data");
3527 spinlock_enter(void)
3533 if (td->td_md.md_spinlock_count == 0) {
3534 flags = intr_disable();
3535 td->td_md.md_spinlock_count = 1;
3536 td->td_md.md_saved_flags = flags;
3538 td->td_md.md_spinlock_count++;
3550 flags = td->td_md.md_saved_flags;
3551 td->td_md.md_spinlock_count--;
3552 if (td->td_md.md_spinlock_count == 0)
3553 intr_restore(flags);
3556 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
3557 static void f00f_hack(void *unused);
3558 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
3561 f00f_hack(void *unused)
3563 struct gate_descriptor *new_idt;
3571 printf("Intel Pentium detected, installing workaround for F00F bug\n");
3573 tmp = kmem_malloc(kernel_arena, PAGE_SIZE * 2, M_WAITOK | M_ZERO);
3575 panic("kmem_malloc returned 0");
3577 /* Put the problematic entry (#6) at the end of the lower page. */
3578 new_idt = (struct gate_descriptor*)
3579 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor));
3580 bcopy(idt, new_idt, sizeof(idt0));
3581 r_idt.rd_base = (u_int)new_idt;
3584 pmap_protect(kernel_pmap, tmp, tmp + PAGE_SIZE, VM_PROT_READ);
3586 #endif /* defined(I586_CPU) && !NO_F00F_HACK */
3589 * Construct a PCB from a trapframe. This is called from kdb_trap() where
3590 * we want to start a backtrace from the function that caused us to enter
3591 * the debugger. We have the context in the trapframe, but base the trace
3592 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
3593 * enough for a backtrace.
3596 makectx(struct trapframe *tf, struct pcb *pcb)
3599 pcb->pcb_edi = tf->tf_edi;
3600 pcb->pcb_esi = tf->tf_esi;
3601 pcb->pcb_ebp = tf->tf_ebp;
3602 pcb->pcb_ebx = tf->tf_ebx;
3603 pcb->pcb_eip = tf->tf_eip;
3604 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8;
3608 ptrace_set_pc(struct thread *td, u_long addr)
3611 td->td_frame->tf_eip = addr;
3616 ptrace_single_step(struct thread *td)
3618 td->td_frame->tf_eflags |= PSL_T;
3623 ptrace_clear_single_step(struct thread *td)
3625 td->td_frame->tf_eflags &= ~PSL_T;
3630 fill_regs(struct thread *td, struct reg *regs)
3633 struct trapframe *tp;
3637 regs->r_gs = pcb->pcb_gs;
3638 return (fill_frame_regs(tp, regs));
3642 fill_frame_regs(struct trapframe *tp, struct reg *regs)
3644 regs->r_fs = tp->tf_fs;
3645 regs->r_es = tp->tf_es;
3646 regs->r_ds = tp->tf_ds;
3647 regs->r_edi = tp->tf_edi;
3648 regs->r_esi = tp->tf_esi;
3649 regs->r_ebp = tp->tf_ebp;
3650 regs->r_ebx = tp->tf_ebx;
3651 regs->r_edx = tp->tf_edx;
3652 regs->r_ecx = tp->tf_ecx;
3653 regs->r_eax = tp->tf_eax;
3654 regs->r_eip = tp->tf_eip;
3655 regs->r_cs = tp->tf_cs;
3656 regs->r_eflags = tp->tf_eflags;
3657 regs->r_esp = tp->tf_esp;
3658 regs->r_ss = tp->tf_ss;
3663 set_regs(struct thread *td, struct reg *regs)
3666 struct trapframe *tp;
3669 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
3670 !CS_SECURE(regs->r_cs))
3673 tp->tf_fs = regs->r_fs;
3674 tp->tf_es = regs->r_es;
3675 tp->tf_ds = regs->r_ds;
3676 tp->tf_edi = regs->r_edi;
3677 tp->tf_esi = regs->r_esi;
3678 tp->tf_ebp = regs->r_ebp;
3679 tp->tf_ebx = regs->r_ebx;
3680 tp->tf_edx = regs->r_edx;
3681 tp->tf_ecx = regs->r_ecx;
3682 tp->tf_eax = regs->r_eax;
3683 tp->tf_eip = regs->r_eip;
3684 tp->tf_cs = regs->r_cs;
3685 tp->tf_eflags = regs->r_eflags;
3686 tp->tf_esp = regs->r_esp;
3687 tp->tf_ss = regs->r_ss;
3688 pcb->pcb_gs = regs->r_gs;
3692 #ifdef CPU_ENABLE_SSE
3694 fill_fpregs_xmm(sv_xmm, sv_87)
3695 struct savexmm *sv_xmm;
3696 struct save87 *sv_87;
3698 register struct env87 *penv_87 = &sv_87->sv_env;
3699 register struct envxmm *penv_xmm = &sv_xmm->sv_env;
3702 bzero(sv_87, sizeof(*sv_87));
3704 /* FPU control/status */
3705 penv_87->en_cw = penv_xmm->en_cw;
3706 penv_87->en_sw = penv_xmm->en_sw;
3707 penv_87->en_tw = penv_xmm->en_tw;
3708 penv_87->en_fip = penv_xmm->en_fip;
3709 penv_87->en_fcs = penv_xmm->en_fcs;
3710 penv_87->en_opcode = penv_xmm->en_opcode;
3711 penv_87->en_foo = penv_xmm->en_foo;
3712 penv_87->en_fos = penv_xmm->en_fos;
3715 for (i = 0; i < 8; ++i)
3716 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
3720 set_fpregs_xmm(sv_87, sv_xmm)
3721 struct save87 *sv_87;
3722 struct savexmm *sv_xmm;
3724 register struct env87 *penv_87 = &sv_87->sv_env;
3725 register struct envxmm *penv_xmm = &sv_xmm->sv_env;
3728 /* FPU control/status */
3729 penv_xmm->en_cw = penv_87->en_cw;
3730 penv_xmm->en_sw = penv_87->en_sw;
3731 penv_xmm->en_tw = penv_87->en_tw;
3732 penv_xmm->en_fip = penv_87->en_fip;
3733 penv_xmm->en_fcs = penv_87->en_fcs;
3734 penv_xmm->en_opcode = penv_87->en_opcode;
3735 penv_xmm->en_foo = penv_87->en_foo;
3736 penv_xmm->en_fos = penv_87->en_fos;
3739 for (i = 0; i < 8; ++i)
3740 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
3742 #endif /* CPU_ENABLE_SSE */
3745 fill_fpregs(struct thread *td, struct fpreg *fpregs)
3748 KASSERT(td == curthread || TD_IS_SUSPENDED(td) ||
3749 P_SHOULDSTOP(td->td_proc),
3750 ("not suspended thread %p", td));
3754 bzero(fpregs, sizeof(*fpregs));
3756 #ifdef CPU_ENABLE_SSE
3758 fill_fpregs_xmm(&get_pcb_user_save_td(td)->sv_xmm,
3759 (struct save87 *)fpregs);
3761 #endif /* CPU_ENABLE_SSE */
3762 bcopy(&get_pcb_user_save_td(td)->sv_87, fpregs,
3768 set_fpregs(struct thread *td, struct fpreg *fpregs)
3771 #ifdef CPU_ENABLE_SSE
3773 set_fpregs_xmm((struct save87 *)fpregs,
3774 &get_pcb_user_save_td(td)->sv_xmm);
3776 #endif /* CPU_ENABLE_SSE */
3777 bcopy(fpregs, &get_pcb_user_save_td(td)->sv_87,
3786 * Get machine context.
3789 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
3791 struct trapframe *tp;
3792 struct segment_descriptor *sdp;
3796 PROC_LOCK(curthread->td_proc);
3797 mcp->mc_onstack = sigonstack(tp->tf_esp);
3798 PROC_UNLOCK(curthread->td_proc);
3799 mcp->mc_gs = td->td_pcb->pcb_gs;
3800 mcp->mc_fs = tp->tf_fs;
3801 mcp->mc_es = tp->tf_es;
3802 mcp->mc_ds = tp->tf_ds;
3803 mcp->mc_edi = tp->tf_edi;
3804 mcp->mc_esi = tp->tf_esi;
3805 mcp->mc_ebp = tp->tf_ebp;
3806 mcp->mc_isp = tp->tf_isp;
3807 mcp->mc_eflags = tp->tf_eflags;
3808 if (flags & GET_MC_CLEAR_RET) {
3811 mcp->mc_eflags &= ~PSL_C;
3813 mcp->mc_eax = tp->tf_eax;
3814 mcp->mc_edx = tp->tf_edx;
3816 mcp->mc_ebx = tp->tf_ebx;
3817 mcp->mc_ecx = tp->tf_ecx;
3818 mcp->mc_eip = tp->tf_eip;
3819 mcp->mc_cs = tp->tf_cs;
3820 mcp->mc_esp = tp->tf_esp;
3821 mcp->mc_ss = tp->tf_ss;
3822 mcp->mc_len = sizeof(*mcp);
3823 get_fpcontext(td, mcp, NULL, 0);
3824 sdp = &td->td_pcb->pcb_fsd;
3825 mcp->mc_fsbase = sdp->sd_hibase << 24 | sdp->sd_lobase;
3826 sdp = &td->td_pcb->pcb_gsd;
3827 mcp->mc_gsbase = sdp->sd_hibase << 24 | sdp->sd_lobase;
3829 mcp->mc_xfpustate = 0;
3830 mcp->mc_xfpustate_len = 0;
3831 bzero(mcp->mc_spare2, sizeof(mcp->mc_spare2));
3836 * Set machine context.
3838 * However, we don't set any but the user modifiable flags, and we won't
3839 * touch the cs selector.
3842 set_mcontext(struct thread *td, mcontext_t *mcp)
3844 struct trapframe *tp;
3849 if (mcp->mc_len != sizeof(*mcp) ||
3850 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0)
3852 eflags = (mcp->mc_eflags & PSL_USERCHANGE) |
3853 (tp->tf_eflags & ~PSL_USERCHANGE);
3854 if (mcp->mc_flags & _MC_HASFPXSTATE) {
3855 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size -
3856 sizeof(union savefpu))
3858 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len);
3859 ret = copyin((void *)mcp->mc_xfpustate, xfpustate,
3860 mcp->mc_xfpustate_len);
3865 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len);
3868 tp->tf_fs = mcp->mc_fs;
3869 tp->tf_es = mcp->mc_es;
3870 tp->tf_ds = mcp->mc_ds;
3871 tp->tf_edi = mcp->mc_edi;
3872 tp->tf_esi = mcp->mc_esi;
3873 tp->tf_ebp = mcp->mc_ebp;
3874 tp->tf_ebx = mcp->mc_ebx;
3875 tp->tf_edx = mcp->mc_edx;
3876 tp->tf_ecx = mcp->mc_ecx;
3877 tp->tf_eax = mcp->mc_eax;
3878 tp->tf_eip = mcp->mc_eip;
3879 tp->tf_eflags = eflags;
3880 tp->tf_esp = mcp->mc_esp;
3881 tp->tf_ss = mcp->mc_ss;
3882 td->td_pcb->pcb_gs = mcp->mc_gs;
3887 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
3888 size_t xfpusave_len)
3890 #ifdef CPU_ENABLE_SSE
3891 size_t max_len, len;
3895 mcp->mc_fpformat = _MC_FPFMT_NODEV;
3896 mcp->mc_ownedfp = _MC_FPOWNED_NONE;
3897 bzero(mcp->mc_fpstate, sizeof(mcp->mc_fpstate));
3899 mcp->mc_ownedfp = npxgetregs(td);
3900 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0],
3901 sizeof(mcp->mc_fpstate));
3902 mcp->mc_fpformat = npxformat();
3903 #ifdef CPU_ENABLE_SSE
3904 if (!use_xsave || xfpusave_len == 0)
3906 max_len = cpu_max_ext_state_size - sizeof(union savefpu);
3908 if (len > max_len) {
3910 bzero(xfpusave + max_len, len - max_len);
3912 mcp->mc_flags |= _MC_HASFPXSTATE;
3913 mcp->mc_xfpustate_len = len;
3914 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len);
3920 set_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpustate,
3921 size_t xfpustate_len)
3923 union savefpu *fpstate;
3926 if (mcp->mc_fpformat == _MC_FPFMT_NODEV)
3928 else if (mcp->mc_fpformat != _MC_FPFMT_387 &&
3929 mcp->mc_fpformat != _MC_FPFMT_XMM)
3931 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) {
3932 /* We don't care what state is left in the FPU or PCB. */
3935 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU ||
3936 mcp->mc_ownedfp == _MC_FPOWNED_PCB) {
3938 fpstate = (union savefpu *)&mcp->mc_fpstate;
3939 #ifdef CPU_ENABLE_SSE
3941 fpstate->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask;
3943 error = npxsetregs(td, fpstate, xfpustate, xfpustate_len);
3953 fpstate_drop(struct thread *td)
3956 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu"));
3959 if (PCPU_GET(fpcurthread) == td)
3963 * XXX force a full drop of the npx. The above only drops it if we
3964 * owned it. npxgetregs() has the same bug in the !cpu_fxsr case.
3966 * XXX I don't much like npxgetregs()'s semantics of doing a full
3967 * drop. Dropping only to the pcb matches fnsave's behaviour.
3968 * We only need to drop to !PCB_INITDONE in sendsig(). But
3969 * sendsig() is the only caller of npxgetregs()... perhaps we just
3970 * have too many layers.
3972 curthread->td_pcb->pcb_flags &= ~(PCB_NPXINITDONE |
3973 PCB_NPXUSERINITDONE);
3978 fill_dbregs(struct thread *td, struct dbreg *dbregs)
3983 dbregs->dr[0] = rdr0();
3984 dbregs->dr[1] = rdr1();
3985 dbregs->dr[2] = rdr2();
3986 dbregs->dr[3] = rdr3();
3987 dbregs->dr[4] = rdr4();
3988 dbregs->dr[5] = rdr5();
3989 dbregs->dr[6] = rdr6();
3990 dbregs->dr[7] = rdr7();
3993 dbregs->dr[0] = pcb->pcb_dr0;
3994 dbregs->dr[1] = pcb->pcb_dr1;
3995 dbregs->dr[2] = pcb->pcb_dr2;
3996 dbregs->dr[3] = pcb->pcb_dr3;
3999 dbregs->dr[6] = pcb->pcb_dr6;
4000 dbregs->dr[7] = pcb->pcb_dr7;
4006 set_dbregs(struct thread *td, struct dbreg *dbregs)
4012 load_dr0(dbregs->dr[0]);
4013 load_dr1(dbregs->dr[1]);
4014 load_dr2(dbregs->dr[2]);
4015 load_dr3(dbregs->dr[3]);
4016 load_dr4(dbregs->dr[4]);
4017 load_dr5(dbregs->dr[5]);
4018 load_dr6(dbregs->dr[6]);
4019 load_dr7(dbregs->dr[7]);
4022 * Don't let an illegal value for dr7 get set. Specifically,
4023 * check for undefined settings. Setting these bit patterns
4024 * result in undefined behaviour and can lead to an unexpected
4027 for (i = 0; i < 4; i++) {
4028 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02)
4030 if (DBREG_DR7_LEN(dbregs->dr[7], i) == 0x02)
4037 * Don't let a process set a breakpoint that is not within the
4038 * process's address space. If a process could do this, it
4039 * could halt the system by setting a breakpoint in the kernel
4040 * (if ddb was enabled). Thus, we need to check to make sure
4041 * that no breakpoints are being enabled for addresses outside
4042 * process's address space.
4044 * XXX - what about when the watched area of the user's
4045 * address space is written into from within the kernel
4046 * ... wouldn't that still cause a breakpoint to be generated
4047 * from within kernel mode?
4050 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) {
4051 /* dr0 is enabled */
4052 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
4056 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) {
4057 /* dr1 is enabled */
4058 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
4062 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) {
4063 /* dr2 is enabled */
4064 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
4068 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) {
4069 /* dr3 is enabled */
4070 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
4074 pcb->pcb_dr0 = dbregs->dr[0];
4075 pcb->pcb_dr1 = dbregs->dr[1];
4076 pcb->pcb_dr2 = dbregs->dr[2];
4077 pcb->pcb_dr3 = dbregs->dr[3];
4078 pcb->pcb_dr6 = dbregs->dr[6];
4079 pcb->pcb_dr7 = dbregs->dr[7];
4081 pcb->pcb_flags |= PCB_DBREGS;
4088 * Return > 0 if a hardware breakpoint has been hit, and the
4089 * breakpoint was in user space. Return 0, otherwise.
4092 user_dbreg_trap(void)
4094 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
4095 u_int32_t bp; /* breakpoint bits extracted from dr6 */
4096 int nbp; /* number of breakpoints that triggered */
4097 caddr_t addr[4]; /* breakpoint addresses */
4101 if ((dr7 & 0x000000ff) == 0) {
4103 * all GE and LE bits in the dr7 register are zero,
4104 * thus the trap couldn't have been caused by the
4105 * hardware debug registers
4112 bp = dr6 & 0x0000000f;
4116 * None of the breakpoint bits are set meaning this
4117 * trap was not caused by any of the debug registers
4123 * at least one of the breakpoints were hit, check to see
4124 * which ones and if any of them are user space addresses
4128 addr[nbp++] = (caddr_t)rdr0();
4131 addr[nbp++] = (caddr_t)rdr1();
4134 addr[nbp++] = (caddr_t)rdr2();
4137 addr[nbp++] = (caddr_t)rdr3();
4140 for (i = 0; i < nbp; i++) {
4141 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
4143 * addr[i] is in user space
4150 * None of the breakpoints are in user space.
4158 * Provide inb() and outb() as functions. They are normally only available as
4159 * inline functions, thus cannot be called from the debugger.
4162 /* silence compiler warnings */
4163 u_char inb_(u_short);
4164 void outb_(u_short, u_char);
4173 outb_(u_short port, u_char data)