2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <sys/cpuset.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_object.h>
133 #include <vm/vm_extern.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_pager.h>
136 #include <vm/vm_phys.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
143 #include <machine/intr_machdep.h>
144 #include <machine/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
156 #include <machine/xbox.h>
159 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
160 #define CPU_ENABLE_SSE
163 #ifndef PMAP_SHPGPERPROC
164 #define PMAP_SHPGPERPROC 200
167 #if !defined(DIAGNOSTIC)
168 #ifdef __GNUC_GNU_INLINE__
169 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
171 #define PMAP_INLINE extern inline
178 #define PV_STAT(x) do { x ; } while (0)
180 #define PV_STAT(x) do { } while (0)
183 #define pa_index(pa) ((pa) >> PDRSHIFT)
184 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
187 * Get PDEs and PTEs for user/kernel address space
189 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
190 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
192 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
193 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
194 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
195 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
196 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
198 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
199 atomic_clear_int((u_int *)(pte), PG_W))
200 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
202 struct pmap kernel_pmap_store;
203 LIST_HEAD(pmaplist, pmap);
204 static struct pmaplist allpmaps;
205 static struct mtx allpmaps_lock;
207 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
208 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
209 int pgeflag = 0; /* PG_G or-in */
210 int pseflag = 0; /* PG_PS or-in */
212 static int nkpt = NKPT;
213 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
214 extern u_int32_t KERNend;
215 extern u_int32_t KPTphys;
217 #if defined(PAE) || defined(PAE_TABLES)
219 static uma_zone_t pdptzone;
222 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
224 static int pat_works = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
226 "Is page attribute table fully functional?");
228 static int pg_ps_enabled = 1;
229 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
230 "Are large page mappings enabled?");
232 #define PAT_INDEX_SIZE 8
233 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
236 * pmap_mapdev support pre initialization (i.e. console)
238 #define PMAP_PREINIT_MAPPING_COUNT 8
239 static struct pmap_preinit_mapping {
244 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
245 static int pmap_initialized;
247 static struct rwlock_padalign pvh_global_lock;
250 * Data for the pv entry allocation mechanism
252 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
253 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
254 static struct md_page *pv_table;
255 static int shpgperproc = PMAP_SHPGPERPROC;
257 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
258 int pv_maxchunks; /* How many chunks we have KVA for */
259 vm_offset_t pv_vafree; /* freelist stored in the PTE */
262 * All those kernel PT submaps that BSD is so fond of
271 static struct sysmaps sysmaps_pcpu[MAXCPU];
273 static pd_entry_t *KPTD;
276 struct msgbuf *msgbufp = 0;
281 static caddr_t crashdumpmap;
283 static pt_entry_t *PMAP1 = 0, *PMAP2;
284 static pt_entry_t *PADDR1 = 0, *PADDR2;
287 static int PMAP1changedcpu;
288 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
290 "Number of times pmap_pte_quick changed CPU with same PMAP1");
292 static int PMAP1changed;
293 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
295 "Number of times pmap_pte_quick changed PMAP1");
296 static int PMAP1unchanged;
297 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
299 "Number of times pmap_pte_quick didn't change PMAP1");
300 static struct mtx PMAP2mutex;
302 static void free_pv_chunk(struct pv_chunk *pc);
303 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
304 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
305 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
306 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
307 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
308 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
309 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
311 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
313 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
314 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
316 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
317 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
318 static void pmap_flush_page(vm_page_t m);
319 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
320 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
321 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
322 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
323 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
324 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
325 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
326 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
327 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
328 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
330 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
331 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
332 struct spglist *free);
333 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
334 struct spglist *free);
335 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
336 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
337 struct spglist *free);
338 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
340 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
341 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
343 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
345 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
347 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
349 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
350 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
351 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
352 static void pmap_pte_release(pt_entry_t *pte);
353 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
354 #if defined(PAE) || defined(PAE_TABLES)
355 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
358 static void pmap_set_pg(void);
360 static __inline void pagezero(void *page);
362 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
363 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
366 * If you get an error here, then you set KVA_PAGES wrong! See the
367 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
368 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
370 CTASSERT(KERNBASE % (1 << 24) == 0);
373 * Bootstrap the system enough to run with virtual memory.
375 * On the i386 this is called after mapping has already been enabled
376 * and just syncs the pmap module with what has already been done.
377 * [We can't call it easily with mapping off since the kernel is not
378 * mapped with PA == VA, hence we would have to relocate every address
379 * from the linked base (virtual) address "KERNBASE" to the actual
380 * (physical) address starting relative to 0]
383 pmap_bootstrap(vm_paddr_t firstaddr)
386 pt_entry_t *pte, *unused;
387 struct sysmaps *sysmaps;
391 * Add a physical memory segment (vm_phys_seg) corresponding to the
392 * preallocated kernel page table pages so that vm_page structures
393 * representing these pages will be created. The vm_page structures
394 * are required for promotion of the corresponding kernel virtual
395 * addresses to superpage mappings.
397 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
400 * Initialize the first available kernel virtual address. However,
401 * using "firstaddr" may waste a few pages of the kernel virtual
402 * address space, because locore may not have mapped every physical
403 * page that it allocated. Preferably, locore would provide a first
404 * unused virtual address in addition to "firstaddr".
406 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
408 virtual_end = VM_MAX_KERNEL_ADDRESS;
411 * Initialize the kernel pmap (which is statically allocated).
413 PMAP_LOCK_INIT(kernel_pmap);
414 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
415 #if defined(PAE) || defined(PAE_TABLES)
416 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
418 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
419 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
422 * Initialize the global pv list lock.
424 rw_init(&pvh_global_lock, "pmap pv global");
426 LIST_INIT(&allpmaps);
429 * Request a spin mutex so that changes to allpmaps cannot be
430 * preempted by smp_rendezvous_cpus(). Otherwise,
431 * pmap_update_pde_kernel() could access allpmaps while it is
434 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
435 mtx_lock_spin(&allpmaps_lock);
436 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
437 mtx_unlock_spin(&allpmaps_lock);
440 * Reserve some special page table entries/VA space for temporary
443 #define SYSMAP(c, p, v, n) \
444 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
450 * CMAP1/CMAP2 are used for zeroing and copying pages.
451 * CMAP3 is used for the idle process page zeroing.
453 for (i = 0; i < MAXCPU; i++) {
454 sysmaps = &sysmaps_pcpu[i];
455 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
456 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
457 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
459 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
464 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
467 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
469 SYSMAP(caddr_t, unused, ptvmmap, 1)
472 * msgbufp is used to map the system message buffer.
474 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
477 * KPTmap is used by pmap_kextract().
479 * KPTmap is first initialized by locore. However, that initial
480 * KPTmap can only support NKPT page table pages. Here, a larger
481 * KPTmap is created that can support KVA_PAGES page table pages.
483 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
485 for (i = 0; i < NKPT; i++)
486 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
489 * Adjust the start of the KPTD and KPTmap so that the implementation
490 * of pmap_kextract() and pmap_growkernel() can be made simpler.
493 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
496 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
499 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
500 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
502 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
507 * Leave in place an identity mapping (virt == phys) for the low 1 MB
508 * physical memory region that is used by the ACPI wakeup code. This
509 * mapping must not have PG_G set.
512 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
513 * an early stadium, we cannot yet neatly map video memory ... :-(
514 * Better fixes are very welcome! */
515 if (!arch_i386_is_xbox)
517 for (i = 1; i < NKPT; i++)
521 * Initialize the PAT MSR if present.
522 * pmap_init_pat() clears and sets CR4_PGE, which, as a
523 * side-effect, invalidates stale PG_G TLB entries that might
524 * have been created in our pre-boot environment. We assume
525 * that PAT support implies PGE and in reverse, PGE presence
526 * comes with PAT. Both features were added for Pentium Pro.
530 /* Turn on PG_G on kernel page(s) */
540 int pat_table[PAT_INDEX_SIZE];
545 /* Set default PAT index table. */
546 for (i = 0; i < PAT_INDEX_SIZE; i++)
548 pat_table[PAT_WRITE_BACK] = 0;
549 pat_table[PAT_WRITE_THROUGH] = 1;
550 pat_table[PAT_UNCACHEABLE] = 3;
551 pat_table[PAT_WRITE_COMBINING] = 3;
552 pat_table[PAT_WRITE_PROTECTED] = 3;
553 pat_table[PAT_UNCACHED] = 3;
556 * Bail if this CPU doesn't implement PAT.
557 * We assume that PAT support implies PGE.
559 if ((cpu_feature & CPUID_PAT) == 0) {
560 for (i = 0; i < PAT_INDEX_SIZE; i++)
561 pat_index[i] = pat_table[i];
567 * Due to some Intel errata, we can only safely use the lower 4
570 * Intel Pentium III Processor Specification Update
571 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
574 * Intel Pentium IV Processor Specification Update
575 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
577 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
578 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
581 /* Initialize default PAT entries. */
582 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
583 PAT_VALUE(1, PAT_WRITE_THROUGH) |
584 PAT_VALUE(2, PAT_UNCACHED) |
585 PAT_VALUE(3, PAT_UNCACHEABLE) |
586 PAT_VALUE(4, PAT_WRITE_BACK) |
587 PAT_VALUE(5, PAT_WRITE_THROUGH) |
588 PAT_VALUE(6, PAT_UNCACHED) |
589 PAT_VALUE(7, PAT_UNCACHEABLE);
593 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
594 * Program 5 and 6 as WP and WC.
595 * Leave 4 and 7 as WB and UC.
597 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
598 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
599 PAT_VALUE(6, PAT_WRITE_COMBINING);
600 pat_table[PAT_UNCACHED] = 2;
601 pat_table[PAT_WRITE_PROTECTED] = 5;
602 pat_table[PAT_WRITE_COMBINING] = 6;
605 * Just replace PAT Index 2 with WC instead of UC-.
607 pat_msr &= ~PAT_MASK(2);
608 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
609 pat_table[PAT_WRITE_COMBINING] = 2;
614 load_cr4(cr4 & ~CR4_PGE);
616 /* Disable caches (CD = 1, NW = 0). */
618 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
620 /* Flushes caches and TLBs. */
624 /* Update PAT and index table. */
625 wrmsr(MSR_PAT, pat_msr);
626 for (i = 0; i < PAT_INDEX_SIZE; i++)
627 pat_index[i] = pat_table[i];
629 /* Flush caches and TLBs again. */
633 /* Restore caches and PGE. */
639 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
645 vm_offset_t va, endva;
650 endva = KERNBASE + KERNend;
653 va = KERNBASE + KERNLOAD;
655 pdir_pde(PTD, va) |= pgeflag;
656 invltlb(); /* Play it safe, invltlb() every time */
660 va = (vm_offset_t)btext;
665 invltlb(); /* Play it safe, invltlb() every time */
672 * Initialize a vm_page's machine-dependent fields.
675 pmap_page_init(vm_page_t m)
678 TAILQ_INIT(&m->md.pv_list);
679 m->md.pat_mode = PAT_WRITE_BACK;
682 #if defined(PAE) || defined(PAE_TABLES)
684 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
687 /* Inform UMA that this allocator uses kernel_map/object. */
688 *flags = UMA_SLAB_KERNEL;
689 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
690 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
695 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
697 * - Must deal with pages in order to ensure that none of the PG_* bits
698 * are ever set, PG_V in particular.
699 * - Assumes we can write to ptes without pte_store() atomic ops, even
700 * on PAE systems. This should be ok.
701 * - Assumes nothing will ever test these addresses for 0 to indicate
702 * no mapping instead of correctly checking PG_V.
703 * - Assumes a vm_offset_t will fit in a pte (true for i386).
704 * Because PG_V is never set, there can be no mappings to invalidate.
707 pmap_ptelist_alloc(vm_offset_t *head)
714 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
718 panic("pmap_ptelist_alloc: va with PG_V set!");
724 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
729 panic("pmap_ptelist_free: freeing va with PG_V set!");
731 *pte = *head; /* virtual! PG_V is 0 though */
736 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
742 for (i = npages - 1; i >= 0; i--) {
743 va = (vm_offset_t)base + i * PAGE_SIZE;
744 pmap_ptelist_free(head, va);
750 * Initialize the pmap module.
751 * Called by vm_init, to initialize any structures that the pmap
752 * system needs to map virtual memory.
757 struct pmap_preinit_mapping *ppim;
763 * Initialize the vm page array entries for the kernel pmap's
766 for (i = 0; i < NKPT; i++) {
767 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
768 KASSERT(mpte >= vm_page_array &&
769 mpte < &vm_page_array[vm_page_array_size],
770 ("pmap_init: page table page is out of range"));
771 mpte->pindex = i + KPTDI;
772 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
776 * Initialize the address space (zone) for the pv entries. Set a
777 * high water mark so that the system can recover from excessive
778 * numbers of pv entries.
780 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
781 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
782 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
783 pv_entry_max = roundup(pv_entry_max, _NPCPV);
784 pv_entry_high_water = 9 * (pv_entry_max / 10);
787 * If the kernel is running on a virtual machine, then it must assume
788 * that MCA is enabled by the hypervisor. Moreover, the kernel must
789 * be prepared for the hypervisor changing the vendor and family that
790 * are reported by CPUID. Consequently, the workaround for AMD Family
791 * 10h Erratum 383 is enabled if the processor's feature set does not
792 * include at least one feature that is only supported by older Intel
793 * or newer AMD processors.
795 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
796 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
797 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
799 workaround_erratum383 = 1;
802 * Are large page mappings supported and enabled?
804 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
807 else if (pg_ps_enabled) {
808 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
809 ("pmap_init: can't assign to pagesizes[1]"));
810 pagesizes[1] = NBPDR;
814 * Calculate the size of the pv head table for superpages.
815 * Handle the possibility that "vm_phys_segs[...].end" is zero.
817 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
818 PAGE_SIZE) / NBPDR + 1;
821 * Allocate memory for the pv head table for superpages.
823 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
825 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
827 for (i = 0; i < pv_npg; i++)
828 TAILQ_INIT(&pv_table[i].pv_list);
830 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
831 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
832 if (pv_chunkbase == NULL)
833 panic("pmap_init: not enough kvm for pv chunks");
834 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
835 #if defined(PAE) || defined(PAE_TABLES)
836 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
837 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
838 UMA_ZONE_VM | UMA_ZONE_NOFREE);
839 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
842 pmap_initialized = 1;
845 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
846 ppim = pmap_preinit_mapping + i;
849 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
850 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
855 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
856 "Max number of PV entries");
857 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
858 "Page share factor per proc");
860 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
861 "2/4MB page mapping counters");
863 static u_long pmap_pde_demotions;
864 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
865 &pmap_pde_demotions, 0, "2/4MB page demotions");
867 static u_long pmap_pde_mappings;
868 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
869 &pmap_pde_mappings, 0, "2/4MB page mappings");
871 static u_long pmap_pde_p_failures;
872 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
873 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
875 static u_long pmap_pde_promotions;
876 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
877 &pmap_pde_promotions, 0, "2/4MB page promotions");
879 /***************************************************
880 * Low level helper routines.....
881 ***************************************************/
884 * Determine the appropriate bits to set in a PTE or PDE for a specified
888 pmap_cache_bits(int mode, boolean_t is_pde)
890 int cache_bits, pat_flag, pat_idx;
892 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
893 panic("Unknown caching mode %d\n", mode);
895 /* The PAT bit is different for PTE's and PDE's. */
896 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
898 /* Map the caching mode to a PAT index. */
899 pat_idx = pat_index[mode];
901 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
904 cache_bits |= pat_flag;
906 cache_bits |= PG_NC_PCD;
908 cache_bits |= PG_NC_PWT;
913 * The caller is responsible for maintaining TLB consistency.
916 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
920 boolean_t PTD_updated;
923 mtx_lock_spin(&allpmaps_lock);
924 LIST_FOREACH(pmap, &allpmaps, pm_list) {
925 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
928 pde = pmap_pde(pmap, va);
929 pde_store(pde, newpde);
931 mtx_unlock_spin(&allpmaps_lock);
933 ("pmap_kenter_pde: current page table is not in allpmaps"));
937 * After changing the page size for the specified virtual address in the page
938 * table, flush the corresponding entries from the processor's TLB. Only the
939 * calling processor's TLB is affected.
941 * The calling thread must be pinned to a processor.
944 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
948 if ((newpde & PG_PS) == 0)
949 /* Demotion: flush a specific 2MB page mapping. */
951 else if ((newpde & PG_G) == 0)
953 * Promotion: flush every 4KB page mapping from the TLB
954 * because there are too many to flush individually.
959 * Promotion: flush every 4KB page mapping from the TLB,
960 * including any global (PG_G) mappings.
963 load_cr4(cr4 & ~CR4_PGE);
965 * Although preemption at this point could be detrimental to
966 * performance, it would not lead to an error. PG_G is simply
967 * ignored if CR4.PGE is clear. Moreover, in case this block
968 * is re-entered, the load_cr4() either above or below will
969 * modify CR4.PGE flushing the TLB.
971 load_cr4(cr4 | CR4_PGE);
976 * For SMP, these functions have to use the IPI mechanism for coherence.
978 * N.B.: Before calling any of the following TLB invalidation functions,
979 * the calling processor must ensure that all stores updating a non-
980 * kernel page table are globally performed. Otherwise, another
981 * processor could cache an old, pre-update entry without being
982 * invalidated. This can happen one of two ways: (1) The pmap becomes
983 * active on another processor after its pm_active field is checked by
984 * one of the following functions but before a store updating the page
985 * table is globally performed. (2) The pmap becomes active on another
986 * processor before its pm_active field is checked but due to
987 * speculative loads one of the following functions stills reads the
988 * pmap as inactive on the other processor.
990 * The kernel page table is exempt because its pm_active field is
991 * immutable. The kernel page table is always active on every
995 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1001 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1005 cpuid = PCPU_GET(cpuid);
1006 other_cpus = all_cpus;
1007 CPU_CLR(cpuid, &other_cpus);
1008 if (CPU_ISSET(cpuid, &pmap->pm_active))
1010 CPU_AND(&other_cpus, &pmap->pm_active);
1011 if (!CPU_EMPTY(&other_cpus))
1012 smp_masked_invlpg(other_cpus, va);
1018 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1020 cpuset_t other_cpus;
1025 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1026 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1028 smp_invlpg_range(sva, eva);
1030 cpuid = PCPU_GET(cpuid);
1031 other_cpus = all_cpus;
1032 CPU_CLR(cpuid, &other_cpus);
1033 if (CPU_ISSET(cpuid, &pmap->pm_active))
1034 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1036 CPU_AND(&other_cpus, &pmap->pm_active);
1037 if (!CPU_EMPTY(&other_cpus))
1038 smp_masked_invlpg_range(other_cpus, sva, eva);
1044 pmap_invalidate_all(pmap_t pmap)
1046 cpuset_t other_cpus;
1050 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1054 cpuid = PCPU_GET(cpuid);
1055 other_cpus = all_cpus;
1056 CPU_CLR(cpuid, &other_cpus);
1057 if (CPU_ISSET(cpuid, &pmap->pm_active))
1059 CPU_AND(&other_cpus, &pmap->pm_active);
1060 if (!CPU_EMPTY(&other_cpus))
1061 smp_masked_invltlb(other_cpus);
1067 pmap_invalidate_cache(void)
1077 cpuset_t invalidate; /* processors that invalidate their TLB */
1081 u_int store; /* processor that updates the PDE */
1085 pmap_update_pde_kernel(void *arg)
1087 struct pde_action *act = arg;
1091 if (act->store == PCPU_GET(cpuid)) {
1094 * Elsewhere, this operation requires allpmaps_lock for
1095 * synchronization. Here, it does not because it is being
1096 * performed in the context of an all_cpus rendezvous.
1098 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1099 pde = pmap_pde(pmap, act->va);
1100 pde_store(pde, act->newpde);
1106 pmap_update_pde_user(void *arg)
1108 struct pde_action *act = arg;
1110 if (act->store == PCPU_GET(cpuid))
1111 pde_store(act->pde, act->newpde);
1115 pmap_update_pde_teardown(void *arg)
1117 struct pde_action *act = arg;
1119 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1120 pmap_update_pde_invalidate(act->va, act->newpde);
1124 * Change the page size for the specified virtual address in a way that
1125 * prevents any possibility of the TLB ever having two entries that map the
1126 * same virtual address using different page sizes. This is the recommended
1127 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1128 * machine check exception for a TLB state that is improperly diagnosed as a
1132 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1134 struct pde_action act;
1135 cpuset_t active, other_cpus;
1139 cpuid = PCPU_GET(cpuid);
1140 other_cpus = all_cpus;
1141 CPU_CLR(cpuid, &other_cpus);
1142 if (pmap == kernel_pmap)
1145 active = pmap->pm_active;
1146 if (CPU_OVERLAP(&active, &other_cpus)) {
1148 act.invalidate = active;
1151 act.newpde = newpde;
1152 CPU_SET(cpuid, &active);
1153 smp_rendezvous_cpus(active,
1154 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1155 pmap_update_pde_kernel : pmap_update_pde_user,
1156 pmap_update_pde_teardown, &act);
1158 if (pmap == kernel_pmap)
1159 pmap_kenter_pde(va, newpde);
1161 pde_store(pde, newpde);
1162 if (CPU_ISSET(cpuid, &active))
1163 pmap_update_pde_invalidate(va, newpde);
1169 * Normal, non-SMP, 486+ invalidation functions.
1170 * We inline these within pmap.c for speed.
1173 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1176 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1181 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1185 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1186 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1191 pmap_invalidate_all(pmap_t pmap)
1194 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1199 pmap_invalidate_cache(void)
1206 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1209 if (pmap == kernel_pmap)
1210 pmap_kenter_pde(va, newpde);
1212 pde_store(pde, newpde);
1213 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1214 pmap_update_pde_invalidate(va, newpde);
1218 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1221 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1225 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1227 KASSERT((sva & PAGE_MASK) == 0,
1228 ("pmap_invalidate_cache_range: sva not page-aligned"));
1229 KASSERT((eva & PAGE_MASK) == 0,
1230 ("pmap_invalidate_cache_range: eva not page-aligned"));
1233 if ((cpu_feature & CPUID_SS) != 0 && !force)
1234 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1235 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1236 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1239 * XXX: Some CPUs fault, hang, or trash the local APIC
1240 * registers if we use CLFLUSH on the local APIC
1241 * range. The local APIC is always uncached, so we
1242 * don't need to flush for that range anyway.
1244 if (pmap_kextract(sva) == lapic_paddr)
1248 * Otherwise, do per-cache line flush. Use the sfence
1249 * instruction to insure that previous stores are
1250 * included in the write-back. The processor
1251 * propagates flush to other processors in the cache
1255 for (; sva < eva; sva += cpu_clflush_line_size)
1258 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1259 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1260 if (pmap_kextract(sva) == lapic_paddr)
1263 * Writes are ordered by CLFLUSH on Intel CPUs.
1265 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1267 for (; sva < eva; sva += cpu_clflush_line_size)
1269 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1274 * No targeted cache flush methods are supported by CPU,
1275 * or the supplied range is bigger than 2MB.
1276 * Globally invalidate cache.
1278 pmap_invalidate_cache();
1283 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1287 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1288 (cpu_feature & CPUID_CLFSH) == 0) {
1289 pmap_invalidate_cache();
1291 for (i = 0; i < count; i++)
1292 pmap_flush_page(pages[i]);
1297 * Are we current address space or kernel? N.B. We return FALSE when
1298 * a pmap's page table is in use because a kernel thread is borrowing
1299 * it. The borrowed page table can change spontaneously, making any
1300 * dependence on its continued use subject to a race condition.
1303 pmap_is_current(pmap_t pmap)
1306 return (pmap == kernel_pmap ||
1307 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1308 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1312 * If the given pmap is not the current or kernel pmap, the returned pte must
1313 * be released by passing it to pmap_pte_release().
1316 pmap_pte(pmap_t pmap, vm_offset_t va)
1321 pde = pmap_pde(pmap, va);
1325 /* are we current address space or kernel? */
1326 if (pmap_is_current(pmap))
1327 return (vtopte(va));
1328 mtx_lock(&PMAP2mutex);
1329 newpf = *pde & PG_FRAME;
1330 if ((*PMAP2 & PG_FRAME) != newpf) {
1331 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1332 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1334 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1340 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1343 static __inline void
1344 pmap_pte_release(pt_entry_t *pte)
1347 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1348 mtx_unlock(&PMAP2mutex);
1352 * NB: The sequence of updating a page table followed by accesses to the
1353 * corresponding pages is subject to the situation described in the "AMD64
1354 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1355 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1356 * right after modifying the PTE bits is crucial.
1358 static __inline void
1359 invlcaddr(void *caddr)
1362 invlpg((u_int)caddr);
1366 * Super fast pmap_pte routine best used when scanning
1367 * the pv lists. This eliminates many coarse-grained
1368 * invltlb calls. Note that many of the pv list
1369 * scans are across different pmaps. It is very wasteful
1370 * to do an entire invltlb for checking a single mapping.
1372 * If the given pmap is not the current pmap, pvh_global_lock
1373 * must be held and curthread pinned to a CPU.
1376 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1381 pde = pmap_pde(pmap, va);
1385 /* are we current address space or kernel? */
1386 if (pmap_is_current(pmap))
1387 return (vtopte(va));
1388 rw_assert(&pvh_global_lock, RA_WLOCKED);
1389 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1390 newpf = *pde & PG_FRAME;
1391 if ((*PMAP1 & PG_FRAME) != newpf) {
1392 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1394 PMAP1cpu = PCPU_GET(cpuid);
1400 if (PMAP1cpu != PCPU_GET(cpuid)) {
1401 PMAP1cpu = PCPU_GET(cpuid);
1407 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1413 * Routine: pmap_extract
1415 * Extract the physical page address associated
1416 * with the given map/virtual_address pair.
1419 pmap_extract(pmap_t pmap, vm_offset_t va)
1427 pde = pmap->pm_pdir[va >> PDRSHIFT];
1429 if ((pde & PG_PS) != 0)
1430 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1432 pte = pmap_pte(pmap, va);
1433 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1434 pmap_pte_release(pte);
1442 * Routine: pmap_extract_and_hold
1444 * Atomically extract and hold the physical page
1445 * with the given pmap and virtual address pair
1446 * if that mapping permits the given protection.
1449 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1452 pt_entry_t pte, *ptep;
1460 pde = *pmap_pde(pmap, va);
1463 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1464 if (vm_page_pa_tryrelock(pmap, (pde &
1465 PG_PS_FRAME) | (va & PDRMASK), &pa))
1467 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1472 ptep = pmap_pte(pmap, va);
1474 pmap_pte_release(ptep);
1476 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1477 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1480 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1490 /***************************************************
1491 * Low level mapping routines.....
1492 ***************************************************/
1495 * Add a wired page to the kva.
1496 * Note: not SMP coherent.
1498 * This function may be used before pmap_bootstrap() is called.
1501 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1506 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1509 static __inline void
1510 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1515 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1519 * Remove a page from the kernel pagetables.
1520 * Note: not SMP coherent.
1522 * This function may be used before pmap_bootstrap() is called.
1525 pmap_kremove(vm_offset_t va)
1534 * Used to map a range of physical addresses into kernel
1535 * virtual address space.
1537 * The value passed in '*virt' is a suggested virtual address for
1538 * the mapping. Architectures which can support a direct-mapped
1539 * physical to virtual region can return the appropriate address
1540 * within that region, leaving '*virt' unchanged. Other
1541 * architectures should map the pages starting at '*virt' and
1542 * update '*virt' with the first usable address after the mapped
1546 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1548 vm_offset_t va, sva;
1549 vm_paddr_t superpage_offset;
1554 * Does the physical address range's size and alignment permit at
1555 * least one superpage mapping to be created?
1557 superpage_offset = start & PDRMASK;
1558 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1560 * Increase the starting virtual address so that its alignment
1561 * does not preclude the use of superpage mappings.
1563 if ((va & PDRMASK) < superpage_offset)
1564 va = (va & ~PDRMASK) + superpage_offset;
1565 else if ((va & PDRMASK) > superpage_offset)
1566 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1569 while (start < end) {
1570 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1572 KASSERT((va & PDRMASK) == 0,
1573 ("pmap_map: misaligned va %#x", va));
1574 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1575 pmap_kenter_pde(va, newpde);
1579 pmap_kenter(va, start);
1584 pmap_invalidate_range(kernel_pmap, sva, va);
1591 * Add a list of wired pages to the kva
1592 * this routine is only used for temporary
1593 * kernel mappings that do not need to have
1594 * page modification or references recorded.
1595 * Note that old mappings are simply written
1596 * over. The page *must* be wired.
1597 * Note: SMP coherent. Uses a ranged shootdown IPI.
1600 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1602 pt_entry_t *endpte, oldpte, pa, *pte;
1607 endpte = pte + count;
1608 while (pte < endpte) {
1610 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1611 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1613 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1617 if (__predict_false((oldpte & PG_V) != 0))
1618 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1623 * This routine tears out page mappings from the
1624 * kernel -- it is meant only for temporary mappings.
1625 * Note: SMP coherent. Uses a ranged shootdown IPI.
1628 pmap_qremove(vm_offset_t sva, int count)
1633 while (count-- > 0) {
1637 pmap_invalidate_range(kernel_pmap, sva, va);
1640 /***************************************************
1641 * Page table page management routines.....
1642 ***************************************************/
1643 static __inline void
1644 pmap_free_zero_pages(struct spglist *free)
1648 while ((m = SLIST_FIRST(free)) != NULL) {
1649 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1650 /* Preserve the page's PG_ZERO setting. */
1651 vm_page_free_toq(m);
1656 * Schedule the specified unused page table page to be freed. Specifically,
1657 * add the page to the specified list of pages that will be released to the
1658 * physical memory manager after the TLB has been updated.
1660 static __inline void
1661 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1662 boolean_t set_PG_ZERO)
1666 m->flags |= PG_ZERO;
1668 m->flags &= ~PG_ZERO;
1669 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1673 * Inserts the specified page table page into the specified pmap's collection
1674 * of idle page table pages. Each of a pmap's page table pages is responsible
1675 * for mapping a distinct range of virtual addresses. The pmap's collection is
1676 * ordered by this virtual address range.
1679 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1682 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1683 return (vm_radix_insert(&pmap->pm_root, mpte));
1687 * Looks for a page table page mapping the specified virtual address in the
1688 * specified pmap's collection of idle page table pages. Returns NULL if there
1689 * is no page table page corresponding to the specified virtual address.
1691 static __inline vm_page_t
1692 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1695 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1696 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1700 * Removes the specified page table page from the specified pmap's collection
1701 * of idle page table pages. The specified page table page must be a member of
1702 * the pmap's collection.
1704 static __inline void
1705 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1708 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1709 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1713 * Decrements a page table page's wire count, which is used to record the
1714 * number of valid page table entries within the page. If the wire count
1715 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1716 * page table page was unmapped and FALSE otherwise.
1718 static inline boolean_t
1719 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1723 if (m->wire_count == 0) {
1724 _pmap_unwire_ptp(pmap, m, free);
1731 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1736 * unmap the page table page
1738 pmap->pm_pdir[m->pindex] = 0;
1739 --pmap->pm_stats.resident_count;
1742 * This is a release store so that the ordinary store unmapping
1743 * the page table page is globally performed before TLB shoot-
1746 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1749 * Do an invltlb to make the invalidated mapping
1750 * take effect immediately.
1752 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1753 pmap_invalidate_page(pmap, pteva);
1756 * Put page on a list so that it is released after
1757 * *ALL* TLB shootdown is done
1759 pmap_add_delayed_free_list(m, free, TRUE);
1763 * After removing a page table entry, this routine is used to
1764 * conditionally free the page, and manage the hold/wire counts.
1767 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1772 if (va >= VM_MAXUSER_ADDRESS)
1774 ptepde = *pmap_pde(pmap, va);
1775 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1776 return (pmap_unwire_ptp(pmap, mpte, free));
1780 * Initialize the pmap for the swapper process.
1783 pmap_pinit0(pmap_t pmap)
1786 PMAP_LOCK_INIT(pmap);
1788 * Since the page table directory is shared with the kernel pmap,
1789 * which is already included in the list "allpmaps", this pmap does
1790 * not need to be inserted into that list.
1792 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1793 #if defined(PAE) || defined(PAE_TABLES)
1794 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1796 pmap->pm_root.rt_root = 0;
1797 CPU_ZERO(&pmap->pm_active);
1798 PCPU_SET(curpmap, pmap);
1799 TAILQ_INIT(&pmap->pm_pvchunk);
1800 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1804 * Initialize a preallocated and zeroed pmap structure,
1805 * such as one in a vmspace structure.
1808 pmap_pinit(pmap_t pmap)
1810 vm_page_t m, ptdpg[NPGPTD];
1815 * No need to allocate page table space yet but we do need a valid
1816 * page directory table.
1818 if (pmap->pm_pdir == NULL) {
1819 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1820 if (pmap->pm_pdir == NULL)
1822 #if defined(PAE) || defined(PAE_TABLES)
1823 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1824 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1825 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1826 ("pmap_pinit: pdpt misaligned"));
1827 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1828 ("pmap_pinit: pdpt above 4g"));
1830 pmap->pm_root.rt_root = 0;
1832 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1833 ("pmap_pinit: pmap has reserved page table page(s)"));
1836 * allocate the page directory page(s)
1838 for (i = 0; i < NPGPTD;) {
1839 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1840 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1848 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1850 for (i = 0; i < NPGPTD; i++)
1851 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1852 pagezero(pmap->pm_pdir + (i * NPDEPG));
1854 mtx_lock_spin(&allpmaps_lock);
1855 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1856 /* Copy the kernel page table directory entries. */
1857 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1858 mtx_unlock_spin(&allpmaps_lock);
1860 /* install self-referential address mapping entry(s) */
1861 for (i = 0; i < NPGPTD; i++) {
1862 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1863 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1864 #if defined(PAE) || defined(PAE_TABLES)
1865 pmap->pm_pdpt[i] = pa | PG_V;
1869 CPU_ZERO(&pmap->pm_active);
1870 TAILQ_INIT(&pmap->pm_pvchunk);
1871 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1877 * this routine is called if the page table page is not
1881 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1887 * Allocate a page table page.
1889 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1890 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1891 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1893 rw_wunlock(&pvh_global_lock);
1895 rw_wlock(&pvh_global_lock);
1900 * Indicate the need to retry. While waiting, the page table
1901 * page may have been allocated.
1905 if ((m->flags & PG_ZERO) == 0)
1909 * Map the pagetable page into the process address space, if
1910 * it isn't already there.
1913 pmap->pm_stats.resident_count++;
1915 ptepa = VM_PAGE_TO_PHYS(m);
1916 pmap->pm_pdir[ptepindex] =
1917 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1923 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1930 * Calculate pagetable page index
1932 ptepindex = va >> PDRSHIFT;
1935 * Get the page directory entry
1937 ptepa = pmap->pm_pdir[ptepindex];
1940 * This supports switching from a 4MB page to a
1943 if (ptepa & PG_PS) {
1944 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1945 ptepa = pmap->pm_pdir[ptepindex];
1949 * If the page table page is mapped, we just increment the
1950 * hold count, and activate it.
1953 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1957 * Here if the pte page isn't mapped, or if it has
1960 m = _pmap_allocpte(pmap, ptepindex, flags);
1961 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1968 /***************************************************
1969 * Pmap allocation/deallocation routines.
1970 ***************************************************/
1974 * Deal with a SMP shootdown of other users of the pmap that we are
1975 * trying to dispose of. This can be a bit hairy.
1977 static cpuset_t *lazymask;
1978 static u_int lazyptd;
1979 static volatile u_int lazywait;
1981 void pmap_lazyfix_action(void);
1984 pmap_lazyfix_action(void)
1988 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1990 if (rcr3() == lazyptd)
1991 load_cr3(curpcb->pcb_cr3);
1992 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1993 atomic_store_rel_int(&lazywait, 1);
1997 pmap_lazyfix_self(u_int cpuid)
2000 if (rcr3() == lazyptd)
2001 load_cr3(curpcb->pcb_cr3);
2002 CPU_CLR_ATOMIC(cpuid, lazymask);
2007 pmap_lazyfix(pmap_t pmap)
2009 cpuset_t mymask, mask;
2013 mask = pmap->pm_active;
2014 while (!CPU_EMPTY(&mask)) {
2017 /* Find least significant set bit. */
2018 lsb = CPU_FFS(&mask);
2021 CPU_SETOF(lsb, &mask);
2022 mtx_lock_spin(&smp_ipi_mtx);
2023 #if defined(PAE) || defined(PAE_TABLES)
2024 lazyptd = vtophys(pmap->pm_pdpt);
2026 lazyptd = vtophys(pmap->pm_pdir);
2028 cpuid = PCPU_GET(cpuid);
2030 /* Use a cpuset just for having an easy check. */
2031 CPU_SETOF(cpuid, &mymask);
2032 if (!CPU_CMP(&mask, &mymask)) {
2033 lazymask = &pmap->pm_active;
2034 pmap_lazyfix_self(cpuid);
2036 atomic_store_rel_int((u_int *)&lazymask,
2037 (u_int)&pmap->pm_active);
2038 atomic_store_rel_int(&lazywait, 0);
2039 ipi_selected(mask, IPI_LAZYPMAP);
2040 while (lazywait == 0) {
2046 mtx_unlock_spin(&smp_ipi_mtx);
2048 printf("pmap_lazyfix: spun for 50000000\n");
2049 mask = pmap->pm_active;
2056 * Cleaning up on uniprocessor is easy. For various reasons, we're
2057 * unlikely to have to even execute this code, including the fact
2058 * that the cleanup is deferred until the parent does a wait(2), which
2059 * means that another userland process has run.
2062 pmap_lazyfix(pmap_t pmap)
2066 cr3 = vtophys(pmap->pm_pdir);
2067 if (cr3 == rcr3()) {
2068 load_cr3(curpcb->pcb_cr3);
2069 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2075 * Release any resources held by the given physical map.
2076 * Called when a pmap initialized by pmap_pinit is being released.
2077 * Should only be called if the map contains no valid mappings.
2080 pmap_release(pmap_t pmap)
2082 vm_page_t m, ptdpg[NPGPTD];
2085 KASSERT(pmap->pm_stats.resident_count == 0,
2086 ("pmap_release: pmap resident count %ld != 0",
2087 pmap->pm_stats.resident_count));
2088 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2089 ("pmap_release: pmap has reserved page table page(s)"));
2092 mtx_lock_spin(&allpmaps_lock);
2093 LIST_REMOVE(pmap, pm_list);
2094 mtx_unlock_spin(&allpmaps_lock);
2096 for (i = 0; i < NPGPTD; i++)
2097 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2100 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2101 sizeof(*pmap->pm_pdir));
2103 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2105 for (i = 0; i < NPGPTD; i++) {
2107 #if defined(PAE) || defined(PAE_TABLES)
2108 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2109 ("pmap_release: got wrong ptd page"));
2112 atomic_subtract_int(&cnt.v_wire_count, 1);
2113 vm_page_free_zero(m);
2118 kvm_size(SYSCTL_HANDLER_ARGS)
2120 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2122 return (sysctl_handle_long(oidp, &ksize, 0, req));
2124 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2125 0, 0, kvm_size, "IU", "Size of KVM");
2128 kvm_free(SYSCTL_HANDLER_ARGS)
2130 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2132 return (sysctl_handle_long(oidp, &kfree, 0, req));
2134 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2135 0, 0, kvm_free, "IU", "Amount of KVM free");
2138 * grow the number of kernel page table entries, if needed
2141 pmap_growkernel(vm_offset_t addr)
2143 vm_paddr_t ptppaddr;
2147 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2148 addr = roundup2(addr, NBPDR);
2149 if (addr - 1 >= kernel_map->max_offset)
2150 addr = kernel_map->max_offset;
2151 while (kernel_vm_end < addr) {
2152 if (pdir_pde(PTD, kernel_vm_end)) {
2153 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2154 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2155 kernel_vm_end = kernel_map->max_offset;
2161 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2162 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2165 panic("pmap_growkernel: no memory to grow kernel");
2169 if ((nkpg->flags & PG_ZERO) == 0)
2170 pmap_zero_page(nkpg);
2171 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2172 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2173 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2175 pmap_kenter_pde(kernel_vm_end, newpdir);
2176 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2177 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2178 kernel_vm_end = kernel_map->max_offset;
2185 /***************************************************
2186 * page management routines.
2187 ***************************************************/
2189 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2190 CTASSERT(_NPCM == 11);
2191 CTASSERT(_NPCPV == 336);
2193 static __inline struct pv_chunk *
2194 pv_to_chunk(pv_entry_t pv)
2197 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2200 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2202 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2203 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2205 static const uint32_t pc_freemask[_NPCM] = {
2206 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2207 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2208 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2209 PC_FREE0_9, PC_FREE10
2212 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2213 "Current number of pv entries");
2216 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2218 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2219 "Current number of pv entry chunks");
2220 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2221 "Current number of pv entry chunks allocated");
2222 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2223 "Current number of pv entry chunks frees");
2224 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2225 "Number of times tried to get a chunk page but failed.");
2227 static long pv_entry_frees, pv_entry_allocs;
2228 static int pv_entry_spare;
2230 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2231 "Current number of pv entry frees");
2232 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2233 "Current number of pv entry allocs");
2234 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2235 "Current number of spare pv entries");
2239 * We are in a serious low memory condition. Resort to
2240 * drastic measures to free some pages so we can allocate
2241 * another pv entry chunk.
2244 pmap_pv_reclaim(pmap_t locked_pmap)
2247 struct pv_chunk *pc;
2248 struct md_page *pvh;
2251 pt_entry_t *pte, tpte;
2255 struct spglist free;
2257 int bit, field, freed;
2259 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2263 TAILQ_INIT(&newtail);
2264 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2265 SLIST_EMPTY(&free))) {
2266 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2267 if (pmap != pc->pc_pmap) {
2269 pmap_invalidate_all(pmap);
2270 if (pmap != locked_pmap)
2274 /* Avoid deadlock and lock recursion. */
2275 if (pmap > locked_pmap)
2277 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2279 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2285 * Destroy every non-wired, 4 KB page mapping in the chunk.
2288 for (field = 0; field < _NPCM; field++) {
2289 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2290 inuse != 0; inuse &= ~(1UL << bit)) {
2292 pv = &pc->pc_pventry[field * 32 + bit];
2294 pde = pmap_pde(pmap, va);
2295 if ((*pde & PG_PS) != 0)
2297 pte = pmap_pte(pmap, va);
2299 if ((tpte & PG_W) == 0)
2300 tpte = pte_load_clear(pte);
2301 pmap_pte_release(pte);
2302 if ((tpte & PG_W) != 0)
2305 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2307 if ((tpte & PG_G) != 0)
2308 pmap_invalidate_page(pmap, va);
2309 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2310 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2312 if ((tpte & PG_A) != 0)
2313 vm_page_aflag_set(m, PGA_REFERENCED);
2314 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2315 if (TAILQ_EMPTY(&m->md.pv_list) &&
2316 (m->flags & PG_FICTITIOUS) == 0) {
2317 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2318 if (TAILQ_EMPTY(&pvh->pv_list)) {
2319 vm_page_aflag_clear(m,
2323 pc->pc_map[field] |= 1UL << bit;
2324 pmap_unuse_pt(pmap, va, &free);
2329 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2332 /* Every freed mapping is for a 4 KB page. */
2333 pmap->pm_stats.resident_count -= freed;
2334 PV_STAT(pv_entry_frees += freed);
2335 PV_STAT(pv_entry_spare += freed);
2336 pv_entry_count -= freed;
2337 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2338 for (field = 0; field < _NPCM; field++)
2339 if (pc->pc_map[field] != pc_freemask[field]) {
2340 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2342 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2345 * One freed pv entry in locked_pmap is
2348 if (pmap == locked_pmap)
2352 if (field == _NPCM) {
2353 PV_STAT(pv_entry_spare -= _NPCPV);
2354 PV_STAT(pc_chunk_count--);
2355 PV_STAT(pc_chunk_frees++);
2356 /* Entire chunk is free; return it. */
2357 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2358 pmap_qremove((vm_offset_t)pc, 1);
2359 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2364 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2366 pmap_invalidate_all(pmap);
2367 if (pmap != locked_pmap)
2370 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2371 m_pc = SLIST_FIRST(&free);
2372 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2373 /* Recycle a freed page table page. */
2374 m_pc->wire_count = 1;
2375 atomic_add_int(&cnt.v_wire_count, 1);
2377 pmap_free_zero_pages(&free);
2382 * free the pv_entry back to the free list
2385 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2387 struct pv_chunk *pc;
2388 int idx, field, bit;
2390 rw_assert(&pvh_global_lock, RA_WLOCKED);
2391 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2392 PV_STAT(pv_entry_frees++);
2393 PV_STAT(pv_entry_spare++);
2395 pc = pv_to_chunk(pv);
2396 idx = pv - &pc->pc_pventry[0];
2399 pc->pc_map[field] |= 1ul << bit;
2400 for (idx = 0; idx < _NPCM; idx++)
2401 if (pc->pc_map[idx] != pc_freemask[idx]) {
2403 * 98% of the time, pc is already at the head of the
2404 * list. If it isn't already, move it to the head.
2406 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2408 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2409 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2414 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2419 free_pv_chunk(struct pv_chunk *pc)
2423 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2424 PV_STAT(pv_entry_spare -= _NPCPV);
2425 PV_STAT(pc_chunk_count--);
2426 PV_STAT(pc_chunk_frees++);
2427 /* entire chunk is free, return it */
2428 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2429 pmap_qremove((vm_offset_t)pc, 1);
2430 vm_page_unwire(m, 0);
2432 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2436 * get a new pv_entry, allocating a block from the system
2440 get_pv_entry(pmap_t pmap, boolean_t try)
2442 static const struct timeval printinterval = { 60, 0 };
2443 static struct timeval lastprint;
2446 struct pv_chunk *pc;
2449 rw_assert(&pvh_global_lock, RA_WLOCKED);
2450 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2451 PV_STAT(pv_entry_allocs++);
2453 if (pv_entry_count > pv_entry_high_water)
2454 if (ratecheck(&lastprint, &printinterval))
2455 printf("Approaching the limit on PV entries, consider "
2456 "increasing either the vm.pmap.shpgperproc or the "
2457 "vm.pmap.pv_entry_max tunable.\n");
2459 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2461 for (field = 0; field < _NPCM; field++) {
2462 if (pc->pc_map[field]) {
2463 bit = bsfl(pc->pc_map[field]);
2467 if (field < _NPCM) {
2468 pv = &pc->pc_pventry[field * 32 + bit];
2469 pc->pc_map[field] &= ~(1ul << bit);
2470 /* If this was the last item, move it to tail */
2471 for (field = 0; field < _NPCM; field++)
2472 if (pc->pc_map[field] != 0) {
2473 PV_STAT(pv_entry_spare--);
2474 return (pv); /* not full, return */
2476 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2477 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2478 PV_STAT(pv_entry_spare--);
2483 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2484 * global lock. If "pv_vafree" is currently non-empty, it will
2485 * remain non-empty until pmap_ptelist_alloc() completes.
2487 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2488 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2491 PV_STAT(pc_chunk_tryfail++);
2494 m = pmap_pv_reclaim(pmap);
2498 PV_STAT(pc_chunk_count++);
2499 PV_STAT(pc_chunk_allocs++);
2500 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2501 pmap_qenter((vm_offset_t)pc, &m, 1);
2503 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2504 for (field = 1; field < _NPCM; field++)
2505 pc->pc_map[field] = pc_freemask[field];
2506 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2507 pv = &pc->pc_pventry[0];
2508 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2509 PV_STAT(pv_entry_spare += _NPCPV - 1);
2513 static __inline pv_entry_t
2514 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2518 rw_assert(&pvh_global_lock, RA_WLOCKED);
2519 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2520 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2521 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2529 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2531 struct md_page *pvh;
2533 vm_offset_t va_last;
2536 rw_assert(&pvh_global_lock, RA_WLOCKED);
2537 KASSERT((pa & PDRMASK) == 0,
2538 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2541 * Transfer the 4mpage's pv entry for this mapping to the first
2544 pvh = pa_to_pvh(pa);
2545 va = trunc_4mpage(va);
2546 pv = pmap_pvh_remove(pvh, pmap, va);
2547 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2548 m = PHYS_TO_VM_PAGE(pa);
2549 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2550 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2551 va_last = va + NBPDR - PAGE_SIZE;
2554 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2555 ("pmap_pv_demote_pde: page %p is not managed", m));
2557 pmap_insert_entry(pmap, va, m);
2558 } while (va < va_last);
2562 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2564 struct md_page *pvh;
2566 vm_offset_t va_last;
2569 rw_assert(&pvh_global_lock, RA_WLOCKED);
2570 KASSERT((pa & PDRMASK) == 0,
2571 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2574 * Transfer the first page's pv entry for this mapping to the
2575 * 4mpage's pv list. Aside from avoiding the cost of a call
2576 * to get_pv_entry(), a transfer avoids the possibility that
2577 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2578 * removes one of the mappings that is being promoted.
2580 m = PHYS_TO_VM_PAGE(pa);
2581 va = trunc_4mpage(va);
2582 pv = pmap_pvh_remove(&m->md, pmap, va);
2583 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2584 pvh = pa_to_pvh(pa);
2585 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2586 /* Free the remaining NPTEPG - 1 pv entries. */
2587 va_last = va + NBPDR - PAGE_SIZE;
2591 pmap_pvh_free(&m->md, pmap, va);
2592 } while (va < va_last);
2596 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2600 pv = pmap_pvh_remove(pvh, pmap, va);
2601 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2602 free_pv_entry(pmap, pv);
2606 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2608 struct md_page *pvh;
2610 rw_assert(&pvh_global_lock, RA_WLOCKED);
2611 pmap_pvh_free(&m->md, pmap, va);
2612 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2613 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2614 if (TAILQ_EMPTY(&pvh->pv_list))
2615 vm_page_aflag_clear(m, PGA_WRITEABLE);
2620 * Create a pv entry for page at pa for
2624 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2628 rw_assert(&pvh_global_lock, RA_WLOCKED);
2629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2630 pv = get_pv_entry(pmap, FALSE);
2632 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2636 * Conditionally create a pv entry.
2639 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2643 rw_assert(&pvh_global_lock, RA_WLOCKED);
2644 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2645 if (pv_entry_count < pv_entry_high_water &&
2646 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2648 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2655 * Create the pv entries for each of the pages within a superpage.
2658 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2660 struct md_page *pvh;
2663 rw_assert(&pvh_global_lock, RA_WLOCKED);
2664 if (pv_entry_count < pv_entry_high_water &&
2665 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2667 pvh = pa_to_pvh(pa);
2668 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2675 * Fills a page table page with mappings to consecutive physical pages.
2678 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2682 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2684 newpte += PAGE_SIZE;
2689 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2690 * 2- or 4MB page mapping is invalidated.
2693 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2695 pd_entry_t newpde, oldpde;
2696 pt_entry_t *firstpte, newpte;
2699 struct spglist free;
2702 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2704 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2705 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2706 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2708 pmap_remove_pt_page(pmap, mpte);
2710 KASSERT((oldpde & PG_W) == 0,
2711 ("pmap_demote_pde: page table page for a wired mapping"
2715 * Invalidate the 2- or 4MB page mapping and return
2716 * "failure" if the mapping was never accessed or the
2717 * allocation of the new page table page fails.
2719 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2720 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2721 VM_ALLOC_WIRED)) == NULL) {
2723 sva = trunc_4mpage(va);
2724 pmap_remove_pde(pmap, pde, sva, &free);
2725 pmap_invalidate_range(pmap, sva, sva + NBPDR - 1);
2726 pmap_free_zero_pages(&free);
2727 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2728 " in pmap %p", va, pmap);
2731 if (va < VM_MAXUSER_ADDRESS)
2732 pmap->pm_stats.resident_count++;
2734 mptepa = VM_PAGE_TO_PHYS(mpte);
2737 * If the page mapping is in the kernel's address space, then the
2738 * KPTmap can provide access to the page table page. Otherwise,
2739 * temporarily map the page table page (mpte) into the kernel's
2740 * address space at either PADDR1 or PADDR2.
2743 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2744 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2745 if ((*PMAP1 & PG_FRAME) != mptepa) {
2746 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2748 PMAP1cpu = PCPU_GET(cpuid);
2754 if (PMAP1cpu != PCPU_GET(cpuid)) {
2755 PMAP1cpu = PCPU_GET(cpuid);
2763 mtx_lock(&PMAP2mutex);
2764 if ((*PMAP2 & PG_FRAME) != mptepa) {
2765 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2766 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2770 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2771 KASSERT((oldpde & PG_A) != 0,
2772 ("pmap_demote_pde: oldpde is missing PG_A"));
2773 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2774 ("pmap_demote_pde: oldpde is missing PG_M"));
2775 newpte = oldpde & ~PG_PS;
2776 if ((newpte & PG_PDE_PAT) != 0)
2777 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2780 * If the page table page is new, initialize it.
2782 if (mpte->wire_count == 1) {
2783 mpte->wire_count = NPTEPG;
2784 pmap_fill_ptp(firstpte, newpte);
2786 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2787 ("pmap_demote_pde: firstpte and newpte map different physical"
2791 * If the mapping has changed attributes, update the page table
2794 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2795 pmap_fill_ptp(firstpte, newpte);
2798 * Demote the mapping. This pmap is locked. The old PDE has
2799 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2800 * set. Thus, there is no danger of a race with another
2801 * processor changing the setting of PG_A and/or PG_M between
2802 * the read above and the store below.
2804 if (workaround_erratum383)
2805 pmap_update_pde(pmap, va, pde, newpde);
2806 else if (pmap == kernel_pmap)
2807 pmap_kenter_pde(va, newpde);
2809 pde_store(pde, newpde);
2810 if (firstpte == PADDR2)
2811 mtx_unlock(&PMAP2mutex);
2814 * Invalidate the recursive mapping of the page table page.
2816 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2819 * Demote the pv entry. This depends on the earlier demotion
2820 * of the mapping. Specifically, the (re)creation of a per-
2821 * page pv entry might trigger the execution of pmap_collect(),
2822 * which might reclaim a newly (re)created per-page pv entry
2823 * and destroy the associated mapping. In order to destroy
2824 * the mapping, the PDE must have already changed from mapping
2825 * the 2mpage to referencing the page table page.
2827 if ((oldpde & PG_MANAGED) != 0)
2828 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2830 pmap_pde_demotions++;
2831 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2832 " in pmap %p", va, pmap);
2837 * Removes a 2- or 4MB page mapping from the kernel pmap.
2840 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2846 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2847 mpte = pmap_lookup_pt_page(pmap, va);
2849 panic("pmap_remove_kernel_pde: Missing pt page.");
2851 pmap_remove_pt_page(pmap, mpte);
2852 mptepa = VM_PAGE_TO_PHYS(mpte);
2853 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2856 * Initialize the page table page.
2858 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2861 * Remove the mapping.
2863 if (workaround_erratum383)
2864 pmap_update_pde(pmap, va, pde, newpde);
2866 pmap_kenter_pde(va, newpde);
2869 * Invalidate the recursive mapping of the page table page.
2871 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2875 * pmap_remove_pde: do the things to unmap a superpage in a process
2878 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2879 struct spglist *free)
2881 struct md_page *pvh;
2883 vm_offset_t eva, va;
2886 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2887 KASSERT((sva & PDRMASK) == 0,
2888 ("pmap_remove_pde: sva is not 4mpage aligned"));
2889 oldpde = pte_load_clear(pdq);
2891 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2894 * Machines that don't support invlpg, also don't support
2897 * When workaround_erratum383 is false, a promotion to a 2M/4M
2898 * page mapping does not invalidate the 512/1024 4K page mappings
2899 * from the TLB. Consequently, at this point, the TLB may
2900 * hold both 4K and 2M/4M page mappings. Therefore, the entire
2901 * range of addresses must be invalidated here. In contrast,
2902 * when workaround_erratum383 is true, a promotion does
2903 * invalidate the 512/1024 4K page mappings, and so a single INVLPG
2904 * suffices to invalidate the 2M/4M page mapping.
2906 if ((oldpde & PG_G) != 0) {
2907 if (workaround_erratum383)
2908 pmap_invalidate_page(kernel_pmap, sva);
2910 pmap_invalidate_range(kernel_pmap, sva,
2914 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2915 if (oldpde & PG_MANAGED) {
2916 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2917 pmap_pvh_free(pvh, pmap, sva);
2919 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2920 va < eva; va += PAGE_SIZE, m++) {
2921 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2924 vm_page_aflag_set(m, PGA_REFERENCED);
2925 if (TAILQ_EMPTY(&m->md.pv_list) &&
2926 TAILQ_EMPTY(&pvh->pv_list))
2927 vm_page_aflag_clear(m, PGA_WRITEABLE);
2930 if (pmap == kernel_pmap) {
2931 pmap_remove_kernel_pde(pmap, pdq, sva);
2933 mpte = pmap_lookup_pt_page(pmap, sva);
2935 pmap_remove_pt_page(pmap, mpte);
2936 pmap->pm_stats.resident_count--;
2937 KASSERT(mpte->wire_count == NPTEPG,
2938 ("pmap_remove_pde: pte page wire count error"));
2939 mpte->wire_count = 0;
2940 pmap_add_delayed_free_list(mpte, free, FALSE);
2941 atomic_subtract_int(&cnt.v_wire_count, 1);
2947 * pmap_remove_pte: do the things to unmap a page in a process
2950 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2951 struct spglist *free)
2956 rw_assert(&pvh_global_lock, RA_WLOCKED);
2957 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2958 oldpte = pte_load_clear(ptq);
2959 KASSERT(oldpte != 0,
2960 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2962 pmap->pm_stats.wired_count -= 1;
2964 * Machines that don't support invlpg, also don't support
2968 pmap_invalidate_page(kernel_pmap, va);
2969 pmap->pm_stats.resident_count -= 1;
2970 if (oldpte & PG_MANAGED) {
2971 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2972 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2975 vm_page_aflag_set(m, PGA_REFERENCED);
2976 pmap_remove_entry(pmap, m, va);
2978 return (pmap_unuse_pt(pmap, va, free));
2982 * Remove a single page from a process address space
2985 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2989 rw_assert(&pvh_global_lock, RA_WLOCKED);
2990 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2991 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2992 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2994 pmap_remove_pte(pmap, pte, va, free);
2995 pmap_invalidate_page(pmap, va);
2999 * Remove the given range of addresses from the specified map.
3001 * It is assumed that the start and end are properly
3002 * rounded to the page size.
3005 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3010 struct spglist free;
3014 * Perform an unsynchronized read. This is, however, safe.
3016 if (pmap->pm_stats.resident_count == 0)
3022 rw_wlock(&pvh_global_lock);
3027 * special handling of removing one page. a very
3028 * common operation and easy to short circuit some
3031 if ((sva + PAGE_SIZE == eva) &&
3032 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3033 pmap_remove_page(pmap, sva, &free);
3037 for (; sva < eva; sva = pdnxt) {
3041 * Calculate index for next page table.
3043 pdnxt = (sva + NBPDR) & ~PDRMASK;
3046 if (pmap->pm_stats.resident_count == 0)
3049 pdirindex = sva >> PDRSHIFT;
3050 ptpaddr = pmap->pm_pdir[pdirindex];
3053 * Weed out invalid mappings. Note: we assume that the page
3054 * directory table is always allocated, and in kernel virtual.
3060 * Check for large page.
3062 if ((ptpaddr & PG_PS) != 0) {
3064 * Are we removing the entire large page? If not,
3065 * demote the mapping and fall through.
3067 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3069 * The TLB entry for a PG_G mapping is
3070 * invalidated by pmap_remove_pde().
3072 if ((ptpaddr & PG_G) == 0)
3074 pmap_remove_pde(pmap,
3075 &pmap->pm_pdir[pdirindex], sva, &free);
3077 } else if (!pmap_demote_pde(pmap,
3078 &pmap->pm_pdir[pdirindex], sva)) {
3079 /* The large page mapping was destroyed. */
3085 * Limit our scan to either the end of the va represented
3086 * by the current page table page, or to the end of the
3087 * range being removed.
3092 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3098 * The TLB entry for a PG_G mapping is invalidated
3099 * by pmap_remove_pte().
3101 if ((*pte & PG_G) == 0)
3103 if (pmap_remove_pte(pmap, pte, sva, &free))
3110 pmap_invalidate_all(pmap);
3111 rw_wunlock(&pvh_global_lock);
3113 pmap_free_zero_pages(&free);
3117 * Routine: pmap_remove_all
3119 * Removes this physical page from
3120 * all physical maps in which it resides.
3121 * Reflects back modify bits to the pager.
3124 * Original versions of this routine were very
3125 * inefficient because they iteratively called
3126 * pmap_remove (slow...)
3130 pmap_remove_all(vm_page_t m)
3132 struct md_page *pvh;
3135 pt_entry_t *pte, tpte;
3138 struct spglist free;
3140 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3141 ("pmap_remove_all: page %p is not managed", m));
3143 rw_wlock(&pvh_global_lock);
3145 if ((m->flags & PG_FICTITIOUS) != 0)
3146 goto small_mappings;
3147 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3148 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3152 pde = pmap_pde(pmap, va);
3153 (void)pmap_demote_pde(pmap, pde, va);
3157 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3160 pmap->pm_stats.resident_count--;
3161 pde = pmap_pde(pmap, pv->pv_va);
3162 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3163 " a 4mpage in page %p's pv list", m));
3164 pte = pmap_pte_quick(pmap, pv->pv_va);
3165 tpte = pte_load_clear(pte);
3166 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3169 pmap->pm_stats.wired_count--;
3171 vm_page_aflag_set(m, PGA_REFERENCED);
3174 * Update the vm_page_t clean and reference bits.
3176 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3178 pmap_unuse_pt(pmap, pv->pv_va, &free);
3179 pmap_invalidate_page(pmap, pv->pv_va);
3180 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3181 free_pv_entry(pmap, pv);
3184 vm_page_aflag_clear(m, PGA_WRITEABLE);
3186 rw_wunlock(&pvh_global_lock);
3187 pmap_free_zero_pages(&free);
3191 * pmap_protect_pde: do the things to protect a 4mpage in a process
3194 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3196 pd_entry_t newpde, oldpde;
3197 vm_offset_t eva, va;
3199 boolean_t anychanged;
3201 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3202 KASSERT((sva & PDRMASK) == 0,
3203 ("pmap_protect_pde: sva is not 4mpage aligned"));
3206 oldpde = newpde = *pde;
3207 if (oldpde & PG_MANAGED) {
3209 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3210 va < eva; va += PAGE_SIZE, m++)
3211 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3214 if ((prot & VM_PROT_WRITE) == 0)
3215 newpde &= ~(PG_RW | PG_M);
3216 #if defined(PAE) || defined(PAE_TABLES)
3217 if ((prot & VM_PROT_EXECUTE) == 0)
3220 if (newpde != oldpde) {
3221 if (!pde_cmpset(pde, oldpde, newpde))
3223 if (oldpde & PG_G) {
3224 /* See pmap_remove_pde() for explanation. */
3225 if (workaround_erratum383)
3226 pmap_invalidate_page(kernel_pmap, sva);
3228 pmap_invalidate_range(kernel_pmap, sva,
3233 return (anychanged);
3237 * Set the physical protection on the
3238 * specified range of this map as requested.
3241 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3246 boolean_t anychanged, pv_lists_locked;
3248 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3249 if (prot == VM_PROT_NONE) {
3250 pmap_remove(pmap, sva, eva);
3254 #if defined(PAE) || defined(PAE_TABLES)
3255 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3256 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3259 if (prot & VM_PROT_WRITE)
3263 if (pmap_is_current(pmap))
3264 pv_lists_locked = FALSE;
3266 pv_lists_locked = TRUE;
3268 rw_wlock(&pvh_global_lock);
3274 for (; sva < eva; sva = pdnxt) {
3275 pt_entry_t obits, pbits;
3278 pdnxt = (sva + NBPDR) & ~PDRMASK;
3282 pdirindex = sva >> PDRSHIFT;
3283 ptpaddr = pmap->pm_pdir[pdirindex];
3286 * Weed out invalid mappings. Note: we assume that the page
3287 * directory table is always allocated, and in kernel virtual.
3293 * Check for large page.
3295 if ((ptpaddr & PG_PS) != 0) {
3297 * Are we protecting the entire large page? If not,
3298 * demote the mapping and fall through.
3300 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3302 * The TLB entry for a PG_G mapping is
3303 * invalidated by pmap_protect_pde().
3305 if (pmap_protect_pde(pmap,
3306 &pmap->pm_pdir[pdirindex], sva, prot))
3310 if (!pv_lists_locked) {
3311 pv_lists_locked = TRUE;
3312 if (!rw_try_wlock(&pvh_global_lock)) {
3314 pmap_invalidate_all(
3321 if (!pmap_demote_pde(pmap,
3322 &pmap->pm_pdir[pdirindex], sva)) {
3324 * The large page mapping was
3335 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3341 * Regardless of whether a pte is 32 or 64 bits in
3342 * size, PG_RW, PG_A, and PG_M are among the least
3343 * significant 32 bits.
3345 obits = pbits = *pte;
3346 if ((pbits & PG_V) == 0)
3349 if ((prot & VM_PROT_WRITE) == 0) {
3350 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3351 (PG_MANAGED | PG_M | PG_RW)) {
3352 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3355 pbits &= ~(PG_RW | PG_M);
3357 #if defined(PAE) || defined(PAE_TABLES)
3358 if ((prot & VM_PROT_EXECUTE) == 0)
3362 if (pbits != obits) {
3363 #if defined(PAE) || defined(PAE_TABLES)
3364 if (!atomic_cmpset_64(pte, obits, pbits))
3367 if (!atomic_cmpset_int((u_int *)pte, obits,
3372 pmap_invalidate_page(pmap, sva);
3379 pmap_invalidate_all(pmap);
3380 if (pv_lists_locked) {
3382 rw_wunlock(&pvh_global_lock);
3388 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3389 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3390 * For promotion to occur, two conditions must be met: (1) the 4KB page
3391 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3392 * mappings must have identical characteristics.
3394 * Managed (PG_MANAGED) mappings within the kernel address space are not
3395 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3396 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3400 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3403 pt_entry_t *firstpte, oldpte, pa, *pte;
3404 vm_offset_t oldpteva;
3407 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3410 * Examine the first PTE in the specified PTP. Abort if this PTE is
3411 * either invalid, unused, or does not map the first 4KB physical page
3412 * within a 2- or 4MB page.
3414 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3417 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3418 pmap_pde_p_failures++;
3419 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3420 " in pmap %p", va, pmap);
3423 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3424 pmap_pde_p_failures++;
3425 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3426 " in pmap %p", va, pmap);
3429 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3431 * When PG_M is already clear, PG_RW can be cleared without
3432 * a TLB invalidation.
3434 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3441 * Examine each of the other PTEs in the specified PTP. Abort if this
3442 * PTE maps an unexpected 4KB physical page or does not have identical
3443 * characteristics to the first PTE.
3445 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3446 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3449 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3450 pmap_pde_p_failures++;
3451 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3452 " in pmap %p", va, pmap);
3455 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3457 * When PG_M is already clear, PG_RW can be cleared
3458 * without a TLB invalidation.
3460 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3464 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3466 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3467 " in pmap %p", oldpteva, pmap);
3469 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3470 pmap_pde_p_failures++;
3471 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3472 " in pmap %p", va, pmap);
3479 * Save the page table page in its current state until the PDE
3480 * mapping the superpage is demoted by pmap_demote_pde() or
3481 * destroyed by pmap_remove_pde().
3483 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3484 KASSERT(mpte >= vm_page_array &&
3485 mpte < &vm_page_array[vm_page_array_size],
3486 ("pmap_promote_pde: page table page is out of range"));
3487 KASSERT(mpte->pindex == va >> PDRSHIFT,
3488 ("pmap_promote_pde: page table page's pindex is wrong"));
3489 if (pmap_insert_pt_page(pmap, mpte)) {
3490 pmap_pde_p_failures++;
3492 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3498 * Promote the pv entries.
3500 if ((newpde & PG_MANAGED) != 0)
3501 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3504 * Propagate the PAT index to its proper position.
3506 if ((newpde & PG_PTE_PAT) != 0)
3507 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3510 * Map the superpage.
3512 if (workaround_erratum383)
3513 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3514 else if (pmap == kernel_pmap)
3515 pmap_kenter_pde(va, PG_PS | newpde);
3517 pde_store(pde, PG_PS | newpde);
3519 pmap_pde_promotions++;
3520 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3521 " in pmap %p", va, pmap);
3525 * Insert the given physical page (p) at
3526 * the specified virtual address (v) in the
3527 * target physical map with the protection requested.
3529 * If specified, the page will be wired down, meaning
3530 * that the related pte can not be reclaimed.
3532 * NB: This is the only routine which MAY NOT lazy-evaluate
3533 * or lose information. That is, this routine must actually
3534 * insert this page into the given map NOW.
3537 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3538 u_int flags, int8_t psind)
3542 pt_entry_t newpte, origpte;
3546 boolean_t invlva, wired;
3548 va = trunc_page(va);
3550 wired = (flags & PMAP_ENTER_WIRED) != 0;
3552 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3553 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3554 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3556 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3557 VM_OBJECT_ASSERT_LOCKED(m->object);
3559 rw_wlock(&pvh_global_lock);
3564 * In the case that a page table page is not
3565 * resident, we are creating it here.
3567 if (va < VM_MAXUSER_ADDRESS) {
3568 mpte = pmap_allocpte(pmap, va, flags);
3570 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3571 ("pmap_allocpte failed with sleep allowed"));
3573 rw_wunlock(&pvh_global_lock);
3575 return (KERN_RESOURCE_SHORTAGE);
3579 pde = pmap_pde(pmap, va);
3580 if ((*pde & PG_PS) != 0)
3581 panic("pmap_enter: attempted pmap_enter on 4MB page");
3582 pte = pmap_pte_quick(pmap, va);
3585 * Page Directory table entry not valid, we need a new PT page
3588 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3589 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3592 pa = VM_PAGE_TO_PHYS(m);
3595 opa = origpte & PG_FRAME;
3598 * Mapping has not changed, must be protection or wiring change.
3600 if (origpte && (opa == pa)) {
3602 * Wiring change, just update stats. We don't worry about
3603 * wiring PT pages as they remain resident as long as there
3604 * are valid mappings in them. Hence, if a user page is wired,
3605 * the PT page will be also.
3607 if (wired && ((origpte & PG_W) == 0))
3608 pmap->pm_stats.wired_count++;
3609 else if (!wired && (origpte & PG_W))
3610 pmap->pm_stats.wired_count--;
3613 * Remove extra pte reference
3618 if (origpte & PG_MANAGED) {
3628 * Mapping has changed, invalidate old range and fall through to
3629 * handle validating new mapping.
3633 pmap->pm_stats.wired_count--;
3634 if (origpte & PG_MANAGED) {
3635 om = PHYS_TO_VM_PAGE(opa);
3636 pv = pmap_pvh_remove(&om->md, pmap, va);
3640 KASSERT(mpte->wire_count > 0,
3641 ("pmap_enter: missing reference to page table page,"
3645 pmap->pm_stats.resident_count++;
3648 * Enter on the PV list if part of our managed memory.
3650 if ((m->oflags & VPO_UNMANAGED) == 0) {
3651 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3652 ("pmap_enter: managed mapping within the clean submap"));
3654 pv = get_pv_entry(pmap, FALSE);
3656 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3658 } else if (pv != NULL)
3659 free_pv_entry(pmap, pv);
3662 * Increment counters
3665 pmap->pm_stats.wired_count++;
3669 * Now validate mapping with desired protection/wiring.
3671 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3672 if ((prot & VM_PROT_WRITE) != 0) {
3674 if ((newpte & PG_MANAGED) != 0)
3675 vm_page_aflag_set(m, PGA_WRITEABLE);
3677 #if defined(PAE) || defined(PAE_TABLES)
3678 if ((prot & VM_PROT_EXECUTE) == 0)
3683 if (va < VM_MAXUSER_ADDRESS)
3685 if (pmap == kernel_pmap)
3689 * if the mapping or permission bits are different, we need
3690 * to update the pte.
3692 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3694 if ((flags & VM_PROT_WRITE) != 0)
3696 if (origpte & PG_V) {
3698 origpte = pte_load_store(pte, newpte);
3699 if (origpte & PG_A) {
3700 if (origpte & PG_MANAGED)
3701 vm_page_aflag_set(om, PGA_REFERENCED);
3702 if (opa != VM_PAGE_TO_PHYS(m))
3704 #if defined(PAE) || defined(PAE_TABLES)
3705 if ((origpte & PG_NX) == 0 &&
3706 (newpte & PG_NX) != 0)
3710 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3711 if ((origpte & PG_MANAGED) != 0)
3713 if ((prot & VM_PROT_WRITE) == 0)
3716 if ((origpte & PG_MANAGED) != 0 &&
3717 TAILQ_EMPTY(&om->md.pv_list) &&
3718 ((om->flags & PG_FICTITIOUS) != 0 ||
3719 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3720 vm_page_aflag_clear(om, PGA_WRITEABLE);
3722 pmap_invalidate_page(pmap, va);
3724 pte_store(pte, newpte);
3728 * If both the page table page and the reservation are fully
3729 * populated, then attempt promotion.
3731 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3732 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3733 vm_reserv_level_iffullpop(m) == 0)
3734 pmap_promote_pde(pmap, pde, va);
3737 rw_wunlock(&pvh_global_lock);
3739 return (KERN_SUCCESS);
3743 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3744 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3745 * blocking, (2) a mapping already exists at the specified virtual address, or
3746 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3749 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3751 pd_entry_t *pde, newpde;
3753 rw_assert(&pvh_global_lock, RA_WLOCKED);
3754 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3755 pde = pmap_pde(pmap, va);
3757 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3758 " in pmap %p", va, pmap);
3761 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3763 if ((m->oflags & VPO_UNMANAGED) == 0) {
3764 newpde |= PG_MANAGED;
3767 * Abort this mapping if its PV entry could not be created.
3769 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3770 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3771 " in pmap %p", va, pmap);
3775 #if defined(PAE) || defined(PAE_TABLES)
3776 if ((prot & VM_PROT_EXECUTE) == 0)
3779 if (va < VM_MAXUSER_ADDRESS)
3783 * Increment counters.
3785 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3788 * Map the superpage.
3790 pde_store(pde, newpde);
3792 pmap_pde_mappings++;
3793 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3794 " in pmap %p", va, pmap);
3799 * Maps a sequence of resident pages belonging to the same object.
3800 * The sequence begins with the given page m_start. This page is
3801 * mapped at the given virtual address start. Each subsequent page is
3802 * mapped at a virtual address that is offset from start by the same
3803 * amount as the page is offset from m_start within the object. The
3804 * last page in the sequence is the page with the largest offset from
3805 * m_start that can be mapped at a virtual address less than the given
3806 * virtual address end. Not every virtual page between start and end
3807 * is mapped; only those for which a resident page exists with the
3808 * corresponding offset from m_start are mapped.
3811 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3812 vm_page_t m_start, vm_prot_t prot)
3816 vm_pindex_t diff, psize;
3818 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3820 psize = atop(end - start);
3823 rw_wlock(&pvh_global_lock);
3825 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3826 va = start + ptoa(diff);
3827 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3828 m->psind == 1 && pg_ps_enabled &&
3829 pmap_enter_pde(pmap, va, m, prot))
3830 m = &m[NBPDR / PAGE_SIZE - 1];
3832 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3834 m = TAILQ_NEXT(m, listq);
3836 rw_wunlock(&pvh_global_lock);
3841 * this code makes some *MAJOR* assumptions:
3842 * 1. Current pmap & pmap exists.
3845 * 4. No page table pages.
3846 * but is *MUCH* faster than pmap_enter...
3850 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3853 rw_wlock(&pvh_global_lock);
3855 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3856 rw_wunlock(&pvh_global_lock);
3861 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3862 vm_prot_t prot, vm_page_t mpte)
3866 struct spglist free;
3868 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3869 (m->oflags & VPO_UNMANAGED) != 0,
3870 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3871 rw_assert(&pvh_global_lock, RA_WLOCKED);
3872 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3875 * In the case that a page table page is not
3876 * resident, we are creating it here.
3878 if (va < VM_MAXUSER_ADDRESS) {
3883 * Calculate pagetable page index
3885 ptepindex = va >> PDRSHIFT;
3886 if (mpte && (mpte->pindex == ptepindex)) {
3890 * Get the page directory entry
3892 ptepa = pmap->pm_pdir[ptepindex];
3895 * If the page table page is mapped, we just increment
3896 * the hold count, and activate it.
3901 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3904 mpte = _pmap_allocpte(pmap, ptepindex,
3905 PMAP_ENTER_NOSLEEP);
3915 * This call to vtopte makes the assumption that we are
3916 * entering the page into the current pmap. In order to support
3917 * quick entry into any pmap, one would likely use pmap_pte_quick.
3918 * But that isn't as quick as vtopte.
3930 * Enter on the PV list if part of our managed memory.
3932 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3933 !pmap_try_insert_pv_entry(pmap, va, m)) {
3936 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3937 pmap_invalidate_page(pmap, va);
3938 pmap_free_zero_pages(&free);
3947 * Increment counters
3949 pmap->pm_stats.resident_count++;
3951 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3952 #if defined(PAE) || defined(PAE_TABLES)
3953 if ((prot & VM_PROT_EXECUTE) == 0)
3958 * Now validate mapping with RO protection
3960 if ((m->oflags & VPO_UNMANAGED) != 0)
3961 pte_store(pte, pa | PG_V | PG_U);
3963 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3968 * Make a temporary mapping for a physical address. This is only intended
3969 * to be used for panic dumps.
3972 pmap_kenter_temporary(vm_paddr_t pa, int i)
3976 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3977 pmap_kenter(va, pa);
3979 return ((void *)crashdumpmap);
3983 * This code maps large physical mmap regions into the
3984 * processor address space. Note that some shortcuts
3985 * are taken, but the code works.
3988 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3989 vm_pindex_t pindex, vm_size_t size)
3992 vm_paddr_t pa, ptepa;
3996 VM_OBJECT_ASSERT_WLOCKED(object);
3997 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3998 ("pmap_object_init_pt: non-device object"));
4000 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4001 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4003 p = vm_page_lookup(object, pindex);
4004 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4005 ("pmap_object_init_pt: invalid page %p", p));
4006 pat_mode = p->md.pat_mode;
4009 * Abort the mapping if the first page is not physically
4010 * aligned to a 2/4MB page boundary.
4012 ptepa = VM_PAGE_TO_PHYS(p);
4013 if (ptepa & (NBPDR - 1))
4017 * Skip the first page. Abort the mapping if the rest of
4018 * the pages are not physically contiguous or have differing
4019 * memory attributes.
4021 p = TAILQ_NEXT(p, listq);
4022 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4024 KASSERT(p->valid == VM_PAGE_BITS_ALL,
4025 ("pmap_object_init_pt: invalid page %p", p));
4026 if (pa != VM_PAGE_TO_PHYS(p) ||
4027 pat_mode != p->md.pat_mode)
4029 p = TAILQ_NEXT(p, listq);
4033 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4034 * "size" is a multiple of 2/4M, adding the PAT setting to
4035 * "pa" will not affect the termination of this loop.
4038 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
4039 size; pa += NBPDR) {
4040 pde = pmap_pde(pmap, addr);
4042 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4043 PG_U | PG_RW | PG_V);
4044 pmap->pm_stats.resident_count += NBPDR /
4046 pmap_pde_mappings++;
4048 /* Else continue on if the PDE is already valid. */
4056 * Clear the wired attribute from the mappings for the specified range of
4057 * addresses in the given pmap. Every valid mapping within that range
4058 * must have the wired attribute set. In contrast, invalid mappings
4059 * cannot have the wired attribute set, so they are ignored.
4061 * The wired attribute of the page table entry is not a hardware feature,
4062 * so there is no need to invalidate any TLB entries.
4065 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4070 boolean_t pv_lists_locked;
4072 if (pmap_is_current(pmap))
4073 pv_lists_locked = FALSE;
4075 pv_lists_locked = TRUE;
4077 rw_wlock(&pvh_global_lock);
4081 for (; sva < eva; sva = pdnxt) {
4082 pdnxt = (sva + NBPDR) & ~PDRMASK;
4085 pde = pmap_pde(pmap, sva);
4086 if ((*pde & PG_V) == 0)
4088 if ((*pde & PG_PS) != 0) {
4089 if ((*pde & PG_W) == 0)
4090 panic("pmap_unwire: pde %#jx is missing PG_W",
4094 * Are we unwiring the entire large page? If not,
4095 * demote the mapping and fall through.
4097 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4099 * Regardless of whether a pde (or pte) is 32
4100 * or 64 bits in size, PG_W is among the least
4101 * significant 32 bits.
4103 atomic_clear_int((u_int *)pde, PG_W);
4104 pmap->pm_stats.wired_count -= NBPDR /
4108 if (!pv_lists_locked) {
4109 pv_lists_locked = TRUE;
4110 if (!rw_try_wlock(&pvh_global_lock)) {
4117 if (!pmap_demote_pde(pmap, pde, sva))
4118 panic("pmap_unwire: demotion failed");
4123 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4125 if ((*pte & PG_V) == 0)
4127 if ((*pte & PG_W) == 0)
4128 panic("pmap_unwire: pte %#jx is missing PG_W",
4132 * PG_W must be cleared atomically. Although the pmap
4133 * lock synchronizes access to PG_W, another processor
4134 * could be setting PG_M and/or PG_A concurrently.
4136 * PG_W is among the least significant 32 bits.
4138 atomic_clear_int((u_int *)pte, PG_W);
4139 pmap->pm_stats.wired_count--;
4142 if (pv_lists_locked) {
4144 rw_wunlock(&pvh_global_lock);
4151 * Copy the range specified by src_addr/len
4152 * from the source map to the range dst_addr/len
4153 * in the destination map.
4155 * This routine is only advisory and need not do anything.
4159 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4160 vm_offset_t src_addr)
4162 struct spglist free;
4164 vm_offset_t end_addr = src_addr + len;
4167 if (dst_addr != src_addr)
4170 if (!pmap_is_current(src_pmap))
4173 rw_wlock(&pvh_global_lock);
4174 if (dst_pmap < src_pmap) {
4175 PMAP_LOCK(dst_pmap);
4176 PMAP_LOCK(src_pmap);
4178 PMAP_LOCK(src_pmap);
4179 PMAP_LOCK(dst_pmap);
4182 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4183 pt_entry_t *src_pte, *dst_pte;
4184 vm_page_t dstmpte, srcmpte;
4185 pd_entry_t srcptepaddr;
4188 KASSERT(addr < UPT_MIN_ADDRESS,
4189 ("pmap_copy: invalid to pmap_copy page tables"));
4191 pdnxt = (addr + NBPDR) & ~PDRMASK;
4194 ptepindex = addr >> PDRSHIFT;
4196 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4197 if (srcptepaddr == 0)
4200 if (srcptepaddr & PG_PS) {
4201 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4203 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4204 ((srcptepaddr & PG_MANAGED) == 0 ||
4205 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4207 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4209 dst_pmap->pm_stats.resident_count +=
4215 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4216 KASSERT(srcmpte->wire_count > 0,
4217 ("pmap_copy: source page table page is unused"));
4219 if (pdnxt > end_addr)
4222 src_pte = vtopte(addr);
4223 while (addr < pdnxt) {
4227 * we only virtual copy managed pages
4229 if ((ptetemp & PG_MANAGED) != 0) {
4230 dstmpte = pmap_allocpte(dst_pmap, addr,
4231 PMAP_ENTER_NOSLEEP);
4232 if (dstmpte == NULL)
4234 dst_pte = pmap_pte_quick(dst_pmap, addr);
4235 if (*dst_pte == 0 &&
4236 pmap_try_insert_pv_entry(dst_pmap, addr,
4237 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4239 * Clear the wired, modified, and
4240 * accessed (referenced) bits
4243 *dst_pte = ptetemp & ~(PG_W | PG_M |
4245 dst_pmap->pm_stats.resident_count++;
4248 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4250 pmap_invalidate_page(dst_pmap,
4252 pmap_free_zero_pages(&free);
4256 if (dstmpte->wire_count >= srcmpte->wire_count)
4265 rw_wunlock(&pvh_global_lock);
4266 PMAP_UNLOCK(src_pmap);
4267 PMAP_UNLOCK(dst_pmap);
4270 static __inline void
4271 pagezero(void *page)
4273 #if defined(I686_CPU)
4274 if (cpu_class == CPUCLASS_686) {
4275 #if defined(CPU_ENABLE_SSE)
4276 if (cpu_feature & CPUID_SSE2)
4277 sse2_pagezero(page);
4280 i686_pagezero(page);
4283 bzero(page, PAGE_SIZE);
4287 * pmap_zero_page zeros the specified hardware page by mapping
4288 * the page into KVM and using bzero to clear its contents.
4291 pmap_zero_page(vm_page_t m)
4293 struct sysmaps *sysmaps;
4295 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4296 mtx_lock(&sysmaps->lock);
4297 if (*sysmaps->CMAP2)
4298 panic("pmap_zero_page: CMAP2 busy");
4300 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4301 pmap_cache_bits(m->md.pat_mode, 0);
4302 invlcaddr(sysmaps->CADDR2);
4303 pagezero(sysmaps->CADDR2);
4304 *sysmaps->CMAP2 = 0;
4306 mtx_unlock(&sysmaps->lock);
4310 * pmap_zero_page_area zeros the specified hardware page by mapping
4311 * the page into KVM and using bzero to clear its contents.
4313 * off and size may not cover an area beyond a single hardware page.
4316 pmap_zero_page_area(vm_page_t m, int off, int size)
4318 struct sysmaps *sysmaps;
4320 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4321 mtx_lock(&sysmaps->lock);
4322 if (*sysmaps->CMAP2)
4323 panic("pmap_zero_page_area: CMAP2 busy");
4325 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4326 pmap_cache_bits(m->md.pat_mode, 0);
4327 invlcaddr(sysmaps->CADDR2);
4328 if (off == 0 && size == PAGE_SIZE)
4329 pagezero(sysmaps->CADDR2);
4331 bzero((char *)sysmaps->CADDR2 + off, size);
4332 *sysmaps->CMAP2 = 0;
4334 mtx_unlock(&sysmaps->lock);
4338 * pmap_zero_page_idle zeros the specified hardware page by mapping
4339 * the page into KVM and using bzero to clear its contents. This
4340 * is intended to be called from the vm_pagezero process only and
4344 pmap_zero_page_idle(vm_page_t m)
4348 panic("pmap_zero_page_idle: CMAP3 busy");
4350 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4351 pmap_cache_bits(m->md.pat_mode, 0);
4359 * pmap_copy_page copies the specified (machine independent)
4360 * page by mapping the page into virtual memory and using
4361 * bcopy to copy the page, one machine dependent page at a
4365 pmap_copy_page(vm_page_t src, vm_page_t dst)
4367 struct sysmaps *sysmaps;
4369 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4370 mtx_lock(&sysmaps->lock);
4371 if (*sysmaps->CMAP1)
4372 panic("pmap_copy_page: CMAP1 busy");
4373 if (*sysmaps->CMAP2)
4374 panic("pmap_copy_page: CMAP2 busy");
4376 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4377 pmap_cache_bits(src->md.pat_mode, 0);
4378 invlcaddr(sysmaps->CADDR1);
4379 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4380 pmap_cache_bits(dst->md.pat_mode, 0);
4381 invlcaddr(sysmaps->CADDR2);
4382 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4383 *sysmaps->CMAP1 = 0;
4384 *sysmaps->CMAP2 = 0;
4386 mtx_unlock(&sysmaps->lock);
4389 int unmapped_buf_allowed = 1;
4392 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4393 vm_offset_t b_offset, int xfersize)
4395 struct sysmaps *sysmaps;
4396 vm_page_t a_pg, b_pg;
4398 vm_offset_t a_pg_offset, b_pg_offset;
4401 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4402 mtx_lock(&sysmaps->lock);
4403 if (*sysmaps->CMAP1 != 0)
4404 panic("pmap_copy_pages: CMAP1 busy");
4405 if (*sysmaps->CMAP2 != 0)
4406 panic("pmap_copy_pages: CMAP2 busy");
4408 while (xfersize > 0) {
4409 a_pg = ma[a_offset >> PAGE_SHIFT];
4410 a_pg_offset = a_offset & PAGE_MASK;
4411 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4412 b_pg = mb[b_offset >> PAGE_SHIFT];
4413 b_pg_offset = b_offset & PAGE_MASK;
4414 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4415 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4416 pmap_cache_bits(a_pg->md.pat_mode, 0);
4417 invlcaddr(sysmaps->CADDR1);
4418 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4419 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4420 invlcaddr(sysmaps->CADDR2);
4421 a_cp = sysmaps->CADDR1 + a_pg_offset;
4422 b_cp = sysmaps->CADDR2 + b_pg_offset;
4423 bcopy(a_cp, b_cp, cnt);
4428 *sysmaps->CMAP1 = 0;
4429 *sysmaps->CMAP2 = 0;
4431 mtx_unlock(&sysmaps->lock);
4435 * Returns true if the pmap's pv is one of the first
4436 * 16 pvs linked to from this page. This count may
4437 * be changed upwards or downwards in the future; it
4438 * is only necessary that true be returned for a small
4439 * subset of pmaps for proper page aging.
4442 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4444 struct md_page *pvh;
4449 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4450 ("pmap_page_exists_quick: page %p is not managed", m));
4452 rw_wlock(&pvh_global_lock);
4453 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4454 if (PV_PMAP(pv) == pmap) {
4462 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4463 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4464 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4465 if (PV_PMAP(pv) == pmap) {
4474 rw_wunlock(&pvh_global_lock);
4479 * pmap_page_wired_mappings:
4481 * Return the number of managed mappings to the given physical page
4485 pmap_page_wired_mappings(vm_page_t m)
4490 if ((m->oflags & VPO_UNMANAGED) != 0)
4492 rw_wlock(&pvh_global_lock);
4493 count = pmap_pvh_wired_mappings(&m->md, count);
4494 if ((m->flags & PG_FICTITIOUS) == 0) {
4495 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4498 rw_wunlock(&pvh_global_lock);
4503 * pmap_pvh_wired_mappings:
4505 * Return the updated number "count" of managed mappings that are wired.
4508 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4514 rw_assert(&pvh_global_lock, RA_WLOCKED);
4516 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4519 pte = pmap_pte_quick(pmap, pv->pv_va);
4520 if ((*pte & PG_W) != 0)
4529 * Returns TRUE if the given page is mapped individually or as part of
4530 * a 4mpage. Otherwise, returns FALSE.
4533 pmap_page_is_mapped(vm_page_t m)
4537 if ((m->oflags & VPO_UNMANAGED) != 0)
4539 rw_wlock(&pvh_global_lock);
4540 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4541 ((m->flags & PG_FICTITIOUS) == 0 &&
4542 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4543 rw_wunlock(&pvh_global_lock);
4548 * Remove all pages from specified address space
4549 * this aids process exit speeds. Also, this code
4550 * is special cased for current process only, but
4551 * can have the more generic (and slightly slower)
4552 * mode enabled. This is much faster than pmap_remove
4553 * in the case of running down an entire address space.
4556 pmap_remove_pages(pmap_t pmap)
4558 pt_entry_t *pte, tpte;
4559 vm_page_t m, mpte, mt;
4561 struct md_page *pvh;
4562 struct pv_chunk *pc, *npc;
4563 struct spglist free;
4566 uint32_t inuse, bitmask;
4569 if (pmap != PCPU_GET(curpmap)) {
4570 printf("warning: pmap_remove_pages called with non-current pmap\n");
4574 rw_wlock(&pvh_global_lock);
4577 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4578 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4581 for (field = 0; field < _NPCM; field++) {
4582 inuse = ~pc->pc_map[field] & pc_freemask[field];
4583 while (inuse != 0) {
4585 bitmask = 1UL << bit;
4586 idx = field * 32 + bit;
4587 pv = &pc->pc_pventry[idx];
4590 pte = pmap_pde(pmap, pv->pv_va);
4592 if ((tpte & PG_PS) == 0) {
4593 pte = vtopte(pv->pv_va);
4594 tpte = *pte & ~PG_PTE_PAT;
4599 "TPTE at %p IS ZERO @ VA %08x\n",
4605 * We cannot remove wired pages from a process' mapping at this time
4612 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4613 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4614 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4615 m, (uintmax_t)m->phys_addr,
4618 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4619 m < &vm_page_array[vm_page_array_size],
4620 ("pmap_remove_pages: bad tpte %#jx",
4626 * Update the vm_page_t clean/reference bits.
4628 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4629 if ((tpte & PG_PS) != 0) {
4630 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4637 PV_STAT(pv_entry_frees++);
4638 PV_STAT(pv_entry_spare++);
4640 pc->pc_map[field] |= bitmask;
4641 if ((tpte & PG_PS) != 0) {
4642 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4643 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4644 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4645 if (TAILQ_EMPTY(&pvh->pv_list)) {
4646 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4647 if (TAILQ_EMPTY(&mt->md.pv_list))
4648 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4650 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4652 pmap_remove_pt_page(pmap, mpte);
4653 pmap->pm_stats.resident_count--;
4654 KASSERT(mpte->wire_count == NPTEPG,
4655 ("pmap_remove_pages: pte page wire count error"));
4656 mpte->wire_count = 0;
4657 pmap_add_delayed_free_list(mpte, &free, FALSE);
4658 atomic_subtract_int(&cnt.v_wire_count, 1);
4661 pmap->pm_stats.resident_count--;
4662 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4663 if (TAILQ_EMPTY(&m->md.pv_list) &&
4664 (m->flags & PG_FICTITIOUS) == 0) {
4665 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4666 if (TAILQ_EMPTY(&pvh->pv_list))
4667 vm_page_aflag_clear(m, PGA_WRITEABLE);
4669 pmap_unuse_pt(pmap, pv->pv_va, &free);
4674 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4679 pmap_invalidate_all(pmap);
4680 rw_wunlock(&pvh_global_lock);
4682 pmap_free_zero_pages(&free);
4688 * Return whether or not the specified physical page was modified
4689 * in any physical maps.
4692 pmap_is_modified(vm_page_t m)
4696 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4697 ("pmap_is_modified: page %p is not managed", m));
4700 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4701 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4702 * is clear, no PTEs can have PG_M set.
4704 VM_OBJECT_ASSERT_WLOCKED(m->object);
4705 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4707 rw_wlock(&pvh_global_lock);
4708 rv = pmap_is_modified_pvh(&m->md) ||
4709 ((m->flags & PG_FICTITIOUS) == 0 &&
4710 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4711 rw_wunlock(&pvh_global_lock);
4716 * Returns TRUE if any of the given mappings were used to modify
4717 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4718 * mappings are supported.
4721 pmap_is_modified_pvh(struct md_page *pvh)
4728 rw_assert(&pvh_global_lock, RA_WLOCKED);
4731 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4734 pte = pmap_pte_quick(pmap, pv->pv_va);
4735 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4745 * pmap_is_prefaultable:
4747 * Return whether or not the specified virtual address is elgible
4751 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4759 pde = pmap_pde(pmap, addr);
4760 if (*pde != 0 && (*pde & PG_PS) == 0) {
4769 * pmap_is_referenced:
4771 * Return whether or not the specified physical page was referenced
4772 * in any physical maps.
4775 pmap_is_referenced(vm_page_t m)
4779 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4780 ("pmap_is_referenced: page %p is not managed", m));
4781 rw_wlock(&pvh_global_lock);
4782 rv = pmap_is_referenced_pvh(&m->md) ||
4783 ((m->flags & PG_FICTITIOUS) == 0 &&
4784 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4785 rw_wunlock(&pvh_global_lock);
4790 * Returns TRUE if any of the given mappings were referenced and FALSE
4791 * otherwise. Both page and 4mpage mappings are supported.
4794 pmap_is_referenced_pvh(struct md_page *pvh)
4801 rw_assert(&pvh_global_lock, RA_WLOCKED);
4804 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4807 pte = pmap_pte_quick(pmap, pv->pv_va);
4808 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4818 * Clear the write and modified bits in each of the given page's mappings.
4821 pmap_remove_write(vm_page_t m)
4823 struct md_page *pvh;
4824 pv_entry_t next_pv, pv;
4827 pt_entry_t oldpte, *pte;
4830 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4831 ("pmap_remove_write: page %p is not managed", m));
4834 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4835 * set by another thread while the object is locked. Thus,
4836 * if PGA_WRITEABLE is clear, no page table entries need updating.
4838 VM_OBJECT_ASSERT_WLOCKED(m->object);
4839 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4841 rw_wlock(&pvh_global_lock);
4843 if ((m->flags & PG_FICTITIOUS) != 0)
4844 goto small_mappings;
4845 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4846 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4850 pde = pmap_pde(pmap, va);
4851 if ((*pde & PG_RW) != 0)
4852 (void)pmap_demote_pde(pmap, pde, va);
4856 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4859 pde = pmap_pde(pmap, pv->pv_va);
4860 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4861 " a 4mpage in page %p's pv list", m));
4862 pte = pmap_pte_quick(pmap, pv->pv_va);
4865 if ((oldpte & PG_RW) != 0) {
4867 * Regardless of whether a pte is 32 or 64 bits
4868 * in size, PG_RW and PG_M are among the least
4869 * significant 32 bits.
4871 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4872 oldpte & ~(PG_RW | PG_M)))
4874 if ((oldpte & PG_M) != 0)
4876 pmap_invalidate_page(pmap, pv->pv_va);
4880 vm_page_aflag_clear(m, PGA_WRITEABLE);
4882 rw_wunlock(&pvh_global_lock);
4885 #define PMAP_TS_REFERENCED_MAX 5
4888 * pmap_ts_referenced:
4890 * Return a count of reference bits for a page, clearing those bits.
4891 * It is not necessary for every reference bit to be cleared, but it
4892 * is necessary that 0 only be returned when there are truly no
4893 * reference bits set.
4895 * XXX: The exact number of bits to check and clear is a matter that
4896 * should be tested and standardized at some point in the future for
4897 * optimal aging of shared pages.
4900 pmap_ts_referenced(vm_page_t m)
4902 struct md_page *pvh;
4910 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4911 ("pmap_ts_referenced: page %p is not managed", m));
4912 pa = VM_PAGE_TO_PHYS(m);
4913 pvh = pa_to_pvh(pa);
4914 rw_wlock(&pvh_global_lock);
4916 if ((m->flags & PG_FICTITIOUS) != 0 ||
4917 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4918 goto small_mappings;
4923 pde = pmap_pde(pmap, pv->pv_va);
4924 if ((*pde & PG_A) != 0) {
4926 * Since this reference bit is shared by either 1024
4927 * or 512 4KB pages, it should not be cleared every
4928 * time it is tested. Apply a simple "hash" function
4929 * on the physical page number, the virtual superpage
4930 * number, and the pmap address to select one 4KB page
4931 * out of the 1024 or 512 on which testing the
4932 * reference bit will result in clearing that bit.
4933 * This function is designed to avoid the selection of
4934 * the same 4KB page for every 2- or 4MB page mapping.
4936 * On demotion, a mapping that hasn't been referenced
4937 * is simply destroyed. To avoid the possibility of a
4938 * subsequent page fault on a demoted wired mapping,
4939 * always leave its reference bit set. Moreover,
4940 * since the superpage is wired, the current state of
4941 * its reference bit won't affect page replacement.
4943 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4944 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4945 (*pde & PG_W) == 0) {
4946 atomic_clear_int((u_int *)pde, PG_A);
4947 pmap_invalidate_page(pmap, pv->pv_va);
4952 /* Rotate the PV list if it has more than one entry. */
4953 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4954 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4955 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4957 if (rtval >= PMAP_TS_REFERENCED_MAX)
4959 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4961 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4967 pde = pmap_pde(pmap, pv->pv_va);
4968 KASSERT((*pde & PG_PS) == 0,
4969 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4971 pte = pmap_pte_quick(pmap, pv->pv_va);
4972 if ((*pte & PG_A) != 0) {
4973 atomic_clear_int((u_int *)pte, PG_A);
4974 pmap_invalidate_page(pmap, pv->pv_va);
4978 /* Rotate the PV list if it has more than one entry. */
4979 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4980 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4981 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4983 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4984 PMAP_TS_REFERENCED_MAX);
4987 rw_wunlock(&pvh_global_lock);
4992 * Apply the given advice to the specified range of addresses within the
4993 * given pmap. Depending on the advice, clear the referenced and/or
4994 * modified flags in each mapping and set the mapped page's dirty field.
4997 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4999 pd_entry_t oldpde, *pde;
5003 boolean_t anychanged, pv_lists_locked;
5005 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5007 if (pmap_is_current(pmap))
5008 pv_lists_locked = FALSE;
5010 pv_lists_locked = TRUE;
5012 rw_wlock(&pvh_global_lock);
5017 for (; sva < eva; sva = pdnxt) {
5018 pdnxt = (sva + NBPDR) & ~PDRMASK;
5021 pde = pmap_pde(pmap, sva);
5023 if ((oldpde & PG_V) == 0)
5025 else if ((oldpde & PG_PS) != 0) {
5026 if ((oldpde & PG_MANAGED) == 0)
5028 if (!pv_lists_locked) {
5029 pv_lists_locked = TRUE;
5030 if (!rw_try_wlock(&pvh_global_lock)) {
5032 pmap_invalidate_all(pmap);
5038 if (!pmap_demote_pde(pmap, pde, sva)) {
5040 * The large page mapping was destroyed.
5046 * Unless the page mappings are wired, remove the
5047 * mapping to a single page so that a subsequent
5048 * access may repromote. Since the underlying page
5049 * table page is fully populated, this removal never
5050 * frees a page table page.
5052 if ((oldpde & PG_W) == 0) {
5053 pte = pmap_pte_quick(pmap, sva);
5054 KASSERT((*pte & PG_V) != 0,
5055 ("pmap_advise: invalid PTE"));
5056 pmap_remove_pte(pmap, pte, sva, NULL);
5062 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5064 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
5067 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5068 if (advice == MADV_DONTNEED) {
5070 * Future calls to pmap_is_modified()
5071 * can be avoided by making the page
5074 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5077 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5078 } else if ((*pte & PG_A) != 0)
5079 atomic_clear_int((u_int *)pte, PG_A);
5082 if ((*pte & PG_G) != 0)
5083 pmap_invalidate_page(pmap, sva);
5089 pmap_invalidate_all(pmap);
5090 if (pv_lists_locked) {
5092 rw_wunlock(&pvh_global_lock);
5098 * Clear the modify bits on the specified physical page.
5101 pmap_clear_modify(vm_page_t m)
5103 struct md_page *pvh;
5104 pv_entry_t next_pv, pv;
5106 pd_entry_t oldpde, *pde;
5107 pt_entry_t oldpte, *pte;
5110 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5111 ("pmap_clear_modify: page %p is not managed", m));
5112 VM_OBJECT_ASSERT_WLOCKED(m->object);
5113 KASSERT(!vm_page_xbusied(m),
5114 ("pmap_clear_modify: page %p is exclusive busied", m));
5117 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5118 * If the object containing the page is locked and the page is not
5119 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5121 if ((m->aflags & PGA_WRITEABLE) == 0)
5123 rw_wlock(&pvh_global_lock);
5125 if ((m->flags & PG_FICTITIOUS) != 0)
5126 goto small_mappings;
5127 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5128 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5132 pde = pmap_pde(pmap, va);
5134 if ((oldpde & PG_RW) != 0) {
5135 if (pmap_demote_pde(pmap, pde, va)) {
5136 if ((oldpde & PG_W) == 0) {
5138 * Write protect the mapping to a
5139 * single page so that a subsequent
5140 * write access may repromote.
5142 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5144 pte = pmap_pte_quick(pmap, va);
5146 if ((oldpte & PG_V) != 0) {
5148 * Regardless of whether a pte is 32 or 64 bits
5149 * in size, PG_RW and PG_M are among the least
5150 * significant 32 bits.
5152 while (!atomic_cmpset_int((u_int *)pte,
5154 oldpte & ~(PG_M | PG_RW)))
5157 pmap_invalidate_page(pmap, va);
5165 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5168 pde = pmap_pde(pmap, pv->pv_va);
5169 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5170 " a 4mpage in page %p's pv list", m));
5171 pte = pmap_pte_quick(pmap, pv->pv_va);
5172 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5174 * Regardless of whether a pte is 32 or 64 bits
5175 * in size, PG_M is among the least significant
5178 atomic_clear_int((u_int *)pte, PG_M);
5179 pmap_invalidate_page(pmap, pv->pv_va);
5184 rw_wunlock(&pvh_global_lock);
5188 * Miscellaneous support routines follow
5191 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5192 static __inline void
5193 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5198 * The cache mode bits are all in the low 32-bits of the
5199 * PTE, so we can just spin on updating the low 32-bits.
5202 opte = *(u_int *)pte;
5203 npte = opte & ~PG_PTE_CACHE;
5205 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5208 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5209 static __inline void
5210 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5215 * The cache mode bits are all in the low 32-bits of the
5216 * PDE, so we can just spin on updating the low 32-bits.
5219 opde = *(u_int *)pde;
5220 npde = opde & ~PG_PDE_CACHE;
5222 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5226 * Map a set of physical memory pages into the kernel virtual
5227 * address space. Return a pointer to where it is mapped. This
5228 * routine is intended to be used for mapping device memory,
5232 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5234 struct pmap_preinit_mapping *ppim;
5235 vm_offset_t va, offset;
5239 offset = pa & PAGE_MASK;
5240 size = round_page(offset + size);
5243 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5245 else if (!pmap_initialized) {
5247 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5248 ppim = pmap_preinit_mapping + i;
5249 if (ppim->va == 0) {
5253 ppim->va = virtual_avail;
5254 virtual_avail += size;
5260 panic("%s: too many preinit mappings", __func__);
5263 * If we have a preinit mapping, re-use it.
5265 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5266 ppim = pmap_preinit_mapping + i;
5267 if (ppim->pa == pa && ppim->sz == size &&
5269 return ((void *)(ppim->va + offset));
5271 va = kva_alloc(size);
5273 panic("%s: Couldn't allocate KVA", __func__);
5275 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5276 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5277 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5278 pmap_invalidate_cache_range(va, va + size, FALSE);
5279 return ((void *)(va + offset));
5283 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5286 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5290 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5293 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5297 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5299 struct pmap_preinit_mapping *ppim;
5303 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5305 offset = va & PAGE_MASK;
5306 size = round_page(offset + size);
5307 va = trunc_page(va);
5308 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5309 ppim = pmap_preinit_mapping + i;
5310 if (ppim->va == va && ppim->sz == size) {
5311 if (pmap_initialized)
5317 if (va + size == virtual_avail)
5322 if (pmap_initialized)
5327 * Sets the memory attribute for the specified page.
5330 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5333 m->md.pat_mode = ma;
5334 if ((m->flags & PG_FICTITIOUS) != 0)
5338 * If "m" is a normal page, flush it from the cache.
5339 * See pmap_invalidate_cache_range().
5341 * First, try to find an existing mapping of the page by sf
5342 * buffer. sf_buf_invalidate_cache() modifies mapping and
5343 * flushes the cache.
5345 if (sf_buf_invalidate_cache(m))
5349 * If page is not mapped by sf buffer, but CPU does not
5350 * support self snoop, map the page transient and do
5351 * invalidation. In the worst case, whole cache is flushed by
5352 * pmap_invalidate_cache_range().
5354 if ((cpu_feature & CPUID_SS) == 0)
5359 pmap_flush_page(vm_page_t m)
5361 struct sysmaps *sysmaps;
5362 vm_offset_t sva, eva;
5365 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5366 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5367 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5368 mtx_lock(&sysmaps->lock);
5369 if (*sysmaps->CMAP2)
5370 panic("pmap_flush_page: CMAP2 busy");
5372 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5373 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5374 invlcaddr(sysmaps->CADDR2);
5375 sva = (vm_offset_t)sysmaps->CADDR2;
5376 eva = sva + PAGE_SIZE;
5379 * Use mfence or sfence despite the ordering implied by
5380 * mtx_{un,}lock() because clflush on non-Intel CPUs
5381 * and clflushopt are not guaranteed to be ordered by
5382 * any other instruction.
5386 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5388 for (; sva < eva; sva += cpu_clflush_line_size) {
5396 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5398 *sysmaps->CMAP2 = 0;
5400 mtx_unlock(&sysmaps->lock);
5402 pmap_invalidate_cache();
5406 * Changes the specified virtual address range's memory type to that given by
5407 * the parameter "mode". The specified virtual address range must be
5408 * completely contained within either the kernel map.
5410 * Returns zero if the change completed successfully, and either EINVAL or
5411 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5412 * of the virtual address range was not mapped, and ENOMEM is returned if
5413 * there was insufficient memory available to complete the change.
5416 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5418 vm_offset_t base, offset, tmpva;
5421 int cache_bits_pte, cache_bits_pde;
5424 base = trunc_page(va);
5425 offset = va & PAGE_MASK;
5426 size = round_page(offset + size);
5429 * Only supported on kernel virtual addresses above the recursive map.
5431 if (base < VM_MIN_KERNEL_ADDRESS)
5434 cache_bits_pde = pmap_cache_bits(mode, 1);
5435 cache_bits_pte = pmap_cache_bits(mode, 0);
5439 * Pages that aren't mapped aren't supported. Also break down
5440 * 2/4MB pages into 4KB pages if required.
5442 PMAP_LOCK(kernel_pmap);
5443 for (tmpva = base; tmpva < base + size; ) {
5444 pde = pmap_pde(kernel_pmap, tmpva);
5446 PMAP_UNLOCK(kernel_pmap);
5451 * If the current 2/4MB page already has
5452 * the required memory type, then we need not
5453 * demote this page. Just increment tmpva to
5454 * the next 2/4MB page frame.
5456 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5457 tmpva = trunc_4mpage(tmpva) + NBPDR;
5462 * If the current offset aligns with a 2/4MB
5463 * page frame and there is at least 2/4MB left
5464 * within the range, then we need not break
5465 * down this page into 4KB pages.
5467 if ((tmpva & PDRMASK) == 0 &&
5468 tmpva + PDRMASK < base + size) {
5472 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5473 PMAP_UNLOCK(kernel_pmap);
5477 pte = vtopte(tmpva);
5479 PMAP_UNLOCK(kernel_pmap);
5484 PMAP_UNLOCK(kernel_pmap);
5487 * Ok, all the pages exist, so run through them updating their
5488 * cache mode if required.
5490 for (tmpva = base; tmpva < base + size; ) {
5491 pde = pmap_pde(kernel_pmap, tmpva);
5493 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5494 pmap_pde_attr(pde, cache_bits_pde);
5497 tmpva = trunc_4mpage(tmpva) + NBPDR;
5499 pte = vtopte(tmpva);
5500 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5501 pmap_pte_attr(pte, cache_bits_pte);
5509 * Flush CPU caches to make sure any data isn't cached that
5510 * shouldn't be, etc.
5513 pmap_invalidate_range(kernel_pmap, base, tmpva);
5514 pmap_invalidate_cache_range(base, tmpva, FALSE);
5520 * perform the pmap work for mincore
5523 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5526 pt_entry_t *ptep, pte;
5532 pdep = pmap_pde(pmap, addr);
5534 if (*pdep & PG_PS) {
5536 /* Compute the physical address of the 4KB page. */
5537 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5539 val = MINCORE_SUPER;
5541 ptep = pmap_pte(pmap, addr);
5543 pmap_pte_release(ptep);
5544 pa = pte & PG_FRAME;
5552 if ((pte & PG_V) != 0) {
5553 val |= MINCORE_INCORE;
5554 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5555 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5556 if ((pte & PG_A) != 0)
5557 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5559 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5560 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5561 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5562 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5563 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5566 PA_UNLOCK_COND(*locked_pa);
5572 pmap_activate(struct thread *td)
5574 pmap_t pmap, oldpmap;
5579 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5580 oldpmap = PCPU_GET(curpmap);
5581 cpuid = PCPU_GET(cpuid);
5583 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5584 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5586 CPU_CLR(cpuid, &oldpmap->pm_active);
5587 CPU_SET(cpuid, &pmap->pm_active);
5589 #if defined(PAE) || defined(PAE_TABLES)
5590 cr3 = vtophys(pmap->pm_pdpt);
5592 cr3 = vtophys(pmap->pm_pdir);
5595 * pmap_activate is for the current thread on the current cpu
5597 td->td_pcb->pcb_cr3 = cr3;
5599 PCPU_SET(curpmap, pmap);
5604 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5609 * Increase the starting virtual address of the given mapping if a
5610 * different alignment might result in more superpage mappings.
5613 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5614 vm_offset_t *addr, vm_size_t size)
5616 vm_offset_t superpage_offset;
5620 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5621 offset += ptoa(object->pg_color);
5622 superpage_offset = offset & PDRMASK;
5623 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5624 (*addr & PDRMASK) == superpage_offset)
5626 if ((*addr & PDRMASK) < superpage_offset)
5627 *addr = (*addr & ~PDRMASK) + superpage_offset;
5629 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5633 #if defined(PMAP_DEBUG)
5634 pmap_pid_dump(int pid)
5641 sx_slock(&allproc_lock);
5642 FOREACH_PROC_IN_SYSTEM(p) {
5643 if (p->p_pid != pid)
5649 pmap = vmspace_pmap(p->p_vmspace);
5650 for (i = 0; i < NPDEPTD; i++) {
5653 vm_offset_t base = i << PDRSHIFT;
5655 pde = &pmap->pm_pdir[i];
5656 if (pde && pmap_pde_v(pde)) {
5657 for (j = 0; j < NPTEPG; j++) {
5658 vm_offset_t va = base + (j << PAGE_SHIFT);
5659 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5664 sx_sunlock(&allproc_lock);
5667 pte = pmap_pte(pmap, va);
5668 if (pte && pmap_pte_v(pte)) {
5672 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5673 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5674 va, pa, m->hold_count, m->wire_count, m->flags);
5689 sx_sunlock(&allproc_lock);
5696 static void pads(pmap_t pm);
5697 void pmap_pvdump(vm_paddr_t pa);
5699 /* print address space of pmap*/
5707 if (pm == kernel_pmap)
5709 for (i = 0; i < NPDEPTD; i++)
5711 for (j = 0; j < NPTEPG; j++) {
5712 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5713 if (pm == kernel_pmap && va < KERNBASE)
5715 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5717 ptep = pmap_pte(pm, va);
5718 if (pmap_pte_v(ptep))
5719 printf("%x:%x ", va, *ptep);
5725 pmap_pvdump(vm_paddr_t pa)
5731 printf("pa %x", pa);
5732 m = PHYS_TO_VM_PAGE(pa);
5733 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5735 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);