2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * In addition to hardware address maps, this
84 * module is called upon to provide software-use-only
85 * maps which may or may not be stored in the same
86 * form as hardware maps. These pseudo-maps are
87 * used to store intermediate results from copy
88 * operations to and from address spaces.
90 * Since the information managed by this module is
91 * also stored by the logical address mapping module,
92 * this module may throw away valid virtual-to-physical
93 * mappings at almost any time. However, invalidations
94 * of virtual-to-physical mappings must be done as
97 * In order to cope with hardware architectures which
98 * make virtual-to-physical map invalidates expensive,
99 * this module may delay invalidate or reduced protection
100 * operations until such time as they are actually
101 * necessary. This module is given full information as
102 * to which processors are currently using which maps,
103 * and to when physical maps must be made correct.
107 #include "opt_pmap.h"
109 #include "opt_xbox.h"
111 #include <sys/param.h>
112 #include <sys/systm.h>
113 #include <sys/kernel.h>
115 #include <sys/lock.h>
116 #include <sys/malloc.h>
117 #include <sys/mman.h>
118 #include <sys/msgbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/sf_buf.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
129 #include <sys/cpuset.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_reserv.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
154 #include <machine/xbox.h>
157 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
158 #define CPU_ENABLE_SSE
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
201 LIST_HEAD(pmaplist, pmap);
202 static struct pmaplist allpmaps;
203 static struct mtx allpmaps_lock;
205 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
206 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
207 int pgeflag = 0; /* PG_G or-in */
208 int pseflag = 0; /* PG_PS or-in */
210 static int nkpt = NKPT;
211 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
212 extern u_int32_t KERNend;
213 extern u_int32_t KPTphys;
217 static uma_zone_t pdptzone;
220 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
222 static int pat_works = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
224 "Is page attribute table fully functional?");
226 static int pg_ps_enabled = 1;
227 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
228 "Are large page mappings enabled?");
230 #define PAT_INDEX_SIZE 8
231 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
234 * Data for the pv entry allocation mechanism
236 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
237 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
238 static struct md_page *pv_table;
239 static int shpgperproc = PMAP_SHPGPERPROC;
241 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
242 int pv_maxchunks; /* How many chunks we have KVA for */
243 vm_offset_t pv_vafree; /* freelist stored in the PTE */
246 * All those kernel PT submaps that BSD is so fond of
255 static struct sysmaps sysmaps_pcpu[MAXCPU];
256 pt_entry_t *CMAP1 = 0;
257 static pt_entry_t *CMAP3;
258 static pd_entry_t *KPTD;
259 caddr_t CADDR1 = 0, ptvmmap = 0;
260 static caddr_t CADDR3;
261 struct msgbuf *msgbufp = 0;
266 static caddr_t crashdumpmap;
268 static pt_entry_t *PMAP1 = 0, *PMAP2;
269 static pt_entry_t *PADDR1 = 0, *PADDR2;
272 static int PMAP1changedcpu;
273 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
275 "Number of times pmap_pte_quick changed CPU with same PMAP1");
277 static int PMAP1changed;
278 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
280 "Number of times pmap_pte_quick changed PMAP1");
281 static int PMAP1unchanged;
282 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
284 "Number of times pmap_pte_quick didn't change PMAP1");
285 static struct mtx PMAP2mutex;
287 static void free_pv_chunk(struct pv_chunk *pc);
288 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
289 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
290 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
292 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
293 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
294 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
296 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
298 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
299 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
301 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
302 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
303 static void pmap_flush_page(vm_page_t m);
304 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
305 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
306 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
307 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
308 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
309 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
310 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
311 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
312 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
313 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
315 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
316 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
318 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
320 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
321 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
323 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
325 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
326 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
328 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
330 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
332 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
334 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags);
335 static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
336 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
337 static void pmap_pte_release(pt_entry_t *pte);
338 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
340 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
342 static void pmap_set_pg(void);
344 static __inline void pagezero(void *page);
346 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
347 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
350 * If you get an error here, then you set KVA_PAGES wrong! See the
351 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
352 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
354 CTASSERT(KERNBASE % (1 << 24) == 0);
357 * Bootstrap the system enough to run with virtual memory.
359 * On the i386 this is called after mapping has already been enabled
360 * and just syncs the pmap module with what has already been done.
361 * [We can't call it easily with mapping off since the kernel is not
362 * mapped with PA == VA, hence we would have to relocate every address
363 * from the linked base (virtual) address "KERNBASE" to the actual
364 * (physical) address starting relative to 0]
367 pmap_bootstrap(vm_paddr_t firstaddr)
370 pt_entry_t *pte, *unused;
371 struct sysmaps *sysmaps;
375 * Initialize the first available kernel virtual address. However,
376 * using "firstaddr" may waste a few pages of the kernel virtual
377 * address space, because locore may not have mapped every physical
378 * page that it allocated. Preferably, locore would provide a first
379 * unused virtual address in addition to "firstaddr".
381 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
383 virtual_end = VM_MAX_KERNEL_ADDRESS;
386 * Initialize the kernel pmap (which is statically allocated).
388 PMAP_LOCK_INIT(kernel_pmap);
389 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
391 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
393 kernel_pmap->pm_root = NULL;
394 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
395 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
396 LIST_INIT(&allpmaps);
399 * Request a spin mutex so that changes to allpmaps cannot be
400 * preempted by smp_rendezvous_cpus(). Otherwise,
401 * pmap_update_pde_kernel() could access allpmaps while it is
404 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
405 mtx_lock_spin(&allpmaps_lock);
406 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
407 mtx_unlock_spin(&allpmaps_lock);
410 * Reserve some special page table entries/VA space for temporary
413 #define SYSMAP(c, p, v, n) \
414 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
420 * CMAP1/CMAP2 are used for zeroing and copying pages.
421 * CMAP3 is used for the idle process page zeroing.
423 for (i = 0; i < MAXCPU; i++) {
424 sysmaps = &sysmaps_pcpu[i];
425 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
426 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
427 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
429 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
430 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
435 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
438 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
440 SYSMAP(caddr_t, unused, ptvmmap, 1)
443 * msgbufp is used to map the system message buffer.
445 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
448 * KPTmap is used by pmap_kextract().
450 * KPTmap is first initialized by locore. However, that initial
451 * KPTmap can only support NKPT page table pages. Here, a larger
452 * KPTmap is created that can support KVA_PAGES page table pages.
454 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
456 for (i = 0; i < NKPT; i++)
457 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
460 * Adjust the start of the KPTD and KPTmap so that the implementation
461 * of pmap_kextract() and pmap_growkernel() can be made simpler.
464 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
467 * ptemap is used for pmap_pte_quick
469 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
470 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
472 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
477 * Leave in place an identity mapping (virt == phys) for the low 1 MB
478 * physical memory region that is used by the ACPI wakeup code. This
479 * mapping must not have PG_G set.
482 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
483 * an early stadium, we cannot yet neatly map video memory ... :-(
484 * Better fixes are very welcome! */
485 if (!arch_i386_is_xbox)
487 for (i = 1; i < NKPT; i++)
490 /* Initialize the PAT MSR if present. */
493 /* Turn on PG_G on kernel page(s) */
503 int pat_table[PAT_INDEX_SIZE];
508 /* Set default PAT index table. */
509 for (i = 0; i < PAT_INDEX_SIZE; i++)
511 pat_table[PAT_WRITE_BACK] = 0;
512 pat_table[PAT_WRITE_THROUGH] = 1;
513 pat_table[PAT_UNCACHEABLE] = 3;
514 pat_table[PAT_WRITE_COMBINING] = 3;
515 pat_table[PAT_WRITE_PROTECTED] = 3;
516 pat_table[PAT_UNCACHED] = 3;
518 /* Bail if this CPU doesn't implement PAT. */
519 if ((cpu_feature & CPUID_PAT) == 0) {
520 for (i = 0; i < PAT_INDEX_SIZE; i++)
521 pat_index[i] = pat_table[i];
527 * Due to some Intel errata, we can only safely use the lower 4
530 * Intel Pentium III Processor Specification Update
531 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
534 * Intel Pentium IV Processor Specification Update
535 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
537 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
538 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
541 /* Initialize default PAT entries. */
542 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
543 PAT_VALUE(1, PAT_WRITE_THROUGH) |
544 PAT_VALUE(2, PAT_UNCACHED) |
545 PAT_VALUE(3, PAT_UNCACHEABLE) |
546 PAT_VALUE(4, PAT_WRITE_BACK) |
547 PAT_VALUE(5, PAT_WRITE_THROUGH) |
548 PAT_VALUE(6, PAT_UNCACHED) |
549 PAT_VALUE(7, PAT_UNCACHEABLE);
553 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
554 * Program 5 and 6 as WP and WC.
555 * Leave 4 and 7 as WB and UC.
557 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
558 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
559 PAT_VALUE(6, PAT_WRITE_COMBINING);
560 pat_table[PAT_UNCACHED] = 2;
561 pat_table[PAT_WRITE_PROTECTED] = 5;
562 pat_table[PAT_WRITE_COMBINING] = 6;
565 * Just replace PAT Index 2 with WC instead of UC-.
567 pat_msr &= ~PAT_MASK(2);
568 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
569 pat_table[PAT_WRITE_COMBINING] = 2;
574 load_cr4(cr4 & ~CR4_PGE);
576 /* Disable caches (CD = 1, NW = 0). */
578 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
580 /* Flushes caches and TLBs. */
584 /* Update PAT and index table. */
585 wrmsr(MSR_PAT, pat_msr);
586 for (i = 0; i < PAT_INDEX_SIZE; i++)
587 pat_index[i] = pat_table[i];
589 /* Flush caches and TLBs again. */
593 /* Restore caches and PGE. */
599 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
605 vm_offset_t va, endva;
610 endva = KERNBASE + KERNend;
613 va = KERNBASE + KERNLOAD;
615 pdir_pde(PTD, va) |= pgeflag;
616 invltlb(); /* Play it safe, invltlb() every time */
620 va = (vm_offset_t)btext;
625 invltlb(); /* Play it safe, invltlb() every time */
632 * Initialize a vm_page's machine-dependent fields.
635 pmap_page_init(vm_page_t m)
638 TAILQ_INIT(&m->md.pv_list);
639 m->md.pat_mode = PAT_WRITE_BACK;
644 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
647 /* Inform UMA that this allocator uses kernel_map/object. */
648 *flags = UMA_SLAB_KERNEL;
649 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
650 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
655 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
657 * - Must deal with pages in order to ensure that none of the PG_* bits
658 * are ever set, PG_V in particular.
659 * - Assumes we can write to ptes without pte_store() atomic ops, even
660 * on PAE systems. This should be ok.
661 * - Assumes nothing will ever test these addresses for 0 to indicate
662 * no mapping instead of correctly checking PG_V.
663 * - Assumes a vm_offset_t will fit in a pte (true for i386).
664 * Because PG_V is never set, there can be no mappings to invalidate.
667 pmap_ptelist_alloc(vm_offset_t *head)
674 return (va); /* Out of memory */
678 panic("pmap_ptelist_alloc: va with PG_V set!");
684 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
689 panic("pmap_ptelist_free: freeing va with PG_V set!");
691 *pte = *head; /* virtual! PG_V is 0 though */
696 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
702 for (i = npages - 1; i >= 0; i--) {
703 va = (vm_offset_t)base + i * PAGE_SIZE;
704 pmap_ptelist_free(head, va);
710 * Initialize the pmap module.
711 * Called by vm_init, to initialize any structures that the pmap
712 * system needs to map virtual memory.
722 * Initialize the vm page array entries for the kernel pmap's
725 for (i = 0; i < NKPT; i++) {
726 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
727 KASSERT(mpte >= vm_page_array &&
728 mpte < &vm_page_array[vm_page_array_size],
729 ("pmap_init: page table page is out of range"));
730 mpte->pindex = i + KPTDI;
731 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
735 * Initialize the address space (zone) for the pv entries. Set a
736 * high water mark so that the system can recover from excessive
737 * numbers of pv entries.
739 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
740 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
741 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
742 pv_entry_max = roundup(pv_entry_max, _NPCPV);
743 pv_entry_high_water = 9 * (pv_entry_max / 10);
746 * If the kernel is running in a virtual machine on an AMD Family 10h
747 * processor, then it must assume that MCA is enabled by the virtual
750 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
751 CPUID_TO_FAMILY(cpu_id) == 0x10)
752 workaround_erratum383 = 1;
755 * Are large page mappings supported and enabled?
757 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
760 else if (pg_ps_enabled) {
761 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
762 ("pmap_init: can't assign to pagesizes[1]"));
763 pagesizes[1] = NBPDR;
767 * Calculate the size of the pv head table for superpages.
769 for (i = 0; phys_avail[i + 1]; i += 2);
770 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
773 * Allocate memory for the pv head table for superpages.
775 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
777 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
778 for (i = 0; i < pv_npg; i++)
779 TAILQ_INIT(&pv_table[i].pv_list);
781 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
782 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
783 PAGE_SIZE * pv_maxchunks);
784 if (pv_chunkbase == NULL)
785 panic("pmap_init: not enough kvm for pv chunks");
786 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
788 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
789 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
790 UMA_ZONE_VM | UMA_ZONE_NOFREE);
791 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
796 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
797 "Max number of PV entries");
798 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
799 "Page share factor per proc");
801 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
802 "2/4MB page mapping counters");
804 static u_long pmap_pde_demotions;
805 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
806 &pmap_pde_demotions, 0, "2/4MB page demotions");
808 static u_long pmap_pde_mappings;
809 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
810 &pmap_pde_mappings, 0, "2/4MB page mappings");
812 static u_long pmap_pde_p_failures;
813 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
814 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
816 static u_long pmap_pde_promotions;
817 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
818 &pmap_pde_promotions, 0, "2/4MB page promotions");
820 /***************************************************
821 * Low level helper routines.....
822 ***************************************************/
825 * Determine the appropriate bits to set in a PTE or PDE for a specified
829 pmap_cache_bits(int mode, boolean_t is_pde)
831 int cache_bits, pat_flag, pat_idx;
833 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
834 panic("Unknown caching mode %d\n", mode);
836 /* The PAT bit is different for PTE's and PDE's. */
837 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
839 /* Map the caching mode to a PAT index. */
840 pat_idx = pat_index[mode];
842 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
845 cache_bits |= pat_flag;
847 cache_bits |= PG_NC_PCD;
849 cache_bits |= PG_NC_PWT;
854 * The caller is responsible for maintaining TLB consistency.
857 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
861 boolean_t PTD_updated;
864 mtx_lock_spin(&allpmaps_lock);
865 LIST_FOREACH(pmap, &allpmaps, pm_list) {
866 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
869 pde = pmap_pde(pmap, va);
870 pde_store(pde, newpde);
872 mtx_unlock_spin(&allpmaps_lock);
874 ("pmap_kenter_pde: current page table is not in allpmaps"));
878 * After changing the page size for the specified virtual address in the page
879 * table, flush the corresponding entries from the processor's TLB. Only the
880 * calling processor's TLB is affected.
882 * The calling thread must be pinned to a processor.
885 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
889 if ((newpde & PG_PS) == 0)
890 /* Demotion: flush a specific 2MB page mapping. */
892 else if ((newpde & PG_G) == 0)
894 * Promotion: flush every 4KB page mapping from the TLB
895 * because there are too many to flush individually.
900 * Promotion: flush every 4KB page mapping from the TLB,
901 * including any global (PG_G) mappings.
904 load_cr4(cr4 & ~CR4_PGE);
906 * Although preemption at this point could be detrimental to
907 * performance, it would not lead to an error. PG_G is simply
908 * ignored if CR4.PGE is clear. Moreover, in case this block
909 * is re-entered, the load_cr4() either above or below will
910 * modify CR4.PGE flushing the TLB.
912 load_cr4(cr4 | CR4_PGE);
917 * For SMP, these functions have to use the IPI mechanism for coherence.
919 * N.B.: Before calling any of the following TLB invalidation functions,
920 * the calling processor must ensure that all stores updating a non-
921 * kernel page table are globally performed. Otherwise, another
922 * processor could cache an old, pre-update entry without being
923 * invalidated. This can happen one of two ways: (1) The pmap becomes
924 * active on another processor after its pm_active field is checked by
925 * one of the following functions but before a store updating the page
926 * table is globally performed. (2) The pmap becomes active on another
927 * processor before its pm_active field is checked but due to
928 * speculative loads one of the following functions stills reads the
929 * pmap as inactive on the other processor.
931 * The kernel page table is exempt because its pm_active field is
932 * immutable. The kernel page table is always active on every
936 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
942 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
946 cpuid = PCPU_GET(cpuid);
947 other_cpus = all_cpus;
948 CPU_CLR(cpuid, &other_cpus);
949 if (CPU_ISSET(cpuid, &pmap->pm_active))
951 CPU_AND(&other_cpus, &pmap->pm_active);
952 if (!CPU_EMPTY(&other_cpus))
953 smp_masked_invlpg(other_cpus, va);
959 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
966 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
967 for (addr = sva; addr < eva; addr += PAGE_SIZE)
969 smp_invlpg_range(sva, eva);
971 cpuid = PCPU_GET(cpuid);
972 other_cpus = all_cpus;
973 CPU_CLR(cpuid, &other_cpus);
974 if (CPU_ISSET(cpuid, &pmap->pm_active))
975 for (addr = sva; addr < eva; addr += PAGE_SIZE)
977 CPU_AND(&other_cpus, &pmap->pm_active);
978 if (!CPU_EMPTY(&other_cpus))
979 smp_masked_invlpg_range(other_cpus, sva, eva);
985 pmap_invalidate_all(pmap_t pmap)
991 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
995 cpuid = PCPU_GET(cpuid);
996 other_cpus = all_cpus;
997 CPU_CLR(cpuid, &other_cpus);
998 if (CPU_ISSET(cpuid, &pmap->pm_active))
1000 CPU_AND(&other_cpus, &pmap->pm_active);
1001 if (!CPU_EMPTY(&other_cpus))
1002 smp_masked_invltlb(other_cpus);
1008 pmap_invalidate_cache(void)
1018 cpuset_t invalidate; /* processors that invalidate their TLB */
1022 u_int store; /* processor that updates the PDE */
1026 pmap_update_pde_kernel(void *arg)
1028 struct pde_action *act = arg;
1032 if (act->store == PCPU_GET(cpuid)) {
1035 * Elsewhere, this operation requires allpmaps_lock for
1036 * synchronization. Here, it does not because it is being
1037 * performed in the context of an all_cpus rendezvous.
1039 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1040 pde = pmap_pde(pmap, act->va);
1041 pde_store(pde, act->newpde);
1047 pmap_update_pde_user(void *arg)
1049 struct pde_action *act = arg;
1051 if (act->store == PCPU_GET(cpuid))
1052 pde_store(act->pde, act->newpde);
1056 pmap_update_pde_teardown(void *arg)
1058 struct pde_action *act = arg;
1060 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1061 pmap_update_pde_invalidate(act->va, act->newpde);
1065 * Change the page size for the specified virtual address in a way that
1066 * prevents any possibility of the TLB ever having two entries that map the
1067 * same virtual address using different page sizes. This is the recommended
1068 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1069 * machine check exception for a TLB state that is improperly diagnosed as a
1073 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1075 struct pde_action act;
1076 cpuset_t active, other_cpus;
1080 cpuid = PCPU_GET(cpuid);
1081 other_cpus = all_cpus;
1082 CPU_CLR(cpuid, &other_cpus);
1083 if (pmap == kernel_pmap)
1086 active = pmap->pm_active;
1087 if (CPU_OVERLAP(&active, &other_cpus)) {
1089 act.invalidate = active;
1092 act.newpde = newpde;
1093 CPU_SET(cpuid, &active);
1094 smp_rendezvous_cpus(active,
1095 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1096 pmap_update_pde_kernel : pmap_update_pde_user,
1097 pmap_update_pde_teardown, &act);
1099 if (pmap == kernel_pmap)
1100 pmap_kenter_pde(va, newpde);
1102 pde_store(pde, newpde);
1103 if (CPU_ISSET(cpuid, &active))
1104 pmap_update_pde_invalidate(va, newpde);
1110 * Normal, non-SMP, 486+ invalidation functions.
1111 * We inline these within pmap.c for speed.
1114 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1117 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1122 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1126 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1127 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1132 pmap_invalidate_all(pmap_t pmap)
1135 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1140 pmap_invalidate_cache(void)
1147 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1150 if (pmap == kernel_pmap)
1151 pmap_kenter_pde(va, newpde);
1153 pde_store(pde, newpde);
1154 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1155 pmap_update_pde_invalidate(va, newpde);
1159 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1162 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1165 KASSERT((sva & PAGE_MASK) == 0,
1166 ("pmap_invalidate_cache_range: sva not page-aligned"));
1167 KASSERT((eva & PAGE_MASK) == 0,
1168 ("pmap_invalidate_cache_range: eva not page-aligned"));
1170 if (cpu_feature & CPUID_SS)
1171 ; /* If "Self Snoop" is supported, do nothing. */
1172 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1173 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1176 * Otherwise, do per-cache line flush. Use the mfence
1177 * instruction to insure that previous stores are
1178 * included in the write-back. The processor
1179 * propagates flush to other processors in the cache
1183 for (; sva < eva; sva += cpu_clflush_line_size)
1189 * No targeted cache flush methods are supported by CPU,
1190 * or the supplied range is bigger than 2MB.
1191 * Globally invalidate cache.
1193 pmap_invalidate_cache();
1198 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1202 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1203 (cpu_feature & CPUID_CLFSH) == 0) {
1204 pmap_invalidate_cache();
1206 for (i = 0; i < count; i++)
1207 pmap_flush_page(pages[i]);
1212 * Are we current address space or kernel? N.B. We return FALSE when
1213 * a pmap's page table is in use because a kernel thread is borrowing
1214 * it. The borrowed page table can change spontaneously, making any
1215 * dependence on its continued use subject to a race condition.
1218 pmap_is_current(pmap_t pmap)
1221 return (pmap == kernel_pmap ||
1222 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1223 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1227 * If the given pmap is not the current or kernel pmap, the returned pte must
1228 * be released by passing it to pmap_pte_release().
1231 pmap_pte(pmap_t pmap, vm_offset_t va)
1236 pde = pmap_pde(pmap, va);
1240 /* are we current address space or kernel? */
1241 if (pmap_is_current(pmap))
1242 return (vtopte(va));
1243 mtx_lock(&PMAP2mutex);
1244 newpf = *pde & PG_FRAME;
1245 if ((*PMAP2 & PG_FRAME) != newpf) {
1246 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1247 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1249 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1255 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1258 static __inline void
1259 pmap_pte_release(pt_entry_t *pte)
1262 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1263 mtx_unlock(&PMAP2mutex);
1266 static __inline void
1267 invlcaddr(void *caddr)
1270 invlpg((u_int)caddr);
1274 * Super fast pmap_pte routine best used when scanning
1275 * the pv lists. This eliminates many coarse-grained
1276 * invltlb calls. Note that many of the pv list
1277 * scans are across different pmaps. It is very wasteful
1278 * to do an entire invltlb for checking a single mapping.
1280 * If the given pmap is not the current pmap, vm_page_queue_mtx
1281 * must be held and curthread pinned to a CPU.
1284 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1289 pde = pmap_pde(pmap, va);
1293 /* are we current address space or kernel? */
1294 if (pmap_is_current(pmap))
1295 return (vtopte(va));
1296 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1297 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1298 newpf = *pde & PG_FRAME;
1299 if ((*PMAP1 & PG_FRAME) != newpf) {
1300 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1302 PMAP1cpu = PCPU_GET(cpuid);
1308 if (PMAP1cpu != PCPU_GET(cpuid)) {
1309 PMAP1cpu = PCPU_GET(cpuid);
1315 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1321 * Routine: pmap_extract
1323 * Extract the physical page address associated
1324 * with the given map/virtual_address pair.
1327 pmap_extract(pmap_t pmap, vm_offset_t va)
1335 pde = pmap->pm_pdir[va >> PDRSHIFT];
1337 if ((pde & PG_PS) != 0)
1338 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1340 pte = pmap_pte(pmap, va);
1341 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1342 pmap_pte_release(pte);
1350 * Routine: pmap_extract_and_hold
1352 * Atomically extract and hold the physical page
1353 * with the given pmap and virtual address pair
1354 * if that mapping permits the given protection.
1357 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1360 pt_entry_t pte, *ptep;
1368 pde = *pmap_pde(pmap, va);
1371 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1372 if (vm_page_pa_tryrelock(pmap, (pde &
1373 PG_PS_FRAME) | (va & PDRMASK), &pa))
1375 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1380 ptep = pmap_pte(pmap, va);
1382 pmap_pte_release(ptep);
1384 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1385 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1388 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1398 /***************************************************
1399 * Low level mapping routines.....
1400 ***************************************************/
1403 * Add a wired page to the kva.
1404 * Note: not SMP coherent.
1406 * This function may be used before pmap_bootstrap() is called.
1409 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1414 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1417 static __inline void
1418 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1423 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1427 * Remove a page from the kernel pagetables.
1428 * Note: not SMP coherent.
1430 * This function may be used before pmap_bootstrap() is called.
1433 pmap_kremove(vm_offset_t va)
1442 * Used to map a range of physical addresses into kernel
1443 * virtual address space.
1445 * The value passed in '*virt' is a suggested virtual address for
1446 * the mapping. Architectures which can support a direct-mapped
1447 * physical to virtual region can return the appropriate address
1448 * within that region, leaving '*virt' unchanged. Other
1449 * architectures should map the pages starting at '*virt' and
1450 * update '*virt' with the first usable address after the mapped
1454 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1456 vm_offset_t va, sva;
1457 vm_paddr_t superpage_offset;
1462 * Does the physical address range's size and alignment permit at
1463 * least one superpage mapping to be created?
1465 superpage_offset = start & PDRMASK;
1466 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1468 * Increase the starting virtual address so that its alignment
1469 * does not preclude the use of superpage mappings.
1471 if ((va & PDRMASK) < superpage_offset)
1472 va = (va & ~PDRMASK) + superpage_offset;
1473 else if ((va & PDRMASK) > superpage_offset)
1474 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1477 while (start < end) {
1478 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1480 KASSERT((va & PDRMASK) == 0,
1481 ("pmap_map: misaligned va %#x", va));
1482 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1483 pmap_kenter_pde(va, newpde);
1487 pmap_kenter(va, start);
1492 pmap_invalidate_range(kernel_pmap, sva, va);
1499 * Add a list of wired pages to the kva
1500 * this routine is only used for temporary
1501 * kernel mappings that do not need to have
1502 * page modification or references recorded.
1503 * Note that old mappings are simply written
1504 * over. The page *must* be wired.
1505 * Note: SMP coherent. Uses a ranged shootdown IPI.
1508 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1510 pt_entry_t *endpte, oldpte, pa, *pte;
1515 endpte = pte + count;
1516 while (pte < endpte) {
1518 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1519 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1521 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1525 if (__predict_false((oldpte & PG_V) != 0))
1526 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1531 * This routine tears out page mappings from the
1532 * kernel -- it is meant only for temporary mappings.
1533 * Note: SMP coherent. Uses a ranged shootdown IPI.
1536 pmap_qremove(vm_offset_t sva, int count)
1541 while (count-- > 0) {
1545 pmap_invalidate_range(kernel_pmap, sva, va);
1548 /***************************************************
1549 * Page table page management routines.....
1550 ***************************************************/
1551 static __inline void
1552 pmap_free_zero_pages(vm_page_t free)
1556 while (free != NULL) {
1559 /* Preserve the page's PG_ZERO setting. */
1560 vm_page_free_toq(m);
1565 * Schedule the specified unused page table page to be freed. Specifically,
1566 * add the page to the specified list of pages that will be released to the
1567 * physical memory manager after the TLB has been updated.
1569 static __inline void
1570 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1574 m->flags |= PG_ZERO;
1576 m->flags &= ~PG_ZERO;
1582 * Inserts the specified page table page into the specified pmap's collection
1583 * of idle page table pages. Each of a pmap's page table pages is responsible
1584 * for mapping a distinct range of virtual addresses. The pmap's collection is
1585 * ordered by this virtual address range.
1588 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1592 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1593 root = pmap->pm_root;
1598 root = vm_page_splay(mpte->pindex, root);
1599 if (mpte->pindex < root->pindex) {
1600 mpte->left = root->left;
1603 } else if (mpte->pindex == root->pindex)
1604 panic("pmap_insert_pt_page: pindex already inserted");
1606 mpte->right = root->right;
1611 pmap->pm_root = mpte;
1615 * Looks for a page table page mapping the specified virtual address in the
1616 * specified pmap's collection of idle page table pages. Returns NULL if there
1617 * is no page table page corresponding to the specified virtual address.
1620 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1623 vm_pindex_t pindex = va >> PDRSHIFT;
1625 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1626 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1627 mpte = vm_page_splay(pindex, mpte);
1628 if ((pmap->pm_root = mpte)->pindex != pindex)
1635 * Removes the specified page table page from the specified pmap's collection
1636 * of idle page table pages. The specified page table page must be a member of
1637 * the pmap's collection.
1640 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1644 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1645 if (mpte != pmap->pm_root)
1646 vm_page_splay(mpte->pindex, pmap->pm_root);
1647 if (mpte->left == NULL)
1650 root = vm_page_splay(mpte->pindex, mpte->left);
1651 root->right = mpte->right;
1653 pmap->pm_root = root;
1657 * This routine unholds page table pages, and if the hold count
1658 * drops to zero, then it decrements the wire count.
1661 pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1665 if (m->wire_count == 0)
1666 return (_pmap_unwire_pte_hold(pmap, m, free));
1672 _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1677 * unmap the page table page
1679 pmap->pm_pdir[m->pindex] = 0;
1680 --pmap->pm_stats.resident_count;
1683 * This is a release store so that the ordinary store unmapping
1684 * the page table page is globally performed before TLB shoot-
1687 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1690 * Do an invltlb to make the invalidated mapping
1691 * take effect immediately.
1693 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1694 pmap_invalidate_page(pmap, pteva);
1697 * Put page on a list so that it is released after
1698 * *ALL* TLB shootdown is done
1700 pmap_add_delayed_free_list(m, free, TRUE);
1706 * After removing a page table entry, this routine is used to
1707 * conditionally free the page, and manage the hold/wire counts.
1710 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1715 if (va >= VM_MAXUSER_ADDRESS)
1717 ptepde = *pmap_pde(pmap, va);
1718 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1719 return (pmap_unwire_pte_hold(pmap, mpte, free));
1723 * Initialize the pmap for the swapper process.
1726 pmap_pinit0(pmap_t pmap)
1729 PMAP_LOCK_INIT(pmap);
1731 * Since the page table directory is shared with the kernel pmap,
1732 * which is already included in the list "allpmaps", this pmap does
1733 * not need to be inserted into that list.
1735 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1737 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1739 pmap->pm_root = NULL;
1740 CPU_ZERO(&pmap->pm_active);
1741 PCPU_SET(curpmap, pmap);
1742 TAILQ_INIT(&pmap->pm_pvchunk);
1743 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1747 * Initialize a preallocated and zeroed pmap structure,
1748 * such as one in a vmspace structure.
1751 pmap_pinit(pmap_t pmap)
1753 vm_page_t m, ptdpg[NPGPTD];
1757 PMAP_LOCK_INIT(pmap);
1760 * No need to allocate page table space yet but we do need a valid
1761 * page directory table.
1763 if (pmap->pm_pdir == NULL) {
1764 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1766 if (pmap->pm_pdir == NULL) {
1767 PMAP_LOCK_DESTROY(pmap);
1771 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1772 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1773 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1774 ("pmap_pinit: pdpt misaligned"));
1775 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1776 ("pmap_pinit: pdpt above 4g"));
1778 pmap->pm_root = NULL;
1780 KASSERT(pmap->pm_root == NULL,
1781 ("pmap_pinit: pmap has reserved page table page(s)"));
1784 * allocate the page directory page(s)
1786 for (i = 0; i < NPGPTD;) {
1787 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1788 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1796 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1798 for (i = 0; i < NPGPTD; i++)
1799 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1800 pagezero(pmap->pm_pdir + (i * NPDEPG));
1802 mtx_lock_spin(&allpmaps_lock);
1803 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1804 /* Copy the kernel page table directory entries. */
1805 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1806 mtx_unlock_spin(&allpmaps_lock);
1808 /* install self-referential address mapping entry(s) */
1809 for (i = 0; i < NPGPTD; i++) {
1810 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1811 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1813 pmap->pm_pdpt[i] = pa | PG_V;
1817 CPU_ZERO(&pmap->pm_active);
1818 TAILQ_INIT(&pmap->pm_pvchunk);
1819 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1825 * this routine is called if the page table page is not
1829 _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags)
1834 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1835 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1836 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1839 * Allocate a page table page.
1841 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1842 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1843 if (flags & M_WAITOK) {
1845 vm_page_unlock_queues();
1847 vm_page_lock_queues();
1852 * Indicate the need to retry. While waiting, the page table
1853 * page may have been allocated.
1857 if ((m->flags & PG_ZERO) == 0)
1861 * Map the pagetable page into the process address space, if
1862 * it isn't already there.
1865 pmap->pm_stats.resident_count++;
1867 ptepa = VM_PAGE_TO_PHYS(m);
1868 pmap->pm_pdir[ptepindex] =
1869 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1875 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1881 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1882 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1883 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1886 * Calculate pagetable page index
1888 ptepindex = va >> PDRSHIFT;
1891 * Get the page directory entry
1893 ptepa = pmap->pm_pdir[ptepindex];
1896 * This supports switching from a 4MB page to a
1899 if (ptepa & PG_PS) {
1900 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1901 ptepa = pmap->pm_pdir[ptepindex];
1905 * If the page table page is mapped, we just increment the
1906 * hold count, and activate it.
1909 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1913 * Here if the pte page isn't mapped, or if it has
1916 m = _pmap_allocpte(pmap, ptepindex, flags);
1917 if (m == NULL && (flags & M_WAITOK))
1924 /***************************************************
1925 * Pmap allocation/deallocation routines.
1926 ***************************************************/
1930 * Deal with a SMP shootdown of other users of the pmap that we are
1931 * trying to dispose of. This can be a bit hairy.
1933 static cpuset_t *lazymask;
1934 static u_int lazyptd;
1935 static volatile u_int lazywait;
1937 void pmap_lazyfix_action(void);
1940 pmap_lazyfix_action(void)
1944 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1946 if (rcr3() == lazyptd)
1947 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1948 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1949 atomic_store_rel_int(&lazywait, 1);
1953 pmap_lazyfix_self(u_int cpuid)
1956 if (rcr3() == lazyptd)
1957 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1958 CPU_CLR_ATOMIC(cpuid, lazymask);
1963 pmap_lazyfix(pmap_t pmap)
1965 cpuset_t mymask, mask;
1969 mask = pmap->pm_active;
1970 while (!CPU_EMPTY(&mask)) {
1973 /* Find least significant set bit. */
1974 lsb = cpusetobj_ffs(&mask);
1977 CPU_SETOF(lsb, &mask);
1978 mtx_lock_spin(&smp_ipi_mtx);
1980 lazyptd = vtophys(pmap->pm_pdpt);
1982 lazyptd = vtophys(pmap->pm_pdir);
1984 cpuid = PCPU_GET(cpuid);
1986 /* Use a cpuset just for having an easy check. */
1987 CPU_SETOF(cpuid, &mymask);
1988 if (!CPU_CMP(&mask, &mymask)) {
1989 lazymask = &pmap->pm_active;
1990 pmap_lazyfix_self(cpuid);
1992 atomic_store_rel_int((u_int *)&lazymask,
1993 (u_int)&pmap->pm_active);
1994 atomic_store_rel_int(&lazywait, 0);
1995 ipi_selected(mask, IPI_LAZYPMAP);
1996 while (lazywait == 0) {
2002 mtx_unlock_spin(&smp_ipi_mtx);
2004 printf("pmap_lazyfix: spun for 50000000\n");
2005 mask = pmap->pm_active;
2012 * Cleaning up on uniprocessor is easy. For various reasons, we're
2013 * unlikely to have to even execute this code, including the fact
2014 * that the cleanup is deferred until the parent does a wait(2), which
2015 * means that another userland process has run.
2018 pmap_lazyfix(pmap_t pmap)
2022 cr3 = vtophys(pmap->pm_pdir);
2023 if (cr3 == rcr3()) {
2024 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
2025 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2031 * Release any resources held by the given physical map.
2032 * Called when a pmap initialized by pmap_pinit is being released.
2033 * Should only be called if the map contains no valid mappings.
2036 pmap_release(pmap_t pmap)
2038 vm_page_t m, ptdpg[NPGPTD];
2041 KASSERT(pmap->pm_stats.resident_count == 0,
2042 ("pmap_release: pmap resident count %ld != 0",
2043 pmap->pm_stats.resident_count));
2044 KASSERT(pmap->pm_root == NULL,
2045 ("pmap_release: pmap has reserved page table page(s)"));
2048 mtx_lock_spin(&allpmaps_lock);
2049 LIST_REMOVE(pmap, pm_list);
2050 mtx_unlock_spin(&allpmaps_lock);
2052 for (i = 0; i < NPGPTD; i++)
2053 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2056 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2057 sizeof(*pmap->pm_pdir));
2059 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2061 for (i = 0; i < NPGPTD; i++) {
2064 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2065 ("pmap_release: got wrong ptd page"));
2068 atomic_subtract_int(&cnt.v_wire_count, 1);
2069 vm_page_free_zero(m);
2071 PMAP_LOCK_DESTROY(pmap);
2075 kvm_size(SYSCTL_HANDLER_ARGS)
2077 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2079 return (sysctl_handle_long(oidp, &ksize, 0, req));
2081 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2082 0, 0, kvm_size, "IU", "Size of KVM");
2085 kvm_free(SYSCTL_HANDLER_ARGS)
2087 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2089 return (sysctl_handle_long(oidp, &kfree, 0, req));
2091 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2092 0, 0, kvm_free, "IU", "Amount of KVM free");
2095 * grow the number of kernel page table entries, if needed
2098 pmap_growkernel(vm_offset_t addr)
2100 vm_paddr_t ptppaddr;
2104 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2105 addr = roundup2(addr, NBPDR);
2106 if (addr - 1 >= kernel_map->max_offset)
2107 addr = kernel_map->max_offset;
2108 while (kernel_vm_end < addr) {
2109 if (pdir_pde(PTD, kernel_vm_end)) {
2110 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2111 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2112 kernel_vm_end = kernel_map->max_offset;
2118 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2119 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2122 panic("pmap_growkernel: no memory to grow kernel");
2126 if ((nkpg->flags & PG_ZERO) == 0)
2127 pmap_zero_page(nkpg);
2128 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2129 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2130 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2132 pmap_kenter_pde(kernel_vm_end, newpdir);
2133 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2134 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2135 kernel_vm_end = kernel_map->max_offset;
2142 /***************************************************
2143 * page management routines.
2144 ***************************************************/
2146 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2147 CTASSERT(_NPCM == 11);
2148 CTASSERT(_NPCPV == 336);
2150 static __inline struct pv_chunk *
2151 pv_to_chunk(pv_entry_t pv)
2154 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2157 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2159 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2160 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2162 static uint32_t pc_freemask[_NPCM] = {
2163 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2164 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2165 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2166 PC_FREE0_9, PC_FREE10
2169 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2170 "Current number of pv entries");
2173 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2175 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2176 "Current number of pv entry chunks");
2177 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2178 "Current number of pv entry chunks allocated");
2179 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2180 "Current number of pv entry chunks frees");
2181 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2182 "Number of times tried to get a chunk page but failed.");
2184 static long pv_entry_frees, pv_entry_allocs;
2185 static int pv_entry_spare;
2187 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2188 "Current number of pv entry frees");
2189 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2190 "Current number of pv entry allocs");
2191 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2192 "Current number of spare pv entries");
2196 * We are in a serious low memory condition. Resort to
2197 * drastic measures to free some pages so we can allocate
2198 * another pv entry chunk.
2201 pmap_pv_reclaim(pmap_t locked_pmap)
2204 struct pv_chunk *pc;
2205 struct md_page *pvh;
2208 pt_entry_t *pte, tpte;
2211 vm_page_t free, m, m_pc;
2212 uint32_t inuse, freemask;
2213 int bit, field, freed;
2215 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2218 TAILQ_INIT(&newtail);
2220 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2222 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2223 if (pmap != pc->pc_pmap) {
2225 pmap_invalidate_all(pmap);
2226 if (pmap != locked_pmap)
2230 /* Avoid deadlock and lock recursion. */
2231 if (pmap > locked_pmap)
2233 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2235 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2241 * Destroy every non-wired, 4 KB page mapping in the chunk.
2244 for (field = 0; field < _NPCM; field++) {
2246 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2247 inuse != 0; inuse &= ~(1UL << bit)) {
2249 pv = &pc->pc_pventry[field * 32 + bit];
2251 pde = pmap_pde(pmap, va);
2252 if ((*pde & PG_PS) != 0)
2254 pte = pmap_pte_quick(pmap, va);
2255 if ((*pte & PG_W) != 0)
2257 tpte = pte_load_clear(pte);
2258 if ((tpte & PG_G) != 0)
2259 pmap_invalidate_page(pmap, va);
2260 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2261 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2263 if ((tpte & PG_A) != 0)
2264 vm_page_aflag_set(m, PGA_REFERENCED);
2265 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2266 if (TAILQ_EMPTY(&m->md.pv_list) &&
2267 (m->flags & PG_FICTITIOUS) == 0) {
2268 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2269 if (TAILQ_EMPTY(&pvh->pv_list)) {
2270 vm_page_aflag_clear(m,
2274 pmap_unuse_pt(pmap, va, &free);
2275 freemask |= 1UL << bit;
2278 pc->pc_map[field] |= freemask;
2281 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2284 pmap->pm_stats.resident_count -= freed;
2285 PV_STAT(pv_entry_frees += freed);
2286 PV_STAT(pv_entry_spare += freed);
2287 pv_entry_count -= freed;
2288 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2289 for (field = 0; field < _NPCM; field++)
2290 if (pc->pc_map[field] != pc_freemask[field]) {
2291 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2293 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2296 * One freed pv entry in locked_pmap is
2299 if (pmap == locked_pmap)
2303 if (field == _NPCM) {
2304 PV_STAT(pv_entry_spare -= _NPCPV);
2305 PV_STAT(pc_chunk_count--);
2306 PV_STAT(pc_chunk_frees++);
2307 /* Entire chunk is free; return it. */
2308 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2309 pmap_qremove((vm_offset_t)pc, 1);
2310 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2316 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2318 pmap_invalidate_all(pmap);
2319 if (pmap != locked_pmap)
2322 if (m_pc == NULL && pv_vafree != 0 && free != NULL) {
2325 /* Recycle a freed page table page. */
2326 m_pc->wire_count = 1;
2327 atomic_add_int(&cnt.v_wire_count, 1);
2329 pmap_free_zero_pages(free);
2334 * free the pv_entry back to the free list
2337 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2339 struct pv_chunk *pc;
2340 int idx, field, bit;
2342 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2343 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2344 PV_STAT(pv_entry_frees++);
2345 PV_STAT(pv_entry_spare++);
2347 pc = pv_to_chunk(pv);
2348 idx = pv - &pc->pc_pventry[0];
2351 pc->pc_map[field] |= 1ul << bit;
2352 /* move to head of list */
2353 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2354 for (idx = 0; idx < _NPCM; idx++)
2355 if (pc->pc_map[idx] != pc_freemask[idx]) {
2356 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2363 free_pv_chunk(struct pv_chunk *pc)
2367 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2368 PV_STAT(pv_entry_spare -= _NPCPV);
2369 PV_STAT(pc_chunk_count--);
2370 PV_STAT(pc_chunk_frees++);
2371 /* entire chunk is free, return it */
2372 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2373 pmap_qremove((vm_offset_t)pc, 1);
2374 vm_page_unwire(m, 0);
2376 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2380 * get a new pv_entry, allocating a block from the system
2384 get_pv_entry(pmap_t pmap, boolean_t try)
2386 static const struct timeval printinterval = { 60, 0 };
2387 static struct timeval lastprint;
2390 struct pv_chunk *pc;
2393 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2394 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2395 PV_STAT(pv_entry_allocs++);
2397 if (pv_entry_count > pv_entry_high_water)
2398 if (ratecheck(&lastprint, &printinterval))
2399 printf("Approaching the limit on PV entries, consider "
2400 "increasing either the vm.pmap.shpgperproc or the "
2401 "vm.pmap.pv_entry_max tunable.\n");
2403 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2405 for (field = 0; field < _NPCM; field++) {
2406 if (pc->pc_map[field]) {
2407 bit = bsfl(pc->pc_map[field]);
2411 if (field < _NPCM) {
2412 pv = &pc->pc_pventry[field * 32 + bit];
2413 pc->pc_map[field] &= ~(1ul << bit);
2414 /* If this was the last item, move it to tail */
2415 for (field = 0; field < _NPCM; field++)
2416 if (pc->pc_map[field] != 0) {
2417 PV_STAT(pv_entry_spare--);
2418 return (pv); /* not full, return */
2420 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2421 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2422 if (pc != TAILQ_LAST(&pv_chunks, pch)) {
2423 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2424 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2426 PV_STAT(pv_entry_spare--);
2431 * Access to the ptelist "pv_vafree" is synchronized by the page
2432 * queues lock. If "pv_vafree" is currently non-empty, it will
2433 * remain non-empty until pmap_ptelist_alloc() completes.
2435 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2436 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2439 PV_STAT(pc_chunk_tryfail++);
2442 m = pmap_pv_reclaim(pmap);
2446 PV_STAT(pc_chunk_count++);
2447 PV_STAT(pc_chunk_allocs++);
2448 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2449 pmap_qenter((vm_offset_t)pc, &m, 1);
2451 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2452 for (field = 1; field < _NPCM; field++)
2453 pc->pc_map[field] = pc_freemask[field];
2454 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2455 pv = &pc->pc_pventry[0];
2456 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2457 PV_STAT(pv_entry_spare += _NPCPV - 1);
2461 static __inline pv_entry_t
2462 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2466 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2467 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2468 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2469 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2477 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2479 struct md_page *pvh;
2481 vm_offset_t va_last;
2484 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2485 KASSERT((pa & PDRMASK) == 0,
2486 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2489 * Transfer the 4mpage's pv entry for this mapping to the first
2492 pvh = pa_to_pvh(pa);
2493 va = trunc_4mpage(va);
2494 pv = pmap_pvh_remove(pvh, pmap, va);
2495 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2496 m = PHYS_TO_VM_PAGE(pa);
2497 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2498 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2499 va_last = va + NBPDR - PAGE_SIZE;
2502 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2503 ("pmap_pv_demote_pde: page %p is not managed", m));
2505 pmap_insert_entry(pmap, va, m);
2506 } while (va < va_last);
2510 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2512 struct md_page *pvh;
2514 vm_offset_t va_last;
2517 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2518 KASSERT((pa & PDRMASK) == 0,
2519 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2522 * Transfer the first page's pv entry for this mapping to the
2523 * 4mpage's pv list. Aside from avoiding the cost of a call
2524 * to get_pv_entry(), a transfer avoids the possibility that
2525 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2526 * removes one of the mappings that is being promoted.
2528 m = PHYS_TO_VM_PAGE(pa);
2529 va = trunc_4mpage(va);
2530 pv = pmap_pvh_remove(&m->md, pmap, va);
2531 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2532 pvh = pa_to_pvh(pa);
2533 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2534 /* Free the remaining NPTEPG - 1 pv entries. */
2535 va_last = va + NBPDR - PAGE_SIZE;
2539 pmap_pvh_free(&m->md, pmap, va);
2540 } while (va < va_last);
2544 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2548 pv = pmap_pvh_remove(pvh, pmap, va);
2549 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2550 free_pv_entry(pmap, pv);
2554 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2556 struct md_page *pvh;
2558 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2559 pmap_pvh_free(&m->md, pmap, va);
2560 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2561 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2562 if (TAILQ_EMPTY(&pvh->pv_list))
2563 vm_page_aflag_clear(m, PGA_WRITEABLE);
2568 * Create a pv entry for page at pa for
2572 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2576 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2577 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2578 pv = get_pv_entry(pmap, FALSE);
2580 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2584 * Conditionally create a pv entry.
2587 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2591 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2592 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2593 if (pv_entry_count < pv_entry_high_water &&
2594 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2596 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2603 * Create the pv entries for each of the pages within a superpage.
2606 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2608 struct md_page *pvh;
2611 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2612 if (pv_entry_count < pv_entry_high_water &&
2613 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2615 pvh = pa_to_pvh(pa);
2616 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2623 * Fills a page table page with mappings to consecutive physical pages.
2626 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2630 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2632 newpte += PAGE_SIZE;
2637 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2638 * 2- or 4MB page mapping is invalidated.
2641 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2643 pd_entry_t newpde, oldpde;
2644 pt_entry_t *firstpte, newpte;
2646 vm_page_t free, mpte;
2648 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2650 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2651 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2652 mpte = pmap_lookup_pt_page(pmap, va);
2654 pmap_remove_pt_page(pmap, mpte);
2656 KASSERT((oldpde & PG_W) == 0,
2657 ("pmap_demote_pde: page table page for a wired mapping"
2661 * Invalidate the 2- or 4MB page mapping and return
2662 * "failure" if the mapping was never accessed or the
2663 * allocation of the new page table page fails.
2665 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2666 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2667 VM_ALLOC_WIRED)) == NULL) {
2669 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2670 pmap_invalidate_page(pmap, trunc_4mpage(va));
2671 pmap_free_zero_pages(free);
2672 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2673 " in pmap %p", va, pmap);
2676 if (va < VM_MAXUSER_ADDRESS)
2677 pmap->pm_stats.resident_count++;
2679 mptepa = VM_PAGE_TO_PHYS(mpte);
2682 * If the page mapping is in the kernel's address space, then the
2683 * KPTmap can provide access to the page table page. Otherwise,
2684 * temporarily map the page table page (mpte) into the kernel's
2685 * address space at either PADDR1 or PADDR2.
2688 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2689 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) {
2690 if ((*PMAP1 & PG_FRAME) != mptepa) {
2691 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2693 PMAP1cpu = PCPU_GET(cpuid);
2699 if (PMAP1cpu != PCPU_GET(cpuid)) {
2700 PMAP1cpu = PCPU_GET(cpuid);
2708 mtx_lock(&PMAP2mutex);
2709 if ((*PMAP2 & PG_FRAME) != mptepa) {
2710 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2711 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2715 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2716 KASSERT((oldpde & PG_A) != 0,
2717 ("pmap_demote_pde: oldpde is missing PG_A"));
2718 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2719 ("pmap_demote_pde: oldpde is missing PG_M"));
2720 newpte = oldpde & ~PG_PS;
2721 if ((newpte & PG_PDE_PAT) != 0)
2722 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2725 * If the page table page is new, initialize it.
2727 if (mpte->wire_count == 1) {
2728 mpte->wire_count = NPTEPG;
2729 pmap_fill_ptp(firstpte, newpte);
2731 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2732 ("pmap_demote_pde: firstpte and newpte map different physical"
2736 * If the mapping has changed attributes, update the page table
2739 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2740 pmap_fill_ptp(firstpte, newpte);
2743 * Demote the mapping. This pmap is locked. The old PDE has
2744 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2745 * set. Thus, there is no danger of a race with another
2746 * processor changing the setting of PG_A and/or PG_M between
2747 * the read above and the store below.
2749 if (workaround_erratum383)
2750 pmap_update_pde(pmap, va, pde, newpde);
2751 else if (pmap == kernel_pmap)
2752 pmap_kenter_pde(va, newpde);
2754 pde_store(pde, newpde);
2755 if (firstpte == PADDR2)
2756 mtx_unlock(&PMAP2mutex);
2759 * Invalidate the recursive mapping of the page table page.
2761 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2764 * Demote the pv entry. This depends on the earlier demotion
2765 * of the mapping. Specifically, the (re)creation of a per-
2766 * page pv entry might trigger the execution of pmap_collect(),
2767 * which might reclaim a newly (re)created per-page pv entry
2768 * and destroy the associated mapping. In order to destroy
2769 * the mapping, the PDE must have already changed from mapping
2770 * the 2mpage to referencing the page table page.
2772 if ((oldpde & PG_MANAGED) != 0)
2773 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2775 pmap_pde_demotions++;
2776 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2777 " in pmap %p", va, pmap);
2782 * pmap_remove_pde: do the things to unmap a superpage in a process
2785 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2788 struct md_page *pvh;
2790 vm_offset_t eva, va;
2793 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2794 KASSERT((sva & PDRMASK) == 0,
2795 ("pmap_remove_pde: sva is not 4mpage aligned"));
2796 oldpde = pte_load_clear(pdq);
2798 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2801 * Machines that don't support invlpg, also don't support
2805 pmap_invalidate_page(kernel_pmap, sva);
2806 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2807 if (oldpde & PG_MANAGED) {
2808 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2809 pmap_pvh_free(pvh, pmap, sva);
2811 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2812 va < eva; va += PAGE_SIZE, m++) {
2813 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2816 vm_page_aflag_set(m, PGA_REFERENCED);
2817 if (TAILQ_EMPTY(&m->md.pv_list) &&
2818 TAILQ_EMPTY(&pvh->pv_list))
2819 vm_page_aflag_clear(m, PGA_WRITEABLE);
2822 if (pmap == kernel_pmap) {
2823 if (!pmap_demote_pde(pmap, pdq, sva))
2824 panic("pmap_remove_pde: failed demotion");
2826 mpte = pmap_lookup_pt_page(pmap, sva);
2828 pmap_remove_pt_page(pmap, mpte);
2829 pmap->pm_stats.resident_count--;
2830 KASSERT(mpte->wire_count == NPTEPG,
2831 ("pmap_remove_pde: pte page wire count error"));
2832 mpte->wire_count = 0;
2833 pmap_add_delayed_free_list(mpte, free, FALSE);
2834 atomic_subtract_int(&cnt.v_wire_count, 1);
2840 * pmap_remove_pte: do the things to unmap a page in a process
2843 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2848 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2849 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2850 oldpte = pte_load_clear(ptq);
2852 pmap->pm_stats.wired_count -= 1;
2854 * Machines that don't support invlpg, also don't support
2858 pmap_invalidate_page(kernel_pmap, va);
2859 pmap->pm_stats.resident_count -= 1;
2860 if (oldpte & PG_MANAGED) {
2861 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2862 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2865 vm_page_aflag_set(m, PGA_REFERENCED);
2866 pmap_remove_entry(pmap, m, va);
2868 return (pmap_unuse_pt(pmap, va, free));
2872 * Remove a single page from a process address space
2875 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2879 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2880 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2881 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2882 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2884 pmap_remove_pte(pmap, pte, va, free);
2885 pmap_invalidate_page(pmap, va);
2889 * Remove the given range of addresses from the specified map.
2891 * It is assumed that the start and end are properly
2892 * rounded to the page size.
2895 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2900 vm_page_t free = NULL;
2904 * Perform an unsynchronized read. This is, however, safe.
2906 if (pmap->pm_stats.resident_count == 0)
2911 vm_page_lock_queues();
2916 * special handling of removing one page. a very
2917 * common operation and easy to short circuit some
2920 if ((sva + PAGE_SIZE == eva) &&
2921 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2922 pmap_remove_page(pmap, sva, &free);
2926 for (; sva < eva; sva = pdnxt) {
2930 * Calculate index for next page table.
2932 pdnxt = (sva + NBPDR) & ~PDRMASK;
2935 if (pmap->pm_stats.resident_count == 0)
2938 pdirindex = sva >> PDRSHIFT;
2939 ptpaddr = pmap->pm_pdir[pdirindex];
2942 * Weed out invalid mappings. Note: we assume that the page
2943 * directory table is always allocated, and in kernel virtual.
2949 * Check for large page.
2951 if ((ptpaddr & PG_PS) != 0) {
2953 * Are we removing the entire large page? If not,
2954 * demote the mapping and fall through.
2956 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2958 * The TLB entry for a PG_G mapping is
2959 * invalidated by pmap_remove_pde().
2961 if ((ptpaddr & PG_G) == 0)
2963 pmap_remove_pde(pmap,
2964 &pmap->pm_pdir[pdirindex], sva, &free);
2966 } else if (!pmap_demote_pde(pmap,
2967 &pmap->pm_pdir[pdirindex], sva)) {
2968 /* The large page mapping was destroyed. */
2974 * Limit our scan to either the end of the va represented
2975 * by the current page table page, or to the end of the
2976 * range being removed.
2981 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2987 * The TLB entry for a PG_G mapping is invalidated
2988 * by pmap_remove_pte().
2990 if ((*pte & PG_G) == 0)
2992 if (pmap_remove_pte(pmap, pte, sva, &free))
2999 pmap_invalidate_all(pmap);
3000 vm_page_unlock_queues();
3002 pmap_free_zero_pages(free);
3006 * Routine: pmap_remove_all
3008 * Removes this physical page from
3009 * all physical maps in which it resides.
3010 * Reflects back modify bits to the pager.
3013 * Original versions of this routine were very
3014 * inefficient because they iteratively called
3015 * pmap_remove (slow...)
3019 pmap_remove_all(vm_page_t m)
3021 struct md_page *pvh;
3024 pt_entry_t *pte, tpte;
3029 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3030 ("pmap_remove_all: page %p is not managed", m));
3032 vm_page_lock_queues();
3034 if ((m->flags & PG_FICTITIOUS) != 0)
3035 goto small_mappings;
3036 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3037 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3041 pde = pmap_pde(pmap, va);
3042 (void)pmap_demote_pde(pmap, pde, va);
3046 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3049 pmap->pm_stats.resident_count--;
3050 pde = pmap_pde(pmap, pv->pv_va);
3051 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3052 " a 4mpage in page %p's pv list", m));
3053 pte = pmap_pte_quick(pmap, pv->pv_va);
3054 tpte = pte_load_clear(pte);
3056 pmap->pm_stats.wired_count--;
3058 vm_page_aflag_set(m, PGA_REFERENCED);
3061 * Update the vm_page_t clean and reference bits.
3063 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3065 pmap_unuse_pt(pmap, pv->pv_va, &free);
3066 pmap_invalidate_page(pmap, pv->pv_va);
3067 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3068 free_pv_entry(pmap, pv);
3071 vm_page_aflag_clear(m, PGA_WRITEABLE);
3073 vm_page_unlock_queues();
3074 pmap_free_zero_pages(free);
3078 * pmap_protect_pde: do the things to protect a 4mpage in a process
3081 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3083 pd_entry_t newpde, oldpde;
3084 vm_offset_t eva, va;
3086 boolean_t anychanged;
3088 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3089 KASSERT((sva & PDRMASK) == 0,
3090 ("pmap_protect_pde: sva is not 4mpage aligned"));
3093 oldpde = newpde = *pde;
3094 if (oldpde & PG_MANAGED) {
3096 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3097 va < eva; va += PAGE_SIZE, m++)
3098 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3101 if ((prot & VM_PROT_WRITE) == 0)
3102 newpde &= ~(PG_RW | PG_M);
3104 if ((prot & VM_PROT_EXECUTE) == 0)
3107 if (newpde != oldpde) {
3108 if (!pde_cmpset(pde, oldpde, newpde))
3111 pmap_invalidate_page(pmap, sva);
3115 return (anychanged);
3119 * Set the physical protection on the
3120 * specified range of this map as requested.
3123 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3130 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3131 pmap_remove(pmap, sva, eva);
3136 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3137 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3140 if (prot & VM_PROT_WRITE)
3146 vm_page_lock_queues();
3149 for (; sva < eva; sva = pdnxt) {
3150 pt_entry_t obits, pbits;
3153 pdnxt = (sva + NBPDR) & ~PDRMASK;
3157 pdirindex = sva >> PDRSHIFT;
3158 ptpaddr = pmap->pm_pdir[pdirindex];
3161 * Weed out invalid mappings. Note: we assume that the page
3162 * directory table is always allocated, and in kernel virtual.
3168 * Check for large page.
3170 if ((ptpaddr & PG_PS) != 0) {
3172 * Are we protecting the entire large page? If not,
3173 * demote the mapping and fall through.
3175 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3177 * The TLB entry for a PG_G mapping is
3178 * invalidated by pmap_protect_pde().
3180 if (pmap_protect_pde(pmap,
3181 &pmap->pm_pdir[pdirindex], sva, prot))
3184 } else if (!pmap_demote_pde(pmap,
3185 &pmap->pm_pdir[pdirindex], sva)) {
3186 /* The large page mapping was destroyed. */
3194 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3200 * Regardless of whether a pte is 32 or 64 bits in
3201 * size, PG_RW, PG_A, and PG_M are among the least
3202 * significant 32 bits.
3204 obits = pbits = *pte;
3205 if ((pbits & PG_V) == 0)
3208 if ((prot & VM_PROT_WRITE) == 0) {
3209 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3210 (PG_MANAGED | PG_M | PG_RW)) {
3211 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3214 pbits &= ~(PG_RW | PG_M);
3217 if ((prot & VM_PROT_EXECUTE) == 0)
3221 if (pbits != obits) {
3223 if (!atomic_cmpset_64(pte, obits, pbits))
3226 if (!atomic_cmpset_int((u_int *)pte, obits,
3231 pmap_invalidate_page(pmap, sva);
3239 pmap_invalidate_all(pmap);
3240 vm_page_unlock_queues();
3245 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3246 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3247 * For promotion to occur, two conditions must be met: (1) the 4KB page
3248 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3249 * mappings must have identical characteristics.
3251 * Managed (PG_MANAGED) mappings within the kernel address space are not
3252 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3253 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3257 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3260 pt_entry_t *firstpte, oldpte, pa, *pte;
3261 vm_offset_t oldpteva;
3264 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3267 * Examine the first PTE in the specified PTP. Abort if this PTE is
3268 * either invalid, unused, or does not map the first 4KB physical page
3269 * within a 2- or 4MB page.
3271 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3274 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3275 pmap_pde_p_failures++;
3276 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3277 " in pmap %p", va, pmap);
3280 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3281 pmap_pde_p_failures++;
3282 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3283 " in pmap %p", va, pmap);
3286 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3288 * When PG_M is already clear, PG_RW can be cleared without
3289 * a TLB invalidation.
3291 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3298 * Examine each of the other PTEs in the specified PTP. Abort if this
3299 * PTE maps an unexpected 4KB physical page or does not have identical
3300 * characteristics to the first PTE.
3302 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3303 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3306 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3307 pmap_pde_p_failures++;
3308 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3309 " in pmap %p", va, pmap);
3312 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3314 * When PG_M is already clear, PG_RW can be cleared
3315 * without a TLB invalidation.
3317 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3321 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3323 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3324 " in pmap %p", oldpteva, pmap);
3326 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3327 pmap_pde_p_failures++;
3328 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3329 " in pmap %p", va, pmap);
3336 * Save the page table page in its current state until the PDE
3337 * mapping the superpage is demoted by pmap_demote_pde() or
3338 * destroyed by pmap_remove_pde().
3340 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3341 KASSERT(mpte >= vm_page_array &&
3342 mpte < &vm_page_array[vm_page_array_size],
3343 ("pmap_promote_pde: page table page is out of range"));
3344 KASSERT(mpte->pindex == va >> PDRSHIFT,
3345 ("pmap_promote_pde: page table page's pindex is wrong"));
3346 pmap_insert_pt_page(pmap, mpte);
3349 * Promote the pv entries.
3351 if ((newpde & PG_MANAGED) != 0)
3352 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3355 * Propagate the PAT index to its proper position.
3357 if ((newpde & PG_PTE_PAT) != 0)
3358 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3361 * Map the superpage.
3363 if (workaround_erratum383)
3364 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3365 else if (pmap == kernel_pmap)
3366 pmap_kenter_pde(va, PG_PS | newpde);
3368 pde_store(pde, PG_PS | newpde);
3370 pmap_pde_promotions++;
3371 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3372 " in pmap %p", va, pmap);
3376 * Insert the given physical page (p) at
3377 * the specified virtual address (v) in the
3378 * target physical map with the protection requested.
3380 * If specified, the page will be wired down, meaning
3381 * that the related pte can not be reclaimed.
3383 * NB: This is the only routine which MAY NOT lazy-evaluate
3384 * or lose information. That is, this routine must actually
3385 * insert this page into the given map NOW.
3388 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3389 vm_prot_t prot, boolean_t wired)
3393 pt_entry_t newpte, origpte;
3399 va = trunc_page(va);
3400 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3401 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3402 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3404 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3405 VM_OBJECT_LOCKED(m->object),
3406 ("pmap_enter: page %p is not busy", m));
3410 vm_page_lock_queues();
3415 * In the case that a page table page is not
3416 * resident, we are creating it here.
3418 if (va < VM_MAXUSER_ADDRESS) {
3419 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3422 pde = pmap_pde(pmap, va);
3423 if ((*pde & PG_PS) != 0)
3424 panic("pmap_enter: attempted pmap_enter on 4MB page");
3425 pte = pmap_pte_quick(pmap, va);
3428 * Page Directory table entry not valid, we need a new PT page
3431 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3432 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3435 pa = VM_PAGE_TO_PHYS(m);
3438 opa = origpte & PG_FRAME;
3441 * Mapping has not changed, must be protection or wiring change.
3443 if (origpte && (opa == pa)) {
3445 * Wiring change, just update stats. We don't worry about
3446 * wiring PT pages as they remain resident as long as there
3447 * are valid mappings in them. Hence, if a user page is wired,
3448 * the PT page will be also.
3450 if (wired && ((origpte & PG_W) == 0))
3451 pmap->pm_stats.wired_count++;
3452 else if (!wired && (origpte & PG_W))
3453 pmap->pm_stats.wired_count--;
3456 * Remove extra pte reference
3461 if (origpte & PG_MANAGED) {
3471 * Mapping has changed, invalidate old range and fall through to
3472 * handle validating new mapping.
3476 pmap->pm_stats.wired_count--;
3477 if (origpte & PG_MANAGED) {
3478 om = PHYS_TO_VM_PAGE(opa);
3479 pv = pmap_pvh_remove(&om->md, pmap, va);
3483 KASSERT(mpte->wire_count > 0,
3484 ("pmap_enter: missing reference to page table page,"
3488 pmap->pm_stats.resident_count++;
3491 * Enter on the PV list if part of our managed memory.
3493 if ((m->oflags & VPO_UNMANAGED) == 0) {
3494 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3495 ("pmap_enter: managed mapping within the clean submap"));
3497 pv = get_pv_entry(pmap, FALSE);
3499 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3501 } else if (pv != NULL)
3502 free_pv_entry(pmap, pv);
3505 * Increment counters
3508 pmap->pm_stats.wired_count++;
3512 * Now validate mapping with desired protection/wiring.
3514 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3515 if ((prot & VM_PROT_WRITE) != 0) {
3517 if ((newpte & PG_MANAGED) != 0)
3518 vm_page_aflag_set(m, PGA_WRITEABLE);
3521 if ((prot & VM_PROT_EXECUTE) == 0)
3526 if (va < VM_MAXUSER_ADDRESS)
3528 if (pmap == kernel_pmap)
3532 * if the mapping or permission bits are different, we need
3533 * to update the pte.
3535 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3537 if ((access & VM_PROT_WRITE) != 0)
3539 if (origpte & PG_V) {
3541 origpte = pte_load_store(pte, newpte);
3542 if (origpte & PG_A) {
3543 if (origpte & PG_MANAGED)
3544 vm_page_aflag_set(om, PGA_REFERENCED);
3545 if (opa != VM_PAGE_TO_PHYS(m))
3548 if ((origpte & PG_NX) == 0 &&
3549 (newpte & PG_NX) != 0)
3553 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3554 if ((origpte & PG_MANAGED) != 0)
3556 if ((prot & VM_PROT_WRITE) == 0)
3559 if ((origpte & PG_MANAGED) != 0 &&
3560 TAILQ_EMPTY(&om->md.pv_list) &&
3561 ((om->flags & PG_FICTITIOUS) != 0 ||
3562 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3563 vm_page_aflag_clear(om, PGA_WRITEABLE);
3565 pmap_invalidate_page(pmap, va);
3567 pte_store(pte, newpte);
3571 * If both the page table page and the reservation are fully
3572 * populated, then attempt promotion.
3574 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3575 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3576 vm_reserv_level_iffullpop(m) == 0)
3577 pmap_promote_pde(pmap, pde, va);
3580 vm_page_unlock_queues();
3585 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3586 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3587 * blocking, (2) a mapping already exists at the specified virtual address, or
3588 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3591 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3593 pd_entry_t *pde, newpde;
3595 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3596 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3597 pde = pmap_pde(pmap, va);
3599 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3600 " in pmap %p", va, pmap);
3603 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3605 if ((m->oflags & VPO_UNMANAGED) == 0) {
3606 newpde |= PG_MANAGED;
3609 * Abort this mapping if its PV entry could not be created.
3611 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3612 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3613 " in pmap %p", va, pmap);
3618 if ((prot & VM_PROT_EXECUTE) == 0)
3621 if (va < VM_MAXUSER_ADDRESS)
3625 * Increment counters.
3627 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3630 * Map the superpage.
3632 pde_store(pde, newpde);
3634 pmap_pde_mappings++;
3635 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3636 " in pmap %p", va, pmap);
3641 * Maps a sequence of resident pages belonging to the same object.
3642 * The sequence begins with the given page m_start. This page is
3643 * mapped at the given virtual address start. Each subsequent page is
3644 * mapped at a virtual address that is offset from start by the same
3645 * amount as the page is offset from m_start within the object. The
3646 * last page in the sequence is the page with the largest offset from
3647 * m_start that can be mapped at a virtual address less than the given
3648 * virtual address end. Not every virtual page between start and end
3649 * is mapped; only those for which a resident page exists with the
3650 * corresponding offset from m_start are mapped.
3653 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3654 vm_page_t m_start, vm_prot_t prot)
3658 vm_pindex_t diff, psize;
3660 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3661 psize = atop(end - start);
3664 vm_page_lock_queues();
3666 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3667 va = start + ptoa(diff);
3668 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3669 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3670 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3671 pmap_enter_pde(pmap, va, m, prot))
3672 m = &m[NBPDR / PAGE_SIZE - 1];
3674 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3676 m = TAILQ_NEXT(m, listq);
3678 vm_page_unlock_queues();
3683 * this code makes some *MAJOR* assumptions:
3684 * 1. Current pmap & pmap exists.
3687 * 4. No page table pages.
3688 * but is *MUCH* faster than pmap_enter...
3692 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3695 vm_page_lock_queues();
3697 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3698 vm_page_unlock_queues();
3703 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3704 vm_prot_t prot, vm_page_t mpte)
3710 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3711 (m->oflags & VPO_UNMANAGED) != 0,
3712 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3713 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3714 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3717 * In the case that a page table page is not
3718 * resident, we are creating it here.
3720 if (va < VM_MAXUSER_ADDRESS) {
3725 * Calculate pagetable page index
3727 ptepindex = va >> PDRSHIFT;
3728 if (mpte && (mpte->pindex == ptepindex)) {
3732 * Get the page directory entry
3734 ptepa = pmap->pm_pdir[ptepindex];
3737 * If the page table page is mapped, we just increment
3738 * the hold count, and activate it.
3743 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3746 mpte = _pmap_allocpte(pmap, ptepindex,
3757 * This call to vtopte makes the assumption that we are
3758 * entering the page into the current pmap. In order to support
3759 * quick entry into any pmap, one would likely use pmap_pte_quick.
3760 * But that isn't as quick as vtopte.
3772 * Enter on the PV list if part of our managed memory.
3774 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3775 !pmap_try_insert_pv_entry(pmap, va, m)) {
3778 if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
3779 pmap_invalidate_page(pmap, va);
3780 pmap_free_zero_pages(free);
3789 * Increment counters
3791 pmap->pm_stats.resident_count++;
3793 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3795 if ((prot & VM_PROT_EXECUTE) == 0)
3800 * Now validate mapping with RO protection
3802 if ((m->oflags & VPO_UNMANAGED) != 0)
3803 pte_store(pte, pa | PG_V | PG_U);
3805 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3810 * Make a temporary mapping for a physical address. This is only intended
3811 * to be used for panic dumps.
3814 pmap_kenter_temporary(vm_paddr_t pa, int i)
3818 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3819 pmap_kenter(va, pa);
3821 return ((void *)crashdumpmap);
3825 * This code maps large physical mmap regions into the
3826 * processor address space. Note that some shortcuts
3827 * are taken, but the code works.
3830 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3831 vm_pindex_t pindex, vm_size_t size)
3834 vm_paddr_t pa, ptepa;
3838 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3839 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3840 ("pmap_object_init_pt: non-device object"));
3842 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3843 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3845 p = vm_page_lookup(object, pindex);
3846 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3847 ("pmap_object_init_pt: invalid page %p", p));
3848 pat_mode = p->md.pat_mode;
3851 * Abort the mapping if the first page is not physically
3852 * aligned to a 2/4MB page boundary.
3854 ptepa = VM_PAGE_TO_PHYS(p);
3855 if (ptepa & (NBPDR - 1))
3859 * Skip the first page. Abort the mapping if the rest of
3860 * the pages are not physically contiguous or have differing
3861 * memory attributes.
3863 p = TAILQ_NEXT(p, listq);
3864 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3866 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3867 ("pmap_object_init_pt: invalid page %p", p));
3868 if (pa != VM_PAGE_TO_PHYS(p) ||
3869 pat_mode != p->md.pat_mode)
3871 p = TAILQ_NEXT(p, listq);
3875 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3876 * "size" is a multiple of 2/4M, adding the PAT setting to
3877 * "pa" will not affect the termination of this loop.
3880 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3881 size; pa += NBPDR) {
3882 pde = pmap_pde(pmap, addr);
3884 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3885 PG_U | PG_RW | PG_V);
3886 pmap->pm_stats.resident_count += NBPDR /
3888 pmap_pde_mappings++;
3890 /* Else continue on if the PDE is already valid. */
3898 * Routine: pmap_change_wiring
3899 * Function: Change the wiring attribute for a map/virtual-address
3901 * In/out conditions:
3902 * The mapping must already exist in the pmap.
3905 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3909 boolean_t are_queues_locked;
3911 are_queues_locked = FALSE;
3914 pde = pmap_pde(pmap, va);
3915 if ((*pde & PG_PS) != 0) {
3916 if (!wired != ((*pde & PG_W) == 0)) {
3917 if (!are_queues_locked) {
3918 are_queues_locked = TRUE;
3919 if (!mtx_trylock(&vm_page_queue_mtx)) {
3921 vm_page_lock_queues();
3925 if (!pmap_demote_pde(pmap, pde, va))
3926 panic("pmap_change_wiring: demotion failed");
3930 pte = pmap_pte(pmap, va);
3932 if (wired && !pmap_pte_w(pte))
3933 pmap->pm_stats.wired_count++;
3934 else if (!wired && pmap_pte_w(pte))
3935 pmap->pm_stats.wired_count--;
3938 * Wiring is not a hardware characteristic so there is no need to
3941 pmap_pte_set_w(pte, wired);
3942 pmap_pte_release(pte);
3944 if (are_queues_locked)
3945 vm_page_unlock_queues();
3952 * Copy the range specified by src_addr/len
3953 * from the source map to the range dst_addr/len
3954 * in the destination map.
3956 * This routine is only advisory and need not do anything.
3960 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3961 vm_offset_t src_addr)
3965 vm_offset_t end_addr = src_addr + len;
3968 if (dst_addr != src_addr)
3971 if (!pmap_is_current(src_pmap))
3974 vm_page_lock_queues();
3975 if (dst_pmap < src_pmap) {
3976 PMAP_LOCK(dst_pmap);
3977 PMAP_LOCK(src_pmap);
3979 PMAP_LOCK(src_pmap);
3980 PMAP_LOCK(dst_pmap);
3983 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3984 pt_entry_t *src_pte, *dst_pte;
3985 vm_page_t dstmpte, srcmpte;
3986 pd_entry_t srcptepaddr;
3989 KASSERT(addr < UPT_MIN_ADDRESS,
3990 ("pmap_copy: invalid to pmap_copy page tables"));
3992 pdnxt = (addr + NBPDR) & ~PDRMASK;
3995 ptepindex = addr >> PDRSHIFT;
3997 srcptepaddr = src_pmap->pm_pdir[ptepindex];
3998 if (srcptepaddr == 0)
4001 if (srcptepaddr & PG_PS) {
4002 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4003 ((srcptepaddr & PG_MANAGED) == 0 ||
4004 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4006 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4008 dst_pmap->pm_stats.resident_count +=
4014 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4015 KASSERT(srcmpte->wire_count > 0,
4016 ("pmap_copy: source page table page is unused"));
4018 if (pdnxt > end_addr)
4021 src_pte = vtopte(addr);
4022 while (addr < pdnxt) {
4026 * we only virtual copy managed pages
4028 if ((ptetemp & PG_MANAGED) != 0) {
4029 dstmpte = pmap_allocpte(dst_pmap, addr,
4031 if (dstmpte == NULL)
4033 dst_pte = pmap_pte_quick(dst_pmap, addr);
4034 if (*dst_pte == 0 &&
4035 pmap_try_insert_pv_entry(dst_pmap, addr,
4036 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4038 * Clear the wired, modified, and
4039 * accessed (referenced) bits
4042 *dst_pte = ptetemp & ~(PG_W | PG_M |
4044 dst_pmap->pm_stats.resident_count++;
4047 if (pmap_unwire_pte_hold(dst_pmap,
4049 pmap_invalidate_page(dst_pmap,
4051 pmap_free_zero_pages(free);
4055 if (dstmpte->wire_count >= srcmpte->wire_count)
4064 vm_page_unlock_queues();
4065 PMAP_UNLOCK(src_pmap);
4066 PMAP_UNLOCK(dst_pmap);
4069 static __inline void
4070 pagezero(void *page)
4072 #if defined(I686_CPU)
4073 if (cpu_class == CPUCLASS_686) {
4074 #if defined(CPU_ENABLE_SSE)
4075 if (cpu_feature & CPUID_SSE2)
4076 sse2_pagezero(page);
4079 i686_pagezero(page);
4082 bzero(page, PAGE_SIZE);
4086 * pmap_zero_page zeros the specified hardware page by mapping
4087 * the page into KVM and using bzero to clear its contents.
4090 pmap_zero_page(vm_page_t m)
4092 struct sysmaps *sysmaps;
4094 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4095 mtx_lock(&sysmaps->lock);
4096 if (*sysmaps->CMAP2)
4097 panic("pmap_zero_page: CMAP2 busy");
4099 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4100 pmap_cache_bits(m->md.pat_mode, 0);
4101 invlcaddr(sysmaps->CADDR2);
4102 pagezero(sysmaps->CADDR2);
4103 *sysmaps->CMAP2 = 0;
4105 mtx_unlock(&sysmaps->lock);
4109 * pmap_zero_page_area zeros the specified hardware page by mapping
4110 * the page into KVM and using bzero to clear its contents.
4112 * off and size may not cover an area beyond a single hardware page.
4115 pmap_zero_page_area(vm_page_t m, int off, int size)
4117 struct sysmaps *sysmaps;
4119 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4120 mtx_lock(&sysmaps->lock);
4121 if (*sysmaps->CMAP2)
4122 panic("pmap_zero_page_area: CMAP2 busy");
4124 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4125 pmap_cache_bits(m->md.pat_mode, 0);
4126 invlcaddr(sysmaps->CADDR2);
4127 if (off == 0 && size == PAGE_SIZE)
4128 pagezero(sysmaps->CADDR2);
4130 bzero((char *)sysmaps->CADDR2 + off, size);
4131 *sysmaps->CMAP2 = 0;
4133 mtx_unlock(&sysmaps->lock);
4137 * pmap_zero_page_idle zeros the specified hardware page by mapping
4138 * the page into KVM and using bzero to clear its contents. This
4139 * is intended to be called from the vm_pagezero process only and
4143 pmap_zero_page_idle(vm_page_t m)
4147 panic("pmap_zero_page_idle: CMAP3 busy");
4149 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4150 pmap_cache_bits(m->md.pat_mode, 0);
4158 * pmap_copy_page copies the specified (machine independent)
4159 * page by mapping the page into virtual memory and using
4160 * bcopy to copy the page, one machine dependent page at a
4164 pmap_copy_page(vm_page_t src, vm_page_t dst)
4166 struct sysmaps *sysmaps;
4168 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4169 mtx_lock(&sysmaps->lock);
4170 if (*sysmaps->CMAP1)
4171 panic("pmap_copy_page: CMAP1 busy");
4172 if (*sysmaps->CMAP2)
4173 panic("pmap_copy_page: CMAP2 busy");
4175 invlpg((u_int)sysmaps->CADDR1);
4176 invlpg((u_int)sysmaps->CADDR2);
4177 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4178 pmap_cache_bits(src->md.pat_mode, 0);
4179 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4180 pmap_cache_bits(dst->md.pat_mode, 0);
4181 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4182 *sysmaps->CMAP1 = 0;
4183 *sysmaps->CMAP2 = 0;
4185 mtx_unlock(&sysmaps->lock);
4189 * Returns true if the pmap's pv is one of the first
4190 * 16 pvs linked to from this page. This count may
4191 * be changed upwards or downwards in the future; it
4192 * is only necessary that true be returned for a small
4193 * subset of pmaps for proper page aging.
4196 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4198 struct md_page *pvh;
4203 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4204 ("pmap_page_exists_quick: page %p is not managed", m));
4206 vm_page_lock_queues();
4207 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4208 if (PV_PMAP(pv) == pmap) {
4216 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4217 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4218 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4219 if (PV_PMAP(pv) == pmap) {
4228 vm_page_unlock_queues();
4233 * pmap_page_wired_mappings:
4235 * Return the number of managed mappings to the given physical page
4239 pmap_page_wired_mappings(vm_page_t m)
4244 if ((m->oflags & VPO_UNMANAGED) != 0)
4246 vm_page_lock_queues();
4247 count = pmap_pvh_wired_mappings(&m->md, count);
4248 if ((m->flags & PG_FICTITIOUS) == 0) {
4249 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4252 vm_page_unlock_queues();
4257 * pmap_pvh_wired_mappings:
4259 * Return the updated number "count" of managed mappings that are wired.
4262 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4268 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4270 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4273 pte = pmap_pte_quick(pmap, pv->pv_va);
4274 if ((*pte & PG_W) != 0)
4283 * Returns TRUE if the given page is mapped individually or as part of
4284 * a 4mpage. Otherwise, returns FALSE.
4287 pmap_page_is_mapped(vm_page_t m)
4291 if ((m->oflags & VPO_UNMANAGED) != 0)
4293 vm_page_lock_queues();
4294 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4295 ((m->flags & PG_FICTITIOUS) == 0 &&
4296 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4297 vm_page_unlock_queues();
4302 * Remove all pages from specified address space
4303 * this aids process exit speeds. Also, this code
4304 * is special cased for current process only, but
4305 * can have the more generic (and slightly slower)
4306 * mode enabled. This is much faster than pmap_remove
4307 * in the case of running down an entire address space.
4310 pmap_remove_pages(pmap_t pmap)
4312 pt_entry_t *pte, tpte;
4313 vm_page_t free = NULL;
4314 vm_page_t m, mpte, mt;
4316 struct md_page *pvh;
4317 struct pv_chunk *pc, *npc;
4320 uint32_t inuse, bitmask;
4323 if (pmap != PCPU_GET(curpmap)) {
4324 printf("warning: pmap_remove_pages called with non-current pmap\n");
4327 vm_page_lock_queues();
4330 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4332 for (field = 0; field < _NPCM; field++) {
4333 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4334 while (inuse != 0) {
4336 bitmask = 1UL << bit;
4337 idx = field * 32 + bit;
4338 pv = &pc->pc_pventry[idx];
4341 pte = pmap_pde(pmap, pv->pv_va);
4343 if ((tpte & PG_PS) == 0) {
4344 pte = vtopte(pv->pv_va);
4345 tpte = *pte & ~PG_PTE_PAT;
4350 "TPTE at %p IS ZERO @ VA %08x\n",
4356 * We cannot remove wired pages from a process' mapping at this time
4363 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4364 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4365 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4366 m, (uintmax_t)m->phys_addr,
4369 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4370 m < &vm_page_array[vm_page_array_size],
4371 ("pmap_remove_pages: bad tpte %#jx",
4377 * Update the vm_page_t clean/reference bits.
4379 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4380 if ((tpte & PG_PS) != 0) {
4381 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4388 PV_STAT(pv_entry_frees++);
4389 PV_STAT(pv_entry_spare++);
4391 pc->pc_map[field] |= bitmask;
4392 if ((tpte & PG_PS) != 0) {
4393 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4394 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4395 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4396 if (TAILQ_EMPTY(&pvh->pv_list)) {
4397 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4398 if (TAILQ_EMPTY(&mt->md.pv_list))
4399 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4401 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4403 pmap_remove_pt_page(pmap, mpte);
4404 pmap->pm_stats.resident_count--;
4405 KASSERT(mpte->wire_count == NPTEPG,
4406 ("pmap_remove_pages: pte page wire count error"));
4407 mpte->wire_count = 0;
4408 pmap_add_delayed_free_list(mpte, &free, FALSE);
4409 atomic_subtract_int(&cnt.v_wire_count, 1);
4412 pmap->pm_stats.resident_count--;
4413 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4414 if (TAILQ_EMPTY(&m->md.pv_list) &&
4415 (m->flags & PG_FICTITIOUS) == 0) {
4416 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4417 if (TAILQ_EMPTY(&pvh->pv_list))
4418 vm_page_aflag_clear(m, PGA_WRITEABLE);
4420 pmap_unuse_pt(pmap, pv->pv_va, &free);
4425 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4430 pmap_invalidate_all(pmap);
4431 vm_page_unlock_queues();
4433 pmap_free_zero_pages(free);
4439 * Return whether or not the specified physical page was modified
4440 * in any physical maps.
4443 pmap_is_modified(vm_page_t m)
4447 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4448 ("pmap_is_modified: page %p is not managed", m));
4451 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4452 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4453 * is clear, no PTEs can have PG_M set.
4455 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4456 if ((m->oflags & VPO_BUSY) == 0 &&
4457 (m->aflags & PGA_WRITEABLE) == 0)
4459 vm_page_lock_queues();
4460 rv = pmap_is_modified_pvh(&m->md) ||
4461 ((m->flags & PG_FICTITIOUS) == 0 &&
4462 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4463 vm_page_unlock_queues();
4468 * Returns TRUE if any of the given mappings were used to modify
4469 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4470 * mappings are supported.
4473 pmap_is_modified_pvh(struct md_page *pvh)
4480 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4483 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4486 pte = pmap_pte_quick(pmap, pv->pv_va);
4487 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4497 * pmap_is_prefaultable:
4499 * Return whether or not the specified virtual address is elgible
4503 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4511 pde = pmap_pde(pmap, addr);
4512 if (*pde != 0 && (*pde & PG_PS) == 0) {
4521 * pmap_is_referenced:
4523 * Return whether or not the specified physical page was referenced
4524 * in any physical maps.
4527 pmap_is_referenced(vm_page_t m)
4531 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4532 ("pmap_is_referenced: page %p is not managed", m));
4533 vm_page_lock_queues();
4534 rv = pmap_is_referenced_pvh(&m->md) ||
4535 ((m->flags & PG_FICTITIOUS) == 0 &&
4536 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4537 vm_page_unlock_queues();
4542 * Returns TRUE if any of the given mappings were referenced and FALSE
4543 * otherwise. Both page and 4mpage mappings are supported.
4546 pmap_is_referenced_pvh(struct md_page *pvh)
4553 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4556 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4559 pte = pmap_pte_quick(pmap, pv->pv_va);
4560 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4570 * Clear the write and modified bits in each of the given page's mappings.
4573 pmap_remove_write(vm_page_t m)
4575 struct md_page *pvh;
4576 pv_entry_t next_pv, pv;
4579 pt_entry_t oldpte, *pte;
4582 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4583 ("pmap_remove_write: page %p is not managed", m));
4586 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4587 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4588 * is clear, no page table entries need updating.
4590 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4591 if ((m->oflags & VPO_BUSY) == 0 &&
4592 (m->aflags & PGA_WRITEABLE) == 0)
4594 vm_page_lock_queues();
4596 if ((m->flags & PG_FICTITIOUS) != 0)
4597 goto small_mappings;
4598 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4599 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4603 pde = pmap_pde(pmap, va);
4604 if ((*pde & PG_RW) != 0)
4605 (void)pmap_demote_pde(pmap, pde, va);
4609 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4612 pde = pmap_pde(pmap, pv->pv_va);
4613 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4614 " a 4mpage in page %p's pv list", m));
4615 pte = pmap_pte_quick(pmap, pv->pv_va);
4618 if ((oldpte & PG_RW) != 0) {
4620 * Regardless of whether a pte is 32 or 64 bits
4621 * in size, PG_RW and PG_M are among the least
4622 * significant 32 bits.
4624 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4625 oldpte & ~(PG_RW | PG_M)))
4627 if ((oldpte & PG_M) != 0)
4629 pmap_invalidate_page(pmap, pv->pv_va);
4633 vm_page_aflag_clear(m, PGA_WRITEABLE);
4635 vm_page_unlock_queues();
4639 * pmap_ts_referenced:
4641 * Return a count of reference bits for a page, clearing those bits.
4642 * It is not necessary for every reference bit to be cleared, but it
4643 * is necessary that 0 only be returned when there are truly no
4644 * reference bits set.
4646 * XXX: The exact number of bits to check and clear is a matter that
4647 * should be tested and standardized at some point in the future for
4648 * optimal aging of shared pages.
4651 pmap_ts_referenced(vm_page_t m)
4653 struct md_page *pvh;
4654 pv_entry_t pv, pvf, pvn;
4656 pd_entry_t oldpde, *pde;
4661 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4662 ("pmap_ts_referenced: page %p is not managed", m));
4663 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4664 vm_page_lock_queues();
4666 if ((m->flags & PG_FICTITIOUS) != 0)
4667 goto small_mappings;
4668 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4672 pde = pmap_pde(pmap, va);
4674 if ((oldpde & PG_A) != 0) {
4675 if (pmap_demote_pde(pmap, pde, va)) {
4676 if ((oldpde & PG_W) == 0) {
4678 * Remove the mapping to a single page
4679 * so that a subsequent access may
4680 * repromote. Since the underlying
4681 * page table page is fully populated,
4682 * this removal never frees a page
4685 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4687 pmap_remove_page(pmap, va, NULL);
4699 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4702 pvn = TAILQ_NEXT(pv, pv_list);
4703 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4704 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4707 pde = pmap_pde(pmap, pv->pv_va);
4708 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4709 " found a 4mpage in page %p's pv list", m));
4710 pte = pmap_pte_quick(pmap, pv->pv_va);
4711 if ((*pte & PG_A) != 0) {
4712 atomic_clear_int((u_int *)pte, PG_A);
4713 pmap_invalidate_page(pmap, pv->pv_va);
4719 } while ((pv = pvn) != NULL && pv != pvf);
4723 vm_page_unlock_queues();
4728 * Clear the modify bits on the specified physical page.
4731 pmap_clear_modify(vm_page_t m)
4733 struct md_page *pvh;
4734 pv_entry_t next_pv, pv;
4736 pd_entry_t oldpde, *pde;
4737 pt_entry_t oldpte, *pte;
4740 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4741 ("pmap_clear_modify: page %p is not managed", m));
4742 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4743 KASSERT((m->oflags & VPO_BUSY) == 0,
4744 ("pmap_clear_modify: page %p is busy", m));
4747 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4748 * If the object containing the page is locked and the page is not
4749 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4751 if ((m->aflags & PGA_WRITEABLE) == 0)
4753 vm_page_lock_queues();
4755 if ((m->flags & PG_FICTITIOUS) != 0)
4756 goto small_mappings;
4757 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4758 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4762 pde = pmap_pde(pmap, va);
4764 if ((oldpde & PG_RW) != 0) {
4765 if (pmap_demote_pde(pmap, pde, va)) {
4766 if ((oldpde & PG_W) == 0) {
4768 * Write protect the mapping to a
4769 * single page so that a subsequent
4770 * write access may repromote.
4772 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4774 pte = pmap_pte_quick(pmap, va);
4776 if ((oldpte & PG_V) != 0) {
4778 * Regardless of whether a pte is 32 or 64 bits
4779 * in size, PG_RW and PG_M are among the least
4780 * significant 32 bits.
4782 while (!atomic_cmpset_int((u_int *)pte,
4784 oldpte & ~(PG_M | PG_RW)))
4787 pmap_invalidate_page(pmap, va);
4795 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4798 pde = pmap_pde(pmap, pv->pv_va);
4799 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4800 " a 4mpage in page %p's pv list", m));
4801 pte = pmap_pte_quick(pmap, pv->pv_va);
4802 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4804 * Regardless of whether a pte is 32 or 64 bits
4805 * in size, PG_M is among the least significant
4808 atomic_clear_int((u_int *)pte, PG_M);
4809 pmap_invalidate_page(pmap, pv->pv_va);
4814 vm_page_unlock_queues();
4818 * pmap_clear_reference:
4820 * Clear the reference bit on the specified physical page.
4823 pmap_clear_reference(vm_page_t m)
4825 struct md_page *pvh;
4826 pv_entry_t next_pv, pv;
4828 pd_entry_t oldpde, *pde;
4832 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4833 ("pmap_clear_reference: page %p is not managed", m));
4834 vm_page_lock_queues();
4836 if ((m->flags & PG_FICTITIOUS) != 0)
4837 goto small_mappings;
4838 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4839 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4843 pde = pmap_pde(pmap, va);
4845 if ((oldpde & PG_A) != 0) {
4846 if (pmap_demote_pde(pmap, pde, va)) {
4848 * Remove the mapping to a single page so
4849 * that a subsequent access may repromote.
4850 * Since the underlying page table page is
4851 * fully populated, this removal never frees
4852 * a page table page.
4854 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4856 pmap_remove_page(pmap, va, NULL);
4862 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4865 pde = pmap_pde(pmap, pv->pv_va);
4866 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4867 " a 4mpage in page %p's pv list", m));
4868 pte = pmap_pte_quick(pmap, pv->pv_va);
4869 if ((*pte & PG_A) != 0) {
4871 * Regardless of whether a pte is 32 or 64 bits
4872 * in size, PG_A is among the least significant
4875 atomic_clear_int((u_int *)pte, PG_A);
4876 pmap_invalidate_page(pmap, pv->pv_va);
4881 vm_page_unlock_queues();
4885 * Miscellaneous support routines follow
4888 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4889 static __inline void
4890 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4895 * The cache mode bits are all in the low 32-bits of the
4896 * PTE, so we can just spin on updating the low 32-bits.
4899 opte = *(u_int *)pte;
4900 npte = opte & ~PG_PTE_CACHE;
4902 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4905 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
4906 static __inline void
4907 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4912 * The cache mode bits are all in the low 32-bits of the
4913 * PDE, so we can just spin on updating the low 32-bits.
4916 opde = *(u_int *)pde;
4917 npde = opde & ~PG_PDE_CACHE;
4919 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4923 * Map a set of physical memory pages into the kernel virtual
4924 * address space. Return a pointer to where it is mapped. This
4925 * routine is intended to be used for mapping device memory,
4929 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4931 vm_offset_t va, offset;
4934 offset = pa & PAGE_MASK;
4935 size = roundup(offset + size, PAGE_SIZE);
4938 if (pa < KERNLOAD && pa + size <= KERNLOAD)
4941 va = kmem_alloc_nofault(kernel_map, size);
4943 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4945 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4946 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
4947 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
4948 pmap_invalidate_cache_range(va, va + size);
4949 return ((void *)(va + offset));
4953 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
4956 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
4960 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4963 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4967 pmap_unmapdev(vm_offset_t va, vm_size_t size)
4969 vm_offset_t base, offset, tmpva;
4971 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
4973 base = trunc_page(va);
4974 offset = va & PAGE_MASK;
4975 size = roundup(offset + size, PAGE_SIZE);
4976 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
4977 pmap_kremove(tmpva);
4978 pmap_invalidate_range(kernel_pmap, va, tmpva);
4979 kmem_free(kernel_map, base, size);
4983 * Sets the memory attribute for the specified page.
4986 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4989 m->md.pat_mode = ma;
4990 if ((m->flags & PG_FICTITIOUS) != 0)
4994 * If "m" is a normal page, flush it from the cache.
4995 * See pmap_invalidate_cache_range().
4997 * First, try to find an existing mapping of the page by sf
4998 * buffer. sf_buf_invalidate_cache() modifies mapping and
4999 * flushes the cache.
5001 if (sf_buf_invalidate_cache(m))
5005 * If page is not mapped by sf buffer, but CPU does not
5006 * support self snoop, map the page transient and do
5007 * invalidation. In the worst case, whole cache is flushed by
5008 * pmap_invalidate_cache_range().
5010 if ((cpu_feature & CPUID_SS) == 0)
5015 pmap_flush_page(vm_page_t m)
5017 struct sysmaps *sysmaps;
5018 vm_offset_t sva, eva;
5020 if ((cpu_feature & CPUID_CLFSH) != 0) {
5021 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5022 mtx_lock(&sysmaps->lock);
5023 if (*sysmaps->CMAP2)
5024 panic("pmap_flush_page: CMAP2 busy");
5026 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5027 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5028 invlcaddr(sysmaps->CADDR2);
5029 sva = (vm_offset_t)sysmaps->CADDR2;
5030 eva = sva + PAGE_SIZE;
5033 * Use mfence despite the ordering implied by
5034 * mtx_{un,}lock() because clflush is not guaranteed
5035 * to be ordered by any other instruction.
5038 for (; sva < eva; sva += cpu_clflush_line_size)
5041 *sysmaps->CMAP2 = 0;
5043 mtx_unlock(&sysmaps->lock);
5045 pmap_invalidate_cache();
5049 * Changes the specified virtual address range's memory type to that given by
5050 * the parameter "mode". The specified virtual address range must be
5051 * completely contained within either the kernel map.
5053 * Returns zero if the change completed successfully, and either EINVAL or
5054 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5055 * of the virtual address range was not mapped, and ENOMEM is returned if
5056 * there was insufficient memory available to complete the change.
5059 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5061 vm_offset_t base, offset, tmpva;
5064 int cache_bits_pte, cache_bits_pde;
5067 base = trunc_page(va);
5068 offset = va & PAGE_MASK;
5069 size = roundup(offset + size, PAGE_SIZE);
5072 * Only supported on kernel virtual addresses above the recursive map.
5074 if (base < VM_MIN_KERNEL_ADDRESS)
5077 cache_bits_pde = pmap_cache_bits(mode, 1);
5078 cache_bits_pte = pmap_cache_bits(mode, 0);
5082 * Pages that aren't mapped aren't supported. Also break down
5083 * 2/4MB pages into 4KB pages if required.
5085 PMAP_LOCK(kernel_pmap);
5086 for (tmpva = base; tmpva < base + size; ) {
5087 pde = pmap_pde(kernel_pmap, tmpva);
5089 PMAP_UNLOCK(kernel_pmap);
5094 * If the current 2/4MB page already has
5095 * the required memory type, then we need not
5096 * demote this page. Just increment tmpva to
5097 * the next 2/4MB page frame.
5099 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5100 tmpva = trunc_4mpage(tmpva) + NBPDR;
5105 * If the current offset aligns with a 2/4MB
5106 * page frame and there is at least 2/4MB left
5107 * within the range, then we need not break
5108 * down this page into 4KB pages.
5110 if ((tmpva & PDRMASK) == 0 &&
5111 tmpva + PDRMASK < base + size) {
5115 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5116 PMAP_UNLOCK(kernel_pmap);
5120 pte = vtopte(tmpva);
5122 PMAP_UNLOCK(kernel_pmap);
5127 PMAP_UNLOCK(kernel_pmap);
5130 * Ok, all the pages exist, so run through them updating their
5131 * cache mode if required.
5133 for (tmpva = base; tmpva < base + size; ) {
5134 pde = pmap_pde(kernel_pmap, tmpva);
5136 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5137 pmap_pde_attr(pde, cache_bits_pde);
5140 tmpva = trunc_4mpage(tmpva) + NBPDR;
5142 pte = vtopte(tmpva);
5143 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5144 pmap_pte_attr(pte, cache_bits_pte);
5152 * Flush CPU caches to make sure any data isn't cached that
5153 * shouldn't be, etc.
5156 pmap_invalidate_range(kernel_pmap, base, tmpva);
5157 pmap_invalidate_cache_range(base, tmpva);
5163 * perform the pmap work for mincore
5166 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5169 pt_entry_t *ptep, pte;
5175 pdep = pmap_pde(pmap, addr);
5177 if (*pdep & PG_PS) {
5179 /* Compute the physical address of the 4KB page. */
5180 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5182 val = MINCORE_SUPER;
5184 ptep = pmap_pte(pmap, addr);
5186 pmap_pte_release(ptep);
5187 pa = pte & PG_FRAME;
5195 if ((pte & PG_V) != 0) {
5196 val |= MINCORE_INCORE;
5197 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5198 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5199 if ((pte & PG_A) != 0)
5200 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5202 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5203 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5204 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5205 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5206 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5209 PA_UNLOCK_COND(*locked_pa);
5215 pmap_activate(struct thread *td)
5217 pmap_t pmap, oldpmap;
5222 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5223 oldpmap = PCPU_GET(curpmap);
5224 cpuid = PCPU_GET(cpuid);
5226 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5227 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5229 CPU_CLR(cpuid, &oldpmap->pm_active);
5230 CPU_SET(cpuid, &pmap->pm_active);
5233 cr3 = vtophys(pmap->pm_pdpt);
5235 cr3 = vtophys(pmap->pm_pdir);
5238 * pmap_activate is for the current thread on the current cpu
5240 td->td_pcb->pcb_cr3 = cr3;
5242 PCPU_SET(curpmap, pmap);
5247 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5252 * Increase the starting virtual address of the given mapping if a
5253 * different alignment might result in more superpage mappings.
5256 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5257 vm_offset_t *addr, vm_size_t size)
5259 vm_offset_t superpage_offset;
5263 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5264 offset += ptoa(object->pg_color);
5265 superpage_offset = offset & PDRMASK;
5266 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5267 (*addr & PDRMASK) == superpage_offset)
5269 if ((*addr & PDRMASK) < superpage_offset)
5270 *addr = (*addr & ~PDRMASK) + superpage_offset;
5272 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5276 #if defined(PMAP_DEBUG)
5277 pmap_pid_dump(int pid)
5284 sx_slock(&allproc_lock);
5285 FOREACH_PROC_IN_SYSTEM(p) {
5286 if (p->p_pid != pid)
5292 pmap = vmspace_pmap(p->p_vmspace);
5293 for (i = 0; i < NPDEPTD; i++) {
5296 vm_offset_t base = i << PDRSHIFT;
5298 pde = &pmap->pm_pdir[i];
5299 if (pde && pmap_pde_v(pde)) {
5300 for (j = 0; j < NPTEPG; j++) {
5301 vm_offset_t va = base + (j << PAGE_SHIFT);
5302 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5307 sx_sunlock(&allproc_lock);
5310 pte = pmap_pte(pmap, va);
5311 if (pte && pmap_pte_v(pte)) {
5315 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5316 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5317 va, pa, m->hold_count, m->wire_count, m->flags);
5332 sx_sunlock(&allproc_lock);
5339 static void pads(pmap_t pm);
5340 void pmap_pvdump(vm_paddr_t pa);
5342 /* print address space of pmap*/
5350 if (pm == kernel_pmap)
5352 for (i = 0; i < NPDEPTD; i++)
5354 for (j = 0; j < NPTEPG; j++) {
5355 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5356 if (pm == kernel_pmap && va < KERNBASE)
5358 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5360 ptep = pmap_pte(pm, va);
5361 if (pmap_pte_v(ptep))
5362 printf("%x:%x ", va, *ptep);
5368 pmap_pvdump(vm_paddr_t pa)
5374 printf("pa %x", pa);
5375 m = PHYS_TO_VM_PAGE(pa);
5376 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
5378 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);