2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * In addition to hardware address maps, this
84 * module is called upon to provide software-use-only
85 * maps which may or may not be stored in the same
86 * form as hardware maps. These pseudo-maps are
87 * used to store intermediate results from copy
88 * operations to and from address spaces.
90 * Since the information managed by this module is
91 * also stored by the logical address mapping module,
92 * this module may throw away valid virtual-to-physical
93 * mappings at almost any time. However, invalidations
94 * of virtual-to-physical mappings must be done as
97 * In order to cope with hardware architectures which
98 * make virtual-to-physical map invalidates expensive,
99 * this module may delay invalidate or reduced protection
100 * operations until such time as they are actually
101 * necessary. This module is given full information as
102 * to which processors are currently using which maps,
103 * and to when physical maps must be made correct.
107 #include "opt_pmap.h"
109 #include "opt_xbox.h"
111 #include <sys/param.h>
112 #include <sys/systm.h>
113 #include <sys/kernel.h>
115 #include <sys/lock.h>
116 #include <sys/malloc.h>
117 #include <sys/mman.h>
118 #include <sys/msgbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/rwlock.h>
122 #include <sys/sf_buf.h>
124 #include <sys/vmmeter.h>
125 #include <sys/sched.h>
126 #include <sys/sysctl.h>
130 #include <sys/cpuset.h>
134 #include <vm/vm_param.h>
135 #include <vm/vm_kern.h>
136 #include <vm/vm_page.h>
137 #include <vm/vm_map.h>
138 #include <vm/vm_object.h>
139 #include <vm/vm_extern.h>
140 #include <vm/vm_pageout.h>
141 #include <vm/vm_pager.h>
142 #include <vm/vm_reserv.h>
145 #include <machine/cpu.h>
146 #include <machine/cputypes.h>
147 #include <machine/md_var.h>
148 #include <machine/pcb.h>
149 #include <machine/specialreg.h>
151 #include <machine/smp.h>
155 #include <machine/xbox.h>
158 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
159 #define CPU_ENABLE_SSE
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
170 #define PMAP_INLINE extern inline
177 #define PV_STAT(x) do { x ; } while (0)
179 #define PV_STAT(x) do { } while (0)
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
186 * Get PDEs and PTEs for user/kernel address space
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
201 struct pmap kernel_pmap_store;
202 LIST_HEAD(pmaplist, pmap);
203 static struct pmaplist allpmaps;
204 static struct mtx allpmaps_lock;
206 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
207 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
208 int pgeflag = 0; /* PG_G or-in */
209 int pseflag = 0; /* PG_PS or-in */
211 static int nkpt = NKPT;
212 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
213 extern u_int32_t KERNend;
214 extern u_int32_t KPTphys;
218 static uma_zone_t pdptzone;
221 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
223 static int pat_works = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
225 "Is page attribute table fully functional?");
227 static int pg_ps_enabled = 1;
228 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
229 "Are large page mappings enabled?");
231 #define PAT_INDEX_SIZE 8
232 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
235 * Isolate the global pv list lock from data and other locks to prevent false
236 * sharing within the cache.
240 char padding[CACHE_LINE_SIZE - sizeof(struct rwlock)];
241 } pvh_global __aligned(CACHE_LINE_SIZE);
243 #define pvh_global_lock pvh_global.lock
246 * Data for the pv entry allocation mechanism
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
258 * All those kernel PT submaps that BSD is so fond of
267 static struct sysmaps sysmaps_pcpu[MAXCPU];
268 pt_entry_t *CMAP1 = 0;
269 static pt_entry_t *CMAP3;
270 static pd_entry_t *KPTD;
271 caddr_t CADDR1 = 0, ptvmmap = 0;
272 static caddr_t CADDR3;
273 struct msgbuf *msgbufp = 0;
278 static caddr_t crashdumpmap;
280 static pt_entry_t *PMAP1 = 0, *PMAP2;
281 static pt_entry_t *PADDR1 = 0, *PADDR2;
284 static int PMAP1changedcpu;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
287 "Number of times pmap_pte_quick changed CPU with same PMAP1");
289 static int PMAP1changed;
290 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
292 "Number of times pmap_pte_quick changed PMAP1");
293 static int PMAP1unchanged;
294 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
296 "Number of times pmap_pte_quick didn't change PMAP1");
297 static struct mtx PMAP2mutex;
299 static void free_pv_chunk(struct pv_chunk *pc);
300 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
301 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
302 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
305 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
306 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
308 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
310 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
311 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
313 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
314 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
315 static void pmap_flush_page(vm_page_t m);
316 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
318 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
319 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
320 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
321 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
322 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
323 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
324 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
325 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
327 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
328 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
330 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
332 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
333 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
335 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
337 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
338 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
340 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
342 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
344 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
346 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags);
347 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free);
348 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
349 static void pmap_pte_release(pt_entry_t *pte);
350 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
352 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
354 static void pmap_set_pg(void);
356 static __inline void pagezero(void *page);
358 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
359 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
362 * If you get an error here, then you set KVA_PAGES wrong! See the
363 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
364 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
366 CTASSERT(KERNBASE % (1 << 24) == 0);
369 * Bootstrap the system enough to run with virtual memory.
371 * On the i386 this is called after mapping has already been enabled
372 * and just syncs the pmap module with what has already been done.
373 * [We can't call it easily with mapping off since the kernel is not
374 * mapped with PA == VA, hence we would have to relocate every address
375 * from the linked base (virtual) address "KERNBASE" to the actual
376 * (physical) address starting relative to 0]
379 pmap_bootstrap(vm_paddr_t firstaddr)
382 pt_entry_t *pte, *unused;
383 struct sysmaps *sysmaps;
387 * Initialize the first available kernel virtual address. However,
388 * using "firstaddr" may waste a few pages of the kernel virtual
389 * address space, because locore may not have mapped every physical
390 * page that it allocated. Preferably, locore would provide a first
391 * unused virtual address in addition to "firstaddr".
393 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
395 virtual_end = VM_MAX_KERNEL_ADDRESS;
398 * Initialize the kernel pmap (which is statically allocated).
400 PMAP_LOCK_INIT(kernel_pmap);
401 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
405 kernel_pmap->pm_root = NULL;
406 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
407 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
410 * Initialize the global pv list lock.
412 rw_init(&pvh_global_lock, "pmap pv global");
414 LIST_INIT(&allpmaps);
417 * Request a spin mutex so that changes to allpmaps cannot be
418 * preempted by smp_rendezvous_cpus(). Otherwise,
419 * pmap_update_pde_kernel() could access allpmaps while it is
422 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
423 mtx_lock_spin(&allpmaps_lock);
424 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
425 mtx_unlock_spin(&allpmaps_lock);
428 * Reserve some special page table entries/VA space for temporary
431 #define SYSMAP(c, p, v, n) \
432 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
438 * CMAP1/CMAP2 are used for zeroing and copying pages.
439 * CMAP3 is used for the idle process page zeroing.
441 for (i = 0; i < MAXCPU; i++) {
442 sysmaps = &sysmaps_pcpu[i];
443 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
444 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
445 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
447 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
448 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
453 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
456 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
458 SYSMAP(caddr_t, unused, ptvmmap, 1)
461 * msgbufp is used to map the system message buffer.
463 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
466 * KPTmap is used by pmap_kextract().
468 * KPTmap is first initialized by locore. However, that initial
469 * KPTmap can only support NKPT page table pages. Here, a larger
470 * KPTmap is created that can support KVA_PAGES page table pages.
472 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
474 for (i = 0; i < NKPT; i++)
475 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
478 * Adjust the start of the KPTD and KPTmap so that the implementation
479 * of pmap_kextract() and pmap_growkernel() can be made simpler.
482 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
485 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
488 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
489 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
491 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
496 * Leave in place an identity mapping (virt == phys) for the low 1 MB
497 * physical memory region that is used by the ACPI wakeup code. This
498 * mapping must not have PG_G set.
501 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
502 * an early stadium, we cannot yet neatly map video memory ... :-(
503 * Better fixes are very welcome! */
504 if (!arch_i386_is_xbox)
506 for (i = 1; i < NKPT; i++)
509 /* Initialize the PAT MSR if present. */
512 /* Turn on PG_G on kernel page(s) */
522 int pat_table[PAT_INDEX_SIZE];
527 /* Set default PAT index table. */
528 for (i = 0; i < PAT_INDEX_SIZE; i++)
530 pat_table[PAT_WRITE_BACK] = 0;
531 pat_table[PAT_WRITE_THROUGH] = 1;
532 pat_table[PAT_UNCACHEABLE] = 3;
533 pat_table[PAT_WRITE_COMBINING] = 3;
534 pat_table[PAT_WRITE_PROTECTED] = 3;
535 pat_table[PAT_UNCACHED] = 3;
537 /* Bail if this CPU doesn't implement PAT. */
538 if ((cpu_feature & CPUID_PAT) == 0) {
539 for (i = 0; i < PAT_INDEX_SIZE; i++)
540 pat_index[i] = pat_table[i];
546 * Due to some Intel errata, we can only safely use the lower 4
549 * Intel Pentium III Processor Specification Update
550 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
553 * Intel Pentium IV Processor Specification Update
554 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
556 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
557 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
560 /* Initialize default PAT entries. */
561 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
562 PAT_VALUE(1, PAT_WRITE_THROUGH) |
563 PAT_VALUE(2, PAT_UNCACHED) |
564 PAT_VALUE(3, PAT_UNCACHEABLE) |
565 PAT_VALUE(4, PAT_WRITE_BACK) |
566 PAT_VALUE(5, PAT_WRITE_THROUGH) |
567 PAT_VALUE(6, PAT_UNCACHED) |
568 PAT_VALUE(7, PAT_UNCACHEABLE);
572 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
573 * Program 5 and 6 as WP and WC.
574 * Leave 4 and 7 as WB and UC.
576 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
577 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
578 PAT_VALUE(6, PAT_WRITE_COMBINING);
579 pat_table[PAT_UNCACHED] = 2;
580 pat_table[PAT_WRITE_PROTECTED] = 5;
581 pat_table[PAT_WRITE_COMBINING] = 6;
584 * Just replace PAT Index 2 with WC instead of UC-.
586 pat_msr &= ~PAT_MASK(2);
587 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
588 pat_table[PAT_WRITE_COMBINING] = 2;
593 load_cr4(cr4 & ~CR4_PGE);
595 /* Disable caches (CD = 1, NW = 0). */
597 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
599 /* Flushes caches and TLBs. */
603 /* Update PAT and index table. */
604 wrmsr(MSR_PAT, pat_msr);
605 for (i = 0; i < PAT_INDEX_SIZE; i++)
606 pat_index[i] = pat_table[i];
608 /* Flush caches and TLBs again. */
612 /* Restore caches and PGE. */
618 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
624 vm_offset_t va, endva;
629 endva = KERNBASE + KERNend;
632 va = KERNBASE + KERNLOAD;
634 pdir_pde(PTD, va) |= pgeflag;
635 invltlb(); /* Play it safe, invltlb() every time */
639 va = (vm_offset_t)btext;
644 invltlb(); /* Play it safe, invltlb() every time */
651 * Initialize a vm_page's machine-dependent fields.
654 pmap_page_init(vm_page_t m)
657 TAILQ_INIT(&m->md.pv_list);
658 m->md.pat_mode = PAT_WRITE_BACK;
663 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
666 /* Inform UMA that this allocator uses kernel_map/object. */
667 *flags = UMA_SLAB_KERNEL;
668 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
669 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
674 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
676 * - Must deal with pages in order to ensure that none of the PG_* bits
677 * are ever set, PG_V in particular.
678 * - Assumes we can write to ptes without pte_store() atomic ops, even
679 * on PAE systems. This should be ok.
680 * - Assumes nothing will ever test these addresses for 0 to indicate
681 * no mapping instead of correctly checking PG_V.
682 * - Assumes a vm_offset_t will fit in a pte (true for i386).
683 * Because PG_V is never set, there can be no mappings to invalidate.
686 pmap_ptelist_alloc(vm_offset_t *head)
693 return (va); /* Out of memory */
697 panic("pmap_ptelist_alloc: va with PG_V set!");
703 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
708 panic("pmap_ptelist_free: freeing va with PG_V set!");
710 *pte = *head; /* virtual! PG_V is 0 though */
715 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
721 for (i = npages - 1; i >= 0; i--) {
722 va = (vm_offset_t)base + i * PAGE_SIZE;
723 pmap_ptelist_free(head, va);
729 * Initialize the pmap module.
730 * Called by vm_init, to initialize any structures that the pmap
731 * system needs to map virtual memory.
741 * Initialize the vm page array entries for the kernel pmap's
744 for (i = 0; i < NKPT; i++) {
745 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
746 KASSERT(mpte >= vm_page_array &&
747 mpte < &vm_page_array[vm_page_array_size],
748 ("pmap_init: page table page is out of range"));
749 mpte->pindex = i + KPTDI;
750 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
754 * Initialize the address space (zone) for the pv entries. Set a
755 * high water mark so that the system can recover from excessive
756 * numbers of pv entries.
758 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
759 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
760 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
761 pv_entry_max = roundup(pv_entry_max, _NPCPV);
762 pv_entry_high_water = 9 * (pv_entry_max / 10);
765 * If the kernel is running in a virtual machine on an AMD Family 10h
766 * processor, then it must assume that MCA is enabled by the virtual
769 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
770 CPUID_TO_FAMILY(cpu_id) == 0x10)
771 workaround_erratum383 = 1;
774 * Are large page mappings supported and enabled?
776 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
779 else if (pg_ps_enabled) {
780 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
781 ("pmap_init: can't assign to pagesizes[1]"));
782 pagesizes[1] = NBPDR;
786 * Calculate the size of the pv head table for superpages.
788 for (i = 0; phys_avail[i + 1]; i += 2);
789 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
792 * Allocate memory for the pv head table for superpages.
794 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
796 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
797 for (i = 0; i < pv_npg; i++)
798 TAILQ_INIT(&pv_table[i].pv_list);
800 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
801 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
802 PAGE_SIZE * pv_maxchunks);
803 if (pv_chunkbase == NULL)
804 panic("pmap_init: not enough kvm for pv chunks");
805 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
807 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
808 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
809 UMA_ZONE_VM | UMA_ZONE_NOFREE);
810 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
815 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
816 "Max number of PV entries");
817 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
818 "Page share factor per proc");
820 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
821 "2/4MB page mapping counters");
823 static u_long pmap_pde_demotions;
824 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
825 &pmap_pde_demotions, 0, "2/4MB page demotions");
827 static u_long pmap_pde_mappings;
828 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
829 &pmap_pde_mappings, 0, "2/4MB page mappings");
831 static u_long pmap_pde_p_failures;
832 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
833 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
835 static u_long pmap_pde_promotions;
836 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
837 &pmap_pde_promotions, 0, "2/4MB page promotions");
839 /***************************************************
840 * Low level helper routines.....
841 ***************************************************/
844 * Determine the appropriate bits to set in a PTE or PDE for a specified
848 pmap_cache_bits(int mode, boolean_t is_pde)
850 int cache_bits, pat_flag, pat_idx;
852 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
853 panic("Unknown caching mode %d\n", mode);
855 /* The PAT bit is different for PTE's and PDE's. */
856 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
858 /* Map the caching mode to a PAT index. */
859 pat_idx = pat_index[mode];
861 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
864 cache_bits |= pat_flag;
866 cache_bits |= PG_NC_PCD;
868 cache_bits |= PG_NC_PWT;
873 * The caller is responsible for maintaining TLB consistency.
876 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
880 boolean_t PTD_updated;
883 mtx_lock_spin(&allpmaps_lock);
884 LIST_FOREACH(pmap, &allpmaps, pm_list) {
885 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
888 pde = pmap_pde(pmap, va);
889 pde_store(pde, newpde);
891 mtx_unlock_spin(&allpmaps_lock);
893 ("pmap_kenter_pde: current page table is not in allpmaps"));
897 * After changing the page size for the specified virtual address in the page
898 * table, flush the corresponding entries from the processor's TLB. Only the
899 * calling processor's TLB is affected.
901 * The calling thread must be pinned to a processor.
904 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
908 if ((newpde & PG_PS) == 0)
909 /* Demotion: flush a specific 2MB page mapping. */
911 else if ((newpde & PG_G) == 0)
913 * Promotion: flush every 4KB page mapping from the TLB
914 * because there are too many to flush individually.
919 * Promotion: flush every 4KB page mapping from the TLB,
920 * including any global (PG_G) mappings.
923 load_cr4(cr4 & ~CR4_PGE);
925 * Although preemption at this point could be detrimental to
926 * performance, it would not lead to an error. PG_G is simply
927 * ignored if CR4.PGE is clear. Moreover, in case this block
928 * is re-entered, the load_cr4() either above or below will
929 * modify CR4.PGE flushing the TLB.
931 load_cr4(cr4 | CR4_PGE);
936 * For SMP, these functions have to use the IPI mechanism for coherence.
938 * N.B.: Before calling any of the following TLB invalidation functions,
939 * the calling processor must ensure that all stores updating a non-
940 * kernel page table are globally performed. Otherwise, another
941 * processor could cache an old, pre-update entry without being
942 * invalidated. This can happen one of two ways: (1) The pmap becomes
943 * active on another processor after its pm_active field is checked by
944 * one of the following functions but before a store updating the page
945 * table is globally performed. (2) The pmap becomes active on another
946 * processor before its pm_active field is checked but due to
947 * speculative loads one of the following functions stills reads the
948 * pmap as inactive on the other processor.
950 * The kernel page table is exempt because its pm_active field is
951 * immutable. The kernel page table is always active on every
955 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
961 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
965 cpuid = PCPU_GET(cpuid);
966 other_cpus = all_cpus;
967 CPU_CLR(cpuid, &other_cpus);
968 if (CPU_ISSET(cpuid, &pmap->pm_active))
970 CPU_AND(&other_cpus, &pmap->pm_active);
971 if (!CPU_EMPTY(&other_cpus))
972 smp_masked_invlpg(other_cpus, va);
978 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
985 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
986 for (addr = sva; addr < eva; addr += PAGE_SIZE)
988 smp_invlpg_range(sva, eva);
990 cpuid = PCPU_GET(cpuid);
991 other_cpus = all_cpus;
992 CPU_CLR(cpuid, &other_cpus);
993 if (CPU_ISSET(cpuid, &pmap->pm_active))
994 for (addr = sva; addr < eva; addr += PAGE_SIZE)
996 CPU_AND(&other_cpus, &pmap->pm_active);
997 if (!CPU_EMPTY(&other_cpus))
998 smp_masked_invlpg_range(other_cpus, sva, eva);
1004 pmap_invalidate_all(pmap_t pmap)
1006 cpuset_t other_cpus;
1010 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1014 cpuid = PCPU_GET(cpuid);
1015 other_cpus = all_cpus;
1016 CPU_CLR(cpuid, &other_cpus);
1017 if (CPU_ISSET(cpuid, &pmap->pm_active))
1019 CPU_AND(&other_cpus, &pmap->pm_active);
1020 if (!CPU_EMPTY(&other_cpus))
1021 smp_masked_invltlb(other_cpus);
1027 pmap_invalidate_cache(void)
1037 cpuset_t invalidate; /* processors that invalidate their TLB */
1041 u_int store; /* processor that updates the PDE */
1045 pmap_update_pde_kernel(void *arg)
1047 struct pde_action *act = arg;
1051 if (act->store == PCPU_GET(cpuid)) {
1054 * Elsewhere, this operation requires allpmaps_lock for
1055 * synchronization. Here, it does not because it is being
1056 * performed in the context of an all_cpus rendezvous.
1058 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1059 pde = pmap_pde(pmap, act->va);
1060 pde_store(pde, act->newpde);
1066 pmap_update_pde_user(void *arg)
1068 struct pde_action *act = arg;
1070 if (act->store == PCPU_GET(cpuid))
1071 pde_store(act->pde, act->newpde);
1075 pmap_update_pde_teardown(void *arg)
1077 struct pde_action *act = arg;
1079 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1080 pmap_update_pde_invalidate(act->va, act->newpde);
1084 * Change the page size for the specified virtual address in a way that
1085 * prevents any possibility of the TLB ever having two entries that map the
1086 * same virtual address using different page sizes. This is the recommended
1087 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1088 * machine check exception for a TLB state that is improperly diagnosed as a
1092 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1094 struct pde_action act;
1095 cpuset_t active, other_cpus;
1099 cpuid = PCPU_GET(cpuid);
1100 other_cpus = all_cpus;
1101 CPU_CLR(cpuid, &other_cpus);
1102 if (pmap == kernel_pmap)
1105 active = pmap->pm_active;
1106 if (CPU_OVERLAP(&active, &other_cpus)) {
1108 act.invalidate = active;
1111 act.newpde = newpde;
1112 CPU_SET(cpuid, &active);
1113 smp_rendezvous_cpus(active,
1114 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1115 pmap_update_pde_kernel : pmap_update_pde_user,
1116 pmap_update_pde_teardown, &act);
1118 if (pmap == kernel_pmap)
1119 pmap_kenter_pde(va, newpde);
1121 pde_store(pde, newpde);
1122 if (CPU_ISSET(cpuid, &active))
1123 pmap_update_pde_invalidate(va, newpde);
1129 * Normal, non-SMP, 486+ invalidation functions.
1130 * We inline these within pmap.c for speed.
1133 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1136 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1141 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1145 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1146 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1151 pmap_invalidate_all(pmap_t pmap)
1154 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1159 pmap_invalidate_cache(void)
1166 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1169 if (pmap == kernel_pmap)
1170 pmap_kenter_pde(va, newpde);
1172 pde_store(pde, newpde);
1173 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1174 pmap_update_pde_invalidate(va, newpde);
1178 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1181 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1184 KASSERT((sva & PAGE_MASK) == 0,
1185 ("pmap_invalidate_cache_range: sva not page-aligned"));
1186 KASSERT((eva & PAGE_MASK) == 0,
1187 ("pmap_invalidate_cache_range: eva not page-aligned"));
1189 if (cpu_feature & CPUID_SS)
1190 ; /* If "Self Snoop" is supported, do nothing. */
1191 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1192 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1195 * Otherwise, do per-cache line flush. Use the mfence
1196 * instruction to insure that previous stores are
1197 * included in the write-back. The processor
1198 * propagates flush to other processors in the cache
1202 for (; sva < eva; sva += cpu_clflush_line_size)
1208 * No targeted cache flush methods are supported by CPU,
1209 * or the supplied range is bigger than 2MB.
1210 * Globally invalidate cache.
1212 pmap_invalidate_cache();
1217 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1221 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1222 (cpu_feature & CPUID_CLFSH) == 0) {
1223 pmap_invalidate_cache();
1225 for (i = 0; i < count; i++)
1226 pmap_flush_page(pages[i]);
1231 * Are we current address space or kernel? N.B. We return FALSE when
1232 * a pmap's page table is in use because a kernel thread is borrowing
1233 * it. The borrowed page table can change spontaneously, making any
1234 * dependence on its continued use subject to a race condition.
1237 pmap_is_current(pmap_t pmap)
1240 return (pmap == kernel_pmap ||
1241 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1242 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1246 * If the given pmap is not the current or kernel pmap, the returned pte must
1247 * be released by passing it to pmap_pte_release().
1250 pmap_pte(pmap_t pmap, vm_offset_t va)
1255 pde = pmap_pde(pmap, va);
1259 /* are we current address space or kernel? */
1260 if (pmap_is_current(pmap))
1261 return (vtopte(va));
1262 mtx_lock(&PMAP2mutex);
1263 newpf = *pde & PG_FRAME;
1264 if ((*PMAP2 & PG_FRAME) != newpf) {
1265 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1266 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1268 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1274 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1277 static __inline void
1278 pmap_pte_release(pt_entry_t *pte)
1281 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1282 mtx_unlock(&PMAP2mutex);
1285 static __inline void
1286 invlcaddr(void *caddr)
1289 invlpg((u_int)caddr);
1293 * Super fast pmap_pte routine best used when scanning
1294 * the pv lists. This eliminates many coarse-grained
1295 * invltlb calls. Note that many of the pv list
1296 * scans are across different pmaps. It is very wasteful
1297 * to do an entire invltlb for checking a single mapping.
1299 * If the given pmap is not the current pmap, pvh_global_lock
1300 * must be held and curthread pinned to a CPU.
1303 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1308 pde = pmap_pde(pmap, va);
1312 /* are we current address space or kernel? */
1313 if (pmap_is_current(pmap))
1314 return (vtopte(va));
1315 rw_assert(&pvh_global_lock, RA_WLOCKED);
1316 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1317 newpf = *pde & PG_FRAME;
1318 if ((*PMAP1 & PG_FRAME) != newpf) {
1319 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1321 PMAP1cpu = PCPU_GET(cpuid);
1327 if (PMAP1cpu != PCPU_GET(cpuid)) {
1328 PMAP1cpu = PCPU_GET(cpuid);
1334 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1340 * Routine: pmap_extract
1342 * Extract the physical page address associated
1343 * with the given map/virtual_address pair.
1346 pmap_extract(pmap_t pmap, vm_offset_t va)
1354 pde = pmap->pm_pdir[va >> PDRSHIFT];
1356 if ((pde & PG_PS) != 0)
1357 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1359 pte = pmap_pte(pmap, va);
1360 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1361 pmap_pte_release(pte);
1369 * Routine: pmap_extract_and_hold
1371 * Atomically extract and hold the physical page
1372 * with the given pmap and virtual address pair
1373 * if that mapping permits the given protection.
1376 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1379 pt_entry_t pte, *ptep;
1387 pde = *pmap_pde(pmap, va);
1390 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1391 if (vm_page_pa_tryrelock(pmap, (pde &
1392 PG_PS_FRAME) | (va & PDRMASK), &pa))
1394 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1399 ptep = pmap_pte(pmap, va);
1401 pmap_pte_release(ptep);
1403 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1404 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1407 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1417 /***************************************************
1418 * Low level mapping routines.....
1419 ***************************************************/
1422 * Add a wired page to the kva.
1423 * Note: not SMP coherent.
1425 * This function may be used before pmap_bootstrap() is called.
1428 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1433 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1436 static __inline void
1437 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1442 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1446 * Remove a page from the kernel pagetables.
1447 * Note: not SMP coherent.
1449 * This function may be used before pmap_bootstrap() is called.
1452 pmap_kremove(vm_offset_t va)
1461 * Used to map a range of physical addresses into kernel
1462 * virtual address space.
1464 * The value passed in '*virt' is a suggested virtual address for
1465 * the mapping. Architectures which can support a direct-mapped
1466 * physical to virtual region can return the appropriate address
1467 * within that region, leaving '*virt' unchanged. Other
1468 * architectures should map the pages starting at '*virt' and
1469 * update '*virt' with the first usable address after the mapped
1473 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1475 vm_offset_t va, sva;
1476 vm_paddr_t superpage_offset;
1481 * Does the physical address range's size and alignment permit at
1482 * least one superpage mapping to be created?
1484 superpage_offset = start & PDRMASK;
1485 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1487 * Increase the starting virtual address so that its alignment
1488 * does not preclude the use of superpage mappings.
1490 if ((va & PDRMASK) < superpage_offset)
1491 va = (va & ~PDRMASK) + superpage_offset;
1492 else if ((va & PDRMASK) > superpage_offset)
1493 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1496 while (start < end) {
1497 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1499 KASSERT((va & PDRMASK) == 0,
1500 ("pmap_map: misaligned va %#x", va));
1501 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1502 pmap_kenter_pde(va, newpde);
1506 pmap_kenter(va, start);
1511 pmap_invalidate_range(kernel_pmap, sva, va);
1518 * Add a list of wired pages to the kva
1519 * this routine is only used for temporary
1520 * kernel mappings that do not need to have
1521 * page modification or references recorded.
1522 * Note that old mappings are simply written
1523 * over. The page *must* be wired.
1524 * Note: SMP coherent. Uses a ranged shootdown IPI.
1527 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1529 pt_entry_t *endpte, oldpte, pa, *pte;
1534 endpte = pte + count;
1535 while (pte < endpte) {
1537 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1538 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1540 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1544 if (__predict_false((oldpte & PG_V) != 0))
1545 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1550 * This routine tears out page mappings from the
1551 * kernel -- it is meant only for temporary mappings.
1552 * Note: SMP coherent. Uses a ranged shootdown IPI.
1555 pmap_qremove(vm_offset_t sva, int count)
1560 while (count-- > 0) {
1564 pmap_invalidate_range(kernel_pmap, sva, va);
1567 /***************************************************
1568 * Page table page management routines.....
1569 ***************************************************/
1570 static __inline void
1571 pmap_free_zero_pages(vm_page_t free)
1575 while (free != NULL) {
1578 /* Preserve the page's PG_ZERO setting. */
1579 vm_page_free_toq(m);
1584 * Schedule the specified unused page table page to be freed. Specifically,
1585 * add the page to the specified list of pages that will be released to the
1586 * physical memory manager after the TLB has been updated.
1588 static __inline void
1589 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1593 m->flags |= PG_ZERO;
1595 m->flags &= ~PG_ZERO;
1601 * Inserts the specified page table page into the specified pmap's collection
1602 * of idle page table pages. Each of a pmap's page table pages is responsible
1603 * for mapping a distinct range of virtual addresses. The pmap's collection is
1604 * ordered by this virtual address range.
1607 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1612 root = pmap->pm_root;
1617 root = vm_page_splay(mpte->pindex, root);
1618 if (mpte->pindex < root->pindex) {
1619 mpte->left = root->left;
1622 } else if (mpte->pindex == root->pindex)
1623 panic("pmap_insert_pt_page: pindex already inserted");
1625 mpte->right = root->right;
1630 pmap->pm_root = mpte;
1634 * Looks for a page table page mapping the specified virtual address in the
1635 * specified pmap's collection of idle page table pages. Returns NULL if there
1636 * is no page table page corresponding to the specified virtual address.
1639 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1642 vm_pindex_t pindex = va >> PDRSHIFT;
1644 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1645 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1646 mpte = vm_page_splay(pindex, mpte);
1647 if ((pmap->pm_root = mpte)->pindex != pindex)
1654 * Removes the specified page table page from the specified pmap's collection
1655 * of idle page table pages. The specified page table page must be a member of
1656 * the pmap's collection.
1659 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1663 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1664 if (mpte != pmap->pm_root)
1665 vm_page_splay(mpte->pindex, pmap->pm_root);
1666 if (mpte->left == NULL)
1669 root = vm_page_splay(mpte->pindex, mpte->left);
1670 root->right = mpte->right;
1672 pmap->pm_root = root;
1676 * Decrements a page table page's wire count, which is used to record the
1677 * number of valid page table entries within the page. If the wire count
1678 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1679 * page table page was unmapped and FALSE otherwise.
1681 static inline boolean_t
1682 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free)
1686 if (m->wire_count == 0) {
1687 _pmap_unwire_ptp(pmap, m, free);
1694 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free)
1699 * unmap the page table page
1701 pmap->pm_pdir[m->pindex] = 0;
1702 --pmap->pm_stats.resident_count;
1705 * This is a release store so that the ordinary store unmapping
1706 * the page table page is globally performed before TLB shoot-
1709 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1712 * Do an invltlb to make the invalidated mapping
1713 * take effect immediately.
1715 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1716 pmap_invalidate_page(pmap, pteva);
1719 * Put page on a list so that it is released after
1720 * *ALL* TLB shootdown is done
1722 pmap_add_delayed_free_list(m, free, TRUE);
1726 * After removing a page table entry, this routine is used to
1727 * conditionally free the page, and manage the hold/wire counts.
1730 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1735 if (va >= VM_MAXUSER_ADDRESS)
1737 ptepde = *pmap_pde(pmap, va);
1738 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1739 return (pmap_unwire_ptp(pmap, mpte, free));
1743 * Initialize the pmap for the swapper process.
1746 pmap_pinit0(pmap_t pmap)
1749 PMAP_LOCK_INIT(pmap);
1751 * Since the page table directory is shared with the kernel pmap,
1752 * which is already included in the list "allpmaps", this pmap does
1753 * not need to be inserted into that list.
1755 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1757 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1759 pmap->pm_root = NULL;
1760 CPU_ZERO(&pmap->pm_active);
1761 PCPU_SET(curpmap, pmap);
1762 TAILQ_INIT(&pmap->pm_pvchunk);
1763 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1767 * Initialize a preallocated and zeroed pmap structure,
1768 * such as one in a vmspace structure.
1771 pmap_pinit(pmap_t pmap)
1773 vm_page_t m, ptdpg[NPGPTD];
1777 PMAP_LOCK_INIT(pmap);
1780 * No need to allocate page table space yet but we do need a valid
1781 * page directory table.
1783 if (pmap->pm_pdir == NULL) {
1784 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1786 if (pmap->pm_pdir == NULL) {
1787 PMAP_LOCK_DESTROY(pmap);
1791 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1792 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1793 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1794 ("pmap_pinit: pdpt misaligned"));
1795 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1796 ("pmap_pinit: pdpt above 4g"));
1798 pmap->pm_root = NULL;
1800 KASSERT(pmap->pm_root == NULL,
1801 ("pmap_pinit: pmap has reserved page table page(s)"));
1804 * allocate the page directory page(s)
1806 for (i = 0; i < NPGPTD;) {
1807 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1808 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1816 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1818 for (i = 0; i < NPGPTD; i++)
1819 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1820 pagezero(pmap->pm_pdir + (i * NPDEPG));
1822 mtx_lock_spin(&allpmaps_lock);
1823 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1824 /* Copy the kernel page table directory entries. */
1825 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1826 mtx_unlock_spin(&allpmaps_lock);
1828 /* install self-referential address mapping entry(s) */
1829 for (i = 0; i < NPGPTD; i++) {
1830 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1831 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1833 pmap->pm_pdpt[i] = pa | PG_V;
1837 CPU_ZERO(&pmap->pm_active);
1838 TAILQ_INIT(&pmap->pm_pvchunk);
1839 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1845 * this routine is called if the page table page is not
1849 _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags)
1854 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1855 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1856 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1859 * Allocate a page table page.
1861 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1862 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1863 if (flags & M_WAITOK) {
1865 rw_wunlock(&pvh_global_lock);
1867 rw_wlock(&pvh_global_lock);
1872 * Indicate the need to retry. While waiting, the page table
1873 * page may have been allocated.
1877 if ((m->flags & PG_ZERO) == 0)
1881 * Map the pagetable page into the process address space, if
1882 * it isn't already there.
1885 pmap->pm_stats.resident_count++;
1887 ptepa = VM_PAGE_TO_PHYS(m);
1888 pmap->pm_pdir[ptepindex] =
1889 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1895 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1901 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1902 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1903 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1906 * Calculate pagetable page index
1908 ptepindex = va >> PDRSHIFT;
1911 * Get the page directory entry
1913 ptepa = pmap->pm_pdir[ptepindex];
1916 * This supports switching from a 4MB page to a
1919 if (ptepa & PG_PS) {
1920 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1921 ptepa = pmap->pm_pdir[ptepindex];
1925 * If the page table page is mapped, we just increment the
1926 * hold count, and activate it.
1929 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1933 * Here if the pte page isn't mapped, or if it has
1936 m = _pmap_allocpte(pmap, ptepindex, flags);
1937 if (m == NULL && (flags & M_WAITOK))
1944 /***************************************************
1945 * Pmap allocation/deallocation routines.
1946 ***************************************************/
1950 * Deal with a SMP shootdown of other users of the pmap that we are
1951 * trying to dispose of. This can be a bit hairy.
1953 static cpuset_t *lazymask;
1954 static u_int lazyptd;
1955 static volatile u_int lazywait;
1957 void pmap_lazyfix_action(void);
1960 pmap_lazyfix_action(void)
1964 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1966 if (rcr3() == lazyptd)
1967 load_cr3(curpcb->pcb_cr3);
1968 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1969 atomic_store_rel_int(&lazywait, 1);
1973 pmap_lazyfix_self(u_int cpuid)
1976 if (rcr3() == lazyptd)
1977 load_cr3(curpcb->pcb_cr3);
1978 CPU_CLR_ATOMIC(cpuid, lazymask);
1983 pmap_lazyfix(pmap_t pmap)
1985 cpuset_t mymask, mask;
1989 mask = pmap->pm_active;
1990 while (!CPU_EMPTY(&mask)) {
1993 /* Find least significant set bit. */
1994 lsb = cpusetobj_ffs(&mask);
1997 CPU_SETOF(lsb, &mask);
1998 mtx_lock_spin(&smp_ipi_mtx);
2000 lazyptd = vtophys(pmap->pm_pdpt);
2002 lazyptd = vtophys(pmap->pm_pdir);
2004 cpuid = PCPU_GET(cpuid);
2006 /* Use a cpuset just for having an easy check. */
2007 CPU_SETOF(cpuid, &mymask);
2008 if (!CPU_CMP(&mask, &mymask)) {
2009 lazymask = &pmap->pm_active;
2010 pmap_lazyfix_self(cpuid);
2012 atomic_store_rel_int((u_int *)&lazymask,
2013 (u_int)&pmap->pm_active);
2014 atomic_store_rel_int(&lazywait, 0);
2015 ipi_selected(mask, IPI_LAZYPMAP);
2016 while (lazywait == 0) {
2022 mtx_unlock_spin(&smp_ipi_mtx);
2024 printf("pmap_lazyfix: spun for 50000000\n");
2025 mask = pmap->pm_active;
2032 * Cleaning up on uniprocessor is easy. For various reasons, we're
2033 * unlikely to have to even execute this code, including the fact
2034 * that the cleanup is deferred until the parent does a wait(2), which
2035 * means that another userland process has run.
2038 pmap_lazyfix(pmap_t pmap)
2042 cr3 = vtophys(pmap->pm_pdir);
2043 if (cr3 == rcr3()) {
2044 load_cr3(curpcb->pcb_cr3);
2045 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2051 * Release any resources held by the given physical map.
2052 * Called when a pmap initialized by pmap_pinit is being released.
2053 * Should only be called if the map contains no valid mappings.
2056 pmap_release(pmap_t pmap)
2058 vm_page_t m, ptdpg[NPGPTD];
2061 KASSERT(pmap->pm_stats.resident_count == 0,
2062 ("pmap_release: pmap resident count %ld != 0",
2063 pmap->pm_stats.resident_count));
2064 KASSERT(pmap->pm_root == NULL,
2065 ("pmap_release: pmap has reserved page table page(s)"));
2068 mtx_lock_spin(&allpmaps_lock);
2069 LIST_REMOVE(pmap, pm_list);
2070 mtx_unlock_spin(&allpmaps_lock);
2072 for (i = 0; i < NPGPTD; i++)
2073 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2076 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2077 sizeof(*pmap->pm_pdir));
2079 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2081 for (i = 0; i < NPGPTD; i++) {
2084 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2085 ("pmap_release: got wrong ptd page"));
2088 atomic_subtract_int(&cnt.v_wire_count, 1);
2089 vm_page_free_zero(m);
2091 PMAP_LOCK_DESTROY(pmap);
2095 kvm_size(SYSCTL_HANDLER_ARGS)
2097 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2099 return (sysctl_handle_long(oidp, &ksize, 0, req));
2101 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2102 0, 0, kvm_size, "IU", "Size of KVM");
2105 kvm_free(SYSCTL_HANDLER_ARGS)
2107 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2109 return (sysctl_handle_long(oidp, &kfree, 0, req));
2111 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2112 0, 0, kvm_free, "IU", "Amount of KVM free");
2115 * grow the number of kernel page table entries, if needed
2118 pmap_growkernel(vm_offset_t addr)
2120 vm_paddr_t ptppaddr;
2124 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2125 addr = roundup2(addr, NBPDR);
2126 if (addr - 1 >= kernel_map->max_offset)
2127 addr = kernel_map->max_offset;
2128 while (kernel_vm_end < addr) {
2129 if (pdir_pde(PTD, kernel_vm_end)) {
2130 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2131 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2132 kernel_vm_end = kernel_map->max_offset;
2138 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2139 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2142 panic("pmap_growkernel: no memory to grow kernel");
2146 if ((nkpg->flags & PG_ZERO) == 0)
2147 pmap_zero_page(nkpg);
2148 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2149 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2150 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2152 pmap_kenter_pde(kernel_vm_end, newpdir);
2153 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2154 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2155 kernel_vm_end = kernel_map->max_offset;
2162 /***************************************************
2163 * page management routines.
2164 ***************************************************/
2166 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2167 CTASSERT(_NPCM == 11);
2168 CTASSERT(_NPCPV == 336);
2170 static __inline struct pv_chunk *
2171 pv_to_chunk(pv_entry_t pv)
2174 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2177 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2179 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2180 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2182 static const uint32_t pc_freemask[_NPCM] = {
2183 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2184 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2185 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2186 PC_FREE0_9, PC_FREE10
2189 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2190 "Current number of pv entries");
2193 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2195 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2196 "Current number of pv entry chunks");
2197 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2198 "Current number of pv entry chunks allocated");
2199 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2200 "Current number of pv entry chunks frees");
2201 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2202 "Number of times tried to get a chunk page but failed.");
2204 static long pv_entry_frees, pv_entry_allocs;
2205 static int pv_entry_spare;
2207 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2208 "Current number of pv entry frees");
2209 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2210 "Current number of pv entry allocs");
2211 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2212 "Current number of spare pv entries");
2216 * We are in a serious low memory condition. Resort to
2217 * drastic measures to free some pages so we can allocate
2218 * another pv entry chunk.
2221 pmap_pv_reclaim(pmap_t locked_pmap)
2224 struct pv_chunk *pc;
2225 struct md_page *pvh;
2228 pt_entry_t *pte, tpte;
2231 vm_page_t free, m, m_pc;
2233 int bit, field, freed;
2235 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2238 TAILQ_INIT(&newtail);
2239 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2241 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2242 if (pmap != pc->pc_pmap) {
2244 pmap_invalidate_all(pmap);
2245 if (pmap != locked_pmap)
2249 /* Avoid deadlock and lock recursion. */
2250 if (pmap > locked_pmap)
2252 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2254 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2260 * Destroy every non-wired, 4 KB page mapping in the chunk.
2263 for (field = 0; field < _NPCM; field++) {
2264 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2265 inuse != 0; inuse &= ~(1UL << bit)) {
2267 pv = &pc->pc_pventry[field * 32 + bit];
2269 pde = pmap_pde(pmap, va);
2270 if ((*pde & PG_PS) != 0)
2272 pte = pmap_pte(pmap, va);
2274 if ((tpte & PG_W) == 0)
2275 tpte = pte_load_clear(pte);
2276 pmap_pte_release(pte);
2277 if ((tpte & PG_W) != 0)
2280 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2282 if ((tpte & PG_G) != 0)
2283 pmap_invalidate_page(pmap, va);
2284 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2285 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2287 if ((tpte & PG_A) != 0)
2288 vm_page_aflag_set(m, PGA_REFERENCED);
2289 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2290 if (TAILQ_EMPTY(&m->md.pv_list) &&
2291 (m->flags & PG_FICTITIOUS) == 0) {
2292 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2293 if (TAILQ_EMPTY(&pvh->pv_list)) {
2294 vm_page_aflag_clear(m,
2298 pc->pc_map[field] |= 1UL << bit;
2299 pmap_unuse_pt(pmap, va, &free);
2304 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2307 /* Every freed mapping is for a 4 KB page. */
2308 pmap->pm_stats.resident_count -= freed;
2309 PV_STAT(pv_entry_frees += freed);
2310 PV_STAT(pv_entry_spare += freed);
2311 pv_entry_count -= freed;
2312 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2313 for (field = 0; field < _NPCM; field++)
2314 if (pc->pc_map[field] != pc_freemask[field]) {
2315 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2317 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2320 * One freed pv entry in locked_pmap is
2323 if (pmap == locked_pmap)
2327 if (field == _NPCM) {
2328 PV_STAT(pv_entry_spare -= _NPCPV);
2329 PV_STAT(pc_chunk_count--);
2330 PV_STAT(pc_chunk_frees++);
2331 /* Entire chunk is free; return it. */
2332 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2333 pmap_qremove((vm_offset_t)pc, 1);
2334 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2339 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2341 pmap_invalidate_all(pmap);
2342 if (pmap != locked_pmap)
2345 if (m_pc == NULL && pv_vafree != 0 && free != NULL) {
2348 /* Recycle a freed page table page. */
2349 m_pc->wire_count = 1;
2350 atomic_add_int(&cnt.v_wire_count, 1);
2352 pmap_free_zero_pages(free);
2357 * free the pv_entry back to the free list
2360 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2362 struct pv_chunk *pc;
2363 int idx, field, bit;
2365 rw_assert(&pvh_global_lock, RA_WLOCKED);
2366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2367 PV_STAT(pv_entry_frees++);
2368 PV_STAT(pv_entry_spare++);
2370 pc = pv_to_chunk(pv);
2371 idx = pv - &pc->pc_pventry[0];
2374 pc->pc_map[field] |= 1ul << bit;
2375 for (idx = 0; idx < _NPCM; idx++)
2376 if (pc->pc_map[idx] != pc_freemask[idx]) {
2378 * 98% of the time, pc is already at the head of the
2379 * list. If it isn't already, move it to the head.
2381 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2383 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2384 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2389 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2394 free_pv_chunk(struct pv_chunk *pc)
2398 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2399 PV_STAT(pv_entry_spare -= _NPCPV);
2400 PV_STAT(pc_chunk_count--);
2401 PV_STAT(pc_chunk_frees++);
2402 /* entire chunk is free, return it */
2403 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2404 pmap_qremove((vm_offset_t)pc, 1);
2405 vm_page_unwire(m, 0);
2407 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2411 * get a new pv_entry, allocating a block from the system
2415 get_pv_entry(pmap_t pmap, boolean_t try)
2417 static const struct timeval printinterval = { 60, 0 };
2418 static struct timeval lastprint;
2421 struct pv_chunk *pc;
2424 rw_assert(&pvh_global_lock, RA_WLOCKED);
2425 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2426 PV_STAT(pv_entry_allocs++);
2428 if (pv_entry_count > pv_entry_high_water)
2429 if (ratecheck(&lastprint, &printinterval))
2430 printf("Approaching the limit on PV entries, consider "
2431 "increasing either the vm.pmap.shpgperproc or the "
2432 "vm.pmap.pv_entry_max tunable.\n");
2434 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2436 for (field = 0; field < _NPCM; field++) {
2437 if (pc->pc_map[field]) {
2438 bit = bsfl(pc->pc_map[field]);
2442 if (field < _NPCM) {
2443 pv = &pc->pc_pventry[field * 32 + bit];
2444 pc->pc_map[field] &= ~(1ul << bit);
2445 /* If this was the last item, move it to tail */
2446 for (field = 0; field < _NPCM; field++)
2447 if (pc->pc_map[field] != 0) {
2448 PV_STAT(pv_entry_spare--);
2449 return (pv); /* not full, return */
2451 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2452 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2453 PV_STAT(pv_entry_spare--);
2458 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2459 * global lock. If "pv_vafree" is currently non-empty, it will
2460 * remain non-empty until pmap_ptelist_alloc() completes.
2462 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2463 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2466 PV_STAT(pc_chunk_tryfail++);
2469 m = pmap_pv_reclaim(pmap);
2473 PV_STAT(pc_chunk_count++);
2474 PV_STAT(pc_chunk_allocs++);
2475 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2476 pmap_qenter((vm_offset_t)pc, &m, 1);
2478 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2479 for (field = 1; field < _NPCM; field++)
2480 pc->pc_map[field] = pc_freemask[field];
2481 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2482 pv = &pc->pc_pventry[0];
2483 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2484 PV_STAT(pv_entry_spare += _NPCPV - 1);
2488 static __inline pv_entry_t
2489 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2493 rw_assert(&pvh_global_lock, RA_WLOCKED);
2494 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2495 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2496 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2504 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2506 struct md_page *pvh;
2508 vm_offset_t va_last;
2511 rw_assert(&pvh_global_lock, RA_WLOCKED);
2512 KASSERT((pa & PDRMASK) == 0,
2513 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2516 * Transfer the 4mpage's pv entry for this mapping to the first
2519 pvh = pa_to_pvh(pa);
2520 va = trunc_4mpage(va);
2521 pv = pmap_pvh_remove(pvh, pmap, va);
2522 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2523 m = PHYS_TO_VM_PAGE(pa);
2524 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2525 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2526 va_last = va + NBPDR - PAGE_SIZE;
2529 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2530 ("pmap_pv_demote_pde: page %p is not managed", m));
2532 pmap_insert_entry(pmap, va, m);
2533 } while (va < va_last);
2537 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2539 struct md_page *pvh;
2541 vm_offset_t va_last;
2544 rw_assert(&pvh_global_lock, RA_WLOCKED);
2545 KASSERT((pa & PDRMASK) == 0,
2546 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2549 * Transfer the first page's pv entry for this mapping to the
2550 * 4mpage's pv list. Aside from avoiding the cost of a call
2551 * to get_pv_entry(), a transfer avoids the possibility that
2552 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2553 * removes one of the mappings that is being promoted.
2555 m = PHYS_TO_VM_PAGE(pa);
2556 va = trunc_4mpage(va);
2557 pv = pmap_pvh_remove(&m->md, pmap, va);
2558 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2559 pvh = pa_to_pvh(pa);
2560 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2561 /* Free the remaining NPTEPG - 1 pv entries. */
2562 va_last = va + NBPDR - PAGE_SIZE;
2566 pmap_pvh_free(&m->md, pmap, va);
2567 } while (va < va_last);
2571 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2575 pv = pmap_pvh_remove(pvh, pmap, va);
2576 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2577 free_pv_entry(pmap, pv);
2581 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2583 struct md_page *pvh;
2585 rw_assert(&pvh_global_lock, RA_WLOCKED);
2586 pmap_pvh_free(&m->md, pmap, va);
2587 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2588 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2589 if (TAILQ_EMPTY(&pvh->pv_list))
2590 vm_page_aflag_clear(m, PGA_WRITEABLE);
2595 * Create a pv entry for page at pa for
2599 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2603 rw_assert(&pvh_global_lock, RA_WLOCKED);
2604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2605 pv = get_pv_entry(pmap, FALSE);
2607 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2611 * Conditionally create a pv entry.
2614 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2618 rw_assert(&pvh_global_lock, RA_WLOCKED);
2619 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2620 if (pv_entry_count < pv_entry_high_water &&
2621 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2623 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2630 * Create the pv entries for each of the pages within a superpage.
2633 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2635 struct md_page *pvh;
2638 rw_assert(&pvh_global_lock, RA_WLOCKED);
2639 if (pv_entry_count < pv_entry_high_water &&
2640 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2642 pvh = pa_to_pvh(pa);
2643 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2650 * Fills a page table page with mappings to consecutive physical pages.
2653 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2657 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2659 newpte += PAGE_SIZE;
2664 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2665 * 2- or 4MB page mapping is invalidated.
2668 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2670 pd_entry_t newpde, oldpde;
2671 pt_entry_t *firstpte, newpte;
2673 vm_page_t free, mpte;
2675 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2677 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2678 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2679 mpte = pmap_lookup_pt_page(pmap, va);
2681 pmap_remove_pt_page(pmap, mpte);
2683 KASSERT((oldpde & PG_W) == 0,
2684 ("pmap_demote_pde: page table page for a wired mapping"
2688 * Invalidate the 2- or 4MB page mapping and return
2689 * "failure" if the mapping was never accessed or the
2690 * allocation of the new page table page fails.
2692 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2693 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2694 VM_ALLOC_WIRED)) == NULL) {
2696 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2697 pmap_invalidate_page(pmap, trunc_4mpage(va));
2698 pmap_free_zero_pages(free);
2699 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2700 " in pmap %p", va, pmap);
2703 if (va < VM_MAXUSER_ADDRESS)
2704 pmap->pm_stats.resident_count++;
2706 mptepa = VM_PAGE_TO_PHYS(mpte);
2709 * If the page mapping is in the kernel's address space, then the
2710 * KPTmap can provide access to the page table page. Otherwise,
2711 * temporarily map the page table page (mpte) into the kernel's
2712 * address space at either PADDR1 or PADDR2.
2715 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2716 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2717 if ((*PMAP1 & PG_FRAME) != mptepa) {
2718 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2720 PMAP1cpu = PCPU_GET(cpuid);
2726 if (PMAP1cpu != PCPU_GET(cpuid)) {
2727 PMAP1cpu = PCPU_GET(cpuid);
2735 mtx_lock(&PMAP2mutex);
2736 if ((*PMAP2 & PG_FRAME) != mptepa) {
2737 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2738 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2742 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2743 KASSERT((oldpde & PG_A) != 0,
2744 ("pmap_demote_pde: oldpde is missing PG_A"));
2745 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2746 ("pmap_demote_pde: oldpde is missing PG_M"));
2747 newpte = oldpde & ~PG_PS;
2748 if ((newpte & PG_PDE_PAT) != 0)
2749 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2752 * If the page table page is new, initialize it.
2754 if (mpte->wire_count == 1) {
2755 mpte->wire_count = NPTEPG;
2756 pmap_fill_ptp(firstpte, newpte);
2758 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2759 ("pmap_demote_pde: firstpte and newpte map different physical"
2763 * If the mapping has changed attributes, update the page table
2766 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2767 pmap_fill_ptp(firstpte, newpte);
2770 * Demote the mapping. This pmap is locked. The old PDE has
2771 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2772 * set. Thus, there is no danger of a race with another
2773 * processor changing the setting of PG_A and/or PG_M between
2774 * the read above and the store below.
2776 if (workaround_erratum383)
2777 pmap_update_pde(pmap, va, pde, newpde);
2778 else if (pmap == kernel_pmap)
2779 pmap_kenter_pde(va, newpde);
2781 pde_store(pde, newpde);
2782 if (firstpte == PADDR2)
2783 mtx_unlock(&PMAP2mutex);
2786 * Invalidate the recursive mapping of the page table page.
2788 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2791 * Demote the pv entry. This depends on the earlier demotion
2792 * of the mapping. Specifically, the (re)creation of a per-
2793 * page pv entry might trigger the execution of pmap_collect(),
2794 * which might reclaim a newly (re)created per-page pv entry
2795 * and destroy the associated mapping. In order to destroy
2796 * the mapping, the PDE must have already changed from mapping
2797 * the 2mpage to referencing the page table page.
2799 if ((oldpde & PG_MANAGED) != 0)
2800 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2802 pmap_pde_demotions++;
2803 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2804 " in pmap %p", va, pmap);
2809 * pmap_remove_pde: do the things to unmap a superpage in a process
2812 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2815 struct md_page *pvh;
2817 vm_offset_t eva, va;
2820 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2821 KASSERT((sva & PDRMASK) == 0,
2822 ("pmap_remove_pde: sva is not 4mpage aligned"));
2823 oldpde = pte_load_clear(pdq);
2825 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2828 * Machines that don't support invlpg, also don't support
2832 pmap_invalidate_page(kernel_pmap, sva);
2833 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2834 if (oldpde & PG_MANAGED) {
2835 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2836 pmap_pvh_free(pvh, pmap, sva);
2838 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2839 va < eva; va += PAGE_SIZE, m++) {
2840 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2843 vm_page_aflag_set(m, PGA_REFERENCED);
2844 if (TAILQ_EMPTY(&m->md.pv_list) &&
2845 TAILQ_EMPTY(&pvh->pv_list))
2846 vm_page_aflag_clear(m, PGA_WRITEABLE);
2849 if (pmap == kernel_pmap) {
2850 if (!pmap_demote_pde(pmap, pdq, sva))
2851 panic("pmap_remove_pde: failed demotion");
2853 mpte = pmap_lookup_pt_page(pmap, sva);
2855 pmap_remove_pt_page(pmap, mpte);
2856 pmap->pm_stats.resident_count--;
2857 KASSERT(mpte->wire_count == NPTEPG,
2858 ("pmap_remove_pde: pte page wire count error"));
2859 mpte->wire_count = 0;
2860 pmap_add_delayed_free_list(mpte, free, FALSE);
2861 atomic_subtract_int(&cnt.v_wire_count, 1);
2867 * pmap_remove_pte: do the things to unmap a page in a process
2870 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2875 rw_assert(&pvh_global_lock, RA_WLOCKED);
2876 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2877 oldpte = pte_load_clear(ptq);
2878 KASSERT(oldpte != 0,
2879 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2881 pmap->pm_stats.wired_count -= 1;
2883 * Machines that don't support invlpg, also don't support
2887 pmap_invalidate_page(kernel_pmap, va);
2888 pmap->pm_stats.resident_count -= 1;
2889 if (oldpte & PG_MANAGED) {
2890 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2891 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2894 vm_page_aflag_set(m, PGA_REFERENCED);
2895 pmap_remove_entry(pmap, m, va);
2897 return (pmap_unuse_pt(pmap, va, free));
2901 * Remove a single page from a process address space
2904 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2908 rw_assert(&pvh_global_lock, RA_WLOCKED);
2909 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2910 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2911 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2913 pmap_remove_pte(pmap, pte, va, free);
2914 pmap_invalidate_page(pmap, va);
2918 * Remove the given range of addresses from the specified map.
2920 * It is assumed that the start and end are properly
2921 * rounded to the page size.
2924 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2929 vm_page_t free = NULL;
2933 * Perform an unsynchronized read. This is, however, safe.
2935 if (pmap->pm_stats.resident_count == 0)
2940 rw_wlock(&pvh_global_lock);
2945 * special handling of removing one page. a very
2946 * common operation and easy to short circuit some
2949 if ((sva + PAGE_SIZE == eva) &&
2950 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2951 pmap_remove_page(pmap, sva, &free);
2955 for (; sva < eva; sva = pdnxt) {
2959 * Calculate index for next page table.
2961 pdnxt = (sva + NBPDR) & ~PDRMASK;
2964 if (pmap->pm_stats.resident_count == 0)
2967 pdirindex = sva >> PDRSHIFT;
2968 ptpaddr = pmap->pm_pdir[pdirindex];
2971 * Weed out invalid mappings. Note: we assume that the page
2972 * directory table is always allocated, and in kernel virtual.
2978 * Check for large page.
2980 if ((ptpaddr & PG_PS) != 0) {
2982 * Are we removing the entire large page? If not,
2983 * demote the mapping and fall through.
2985 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2987 * The TLB entry for a PG_G mapping is
2988 * invalidated by pmap_remove_pde().
2990 if ((ptpaddr & PG_G) == 0)
2992 pmap_remove_pde(pmap,
2993 &pmap->pm_pdir[pdirindex], sva, &free);
2995 } else if (!pmap_demote_pde(pmap,
2996 &pmap->pm_pdir[pdirindex], sva)) {
2997 /* The large page mapping was destroyed. */
3003 * Limit our scan to either the end of the va represented
3004 * by the current page table page, or to the end of the
3005 * range being removed.
3010 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3016 * The TLB entry for a PG_G mapping is invalidated
3017 * by pmap_remove_pte().
3019 if ((*pte & PG_G) == 0)
3021 if (pmap_remove_pte(pmap, pte, sva, &free))
3028 pmap_invalidate_all(pmap);
3029 rw_wunlock(&pvh_global_lock);
3031 pmap_free_zero_pages(free);
3035 * Routine: pmap_remove_all
3037 * Removes this physical page from
3038 * all physical maps in which it resides.
3039 * Reflects back modify bits to the pager.
3042 * Original versions of this routine were very
3043 * inefficient because they iteratively called
3044 * pmap_remove (slow...)
3048 pmap_remove_all(vm_page_t m)
3050 struct md_page *pvh;
3053 pt_entry_t *pte, tpte;
3058 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3059 ("pmap_remove_all: page %p is not managed", m));
3061 rw_wlock(&pvh_global_lock);
3063 if ((m->flags & PG_FICTITIOUS) != 0)
3064 goto small_mappings;
3065 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3066 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3070 pde = pmap_pde(pmap, va);
3071 (void)pmap_demote_pde(pmap, pde, va);
3075 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3078 pmap->pm_stats.resident_count--;
3079 pde = pmap_pde(pmap, pv->pv_va);
3080 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3081 " a 4mpage in page %p's pv list", m));
3082 pte = pmap_pte_quick(pmap, pv->pv_va);
3083 tpte = pte_load_clear(pte);
3084 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3087 pmap->pm_stats.wired_count--;
3089 vm_page_aflag_set(m, PGA_REFERENCED);
3092 * Update the vm_page_t clean and reference bits.
3094 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3096 pmap_unuse_pt(pmap, pv->pv_va, &free);
3097 pmap_invalidate_page(pmap, pv->pv_va);
3098 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
3099 free_pv_entry(pmap, pv);
3102 vm_page_aflag_clear(m, PGA_WRITEABLE);
3104 rw_wunlock(&pvh_global_lock);
3105 pmap_free_zero_pages(free);
3109 * pmap_protect_pde: do the things to protect a 4mpage in a process
3112 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3114 pd_entry_t newpde, oldpde;
3115 vm_offset_t eva, va;
3117 boolean_t anychanged;
3119 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3120 KASSERT((sva & PDRMASK) == 0,
3121 ("pmap_protect_pde: sva is not 4mpage aligned"));
3124 oldpde = newpde = *pde;
3125 if (oldpde & PG_MANAGED) {
3127 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3128 va < eva; va += PAGE_SIZE, m++)
3129 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3132 if ((prot & VM_PROT_WRITE) == 0)
3133 newpde &= ~(PG_RW | PG_M);
3135 if ((prot & VM_PROT_EXECUTE) == 0)
3138 if (newpde != oldpde) {
3139 if (!pde_cmpset(pde, oldpde, newpde))
3142 pmap_invalidate_page(pmap, sva);
3146 return (anychanged);
3150 * Set the physical protection on the
3151 * specified range of this map as requested.
3154 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3159 boolean_t anychanged, pv_lists_locked;
3161 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3162 pmap_remove(pmap, sva, eva);
3167 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3168 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3171 if (prot & VM_PROT_WRITE)
3175 if (pmap_is_current(pmap))
3176 pv_lists_locked = FALSE;
3178 pv_lists_locked = TRUE;
3180 rw_wlock(&pvh_global_lock);
3186 for (; sva < eva; sva = pdnxt) {
3187 pt_entry_t obits, pbits;
3190 pdnxt = (sva + NBPDR) & ~PDRMASK;
3194 pdirindex = sva >> PDRSHIFT;
3195 ptpaddr = pmap->pm_pdir[pdirindex];
3198 * Weed out invalid mappings. Note: we assume that the page
3199 * directory table is always allocated, and in kernel virtual.
3205 * Check for large page.
3207 if ((ptpaddr & PG_PS) != 0) {
3209 * Are we protecting the entire large page? If not,
3210 * demote the mapping and fall through.
3212 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3214 * The TLB entry for a PG_G mapping is
3215 * invalidated by pmap_protect_pde().
3217 if (pmap_protect_pde(pmap,
3218 &pmap->pm_pdir[pdirindex], sva, prot))
3222 if (!pv_lists_locked) {
3223 pv_lists_locked = TRUE;
3224 if (!rw_try_wlock(&pvh_global_lock)) {
3226 pmap_invalidate_all(
3233 if (!pmap_demote_pde(pmap,
3234 &pmap->pm_pdir[pdirindex], sva)) {
3236 * The large page mapping was
3247 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3253 * Regardless of whether a pte is 32 or 64 bits in
3254 * size, PG_RW, PG_A, and PG_M are among the least
3255 * significant 32 bits.
3257 obits = pbits = *pte;
3258 if ((pbits & PG_V) == 0)
3261 if ((prot & VM_PROT_WRITE) == 0) {
3262 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3263 (PG_MANAGED | PG_M | PG_RW)) {
3264 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3267 pbits &= ~(PG_RW | PG_M);
3270 if ((prot & VM_PROT_EXECUTE) == 0)
3274 if (pbits != obits) {
3276 if (!atomic_cmpset_64(pte, obits, pbits))
3279 if (!atomic_cmpset_int((u_int *)pte, obits,
3284 pmap_invalidate_page(pmap, sva);
3291 pmap_invalidate_all(pmap);
3292 if (pv_lists_locked) {
3294 rw_wunlock(&pvh_global_lock);
3300 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3301 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3302 * For promotion to occur, two conditions must be met: (1) the 4KB page
3303 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3304 * mappings must have identical characteristics.
3306 * Managed (PG_MANAGED) mappings within the kernel address space are not
3307 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3308 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3312 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3315 pt_entry_t *firstpte, oldpte, pa, *pte;
3316 vm_offset_t oldpteva;
3319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3322 * Examine the first PTE in the specified PTP. Abort if this PTE is
3323 * either invalid, unused, or does not map the first 4KB physical page
3324 * within a 2- or 4MB page.
3326 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3329 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3330 pmap_pde_p_failures++;
3331 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3332 " in pmap %p", va, pmap);
3335 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3336 pmap_pde_p_failures++;
3337 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3338 " in pmap %p", va, pmap);
3341 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3343 * When PG_M is already clear, PG_RW can be cleared without
3344 * a TLB invalidation.
3346 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3353 * Examine each of the other PTEs in the specified PTP. Abort if this
3354 * PTE maps an unexpected 4KB physical page or does not have identical
3355 * characteristics to the first PTE.
3357 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3358 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3361 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3362 pmap_pde_p_failures++;
3363 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3364 " in pmap %p", va, pmap);
3367 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3369 * When PG_M is already clear, PG_RW can be cleared
3370 * without a TLB invalidation.
3372 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3376 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3378 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3379 " in pmap %p", oldpteva, pmap);
3381 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3382 pmap_pde_p_failures++;
3383 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3384 " in pmap %p", va, pmap);
3391 * Save the page table page in its current state until the PDE
3392 * mapping the superpage is demoted by pmap_demote_pde() or
3393 * destroyed by pmap_remove_pde().
3395 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3396 KASSERT(mpte >= vm_page_array &&
3397 mpte < &vm_page_array[vm_page_array_size],
3398 ("pmap_promote_pde: page table page is out of range"));
3399 KASSERT(mpte->pindex == va >> PDRSHIFT,
3400 ("pmap_promote_pde: page table page's pindex is wrong"));
3401 pmap_insert_pt_page(pmap, mpte);
3404 * Promote the pv entries.
3406 if ((newpde & PG_MANAGED) != 0)
3407 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3410 * Propagate the PAT index to its proper position.
3412 if ((newpde & PG_PTE_PAT) != 0)
3413 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3416 * Map the superpage.
3418 if (workaround_erratum383)
3419 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3420 else if (pmap == kernel_pmap)
3421 pmap_kenter_pde(va, PG_PS | newpde);
3423 pde_store(pde, PG_PS | newpde);
3425 pmap_pde_promotions++;
3426 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3427 " in pmap %p", va, pmap);
3431 * Insert the given physical page (p) at
3432 * the specified virtual address (v) in the
3433 * target physical map with the protection requested.
3435 * If specified, the page will be wired down, meaning
3436 * that the related pte can not be reclaimed.
3438 * NB: This is the only routine which MAY NOT lazy-evaluate
3439 * or lose information. That is, this routine must actually
3440 * insert this page into the given map NOW.
3443 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3444 vm_prot_t prot, boolean_t wired)
3448 pt_entry_t newpte, origpte;
3454 va = trunc_page(va);
3455 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3456 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3457 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3459 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3460 VM_OBJECT_LOCKED(m->object),
3461 ("pmap_enter: page %p is not busy", m));
3465 rw_wlock(&pvh_global_lock);
3470 * In the case that a page table page is not
3471 * resident, we are creating it here.
3473 if (va < VM_MAXUSER_ADDRESS) {
3474 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3477 pde = pmap_pde(pmap, va);
3478 if ((*pde & PG_PS) != 0)
3479 panic("pmap_enter: attempted pmap_enter on 4MB page");
3480 pte = pmap_pte_quick(pmap, va);
3483 * Page Directory table entry not valid, we need a new PT page
3486 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3487 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3490 pa = VM_PAGE_TO_PHYS(m);
3493 opa = origpte & PG_FRAME;
3496 * Mapping has not changed, must be protection or wiring change.
3498 if (origpte && (opa == pa)) {
3500 * Wiring change, just update stats. We don't worry about
3501 * wiring PT pages as they remain resident as long as there
3502 * are valid mappings in them. Hence, if a user page is wired,
3503 * the PT page will be also.
3505 if (wired && ((origpte & PG_W) == 0))
3506 pmap->pm_stats.wired_count++;
3507 else if (!wired && (origpte & PG_W))
3508 pmap->pm_stats.wired_count--;
3511 * Remove extra pte reference
3516 if (origpte & PG_MANAGED) {
3526 * Mapping has changed, invalidate old range and fall through to
3527 * handle validating new mapping.
3531 pmap->pm_stats.wired_count--;
3532 if (origpte & PG_MANAGED) {
3533 om = PHYS_TO_VM_PAGE(opa);
3534 pv = pmap_pvh_remove(&om->md, pmap, va);
3538 KASSERT(mpte->wire_count > 0,
3539 ("pmap_enter: missing reference to page table page,"
3543 pmap->pm_stats.resident_count++;
3546 * Enter on the PV list if part of our managed memory.
3548 if ((m->oflags & VPO_UNMANAGED) == 0) {
3549 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3550 ("pmap_enter: managed mapping within the clean submap"));
3552 pv = get_pv_entry(pmap, FALSE);
3554 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3556 } else if (pv != NULL)
3557 free_pv_entry(pmap, pv);
3560 * Increment counters
3563 pmap->pm_stats.wired_count++;
3567 * Now validate mapping with desired protection/wiring.
3569 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3570 if ((prot & VM_PROT_WRITE) != 0) {
3572 if ((newpte & PG_MANAGED) != 0)
3573 vm_page_aflag_set(m, PGA_WRITEABLE);
3576 if ((prot & VM_PROT_EXECUTE) == 0)
3581 if (va < VM_MAXUSER_ADDRESS)
3583 if (pmap == kernel_pmap)
3587 * if the mapping or permission bits are different, we need
3588 * to update the pte.
3590 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3592 if ((access & VM_PROT_WRITE) != 0)
3594 if (origpte & PG_V) {
3596 origpte = pte_load_store(pte, newpte);
3597 if (origpte & PG_A) {
3598 if (origpte & PG_MANAGED)
3599 vm_page_aflag_set(om, PGA_REFERENCED);
3600 if (opa != VM_PAGE_TO_PHYS(m))
3603 if ((origpte & PG_NX) == 0 &&
3604 (newpte & PG_NX) != 0)
3608 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3609 if ((origpte & PG_MANAGED) != 0)
3611 if ((prot & VM_PROT_WRITE) == 0)
3614 if ((origpte & PG_MANAGED) != 0 &&
3615 TAILQ_EMPTY(&om->md.pv_list) &&
3616 ((om->flags & PG_FICTITIOUS) != 0 ||
3617 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3618 vm_page_aflag_clear(om, PGA_WRITEABLE);
3620 pmap_invalidate_page(pmap, va);
3622 pte_store(pte, newpte);
3626 * If both the page table page and the reservation are fully
3627 * populated, then attempt promotion.
3629 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3630 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3631 vm_reserv_level_iffullpop(m) == 0)
3632 pmap_promote_pde(pmap, pde, va);
3635 rw_wunlock(&pvh_global_lock);
3640 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3641 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3642 * blocking, (2) a mapping already exists at the specified virtual address, or
3643 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3646 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3648 pd_entry_t *pde, newpde;
3650 rw_assert(&pvh_global_lock, RA_WLOCKED);
3651 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3652 pde = pmap_pde(pmap, va);
3654 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3655 " in pmap %p", va, pmap);
3658 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3660 if ((m->oflags & VPO_UNMANAGED) == 0) {
3661 newpde |= PG_MANAGED;
3664 * Abort this mapping if its PV entry could not be created.
3666 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3667 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3668 " in pmap %p", va, pmap);
3673 if ((prot & VM_PROT_EXECUTE) == 0)
3676 if (va < VM_MAXUSER_ADDRESS)
3680 * Increment counters.
3682 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3685 * Map the superpage.
3687 pde_store(pde, newpde);
3689 pmap_pde_mappings++;
3690 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3691 " in pmap %p", va, pmap);
3696 * Maps a sequence of resident pages belonging to the same object.
3697 * The sequence begins with the given page m_start. This page is
3698 * mapped at the given virtual address start. Each subsequent page is
3699 * mapped at a virtual address that is offset from start by the same
3700 * amount as the page is offset from m_start within the object. The
3701 * last page in the sequence is the page with the largest offset from
3702 * m_start that can be mapped at a virtual address less than the given
3703 * virtual address end. Not every virtual page between start and end
3704 * is mapped; only those for which a resident page exists with the
3705 * corresponding offset from m_start are mapped.
3708 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3709 vm_page_t m_start, vm_prot_t prot)
3713 vm_pindex_t diff, psize;
3715 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3716 psize = atop(end - start);
3719 rw_wlock(&pvh_global_lock);
3721 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3722 va = start + ptoa(diff);
3723 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3724 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3725 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3726 pmap_enter_pde(pmap, va, m, prot))
3727 m = &m[NBPDR / PAGE_SIZE - 1];
3729 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3731 m = TAILQ_NEXT(m, listq);
3733 rw_wunlock(&pvh_global_lock);
3738 * this code makes some *MAJOR* assumptions:
3739 * 1. Current pmap & pmap exists.
3742 * 4. No page table pages.
3743 * but is *MUCH* faster than pmap_enter...
3747 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3750 rw_wlock(&pvh_global_lock);
3752 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3753 rw_wunlock(&pvh_global_lock);
3758 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3759 vm_prot_t prot, vm_page_t mpte)
3765 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3766 (m->oflags & VPO_UNMANAGED) != 0,
3767 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3768 rw_assert(&pvh_global_lock, RA_WLOCKED);
3769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3772 * In the case that a page table page is not
3773 * resident, we are creating it here.
3775 if (va < VM_MAXUSER_ADDRESS) {
3780 * Calculate pagetable page index
3782 ptepindex = va >> PDRSHIFT;
3783 if (mpte && (mpte->pindex == ptepindex)) {
3787 * Get the page directory entry
3789 ptepa = pmap->pm_pdir[ptepindex];
3792 * If the page table page is mapped, we just increment
3793 * the hold count, and activate it.
3798 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3801 mpte = _pmap_allocpte(pmap, ptepindex,
3812 * This call to vtopte makes the assumption that we are
3813 * entering the page into the current pmap. In order to support
3814 * quick entry into any pmap, one would likely use pmap_pte_quick.
3815 * But that isn't as quick as vtopte.
3827 * Enter on the PV list if part of our managed memory.
3829 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3830 !pmap_try_insert_pv_entry(pmap, va, m)) {
3833 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3834 pmap_invalidate_page(pmap, va);
3835 pmap_free_zero_pages(free);
3844 * Increment counters
3846 pmap->pm_stats.resident_count++;
3848 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3850 if ((prot & VM_PROT_EXECUTE) == 0)
3855 * Now validate mapping with RO protection
3857 if ((m->oflags & VPO_UNMANAGED) != 0)
3858 pte_store(pte, pa | PG_V | PG_U);
3860 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3865 * Make a temporary mapping for a physical address. This is only intended
3866 * to be used for panic dumps.
3869 pmap_kenter_temporary(vm_paddr_t pa, int i)
3873 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3874 pmap_kenter(va, pa);
3876 return ((void *)crashdumpmap);
3880 * This code maps large physical mmap regions into the
3881 * processor address space. Note that some shortcuts
3882 * are taken, but the code works.
3885 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3886 vm_pindex_t pindex, vm_size_t size)
3889 vm_paddr_t pa, ptepa;
3893 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3894 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3895 ("pmap_object_init_pt: non-device object"));
3897 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3898 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3900 p = vm_page_lookup(object, pindex);
3901 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3902 ("pmap_object_init_pt: invalid page %p", p));
3903 pat_mode = p->md.pat_mode;
3906 * Abort the mapping if the first page is not physically
3907 * aligned to a 2/4MB page boundary.
3909 ptepa = VM_PAGE_TO_PHYS(p);
3910 if (ptepa & (NBPDR - 1))
3914 * Skip the first page. Abort the mapping if the rest of
3915 * the pages are not physically contiguous or have differing
3916 * memory attributes.
3918 p = TAILQ_NEXT(p, listq);
3919 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3921 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3922 ("pmap_object_init_pt: invalid page %p", p));
3923 if (pa != VM_PAGE_TO_PHYS(p) ||
3924 pat_mode != p->md.pat_mode)
3926 p = TAILQ_NEXT(p, listq);
3930 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3931 * "size" is a multiple of 2/4M, adding the PAT setting to
3932 * "pa" will not affect the termination of this loop.
3935 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3936 size; pa += NBPDR) {
3937 pde = pmap_pde(pmap, addr);
3939 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3940 PG_U | PG_RW | PG_V);
3941 pmap->pm_stats.resident_count += NBPDR /
3943 pmap_pde_mappings++;
3945 /* Else continue on if the PDE is already valid. */
3953 * Routine: pmap_change_wiring
3954 * Function: Change the wiring attribute for a map/virtual-address
3956 * In/out conditions:
3957 * The mapping must already exist in the pmap.
3960 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3964 boolean_t are_queues_locked;
3966 are_queues_locked = FALSE;
3969 pde = pmap_pde(pmap, va);
3970 if ((*pde & PG_PS) != 0) {
3971 if (!wired != ((*pde & PG_W) == 0)) {
3972 if (!are_queues_locked) {
3973 are_queues_locked = TRUE;
3974 if (!rw_try_wlock(&pvh_global_lock)) {
3976 rw_wlock(&pvh_global_lock);
3980 if (!pmap_demote_pde(pmap, pde, va))
3981 panic("pmap_change_wiring: demotion failed");
3985 pte = pmap_pte(pmap, va);
3987 if (wired && !pmap_pte_w(pte))
3988 pmap->pm_stats.wired_count++;
3989 else if (!wired && pmap_pte_w(pte))
3990 pmap->pm_stats.wired_count--;
3993 * Wiring is not a hardware characteristic so there is no need to
3996 pmap_pte_set_w(pte, wired);
3997 pmap_pte_release(pte);
3999 if (are_queues_locked)
4000 rw_wunlock(&pvh_global_lock);
4007 * Copy the range specified by src_addr/len
4008 * from the source map to the range dst_addr/len
4009 * in the destination map.
4011 * This routine is only advisory and need not do anything.
4015 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4016 vm_offset_t src_addr)
4020 vm_offset_t end_addr = src_addr + len;
4023 if (dst_addr != src_addr)
4026 if (!pmap_is_current(src_pmap))
4029 rw_wlock(&pvh_global_lock);
4030 if (dst_pmap < src_pmap) {
4031 PMAP_LOCK(dst_pmap);
4032 PMAP_LOCK(src_pmap);
4034 PMAP_LOCK(src_pmap);
4035 PMAP_LOCK(dst_pmap);
4038 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4039 pt_entry_t *src_pte, *dst_pte;
4040 vm_page_t dstmpte, srcmpte;
4041 pd_entry_t srcptepaddr;
4044 KASSERT(addr < UPT_MIN_ADDRESS,
4045 ("pmap_copy: invalid to pmap_copy page tables"));
4047 pdnxt = (addr + NBPDR) & ~PDRMASK;
4050 ptepindex = addr >> PDRSHIFT;
4052 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4053 if (srcptepaddr == 0)
4056 if (srcptepaddr & PG_PS) {
4057 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4058 ((srcptepaddr & PG_MANAGED) == 0 ||
4059 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4061 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4063 dst_pmap->pm_stats.resident_count +=
4069 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4070 KASSERT(srcmpte->wire_count > 0,
4071 ("pmap_copy: source page table page is unused"));
4073 if (pdnxt > end_addr)
4076 src_pte = vtopte(addr);
4077 while (addr < pdnxt) {
4081 * we only virtual copy managed pages
4083 if ((ptetemp & PG_MANAGED) != 0) {
4084 dstmpte = pmap_allocpte(dst_pmap, addr,
4086 if (dstmpte == NULL)
4088 dst_pte = pmap_pte_quick(dst_pmap, addr);
4089 if (*dst_pte == 0 &&
4090 pmap_try_insert_pv_entry(dst_pmap, addr,
4091 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4093 * Clear the wired, modified, and
4094 * accessed (referenced) bits
4097 *dst_pte = ptetemp & ~(PG_W | PG_M |
4099 dst_pmap->pm_stats.resident_count++;
4102 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4104 pmap_invalidate_page(dst_pmap,
4106 pmap_free_zero_pages(free);
4110 if (dstmpte->wire_count >= srcmpte->wire_count)
4119 rw_wunlock(&pvh_global_lock);
4120 PMAP_UNLOCK(src_pmap);
4121 PMAP_UNLOCK(dst_pmap);
4124 static __inline void
4125 pagezero(void *page)
4127 #if defined(I686_CPU)
4128 if (cpu_class == CPUCLASS_686) {
4129 #if defined(CPU_ENABLE_SSE)
4130 if (cpu_feature & CPUID_SSE2)
4131 sse2_pagezero(page);
4134 i686_pagezero(page);
4137 bzero(page, PAGE_SIZE);
4141 * pmap_zero_page zeros the specified hardware page by mapping
4142 * the page into KVM and using bzero to clear its contents.
4145 pmap_zero_page(vm_page_t m)
4147 struct sysmaps *sysmaps;
4149 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4150 mtx_lock(&sysmaps->lock);
4151 if (*sysmaps->CMAP2)
4152 panic("pmap_zero_page: CMAP2 busy");
4154 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4155 pmap_cache_bits(m->md.pat_mode, 0);
4156 invlcaddr(sysmaps->CADDR2);
4157 pagezero(sysmaps->CADDR2);
4158 *sysmaps->CMAP2 = 0;
4160 mtx_unlock(&sysmaps->lock);
4164 * pmap_zero_page_area zeros the specified hardware page by mapping
4165 * the page into KVM and using bzero to clear its contents.
4167 * off and size may not cover an area beyond a single hardware page.
4170 pmap_zero_page_area(vm_page_t m, int off, int size)
4172 struct sysmaps *sysmaps;
4174 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4175 mtx_lock(&sysmaps->lock);
4176 if (*sysmaps->CMAP2)
4177 panic("pmap_zero_page_area: CMAP2 busy");
4179 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4180 pmap_cache_bits(m->md.pat_mode, 0);
4181 invlcaddr(sysmaps->CADDR2);
4182 if (off == 0 && size == PAGE_SIZE)
4183 pagezero(sysmaps->CADDR2);
4185 bzero((char *)sysmaps->CADDR2 + off, size);
4186 *sysmaps->CMAP2 = 0;
4188 mtx_unlock(&sysmaps->lock);
4192 * pmap_zero_page_idle zeros the specified hardware page by mapping
4193 * the page into KVM and using bzero to clear its contents. This
4194 * is intended to be called from the vm_pagezero process only and
4198 pmap_zero_page_idle(vm_page_t m)
4202 panic("pmap_zero_page_idle: CMAP3 busy");
4204 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4205 pmap_cache_bits(m->md.pat_mode, 0);
4213 * pmap_copy_page copies the specified (machine independent)
4214 * page by mapping the page into virtual memory and using
4215 * bcopy to copy the page, one machine dependent page at a
4219 pmap_copy_page(vm_page_t src, vm_page_t dst)
4221 struct sysmaps *sysmaps;
4223 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4224 mtx_lock(&sysmaps->lock);
4225 if (*sysmaps->CMAP1)
4226 panic("pmap_copy_page: CMAP1 busy");
4227 if (*sysmaps->CMAP2)
4228 panic("pmap_copy_page: CMAP2 busy");
4230 invlpg((u_int)sysmaps->CADDR1);
4231 invlpg((u_int)sysmaps->CADDR2);
4232 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4233 pmap_cache_bits(src->md.pat_mode, 0);
4234 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4235 pmap_cache_bits(dst->md.pat_mode, 0);
4236 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4237 *sysmaps->CMAP1 = 0;
4238 *sysmaps->CMAP2 = 0;
4240 mtx_unlock(&sysmaps->lock);
4244 * Returns true if the pmap's pv is one of the first
4245 * 16 pvs linked to from this page. This count may
4246 * be changed upwards or downwards in the future; it
4247 * is only necessary that true be returned for a small
4248 * subset of pmaps for proper page aging.
4251 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4253 struct md_page *pvh;
4258 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4259 ("pmap_page_exists_quick: page %p is not managed", m));
4261 rw_wlock(&pvh_global_lock);
4262 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4263 if (PV_PMAP(pv) == pmap) {
4271 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4272 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4273 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4274 if (PV_PMAP(pv) == pmap) {
4283 rw_wunlock(&pvh_global_lock);
4288 * pmap_page_wired_mappings:
4290 * Return the number of managed mappings to the given physical page
4294 pmap_page_wired_mappings(vm_page_t m)
4299 if ((m->oflags & VPO_UNMANAGED) != 0)
4301 rw_wlock(&pvh_global_lock);
4302 count = pmap_pvh_wired_mappings(&m->md, count);
4303 if ((m->flags & PG_FICTITIOUS) == 0) {
4304 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4307 rw_wunlock(&pvh_global_lock);
4312 * pmap_pvh_wired_mappings:
4314 * Return the updated number "count" of managed mappings that are wired.
4317 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4323 rw_assert(&pvh_global_lock, RA_WLOCKED);
4325 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4328 pte = pmap_pte_quick(pmap, pv->pv_va);
4329 if ((*pte & PG_W) != 0)
4338 * Returns TRUE if the given page is mapped individually or as part of
4339 * a 4mpage. Otherwise, returns FALSE.
4342 pmap_page_is_mapped(vm_page_t m)
4346 if ((m->oflags & VPO_UNMANAGED) != 0)
4348 rw_wlock(&pvh_global_lock);
4349 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4350 ((m->flags & PG_FICTITIOUS) == 0 &&
4351 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4352 rw_wunlock(&pvh_global_lock);
4357 * Remove all pages from specified address space
4358 * this aids process exit speeds. Also, this code
4359 * is special cased for current process only, but
4360 * can have the more generic (and slightly slower)
4361 * mode enabled. This is much faster than pmap_remove
4362 * in the case of running down an entire address space.
4365 pmap_remove_pages(pmap_t pmap)
4367 pt_entry_t *pte, tpte;
4368 vm_page_t free = NULL;
4369 vm_page_t m, mpte, mt;
4371 struct md_page *pvh;
4372 struct pv_chunk *pc, *npc;
4375 uint32_t inuse, bitmask;
4378 if (pmap != PCPU_GET(curpmap)) {
4379 printf("warning: pmap_remove_pages called with non-current pmap\n");
4382 rw_wlock(&pvh_global_lock);
4385 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4386 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4389 for (field = 0; field < _NPCM; field++) {
4390 inuse = ~pc->pc_map[field] & pc_freemask[field];
4391 while (inuse != 0) {
4393 bitmask = 1UL << bit;
4394 idx = field * 32 + bit;
4395 pv = &pc->pc_pventry[idx];
4398 pte = pmap_pde(pmap, pv->pv_va);
4400 if ((tpte & PG_PS) == 0) {
4401 pte = vtopte(pv->pv_va);
4402 tpte = *pte & ~PG_PTE_PAT;
4407 "TPTE at %p IS ZERO @ VA %08x\n",
4413 * We cannot remove wired pages from a process' mapping at this time
4420 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4421 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4422 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4423 m, (uintmax_t)m->phys_addr,
4426 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4427 m < &vm_page_array[vm_page_array_size],
4428 ("pmap_remove_pages: bad tpte %#jx",
4434 * Update the vm_page_t clean/reference bits.
4436 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4437 if ((tpte & PG_PS) != 0) {
4438 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4445 PV_STAT(pv_entry_frees++);
4446 PV_STAT(pv_entry_spare++);
4448 pc->pc_map[field] |= bitmask;
4449 if ((tpte & PG_PS) != 0) {
4450 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4451 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4452 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4453 if (TAILQ_EMPTY(&pvh->pv_list)) {
4454 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4455 if (TAILQ_EMPTY(&mt->md.pv_list))
4456 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4458 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4460 pmap_remove_pt_page(pmap, mpte);
4461 pmap->pm_stats.resident_count--;
4462 KASSERT(mpte->wire_count == NPTEPG,
4463 ("pmap_remove_pages: pte page wire count error"));
4464 mpte->wire_count = 0;
4465 pmap_add_delayed_free_list(mpte, &free, FALSE);
4466 atomic_subtract_int(&cnt.v_wire_count, 1);
4469 pmap->pm_stats.resident_count--;
4470 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4471 if (TAILQ_EMPTY(&m->md.pv_list) &&
4472 (m->flags & PG_FICTITIOUS) == 0) {
4473 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4474 if (TAILQ_EMPTY(&pvh->pv_list))
4475 vm_page_aflag_clear(m, PGA_WRITEABLE);
4477 pmap_unuse_pt(pmap, pv->pv_va, &free);
4482 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4487 pmap_invalidate_all(pmap);
4488 rw_wunlock(&pvh_global_lock);
4490 pmap_free_zero_pages(free);
4496 * Return whether or not the specified physical page was modified
4497 * in any physical maps.
4500 pmap_is_modified(vm_page_t m)
4504 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4505 ("pmap_is_modified: page %p is not managed", m));
4508 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4509 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4510 * is clear, no PTEs can have PG_M set.
4512 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4513 if ((m->oflags & VPO_BUSY) == 0 &&
4514 (m->aflags & PGA_WRITEABLE) == 0)
4516 rw_wlock(&pvh_global_lock);
4517 rv = pmap_is_modified_pvh(&m->md) ||
4518 ((m->flags & PG_FICTITIOUS) == 0 &&
4519 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4520 rw_wunlock(&pvh_global_lock);
4525 * Returns TRUE if any of the given mappings were used to modify
4526 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4527 * mappings are supported.
4530 pmap_is_modified_pvh(struct md_page *pvh)
4537 rw_assert(&pvh_global_lock, RA_WLOCKED);
4540 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4543 pte = pmap_pte_quick(pmap, pv->pv_va);
4544 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4554 * pmap_is_prefaultable:
4556 * Return whether or not the specified virtual address is elgible
4560 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4568 pde = pmap_pde(pmap, addr);
4569 if (*pde != 0 && (*pde & PG_PS) == 0) {
4578 * pmap_is_referenced:
4580 * Return whether or not the specified physical page was referenced
4581 * in any physical maps.
4584 pmap_is_referenced(vm_page_t m)
4588 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4589 ("pmap_is_referenced: page %p is not managed", m));
4590 rw_wlock(&pvh_global_lock);
4591 rv = pmap_is_referenced_pvh(&m->md) ||
4592 ((m->flags & PG_FICTITIOUS) == 0 &&
4593 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4594 rw_wunlock(&pvh_global_lock);
4599 * Returns TRUE if any of the given mappings were referenced and FALSE
4600 * otherwise. Both page and 4mpage mappings are supported.
4603 pmap_is_referenced_pvh(struct md_page *pvh)
4610 rw_assert(&pvh_global_lock, RA_WLOCKED);
4613 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4616 pte = pmap_pte_quick(pmap, pv->pv_va);
4617 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4627 * Clear the write and modified bits in each of the given page's mappings.
4630 pmap_remove_write(vm_page_t m)
4632 struct md_page *pvh;
4633 pv_entry_t next_pv, pv;
4636 pt_entry_t oldpte, *pte;
4639 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4640 ("pmap_remove_write: page %p is not managed", m));
4643 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4644 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4645 * is clear, no page table entries need updating.
4647 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4648 if ((m->oflags & VPO_BUSY) == 0 &&
4649 (m->aflags & PGA_WRITEABLE) == 0)
4651 rw_wlock(&pvh_global_lock);
4653 if ((m->flags & PG_FICTITIOUS) != 0)
4654 goto small_mappings;
4655 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4656 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4660 pde = pmap_pde(pmap, va);
4661 if ((*pde & PG_RW) != 0)
4662 (void)pmap_demote_pde(pmap, pde, va);
4666 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4669 pde = pmap_pde(pmap, pv->pv_va);
4670 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4671 " a 4mpage in page %p's pv list", m));
4672 pte = pmap_pte_quick(pmap, pv->pv_va);
4675 if ((oldpte & PG_RW) != 0) {
4677 * Regardless of whether a pte is 32 or 64 bits
4678 * in size, PG_RW and PG_M are among the least
4679 * significant 32 bits.
4681 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4682 oldpte & ~(PG_RW | PG_M)))
4684 if ((oldpte & PG_M) != 0)
4686 pmap_invalidate_page(pmap, pv->pv_va);
4690 vm_page_aflag_clear(m, PGA_WRITEABLE);
4692 rw_wunlock(&pvh_global_lock);
4696 * pmap_ts_referenced:
4698 * Return a count of reference bits for a page, clearing those bits.
4699 * It is not necessary for every reference bit to be cleared, but it
4700 * is necessary that 0 only be returned when there are truly no
4701 * reference bits set.
4703 * XXX: The exact number of bits to check and clear is a matter that
4704 * should be tested and standardized at some point in the future for
4705 * optimal aging of shared pages.
4708 pmap_ts_referenced(vm_page_t m)
4710 struct md_page *pvh;
4711 pv_entry_t pv, pvf, pvn;
4713 pd_entry_t oldpde, *pde;
4718 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4719 ("pmap_ts_referenced: page %p is not managed", m));
4720 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4721 rw_wlock(&pvh_global_lock);
4723 if ((m->flags & PG_FICTITIOUS) != 0)
4724 goto small_mappings;
4725 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4729 pde = pmap_pde(pmap, va);
4731 if ((oldpde & PG_A) != 0) {
4732 if (pmap_demote_pde(pmap, pde, va)) {
4733 if ((oldpde & PG_W) == 0) {
4735 * Remove the mapping to a single page
4736 * so that a subsequent access may
4737 * repromote. Since the underlying
4738 * page table page is fully populated,
4739 * this removal never frees a page
4742 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4744 pmap_remove_page(pmap, va, NULL);
4756 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4759 pvn = TAILQ_NEXT(pv, pv_list);
4760 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4761 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4764 pde = pmap_pde(pmap, pv->pv_va);
4765 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4766 " found a 4mpage in page %p's pv list", m));
4767 pte = pmap_pte_quick(pmap, pv->pv_va);
4768 if ((*pte & PG_A) != 0) {
4769 atomic_clear_int((u_int *)pte, PG_A);
4770 pmap_invalidate_page(pmap, pv->pv_va);
4776 } while ((pv = pvn) != NULL && pv != pvf);
4780 rw_wunlock(&pvh_global_lock);
4785 * Clear the modify bits on the specified physical page.
4788 pmap_clear_modify(vm_page_t m)
4790 struct md_page *pvh;
4791 pv_entry_t next_pv, pv;
4793 pd_entry_t oldpde, *pde;
4794 pt_entry_t oldpte, *pte;
4797 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4798 ("pmap_clear_modify: page %p is not managed", m));
4799 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4800 KASSERT((m->oflags & VPO_BUSY) == 0,
4801 ("pmap_clear_modify: page %p is busy", m));
4804 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4805 * If the object containing the page is locked and the page is not
4806 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4808 if ((m->aflags & PGA_WRITEABLE) == 0)
4810 rw_wlock(&pvh_global_lock);
4812 if ((m->flags & PG_FICTITIOUS) != 0)
4813 goto small_mappings;
4814 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4815 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4819 pde = pmap_pde(pmap, va);
4821 if ((oldpde & PG_RW) != 0) {
4822 if (pmap_demote_pde(pmap, pde, va)) {
4823 if ((oldpde & PG_W) == 0) {
4825 * Write protect the mapping to a
4826 * single page so that a subsequent
4827 * write access may repromote.
4829 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4831 pte = pmap_pte_quick(pmap, va);
4833 if ((oldpte & PG_V) != 0) {
4835 * Regardless of whether a pte is 32 or 64 bits
4836 * in size, PG_RW and PG_M are among the least
4837 * significant 32 bits.
4839 while (!atomic_cmpset_int((u_int *)pte,
4841 oldpte & ~(PG_M | PG_RW)))
4844 pmap_invalidate_page(pmap, va);
4852 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4855 pde = pmap_pde(pmap, pv->pv_va);
4856 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4857 " a 4mpage in page %p's pv list", m));
4858 pte = pmap_pte_quick(pmap, pv->pv_va);
4859 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4861 * Regardless of whether a pte is 32 or 64 bits
4862 * in size, PG_M is among the least significant
4865 atomic_clear_int((u_int *)pte, PG_M);
4866 pmap_invalidate_page(pmap, pv->pv_va);
4871 rw_wunlock(&pvh_global_lock);
4875 * pmap_clear_reference:
4877 * Clear the reference bit on the specified physical page.
4880 pmap_clear_reference(vm_page_t m)
4882 struct md_page *pvh;
4883 pv_entry_t next_pv, pv;
4885 pd_entry_t oldpde, *pde;
4889 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4890 ("pmap_clear_reference: page %p is not managed", m));
4891 rw_wlock(&pvh_global_lock);
4893 if ((m->flags & PG_FICTITIOUS) != 0)
4894 goto small_mappings;
4895 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4896 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4900 pde = pmap_pde(pmap, va);
4902 if ((oldpde & PG_A) != 0) {
4903 if (pmap_demote_pde(pmap, pde, va)) {
4905 * Remove the mapping to a single page so
4906 * that a subsequent access may repromote.
4907 * Since the underlying page table page is
4908 * fully populated, this removal never frees
4909 * a page table page.
4911 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4913 pmap_remove_page(pmap, va, NULL);
4919 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4922 pde = pmap_pde(pmap, pv->pv_va);
4923 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4924 " a 4mpage in page %p's pv list", m));
4925 pte = pmap_pte_quick(pmap, pv->pv_va);
4926 if ((*pte & PG_A) != 0) {
4928 * Regardless of whether a pte is 32 or 64 bits
4929 * in size, PG_A is among the least significant
4932 atomic_clear_int((u_int *)pte, PG_A);
4933 pmap_invalidate_page(pmap, pv->pv_va);
4938 rw_wunlock(&pvh_global_lock);
4942 * Miscellaneous support routines follow
4945 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4946 static __inline void
4947 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4952 * The cache mode bits are all in the low 32-bits of the
4953 * PTE, so we can just spin on updating the low 32-bits.
4956 opte = *(u_int *)pte;
4957 npte = opte & ~PG_PTE_CACHE;
4959 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4962 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
4963 static __inline void
4964 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4969 * The cache mode bits are all in the low 32-bits of the
4970 * PDE, so we can just spin on updating the low 32-bits.
4973 opde = *(u_int *)pde;
4974 npde = opde & ~PG_PDE_CACHE;
4976 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4980 * Map a set of physical memory pages into the kernel virtual
4981 * address space. Return a pointer to where it is mapped. This
4982 * routine is intended to be used for mapping device memory,
4986 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4988 vm_offset_t va, offset;
4991 offset = pa & PAGE_MASK;
4992 size = roundup(offset + size, PAGE_SIZE);
4995 if (pa < KERNLOAD && pa + size <= KERNLOAD)
4998 va = kmem_alloc_nofault(kernel_map, size);
5000 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5002 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5003 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5004 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5005 pmap_invalidate_cache_range(va, va + size);
5006 return ((void *)(va + offset));
5010 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5013 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5017 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5020 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5024 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5026 vm_offset_t base, offset;
5028 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5030 base = trunc_page(va);
5031 offset = va & PAGE_MASK;
5032 size = roundup(offset + size, PAGE_SIZE);
5033 kmem_free(kernel_map, base, size);
5037 * Sets the memory attribute for the specified page.
5040 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5043 m->md.pat_mode = ma;
5044 if ((m->flags & PG_FICTITIOUS) != 0)
5048 * If "m" is a normal page, flush it from the cache.
5049 * See pmap_invalidate_cache_range().
5051 * First, try to find an existing mapping of the page by sf
5052 * buffer. sf_buf_invalidate_cache() modifies mapping and
5053 * flushes the cache.
5055 if (sf_buf_invalidate_cache(m))
5059 * If page is not mapped by sf buffer, but CPU does not
5060 * support self snoop, map the page transient and do
5061 * invalidation. In the worst case, whole cache is flushed by
5062 * pmap_invalidate_cache_range().
5064 if ((cpu_feature & CPUID_SS) == 0)
5069 pmap_flush_page(vm_page_t m)
5071 struct sysmaps *sysmaps;
5072 vm_offset_t sva, eva;
5074 if ((cpu_feature & CPUID_CLFSH) != 0) {
5075 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5076 mtx_lock(&sysmaps->lock);
5077 if (*sysmaps->CMAP2)
5078 panic("pmap_flush_page: CMAP2 busy");
5080 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5081 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5082 invlcaddr(sysmaps->CADDR2);
5083 sva = (vm_offset_t)sysmaps->CADDR2;
5084 eva = sva + PAGE_SIZE;
5087 * Use mfence despite the ordering implied by
5088 * mtx_{un,}lock() because clflush is not guaranteed
5089 * to be ordered by any other instruction.
5092 for (; sva < eva; sva += cpu_clflush_line_size)
5095 *sysmaps->CMAP2 = 0;
5097 mtx_unlock(&sysmaps->lock);
5099 pmap_invalidate_cache();
5103 * Changes the specified virtual address range's memory type to that given by
5104 * the parameter "mode". The specified virtual address range must be
5105 * completely contained within either the kernel map.
5107 * Returns zero if the change completed successfully, and either EINVAL or
5108 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5109 * of the virtual address range was not mapped, and ENOMEM is returned if
5110 * there was insufficient memory available to complete the change.
5113 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5115 vm_offset_t base, offset, tmpva;
5118 int cache_bits_pte, cache_bits_pde;
5121 base = trunc_page(va);
5122 offset = va & PAGE_MASK;
5123 size = roundup(offset + size, PAGE_SIZE);
5126 * Only supported on kernel virtual addresses above the recursive map.
5128 if (base < VM_MIN_KERNEL_ADDRESS)
5131 cache_bits_pde = pmap_cache_bits(mode, 1);
5132 cache_bits_pte = pmap_cache_bits(mode, 0);
5136 * Pages that aren't mapped aren't supported. Also break down
5137 * 2/4MB pages into 4KB pages if required.
5139 PMAP_LOCK(kernel_pmap);
5140 for (tmpva = base; tmpva < base + size; ) {
5141 pde = pmap_pde(kernel_pmap, tmpva);
5143 PMAP_UNLOCK(kernel_pmap);
5148 * If the current 2/4MB page already has
5149 * the required memory type, then we need not
5150 * demote this page. Just increment tmpva to
5151 * the next 2/4MB page frame.
5153 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5154 tmpva = trunc_4mpage(tmpva) + NBPDR;
5159 * If the current offset aligns with a 2/4MB
5160 * page frame and there is at least 2/4MB left
5161 * within the range, then we need not break
5162 * down this page into 4KB pages.
5164 if ((tmpva & PDRMASK) == 0 &&
5165 tmpva + PDRMASK < base + size) {
5169 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5170 PMAP_UNLOCK(kernel_pmap);
5174 pte = vtopte(tmpva);
5176 PMAP_UNLOCK(kernel_pmap);
5181 PMAP_UNLOCK(kernel_pmap);
5184 * Ok, all the pages exist, so run through them updating their
5185 * cache mode if required.
5187 for (tmpva = base; tmpva < base + size; ) {
5188 pde = pmap_pde(kernel_pmap, tmpva);
5190 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5191 pmap_pde_attr(pde, cache_bits_pde);
5194 tmpva = trunc_4mpage(tmpva) + NBPDR;
5196 pte = vtopte(tmpva);
5197 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5198 pmap_pte_attr(pte, cache_bits_pte);
5206 * Flush CPU caches to make sure any data isn't cached that
5207 * shouldn't be, etc.
5210 pmap_invalidate_range(kernel_pmap, base, tmpva);
5211 pmap_invalidate_cache_range(base, tmpva);
5217 * perform the pmap work for mincore
5220 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5223 pt_entry_t *ptep, pte;
5229 pdep = pmap_pde(pmap, addr);
5231 if (*pdep & PG_PS) {
5233 /* Compute the physical address of the 4KB page. */
5234 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5236 val = MINCORE_SUPER;
5238 ptep = pmap_pte(pmap, addr);
5240 pmap_pte_release(ptep);
5241 pa = pte & PG_FRAME;
5249 if ((pte & PG_V) != 0) {
5250 val |= MINCORE_INCORE;
5251 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5252 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5253 if ((pte & PG_A) != 0)
5254 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5256 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5257 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5258 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5259 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5260 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5263 PA_UNLOCK_COND(*locked_pa);
5269 pmap_activate(struct thread *td)
5271 pmap_t pmap, oldpmap;
5276 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5277 oldpmap = PCPU_GET(curpmap);
5278 cpuid = PCPU_GET(cpuid);
5280 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5281 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5283 CPU_CLR(cpuid, &oldpmap->pm_active);
5284 CPU_SET(cpuid, &pmap->pm_active);
5287 cr3 = vtophys(pmap->pm_pdpt);
5289 cr3 = vtophys(pmap->pm_pdir);
5292 * pmap_activate is for the current thread on the current cpu
5294 td->td_pcb->pcb_cr3 = cr3;
5296 PCPU_SET(curpmap, pmap);
5301 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5306 * Increase the starting virtual address of the given mapping if a
5307 * different alignment might result in more superpage mappings.
5310 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5311 vm_offset_t *addr, vm_size_t size)
5313 vm_offset_t superpage_offset;
5317 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5318 offset += ptoa(object->pg_color);
5319 superpage_offset = offset & PDRMASK;
5320 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5321 (*addr & PDRMASK) == superpage_offset)
5323 if ((*addr & PDRMASK) < superpage_offset)
5324 *addr = (*addr & ~PDRMASK) + superpage_offset;
5326 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5330 #if defined(PMAP_DEBUG)
5331 pmap_pid_dump(int pid)
5338 sx_slock(&allproc_lock);
5339 FOREACH_PROC_IN_SYSTEM(p) {
5340 if (p->p_pid != pid)
5346 pmap = vmspace_pmap(p->p_vmspace);
5347 for (i = 0; i < NPDEPTD; i++) {
5350 vm_offset_t base = i << PDRSHIFT;
5352 pde = &pmap->pm_pdir[i];
5353 if (pde && pmap_pde_v(pde)) {
5354 for (j = 0; j < NPTEPG; j++) {
5355 vm_offset_t va = base + (j << PAGE_SHIFT);
5356 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5361 sx_sunlock(&allproc_lock);
5364 pte = pmap_pte(pmap, va);
5365 if (pte && pmap_pte_v(pte)) {
5369 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5370 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5371 va, pa, m->hold_count, m->wire_count, m->flags);
5386 sx_sunlock(&allproc_lock);
5393 static void pads(pmap_t pm);
5394 void pmap_pvdump(vm_paddr_t pa);
5396 /* print address space of pmap*/
5404 if (pm == kernel_pmap)
5406 for (i = 0; i < NPDEPTD; i++)
5408 for (j = 0; j < NPTEPG; j++) {
5409 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5410 if (pm == kernel_pmap && va < KERNBASE)
5412 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5414 ptep = pmap_pte(pm, va);
5415 if (pmap_pte_v(ptep))
5416 printf("%x:%x ", va, *ptep);
5422 pmap_pvdump(vm_paddr_t pa)
5428 printf("pa %x", pa);
5429 m = PHYS_TO_VM_PAGE(pa);
5430 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
5432 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);