2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * In addition to hardware address maps, this
84 * module is called upon to provide software-use-only
85 * maps which may or may not be stored in the same
86 * form as hardware maps. These pseudo-maps are
87 * used to store intermediate results from copy
88 * operations to and from address spaces.
90 * Since the information managed by this module is
91 * also stored by the logical address mapping module,
92 * this module may throw away valid virtual-to-physical
93 * mappings at almost any time. However, invalidations
94 * of virtual-to-physical mappings must be done as
97 * In order to cope with hardware architectures which
98 * make virtual-to-physical map invalidates expensive,
99 * this module may delay invalidate or reduced protection
100 * operations until such time as they are actually
101 * necessary. This module is given full information as
102 * to which processors are currently using which maps,
103 * and to when physical maps must be made correct.
107 #include "opt_pmap.h"
109 #include "opt_xbox.h"
111 #include <sys/param.h>
112 #include <sys/systm.h>
113 #include <sys/kernel.h>
115 #include <sys/lock.h>
116 #include <sys/malloc.h>
117 #include <sys/mman.h>
118 #include <sys/msgbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/sf_buf.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
129 #include <sys/cpuset.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
141 #include <vm/vm_reserv.h>
144 #include <machine/cpu.h>
145 #include <machine/cputypes.h>
146 #include <machine/md_var.h>
147 #include <machine/pcb.h>
148 #include <machine/specialreg.h>
150 #include <machine/smp.h>
154 #include <machine/xbox.h>
157 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
158 #define CPU_ENABLE_SSE
161 #ifndef PMAP_SHPGPERPROC
162 #define PMAP_SHPGPERPROC 200
165 #if !defined(DIAGNOSTIC)
166 #ifdef __GNUC_GNU_INLINE__
167 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #define PMAP_INLINE extern inline
176 #define PV_STAT(x) do { x ; } while (0)
178 #define PV_STAT(x) do { } while (0)
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
185 * Get PDEs and PTEs for user/kernel address space
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200 struct pmap kernel_pmap_store;
201 LIST_HEAD(pmaplist, pmap);
202 static struct pmaplist allpmaps;
203 static struct mtx allpmaps_lock;
205 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
206 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
207 int pgeflag = 0; /* PG_G or-in */
208 int pseflag = 0; /* PG_PS or-in */
210 static int nkpt = NKPT;
211 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
212 extern u_int32_t KERNend;
213 extern u_int32_t KPTphys;
217 static uma_zone_t pdptzone;
220 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
222 static int pat_works = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
224 "Is page attribute table fully functional?");
226 static int pg_ps_enabled = 1;
227 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
228 "Are large page mappings enabled?");
230 #define PAT_INDEX_SIZE 8
231 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
234 * Data for the pv entry allocation mechanism
236 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
237 static struct md_page *pv_table;
238 static int shpgperproc = PMAP_SHPGPERPROC;
240 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
241 int pv_maxchunks; /* How many chunks we have KVA for */
242 vm_offset_t pv_vafree; /* freelist stored in the PTE */
245 * All those kernel PT submaps that BSD is so fond of
254 static struct sysmaps sysmaps_pcpu[MAXCPU];
255 pt_entry_t *CMAP1 = 0;
256 static pt_entry_t *CMAP3;
257 static pd_entry_t *KPTD;
258 caddr_t CADDR1 = 0, ptvmmap = 0;
259 static caddr_t CADDR3;
260 struct msgbuf *msgbufp = 0;
265 static caddr_t crashdumpmap;
267 static pt_entry_t *PMAP1 = 0, *PMAP2;
268 static pt_entry_t *PADDR1 = 0, *PADDR2;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
286 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
287 static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try);
288 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
289 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
292 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
294 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
296 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
297 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
299 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
300 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
301 static void pmap_flush_page(vm_page_t m);
302 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
303 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
304 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
305 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
306 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
307 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
308 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
309 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
310 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
311 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
313 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
314 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
316 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
318 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
319 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
321 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
323 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
324 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
326 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
328 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
330 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
332 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags);
333 static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
334 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
335 static void pmap_pte_release(pt_entry_t *pte);
336 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
338 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
340 static void pmap_set_pg(void);
342 static __inline void pagezero(void *page);
344 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
345 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
348 * If you get an error here, then you set KVA_PAGES wrong! See the
349 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
350 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
352 CTASSERT(KERNBASE % (1 << 24) == 0);
355 * Bootstrap the system enough to run with virtual memory.
357 * On the i386 this is called after mapping has already been enabled
358 * and just syncs the pmap module with what has already been done.
359 * [We can't call it easily with mapping off since the kernel is not
360 * mapped with PA == VA, hence we would have to relocate every address
361 * from the linked base (virtual) address "KERNBASE" to the actual
362 * (physical) address starting relative to 0]
365 pmap_bootstrap(vm_paddr_t firstaddr)
368 pt_entry_t *pte, *unused;
369 struct sysmaps *sysmaps;
373 * Initialize the first available kernel virtual address. However,
374 * using "firstaddr" may waste a few pages of the kernel virtual
375 * address space, because locore may not have mapped every physical
376 * page that it allocated. Preferably, locore would provide a first
377 * unused virtual address in addition to "firstaddr".
379 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
381 virtual_end = VM_MAX_KERNEL_ADDRESS;
384 * Initialize the kernel pmap (which is statically allocated).
386 PMAP_LOCK_INIT(kernel_pmap);
387 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
389 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
391 kernel_pmap->pm_root = NULL;
392 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
393 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
394 LIST_INIT(&allpmaps);
397 * Request a spin mutex so that changes to allpmaps cannot be
398 * preempted by smp_rendezvous_cpus(). Otherwise,
399 * pmap_update_pde_kernel() could access allpmaps while it is
402 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
403 mtx_lock_spin(&allpmaps_lock);
404 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
405 mtx_unlock_spin(&allpmaps_lock);
408 * Reserve some special page table entries/VA space for temporary
411 #define SYSMAP(c, p, v, n) \
412 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
418 * CMAP1/CMAP2 are used for zeroing and copying pages.
419 * CMAP3 is used for the idle process page zeroing.
421 for (i = 0; i < MAXCPU; i++) {
422 sysmaps = &sysmaps_pcpu[i];
423 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
424 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
425 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
427 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
428 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
433 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
436 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
438 SYSMAP(caddr_t, unused, ptvmmap, 1)
441 * msgbufp is used to map the system message buffer.
443 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
446 * KPTmap is used by pmap_kextract().
448 * KPTmap is first initialized by locore. However, that initial
449 * KPTmap can only support NKPT page table pages. Here, a larger
450 * KPTmap is created that can support KVA_PAGES page table pages.
452 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
454 for (i = 0; i < NKPT; i++)
455 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
458 * Adjust the start of the KPTD and KPTmap so that the implementation
459 * of pmap_kextract() and pmap_growkernel() can be made simpler.
462 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
465 * ptemap is used for pmap_pte_quick
467 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
468 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
470 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
475 * Leave in place an identity mapping (virt == phys) for the low 1 MB
476 * physical memory region that is used by the ACPI wakeup code. This
477 * mapping must not have PG_G set.
480 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
481 * an early stadium, we cannot yet neatly map video memory ... :-(
482 * Better fixes are very welcome! */
483 if (!arch_i386_is_xbox)
485 for (i = 1; i < NKPT; i++)
488 /* Initialize the PAT MSR if present. */
491 /* Turn on PG_G on kernel page(s) */
501 int pat_table[PAT_INDEX_SIZE];
506 /* Set default PAT index table. */
507 for (i = 0; i < PAT_INDEX_SIZE; i++)
509 pat_table[PAT_WRITE_BACK] = 0;
510 pat_table[PAT_WRITE_THROUGH] = 1;
511 pat_table[PAT_UNCACHEABLE] = 3;
512 pat_table[PAT_WRITE_COMBINING] = 3;
513 pat_table[PAT_WRITE_PROTECTED] = 3;
514 pat_table[PAT_UNCACHED] = 3;
516 /* Bail if this CPU doesn't implement PAT. */
517 if ((cpu_feature & CPUID_PAT) == 0) {
518 for (i = 0; i < PAT_INDEX_SIZE; i++)
519 pat_index[i] = pat_table[i];
525 * Due to some Intel errata, we can only safely use the lower 4
528 * Intel Pentium III Processor Specification Update
529 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
532 * Intel Pentium IV Processor Specification Update
533 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
535 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
536 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
539 /* Initialize default PAT entries. */
540 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
541 PAT_VALUE(1, PAT_WRITE_THROUGH) |
542 PAT_VALUE(2, PAT_UNCACHED) |
543 PAT_VALUE(3, PAT_UNCACHEABLE) |
544 PAT_VALUE(4, PAT_WRITE_BACK) |
545 PAT_VALUE(5, PAT_WRITE_THROUGH) |
546 PAT_VALUE(6, PAT_UNCACHED) |
547 PAT_VALUE(7, PAT_UNCACHEABLE);
551 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
552 * Program 5 and 6 as WP and WC.
553 * Leave 4 and 7 as WB and UC.
555 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
556 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
557 PAT_VALUE(6, PAT_WRITE_COMBINING);
558 pat_table[PAT_UNCACHED] = 2;
559 pat_table[PAT_WRITE_PROTECTED] = 5;
560 pat_table[PAT_WRITE_COMBINING] = 6;
563 * Just replace PAT Index 2 with WC instead of UC-.
565 pat_msr &= ~PAT_MASK(2);
566 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
567 pat_table[PAT_WRITE_COMBINING] = 2;
572 load_cr4(cr4 & ~CR4_PGE);
574 /* Disable caches (CD = 1, NW = 0). */
576 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
578 /* Flushes caches and TLBs. */
582 /* Update PAT and index table. */
583 wrmsr(MSR_PAT, pat_msr);
584 for (i = 0; i < PAT_INDEX_SIZE; i++)
585 pat_index[i] = pat_table[i];
587 /* Flush caches and TLBs again. */
591 /* Restore caches and PGE. */
597 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
603 vm_offset_t va, endva;
608 endva = KERNBASE + KERNend;
611 va = KERNBASE + KERNLOAD;
613 pdir_pde(PTD, va) |= pgeflag;
614 invltlb(); /* Play it safe, invltlb() every time */
618 va = (vm_offset_t)btext;
623 invltlb(); /* Play it safe, invltlb() every time */
630 * Initialize a vm_page's machine-dependent fields.
633 pmap_page_init(vm_page_t m)
636 TAILQ_INIT(&m->md.pv_list);
637 m->md.pat_mode = PAT_WRITE_BACK;
642 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
645 /* Inform UMA that this allocator uses kernel_map/object. */
646 *flags = UMA_SLAB_KERNEL;
647 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
648 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
653 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
655 * - Must deal with pages in order to ensure that none of the PG_* bits
656 * are ever set, PG_V in particular.
657 * - Assumes we can write to ptes without pte_store() atomic ops, even
658 * on PAE systems. This should be ok.
659 * - Assumes nothing will ever test these addresses for 0 to indicate
660 * no mapping instead of correctly checking PG_V.
661 * - Assumes a vm_offset_t will fit in a pte (true for i386).
662 * Because PG_V is never set, there can be no mappings to invalidate.
665 pmap_ptelist_alloc(vm_offset_t *head)
672 return (va); /* Out of memory */
676 panic("pmap_ptelist_alloc: va with PG_V set!");
682 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
687 panic("pmap_ptelist_free: freeing va with PG_V set!");
689 *pte = *head; /* virtual! PG_V is 0 though */
694 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
700 for (i = npages - 1; i >= 0; i--) {
701 va = (vm_offset_t)base + i * PAGE_SIZE;
702 pmap_ptelist_free(head, va);
708 * Initialize the pmap module.
709 * Called by vm_init, to initialize any structures that the pmap
710 * system needs to map virtual memory.
720 * Initialize the vm page array entries for the kernel pmap's
723 for (i = 0; i < NKPT; i++) {
724 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
725 KASSERT(mpte >= vm_page_array &&
726 mpte < &vm_page_array[vm_page_array_size],
727 ("pmap_init: page table page is out of range"));
728 mpte->pindex = i + KPTDI;
729 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
733 * Initialize the address space (zone) for the pv entries. Set a
734 * high water mark so that the system can recover from excessive
735 * numbers of pv entries.
737 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
738 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
739 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
740 pv_entry_max = roundup(pv_entry_max, _NPCPV);
741 pv_entry_high_water = 9 * (pv_entry_max / 10);
744 * If the kernel is running in a virtual machine on an AMD Family 10h
745 * processor, then it must assume that MCA is enabled by the virtual
748 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
749 CPUID_TO_FAMILY(cpu_id) == 0x10)
750 workaround_erratum383 = 1;
753 * Are large page mappings supported and enabled?
755 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
758 else if (pg_ps_enabled) {
759 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
760 ("pmap_init: can't assign to pagesizes[1]"));
761 pagesizes[1] = NBPDR;
765 * Calculate the size of the pv head table for superpages.
767 for (i = 0; phys_avail[i + 1]; i += 2);
768 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
771 * Allocate memory for the pv head table for superpages.
773 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
775 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
776 for (i = 0; i < pv_npg; i++)
777 TAILQ_INIT(&pv_table[i].pv_list);
779 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
780 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
781 PAGE_SIZE * pv_maxchunks);
782 if (pv_chunkbase == NULL)
783 panic("pmap_init: not enough kvm for pv chunks");
784 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
786 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
787 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
788 UMA_ZONE_VM | UMA_ZONE_NOFREE);
789 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
794 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
795 "Max number of PV entries");
796 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
797 "Page share factor per proc");
799 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
800 "2/4MB page mapping counters");
802 static u_long pmap_pde_demotions;
803 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
804 &pmap_pde_demotions, 0, "2/4MB page demotions");
806 static u_long pmap_pde_mappings;
807 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
808 &pmap_pde_mappings, 0, "2/4MB page mappings");
810 static u_long pmap_pde_p_failures;
811 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
812 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
814 static u_long pmap_pde_promotions;
815 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
816 &pmap_pde_promotions, 0, "2/4MB page promotions");
818 /***************************************************
819 * Low level helper routines.....
820 ***************************************************/
823 * Determine the appropriate bits to set in a PTE or PDE for a specified
827 pmap_cache_bits(int mode, boolean_t is_pde)
829 int cache_bits, pat_flag, pat_idx;
831 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
832 panic("Unknown caching mode %d\n", mode);
834 /* The PAT bit is different for PTE's and PDE's. */
835 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
837 /* Map the caching mode to a PAT index. */
838 pat_idx = pat_index[mode];
840 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
843 cache_bits |= pat_flag;
845 cache_bits |= PG_NC_PCD;
847 cache_bits |= PG_NC_PWT;
852 * The caller is responsible for maintaining TLB consistency.
855 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
859 boolean_t PTD_updated;
862 mtx_lock_spin(&allpmaps_lock);
863 LIST_FOREACH(pmap, &allpmaps, pm_list) {
864 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
867 pde = pmap_pde(pmap, va);
868 pde_store(pde, newpde);
870 mtx_unlock_spin(&allpmaps_lock);
872 ("pmap_kenter_pde: current page table is not in allpmaps"));
876 * After changing the page size for the specified virtual address in the page
877 * table, flush the corresponding entries from the processor's TLB. Only the
878 * calling processor's TLB is affected.
880 * The calling thread must be pinned to a processor.
883 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
887 if ((newpde & PG_PS) == 0)
888 /* Demotion: flush a specific 2MB page mapping. */
890 else if ((newpde & PG_G) == 0)
892 * Promotion: flush every 4KB page mapping from the TLB
893 * because there are too many to flush individually.
898 * Promotion: flush every 4KB page mapping from the TLB,
899 * including any global (PG_G) mappings.
902 load_cr4(cr4 & ~CR4_PGE);
904 * Although preemption at this point could be detrimental to
905 * performance, it would not lead to an error. PG_G is simply
906 * ignored if CR4.PGE is clear. Moreover, in case this block
907 * is re-entered, the load_cr4() either above or below will
908 * modify CR4.PGE flushing the TLB.
910 load_cr4(cr4 | CR4_PGE);
915 * For SMP, these functions have to use the IPI mechanism for coherence.
917 * N.B.: Before calling any of the following TLB invalidation functions,
918 * the calling processor must ensure that all stores updating a non-
919 * kernel page table are globally performed. Otherwise, another
920 * processor could cache an old, pre-update entry without being
921 * invalidated. This can happen one of two ways: (1) The pmap becomes
922 * active on another processor after its pm_active field is checked by
923 * one of the following functions but before a store updating the page
924 * table is globally performed. (2) The pmap becomes active on another
925 * processor before its pm_active field is checked but due to
926 * speculative loads one of the following functions stills reads the
927 * pmap as inactive on the other processor.
929 * The kernel page table is exempt because its pm_active field is
930 * immutable. The kernel page table is always active on every
934 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
940 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
944 cpuid = PCPU_GET(cpuid);
945 other_cpus = all_cpus;
946 CPU_CLR(cpuid, &other_cpus);
947 if (CPU_ISSET(cpuid, &pmap->pm_active))
949 CPU_AND(&other_cpus, &pmap->pm_active);
950 if (!CPU_EMPTY(&other_cpus))
951 smp_masked_invlpg(other_cpus, va);
957 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
964 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
965 for (addr = sva; addr < eva; addr += PAGE_SIZE)
967 smp_invlpg_range(sva, eva);
969 cpuid = PCPU_GET(cpuid);
970 other_cpus = all_cpus;
971 CPU_CLR(cpuid, &other_cpus);
972 if (CPU_ISSET(cpuid, &pmap->pm_active))
973 for (addr = sva; addr < eva; addr += PAGE_SIZE)
975 CPU_AND(&other_cpus, &pmap->pm_active);
976 if (!CPU_EMPTY(&other_cpus))
977 smp_masked_invlpg_range(other_cpus, sva, eva);
983 pmap_invalidate_all(pmap_t pmap)
989 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
993 cpuid = PCPU_GET(cpuid);
994 other_cpus = all_cpus;
995 CPU_CLR(cpuid, &other_cpus);
996 if (CPU_ISSET(cpuid, &pmap->pm_active))
998 CPU_AND(&other_cpus, &pmap->pm_active);
999 if (!CPU_EMPTY(&other_cpus))
1000 smp_masked_invltlb(other_cpus);
1006 pmap_invalidate_cache(void)
1016 cpuset_t invalidate; /* processors that invalidate their TLB */
1020 u_int store; /* processor that updates the PDE */
1024 pmap_update_pde_kernel(void *arg)
1026 struct pde_action *act = arg;
1030 if (act->store == PCPU_GET(cpuid)) {
1033 * Elsewhere, this operation requires allpmaps_lock for
1034 * synchronization. Here, it does not because it is being
1035 * performed in the context of an all_cpus rendezvous.
1037 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1038 pde = pmap_pde(pmap, act->va);
1039 pde_store(pde, act->newpde);
1045 pmap_update_pde_user(void *arg)
1047 struct pde_action *act = arg;
1049 if (act->store == PCPU_GET(cpuid))
1050 pde_store(act->pde, act->newpde);
1054 pmap_update_pde_teardown(void *arg)
1056 struct pde_action *act = arg;
1058 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1059 pmap_update_pde_invalidate(act->va, act->newpde);
1063 * Change the page size for the specified virtual address in a way that
1064 * prevents any possibility of the TLB ever having two entries that map the
1065 * same virtual address using different page sizes. This is the recommended
1066 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1067 * machine check exception for a TLB state that is improperly diagnosed as a
1071 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1073 struct pde_action act;
1074 cpuset_t active, other_cpus;
1078 cpuid = PCPU_GET(cpuid);
1079 other_cpus = all_cpus;
1080 CPU_CLR(cpuid, &other_cpus);
1081 if (pmap == kernel_pmap)
1084 active = pmap->pm_active;
1085 if (CPU_OVERLAP(&active, &other_cpus)) {
1087 act.invalidate = active;
1090 act.newpde = newpde;
1091 CPU_SET(cpuid, &active);
1092 smp_rendezvous_cpus(active,
1093 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1094 pmap_update_pde_kernel : pmap_update_pde_user,
1095 pmap_update_pde_teardown, &act);
1097 if (pmap == kernel_pmap)
1098 pmap_kenter_pde(va, newpde);
1100 pde_store(pde, newpde);
1101 if (CPU_ISSET(cpuid, &active))
1102 pmap_update_pde_invalidate(va, newpde);
1108 * Normal, non-SMP, 486+ invalidation functions.
1109 * We inline these within pmap.c for speed.
1112 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1115 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1120 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1124 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1125 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1130 pmap_invalidate_all(pmap_t pmap)
1133 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1138 pmap_invalidate_cache(void)
1145 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1148 if (pmap == kernel_pmap)
1149 pmap_kenter_pde(va, newpde);
1151 pde_store(pde, newpde);
1152 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1153 pmap_update_pde_invalidate(va, newpde);
1157 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1160 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1163 KASSERT((sva & PAGE_MASK) == 0,
1164 ("pmap_invalidate_cache_range: sva not page-aligned"));
1165 KASSERT((eva & PAGE_MASK) == 0,
1166 ("pmap_invalidate_cache_range: eva not page-aligned"));
1168 if (cpu_feature & CPUID_SS)
1169 ; /* If "Self Snoop" is supported, do nothing. */
1170 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1171 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1174 * Otherwise, do per-cache line flush. Use the mfence
1175 * instruction to insure that previous stores are
1176 * included in the write-back. The processor
1177 * propagates flush to other processors in the cache
1181 for (; sva < eva; sva += cpu_clflush_line_size)
1187 * No targeted cache flush methods are supported by CPU,
1188 * or the supplied range is bigger than 2MB.
1189 * Globally invalidate cache.
1191 pmap_invalidate_cache();
1196 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1200 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1201 (cpu_feature & CPUID_CLFSH) == 0) {
1202 pmap_invalidate_cache();
1204 for (i = 0; i < count; i++)
1205 pmap_flush_page(pages[i]);
1210 * Are we current address space or kernel? N.B. We return FALSE when
1211 * a pmap's page table is in use because a kernel thread is borrowing
1212 * it. The borrowed page table can change spontaneously, making any
1213 * dependence on its continued use subject to a race condition.
1216 pmap_is_current(pmap_t pmap)
1219 return (pmap == kernel_pmap ||
1220 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1221 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1225 * If the given pmap is not the current or kernel pmap, the returned pte must
1226 * be released by passing it to pmap_pte_release().
1229 pmap_pte(pmap_t pmap, vm_offset_t va)
1234 pde = pmap_pde(pmap, va);
1238 /* are we current address space or kernel? */
1239 if (pmap_is_current(pmap))
1240 return (vtopte(va));
1241 mtx_lock(&PMAP2mutex);
1242 newpf = *pde & PG_FRAME;
1243 if ((*PMAP2 & PG_FRAME) != newpf) {
1244 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1245 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1247 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1253 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1256 static __inline void
1257 pmap_pte_release(pt_entry_t *pte)
1260 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1261 mtx_unlock(&PMAP2mutex);
1264 static __inline void
1265 invlcaddr(void *caddr)
1268 invlpg((u_int)caddr);
1272 * Super fast pmap_pte routine best used when scanning
1273 * the pv lists. This eliminates many coarse-grained
1274 * invltlb calls. Note that many of the pv list
1275 * scans are across different pmaps. It is very wasteful
1276 * to do an entire invltlb for checking a single mapping.
1278 * If the given pmap is not the current pmap, vm_page_queue_mtx
1279 * must be held and curthread pinned to a CPU.
1282 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1287 pde = pmap_pde(pmap, va);
1291 /* are we current address space or kernel? */
1292 if (pmap_is_current(pmap))
1293 return (vtopte(va));
1294 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1295 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1296 newpf = *pde & PG_FRAME;
1297 if ((*PMAP1 & PG_FRAME) != newpf) {
1298 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1300 PMAP1cpu = PCPU_GET(cpuid);
1306 if (PMAP1cpu != PCPU_GET(cpuid)) {
1307 PMAP1cpu = PCPU_GET(cpuid);
1313 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1319 * Routine: pmap_extract
1321 * Extract the physical page address associated
1322 * with the given map/virtual_address pair.
1325 pmap_extract(pmap_t pmap, vm_offset_t va)
1333 pde = pmap->pm_pdir[va >> PDRSHIFT];
1335 if ((pde & PG_PS) != 0)
1336 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1338 pte = pmap_pte(pmap, va);
1339 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1340 pmap_pte_release(pte);
1348 * Routine: pmap_extract_and_hold
1350 * Atomically extract and hold the physical page
1351 * with the given pmap and virtual address pair
1352 * if that mapping permits the given protection.
1355 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1358 pt_entry_t pte, *ptep;
1366 pde = *pmap_pde(pmap, va);
1369 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1370 if (vm_page_pa_tryrelock(pmap, (pde &
1371 PG_PS_FRAME) | (va & PDRMASK), &pa))
1373 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1378 ptep = pmap_pte(pmap, va);
1380 pmap_pte_release(ptep);
1382 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1383 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1386 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1396 /***************************************************
1397 * Low level mapping routines.....
1398 ***************************************************/
1401 * Add a wired page to the kva.
1402 * Note: not SMP coherent.
1404 * This function may be used before pmap_bootstrap() is called.
1407 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1412 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1415 static __inline void
1416 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1421 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1425 * Remove a page from the kernel pagetables.
1426 * Note: not SMP coherent.
1428 * This function may be used before pmap_bootstrap() is called.
1431 pmap_kremove(vm_offset_t va)
1440 * Used to map a range of physical addresses into kernel
1441 * virtual address space.
1443 * The value passed in '*virt' is a suggested virtual address for
1444 * the mapping. Architectures which can support a direct-mapped
1445 * physical to virtual region can return the appropriate address
1446 * within that region, leaving '*virt' unchanged. Other
1447 * architectures should map the pages starting at '*virt' and
1448 * update '*virt' with the first usable address after the mapped
1452 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1454 vm_offset_t va, sva;
1455 vm_paddr_t superpage_offset;
1460 * Does the physical address range's size and alignment permit at
1461 * least one superpage mapping to be created?
1463 superpage_offset = start & PDRMASK;
1464 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1466 * Increase the starting virtual address so that its alignment
1467 * does not preclude the use of superpage mappings.
1469 if ((va & PDRMASK) < superpage_offset)
1470 va = (va & ~PDRMASK) + superpage_offset;
1471 else if ((va & PDRMASK) > superpage_offset)
1472 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1475 while (start < end) {
1476 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1478 KASSERT((va & PDRMASK) == 0,
1479 ("pmap_map: misaligned va %#x", va));
1480 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1481 pmap_kenter_pde(va, newpde);
1485 pmap_kenter(va, start);
1490 pmap_invalidate_range(kernel_pmap, sva, va);
1497 * Add a list of wired pages to the kva
1498 * this routine is only used for temporary
1499 * kernel mappings that do not need to have
1500 * page modification or references recorded.
1501 * Note that old mappings are simply written
1502 * over. The page *must* be wired.
1503 * Note: SMP coherent. Uses a ranged shootdown IPI.
1506 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1508 pt_entry_t *endpte, oldpte, pa, *pte;
1513 endpte = pte + count;
1514 while (pte < endpte) {
1516 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1517 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1519 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1523 if (__predict_false((oldpte & PG_V) != 0))
1524 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1529 * This routine tears out page mappings from the
1530 * kernel -- it is meant only for temporary mappings.
1531 * Note: SMP coherent. Uses a ranged shootdown IPI.
1534 pmap_qremove(vm_offset_t sva, int count)
1539 while (count-- > 0) {
1543 pmap_invalidate_range(kernel_pmap, sva, va);
1546 /***************************************************
1547 * Page table page management routines.....
1548 ***************************************************/
1549 static __inline void
1550 pmap_free_zero_pages(vm_page_t free)
1554 while (free != NULL) {
1557 /* Preserve the page's PG_ZERO setting. */
1558 vm_page_free_toq(m);
1563 * Schedule the specified unused page table page to be freed. Specifically,
1564 * add the page to the specified list of pages that will be released to the
1565 * physical memory manager after the TLB has been updated.
1567 static __inline void
1568 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1572 m->flags |= PG_ZERO;
1574 m->flags &= ~PG_ZERO;
1580 * Inserts the specified page table page into the specified pmap's collection
1581 * of idle page table pages. Each of a pmap's page table pages is responsible
1582 * for mapping a distinct range of virtual addresses. The pmap's collection is
1583 * ordered by this virtual address range.
1586 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1590 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1591 root = pmap->pm_root;
1596 root = vm_page_splay(mpte->pindex, root);
1597 if (mpte->pindex < root->pindex) {
1598 mpte->left = root->left;
1601 } else if (mpte->pindex == root->pindex)
1602 panic("pmap_insert_pt_page: pindex already inserted");
1604 mpte->right = root->right;
1609 pmap->pm_root = mpte;
1613 * Looks for a page table page mapping the specified virtual address in the
1614 * specified pmap's collection of idle page table pages. Returns NULL if there
1615 * is no page table page corresponding to the specified virtual address.
1618 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1621 vm_pindex_t pindex = va >> PDRSHIFT;
1623 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1624 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1625 mpte = vm_page_splay(pindex, mpte);
1626 if ((pmap->pm_root = mpte)->pindex != pindex)
1633 * Removes the specified page table page from the specified pmap's collection
1634 * of idle page table pages. The specified page table page must be a member of
1635 * the pmap's collection.
1638 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1642 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1643 if (mpte != pmap->pm_root)
1644 vm_page_splay(mpte->pindex, pmap->pm_root);
1645 if (mpte->left == NULL)
1648 root = vm_page_splay(mpte->pindex, mpte->left);
1649 root->right = mpte->right;
1651 pmap->pm_root = root;
1655 * This routine unholds page table pages, and if the hold count
1656 * drops to zero, then it decrements the wire count.
1659 pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1663 if (m->wire_count == 0)
1664 return (_pmap_unwire_pte_hold(pmap, m, free));
1670 _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1675 * unmap the page table page
1677 pmap->pm_pdir[m->pindex] = 0;
1678 --pmap->pm_stats.resident_count;
1681 * This is a release store so that the ordinary store unmapping
1682 * the page table page is globally performed before TLB shoot-
1685 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1688 * Do an invltlb to make the invalidated mapping
1689 * take effect immediately.
1691 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1692 pmap_invalidate_page(pmap, pteva);
1695 * Put page on a list so that it is released after
1696 * *ALL* TLB shootdown is done
1698 pmap_add_delayed_free_list(m, free, TRUE);
1704 * After removing a page table entry, this routine is used to
1705 * conditionally free the page, and manage the hold/wire counts.
1708 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1713 if (va >= VM_MAXUSER_ADDRESS)
1715 ptepde = *pmap_pde(pmap, va);
1716 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1717 return (pmap_unwire_pte_hold(pmap, mpte, free));
1721 * Initialize the pmap for the swapper process.
1724 pmap_pinit0(pmap_t pmap)
1727 PMAP_LOCK_INIT(pmap);
1729 * Since the page table directory is shared with the kernel pmap,
1730 * which is already included in the list "allpmaps", this pmap does
1731 * not need to be inserted into that list.
1733 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1735 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1737 pmap->pm_root = NULL;
1738 CPU_ZERO(&pmap->pm_active);
1739 PCPU_SET(curpmap, pmap);
1740 TAILQ_INIT(&pmap->pm_pvchunk);
1741 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1745 * Initialize a preallocated and zeroed pmap structure,
1746 * such as one in a vmspace structure.
1749 pmap_pinit(pmap_t pmap)
1751 vm_page_t m, ptdpg[NPGPTD];
1755 PMAP_LOCK_INIT(pmap);
1758 * No need to allocate page table space yet but we do need a valid
1759 * page directory table.
1761 if (pmap->pm_pdir == NULL) {
1762 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1764 if (pmap->pm_pdir == NULL) {
1765 PMAP_LOCK_DESTROY(pmap);
1769 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1770 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1771 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1772 ("pmap_pinit: pdpt misaligned"));
1773 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1774 ("pmap_pinit: pdpt above 4g"));
1776 pmap->pm_root = NULL;
1778 KASSERT(pmap->pm_root == NULL,
1779 ("pmap_pinit: pmap has reserved page table page(s)"));
1782 * allocate the page directory page(s)
1784 for (i = 0; i < NPGPTD;) {
1785 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1786 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1794 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1796 for (i = 0; i < NPGPTD; i++)
1797 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1798 pagezero(pmap->pm_pdir + (i * NPDEPG));
1800 mtx_lock_spin(&allpmaps_lock);
1801 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1802 /* Copy the kernel page table directory entries. */
1803 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1804 mtx_unlock_spin(&allpmaps_lock);
1806 /* install self-referential address mapping entry(s) */
1807 for (i = 0; i < NPGPTD; i++) {
1808 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1809 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1811 pmap->pm_pdpt[i] = pa | PG_V;
1815 CPU_ZERO(&pmap->pm_active);
1816 TAILQ_INIT(&pmap->pm_pvchunk);
1817 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1823 * this routine is called if the page table page is not
1827 _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags)
1832 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1833 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1834 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1837 * Allocate a page table page.
1839 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1840 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1841 if (flags & M_WAITOK) {
1843 vm_page_unlock_queues();
1845 vm_page_lock_queues();
1850 * Indicate the need to retry. While waiting, the page table
1851 * page may have been allocated.
1855 if ((m->flags & PG_ZERO) == 0)
1859 * Map the pagetable page into the process address space, if
1860 * it isn't already there.
1863 pmap->pm_stats.resident_count++;
1865 ptepa = VM_PAGE_TO_PHYS(m);
1866 pmap->pm_pdir[ptepindex] =
1867 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1873 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1879 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1880 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1881 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1884 * Calculate pagetable page index
1886 ptepindex = va >> PDRSHIFT;
1889 * Get the page directory entry
1891 ptepa = pmap->pm_pdir[ptepindex];
1894 * This supports switching from a 4MB page to a
1897 if (ptepa & PG_PS) {
1898 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1899 ptepa = pmap->pm_pdir[ptepindex];
1903 * If the page table page is mapped, we just increment the
1904 * hold count, and activate it.
1907 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1911 * Here if the pte page isn't mapped, or if it has
1914 m = _pmap_allocpte(pmap, ptepindex, flags);
1915 if (m == NULL && (flags & M_WAITOK))
1922 /***************************************************
1923 * Pmap allocation/deallocation routines.
1924 ***************************************************/
1928 * Deal with a SMP shootdown of other users of the pmap that we are
1929 * trying to dispose of. This can be a bit hairy.
1931 static cpuset_t *lazymask;
1932 static u_int lazyptd;
1933 static volatile u_int lazywait;
1935 void pmap_lazyfix_action(void);
1938 pmap_lazyfix_action(void)
1942 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1944 if (rcr3() == lazyptd)
1945 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1946 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1947 atomic_store_rel_int(&lazywait, 1);
1951 pmap_lazyfix_self(u_int cpuid)
1954 if (rcr3() == lazyptd)
1955 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1956 CPU_CLR_ATOMIC(cpuid, lazymask);
1961 pmap_lazyfix(pmap_t pmap)
1963 cpuset_t mymask, mask;
1967 mask = pmap->pm_active;
1968 while (!CPU_EMPTY(&mask)) {
1971 /* Find least significant set bit. */
1972 lsb = cpusetobj_ffs(&mask);
1975 CPU_SETOF(lsb, &mask);
1976 mtx_lock_spin(&smp_ipi_mtx);
1978 lazyptd = vtophys(pmap->pm_pdpt);
1980 lazyptd = vtophys(pmap->pm_pdir);
1982 cpuid = PCPU_GET(cpuid);
1984 /* Use a cpuset just for having an easy check. */
1985 CPU_SETOF(cpuid, &mymask);
1986 if (!CPU_CMP(&mask, &mymask)) {
1987 lazymask = &pmap->pm_active;
1988 pmap_lazyfix_self(cpuid);
1990 atomic_store_rel_int((u_int *)&lazymask,
1991 (u_int)&pmap->pm_active);
1992 atomic_store_rel_int(&lazywait, 0);
1993 ipi_selected(mask, IPI_LAZYPMAP);
1994 while (lazywait == 0) {
2000 mtx_unlock_spin(&smp_ipi_mtx);
2002 printf("pmap_lazyfix: spun for 50000000\n");
2003 mask = pmap->pm_active;
2010 * Cleaning up on uniprocessor is easy. For various reasons, we're
2011 * unlikely to have to even execute this code, including the fact
2012 * that the cleanup is deferred until the parent does a wait(2), which
2013 * means that another userland process has run.
2016 pmap_lazyfix(pmap_t pmap)
2020 cr3 = vtophys(pmap->pm_pdir);
2021 if (cr3 == rcr3()) {
2022 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
2023 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2029 * Release any resources held by the given physical map.
2030 * Called when a pmap initialized by pmap_pinit is being released.
2031 * Should only be called if the map contains no valid mappings.
2034 pmap_release(pmap_t pmap)
2036 vm_page_t m, ptdpg[NPGPTD];
2039 KASSERT(pmap->pm_stats.resident_count == 0,
2040 ("pmap_release: pmap resident count %ld != 0",
2041 pmap->pm_stats.resident_count));
2042 KASSERT(pmap->pm_root == NULL,
2043 ("pmap_release: pmap has reserved page table page(s)"));
2046 mtx_lock_spin(&allpmaps_lock);
2047 LIST_REMOVE(pmap, pm_list);
2048 mtx_unlock_spin(&allpmaps_lock);
2050 for (i = 0; i < NPGPTD; i++)
2051 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2054 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2055 sizeof(*pmap->pm_pdir));
2057 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2059 for (i = 0; i < NPGPTD; i++) {
2062 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2063 ("pmap_release: got wrong ptd page"));
2066 atomic_subtract_int(&cnt.v_wire_count, 1);
2067 vm_page_free_zero(m);
2069 PMAP_LOCK_DESTROY(pmap);
2073 kvm_size(SYSCTL_HANDLER_ARGS)
2075 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2077 return (sysctl_handle_long(oidp, &ksize, 0, req));
2079 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2080 0, 0, kvm_size, "IU", "Size of KVM");
2083 kvm_free(SYSCTL_HANDLER_ARGS)
2085 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2087 return (sysctl_handle_long(oidp, &kfree, 0, req));
2089 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2090 0, 0, kvm_free, "IU", "Amount of KVM free");
2093 * grow the number of kernel page table entries, if needed
2096 pmap_growkernel(vm_offset_t addr)
2098 vm_paddr_t ptppaddr;
2102 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2103 addr = roundup2(addr, NBPDR);
2104 if (addr - 1 >= kernel_map->max_offset)
2105 addr = kernel_map->max_offset;
2106 while (kernel_vm_end < addr) {
2107 if (pdir_pde(PTD, kernel_vm_end)) {
2108 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2109 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2110 kernel_vm_end = kernel_map->max_offset;
2116 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2117 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2120 panic("pmap_growkernel: no memory to grow kernel");
2124 if ((nkpg->flags & PG_ZERO) == 0)
2125 pmap_zero_page(nkpg);
2126 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2127 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2128 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2130 pmap_kenter_pde(kernel_vm_end, newpdir);
2131 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2132 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2133 kernel_vm_end = kernel_map->max_offset;
2140 /***************************************************
2141 * page management routines.
2142 ***************************************************/
2144 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2145 CTASSERT(_NPCM == 11);
2147 static __inline struct pv_chunk *
2148 pv_to_chunk(pv_entry_t pv)
2151 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2154 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2156 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2157 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2159 static uint32_t pc_freemask[11] = {
2160 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2161 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2162 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2163 PC_FREE0_9, PC_FREE10
2166 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2167 "Current number of pv entries");
2170 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2173 "Current number of pv entry chunks");
2174 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2175 "Current number of pv entry chunks allocated");
2176 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2177 "Current number of pv entry chunks frees");
2178 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2179 "Number of times tried to get a chunk page but failed.");
2181 static long pv_entry_frees, pv_entry_allocs;
2182 static int pv_entry_spare;
2184 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2185 "Current number of pv entry frees");
2186 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2187 "Current number of pv entry allocs");
2188 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2189 "Current number of spare pv entries");
2191 static int pmap_collect_inactive, pmap_collect_active;
2193 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
2194 "Current number times pmap_collect called on inactive queue");
2195 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
2196 "Current number times pmap_collect called on active queue");
2200 * We are in a serious low memory condition. Resort to
2201 * drastic measures to free some pages so we can allocate
2202 * another pv entry chunk. This is normally called to
2203 * unmap inactive pages, and if necessary, active pages.
2206 pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
2210 pt_entry_t *pte, tpte;
2211 pv_entry_t next_pv, pv;
2216 TAILQ_FOREACH(m, &vpq->pl, pageq) {
2217 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy)
2219 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2222 /* Avoid deadlock and lock recursion. */
2223 if (pmap > locked_pmap)
2225 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2227 pmap->pm_stats.resident_count--;
2228 pde = pmap_pde(pmap, va);
2229 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found"
2230 " a 4mpage in page %p's pv list", m));
2231 pte = pmap_pte_quick(pmap, va);
2232 tpte = pte_load_clear(pte);
2233 KASSERT((tpte & PG_W) == 0,
2234 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte));
2236 vm_page_aflag_set(m, PGA_REFERENCED);
2237 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2240 pmap_unuse_pt(pmap, va, &free);
2241 pmap_invalidate_page(pmap, va);
2242 pmap_free_zero_pages(free);
2243 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2244 free_pv_entry(pmap, pv);
2245 if (pmap != locked_pmap)
2248 if (TAILQ_EMPTY(&m->md.pv_list) &&
2249 TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list))
2250 vm_page_aflag_clear(m, PGA_WRITEABLE);
2257 * free the pv_entry back to the free list
2260 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2263 struct pv_chunk *pc;
2264 int idx, field, bit;
2266 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2268 PV_STAT(pv_entry_frees++);
2269 PV_STAT(pv_entry_spare++);
2271 pc = pv_to_chunk(pv);
2272 idx = pv - &pc->pc_pventry[0];
2275 pc->pc_map[field] |= 1ul << bit;
2276 /* move to head of list */
2277 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2278 for (idx = 0; idx < _NPCM; idx++)
2279 if (pc->pc_map[idx] != pc_freemask[idx]) {
2280 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2283 PV_STAT(pv_entry_spare -= _NPCPV);
2284 PV_STAT(pc_chunk_count--);
2285 PV_STAT(pc_chunk_frees++);
2286 /* entire chunk is free, return it */
2287 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2288 pmap_qremove((vm_offset_t)pc, 1);
2289 vm_page_unwire(m, 0);
2291 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2295 * get a new pv_entry, allocating a block from the system
2299 get_pv_entry(pmap_t pmap, int try)
2301 static const struct timeval printinterval = { 60, 0 };
2302 static struct timeval lastprint;
2303 struct vpgqueues *pq;
2306 struct pv_chunk *pc;
2309 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2310 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2311 PV_STAT(pv_entry_allocs++);
2313 if (pv_entry_count > pv_entry_high_water)
2314 if (ratecheck(&lastprint, &printinterval))
2315 printf("Approaching the limit on PV entries, consider "
2316 "increasing either the vm.pmap.shpgperproc or the "
2317 "vm.pmap.pv_entry_max tunable.\n");
2320 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2322 for (field = 0; field < _NPCM; field++) {
2323 if (pc->pc_map[field]) {
2324 bit = bsfl(pc->pc_map[field]);
2328 if (field < _NPCM) {
2329 pv = &pc->pc_pventry[field * 32 + bit];
2330 pc->pc_map[field] &= ~(1ul << bit);
2331 /* If this was the last item, move it to tail */
2332 for (field = 0; field < _NPCM; field++)
2333 if (pc->pc_map[field] != 0) {
2334 PV_STAT(pv_entry_spare--);
2335 return (pv); /* not full, return */
2337 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2338 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2339 PV_STAT(pv_entry_spare--);
2344 * Access to the ptelist "pv_vafree" is synchronized by the page
2345 * queues lock. If "pv_vafree" is currently non-empty, it will
2346 * remain non-empty until pmap_ptelist_alloc() completes.
2348 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, (pq ==
2349 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) |
2350 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2353 PV_STAT(pc_chunk_tryfail++);
2357 * Reclaim pv entries: At first, destroy mappings to
2358 * inactive pages. After that, if a pv chunk entry
2359 * is still needed, destroy mappings to active pages.
2362 PV_STAT(pmap_collect_inactive++);
2363 pq = &vm_page_queues[PQ_INACTIVE];
2364 } else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2365 PV_STAT(pmap_collect_active++);
2366 pq = &vm_page_queues[PQ_ACTIVE];
2368 panic("get_pv_entry: increase vm.pmap.shpgperproc");
2369 pmap_collect(pmap, pq);
2372 PV_STAT(pc_chunk_count++);
2373 PV_STAT(pc_chunk_allocs++);
2374 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2375 pmap_qenter((vm_offset_t)pc, &m, 1);
2377 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2378 for (field = 1; field < _NPCM; field++)
2379 pc->pc_map[field] = pc_freemask[field];
2380 pv = &pc->pc_pventry[0];
2381 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2382 PV_STAT(pv_entry_spare += _NPCPV - 1);
2386 static __inline pv_entry_t
2387 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2391 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2393 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2394 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2402 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2404 struct md_page *pvh;
2406 vm_offset_t va_last;
2409 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2410 KASSERT((pa & PDRMASK) == 0,
2411 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2414 * Transfer the 4mpage's pv entry for this mapping to the first
2417 pvh = pa_to_pvh(pa);
2418 va = trunc_4mpage(va);
2419 pv = pmap_pvh_remove(pvh, pmap, va);
2420 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2421 m = PHYS_TO_VM_PAGE(pa);
2422 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2423 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2424 va_last = va + NBPDR - PAGE_SIZE;
2427 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2428 ("pmap_pv_demote_pde: page %p is not managed", m));
2430 pmap_insert_entry(pmap, va, m);
2431 } while (va < va_last);
2435 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2437 struct md_page *pvh;
2439 vm_offset_t va_last;
2442 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2443 KASSERT((pa & PDRMASK) == 0,
2444 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2447 * Transfer the first page's pv entry for this mapping to the
2448 * 4mpage's pv list. Aside from avoiding the cost of a call
2449 * to get_pv_entry(), a transfer avoids the possibility that
2450 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2451 * removes one of the mappings that is being promoted.
2453 m = PHYS_TO_VM_PAGE(pa);
2454 va = trunc_4mpage(va);
2455 pv = pmap_pvh_remove(&m->md, pmap, va);
2456 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2457 pvh = pa_to_pvh(pa);
2458 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2459 /* Free the remaining NPTEPG - 1 pv entries. */
2460 va_last = va + NBPDR - PAGE_SIZE;
2464 pmap_pvh_free(&m->md, pmap, va);
2465 } while (va < va_last);
2469 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2473 pv = pmap_pvh_remove(pvh, pmap, va);
2474 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2475 free_pv_entry(pmap, pv);
2479 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2481 struct md_page *pvh;
2483 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2484 pmap_pvh_free(&m->md, pmap, va);
2485 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2486 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2487 if (TAILQ_EMPTY(&pvh->pv_list))
2488 vm_page_aflag_clear(m, PGA_WRITEABLE);
2493 * Create a pv entry for page at pa for
2497 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2501 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2502 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2503 pv = get_pv_entry(pmap, FALSE);
2505 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2509 * Conditionally create a pv entry.
2512 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2516 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2517 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2518 if (pv_entry_count < pv_entry_high_water &&
2519 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2521 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2528 * Create the pv entries for each of the pages within a superpage.
2531 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2533 struct md_page *pvh;
2536 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2537 if (pv_entry_count < pv_entry_high_water &&
2538 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2540 pvh = pa_to_pvh(pa);
2541 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2548 * Fills a page table page with mappings to consecutive physical pages.
2551 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2555 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2557 newpte += PAGE_SIZE;
2562 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2563 * 2- or 4MB page mapping is invalidated.
2566 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2568 pd_entry_t newpde, oldpde;
2569 pt_entry_t *firstpte, newpte;
2571 vm_page_t free, mpte;
2573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2575 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2576 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2577 mpte = pmap_lookup_pt_page(pmap, va);
2579 pmap_remove_pt_page(pmap, mpte);
2581 KASSERT((oldpde & PG_W) == 0,
2582 ("pmap_demote_pde: page table page for a wired mapping"
2586 * Invalidate the 2- or 4MB page mapping and return
2587 * "failure" if the mapping was never accessed or the
2588 * allocation of the new page table page fails.
2590 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2591 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2592 VM_ALLOC_WIRED)) == NULL) {
2594 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2595 pmap_invalidate_page(pmap, trunc_4mpage(va));
2596 pmap_free_zero_pages(free);
2597 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2598 " in pmap %p", va, pmap);
2601 if (va < VM_MAXUSER_ADDRESS)
2602 pmap->pm_stats.resident_count++;
2604 mptepa = VM_PAGE_TO_PHYS(mpte);
2607 * If the page mapping is in the kernel's address space, then the
2608 * KPTmap can provide access to the page table page. Otherwise,
2609 * temporarily map the page table page (mpte) into the kernel's
2610 * address space at either PADDR1 or PADDR2.
2613 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2614 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) {
2615 if ((*PMAP1 & PG_FRAME) != mptepa) {
2616 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2618 PMAP1cpu = PCPU_GET(cpuid);
2624 if (PMAP1cpu != PCPU_GET(cpuid)) {
2625 PMAP1cpu = PCPU_GET(cpuid);
2633 mtx_lock(&PMAP2mutex);
2634 if ((*PMAP2 & PG_FRAME) != mptepa) {
2635 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2636 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2640 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2641 KASSERT((oldpde & PG_A) != 0,
2642 ("pmap_demote_pde: oldpde is missing PG_A"));
2643 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2644 ("pmap_demote_pde: oldpde is missing PG_M"));
2645 newpte = oldpde & ~PG_PS;
2646 if ((newpte & PG_PDE_PAT) != 0)
2647 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2650 * If the page table page is new, initialize it.
2652 if (mpte->wire_count == 1) {
2653 mpte->wire_count = NPTEPG;
2654 pmap_fill_ptp(firstpte, newpte);
2656 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2657 ("pmap_demote_pde: firstpte and newpte map different physical"
2661 * If the mapping has changed attributes, update the page table
2664 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2665 pmap_fill_ptp(firstpte, newpte);
2668 * Demote the mapping. This pmap is locked. The old PDE has
2669 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2670 * set. Thus, there is no danger of a race with another
2671 * processor changing the setting of PG_A and/or PG_M between
2672 * the read above and the store below.
2674 if (workaround_erratum383)
2675 pmap_update_pde(pmap, va, pde, newpde);
2676 else if (pmap == kernel_pmap)
2677 pmap_kenter_pde(va, newpde);
2679 pde_store(pde, newpde);
2680 if (firstpte == PADDR2)
2681 mtx_unlock(&PMAP2mutex);
2684 * Invalidate the recursive mapping of the page table page.
2686 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2689 * Demote the pv entry. This depends on the earlier demotion
2690 * of the mapping. Specifically, the (re)creation of a per-
2691 * page pv entry might trigger the execution of pmap_collect(),
2692 * which might reclaim a newly (re)created per-page pv entry
2693 * and destroy the associated mapping. In order to destroy
2694 * the mapping, the PDE must have already changed from mapping
2695 * the 2mpage to referencing the page table page.
2697 if ((oldpde & PG_MANAGED) != 0)
2698 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2700 pmap_pde_demotions++;
2701 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2702 " in pmap %p", va, pmap);
2707 * pmap_remove_pde: do the things to unmap a superpage in a process
2710 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2713 struct md_page *pvh;
2715 vm_offset_t eva, va;
2718 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2719 KASSERT((sva & PDRMASK) == 0,
2720 ("pmap_remove_pde: sva is not 4mpage aligned"));
2721 oldpde = pte_load_clear(pdq);
2723 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2726 * Machines that don't support invlpg, also don't support
2730 pmap_invalidate_page(kernel_pmap, sva);
2731 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2732 if (oldpde & PG_MANAGED) {
2733 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2734 pmap_pvh_free(pvh, pmap, sva);
2736 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2737 va < eva; va += PAGE_SIZE, m++) {
2738 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2741 vm_page_aflag_set(m, PGA_REFERENCED);
2742 if (TAILQ_EMPTY(&m->md.pv_list) &&
2743 TAILQ_EMPTY(&pvh->pv_list))
2744 vm_page_aflag_clear(m, PGA_WRITEABLE);
2747 if (pmap == kernel_pmap) {
2748 if (!pmap_demote_pde(pmap, pdq, sva))
2749 panic("pmap_remove_pde: failed demotion");
2751 mpte = pmap_lookup_pt_page(pmap, sva);
2753 pmap_remove_pt_page(pmap, mpte);
2754 pmap->pm_stats.resident_count--;
2755 KASSERT(mpte->wire_count == NPTEPG,
2756 ("pmap_remove_pde: pte page wire count error"));
2757 mpte->wire_count = 0;
2758 pmap_add_delayed_free_list(mpte, free, FALSE);
2759 atomic_subtract_int(&cnt.v_wire_count, 1);
2765 * pmap_remove_pte: do the things to unmap a page in a process
2768 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2773 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2774 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2775 oldpte = pte_load_clear(ptq);
2777 pmap->pm_stats.wired_count -= 1;
2779 * Machines that don't support invlpg, also don't support
2783 pmap_invalidate_page(kernel_pmap, va);
2784 pmap->pm_stats.resident_count -= 1;
2785 if (oldpte & PG_MANAGED) {
2786 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2787 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2790 vm_page_aflag_set(m, PGA_REFERENCED);
2791 pmap_remove_entry(pmap, m, va);
2793 return (pmap_unuse_pt(pmap, va, free));
2797 * Remove a single page from a process address space
2800 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2804 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2805 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2806 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2807 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2809 pmap_remove_pte(pmap, pte, va, free);
2810 pmap_invalidate_page(pmap, va);
2814 * Remove the given range of addresses from the specified map.
2816 * It is assumed that the start and end are properly
2817 * rounded to the page size.
2820 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2825 vm_page_t free = NULL;
2829 * Perform an unsynchronized read. This is, however, safe.
2831 if (pmap->pm_stats.resident_count == 0)
2836 vm_page_lock_queues();
2841 * special handling of removing one page. a very
2842 * common operation and easy to short circuit some
2845 if ((sva + PAGE_SIZE == eva) &&
2846 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2847 pmap_remove_page(pmap, sva, &free);
2851 for (; sva < eva; sva = pdnxt) {
2855 * Calculate index for next page table.
2857 pdnxt = (sva + NBPDR) & ~PDRMASK;
2860 if (pmap->pm_stats.resident_count == 0)
2863 pdirindex = sva >> PDRSHIFT;
2864 ptpaddr = pmap->pm_pdir[pdirindex];
2867 * Weed out invalid mappings. Note: we assume that the page
2868 * directory table is always allocated, and in kernel virtual.
2874 * Check for large page.
2876 if ((ptpaddr & PG_PS) != 0) {
2878 * Are we removing the entire large page? If not,
2879 * demote the mapping and fall through.
2881 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2883 * The TLB entry for a PG_G mapping is
2884 * invalidated by pmap_remove_pde().
2886 if ((ptpaddr & PG_G) == 0)
2888 pmap_remove_pde(pmap,
2889 &pmap->pm_pdir[pdirindex], sva, &free);
2891 } else if (!pmap_demote_pde(pmap,
2892 &pmap->pm_pdir[pdirindex], sva)) {
2893 /* The large page mapping was destroyed. */
2899 * Limit our scan to either the end of the va represented
2900 * by the current page table page, or to the end of the
2901 * range being removed.
2906 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2912 * The TLB entry for a PG_G mapping is invalidated
2913 * by pmap_remove_pte().
2915 if ((*pte & PG_G) == 0)
2917 if (pmap_remove_pte(pmap, pte, sva, &free))
2924 pmap_invalidate_all(pmap);
2925 vm_page_unlock_queues();
2927 pmap_free_zero_pages(free);
2931 * Routine: pmap_remove_all
2933 * Removes this physical page from
2934 * all physical maps in which it resides.
2935 * Reflects back modify bits to the pager.
2938 * Original versions of this routine were very
2939 * inefficient because they iteratively called
2940 * pmap_remove (slow...)
2944 pmap_remove_all(vm_page_t m)
2946 struct md_page *pvh;
2949 pt_entry_t *pte, tpte;
2954 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2955 ("pmap_remove_all: page %p is not managed", m));
2957 vm_page_lock_queues();
2959 if ((m->flags & PG_FICTITIOUS) != 0)
2960 goto small_mappings;
2961 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2962 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2966 pde = pmap_pde(pmap, va);
2967 (void)pmap_demote_pde(pmap, pde, va);
2971 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2974 pmap->pm_stats.resident_count--;
2975 pde = pmap_pde(pmap, pv->pv_va);
2976 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
2977 " a 4mpage in page %p's pv list", m));
2978 pte = pmap_pte_quick(pmap, pv->pv_va);
2979 tpte = pte_load_clear(pte);
2981 pmap->pm_stats.wired_count--;
2983 vm_page_aflag_set(m, PGA_REFERENCED);
2986 * Update the vm_page_t clean and reference bits.
2988 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2990 pmap_unuse_pt(pmap, pv->pv_va, &free);
2991 pmap_invalidate_page(pmap, pv->pv_va);
2992 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2993 free_pv_entry(pmap, pv);
2996 vm_page_aflag_clear(m, PGA_WRITEABLE);
2998 vm_page_unlock_queues();
2999 pmap_free_zero_pages(free);
3003 * pmap_protect_pde: do the things to protect a 4mpage in a process
3006 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3008 pd_entry_t newpde, oldpde;
3009 vm_offset_t eva, va;
3011 boolean_t anychanged;
3013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3014 KASSERT((sva & PDRMASK) == 0,
3015 ("pmap_protect_pde: sva is not 4mpage aligned"));
3018 oldpde = newpde = *pde;
3019 if (oldpde & PG_MANAGED) {
3021 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3022 va < eva; va += PAGE_SIZE, m++)
3023 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3026 if ((prot & VM_PROT_WRITE) == 0)
3027 newpde &= ~(PG_RW | PG_M);
3029 if ((prot & VM_PROT_EXECUTE) == 0)
3032 if (newpde != oldpde) {
3033 if (!pde_cmpset(pde, oldpde, newpde))
3036 pmap_invalidate_page(pmap, sva);
3040 return (anychanged);
3044 * Set the physical protection on the
3045 * specified range of this map as requested.
3048 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3055 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3056 pmap_remove(pmap, sva, eva);
3061 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3062 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3065 if (prot & VM_PROT_WRITE)
3071 vm_page_lock_queues();
3074 for (; sva < eva; sva = pdnxt) {
3075 pt_entry_t obits, pbits;
3078 pdnxt = (sva + NBPDR) & ~PDRMASK;
3082 pdirindex = sva >> PDRSHIFT;
3083 ptpaddr = pmap->pm_pdir[pdirindex];
3086 * Weed out invalid mappings. Note: we assume that the page
3087 * directory table is always allocated, and in kernel virtual.
3093 * Check for large page.
3095 if ((ptpaddr & PG_PS) != 0) {
3097 * Are we protecting the entire large page? If not,
3098 * demote the mapping and fall through.
3100 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3102 * The TLB entry for a PG_G mapping is
3103 * invalidated by pmap_protect_pde().
3105 if (pmap_protect_pde(pmap,
3106 &pmap->pm_pdir[pdirindex], sva, prot))
3109 } else if (!pmap_demote_pde(pmap,
3110 &pmap->pm_pdir[pdirindex], sva)) {
3111 /* The large page mapping was destroyed. */
3119 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3125 * Regardless of whether a pte is 32 or 64 bits in
3126 * size, PG_RW, PG_A, and PG_M are among the least
3127 * significant 32 bits.
3129 obits = pbits = *pte;
3130 if ((pbits & PG_V) == 0)
3133 if ((prot & VM_PROT_WRITE) == 0) {
3134 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3135 (PG_MANAGED | PG_M | PG_RW)) {
3136 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3139 pbits &= ~(PG_RW | PG_M);
3142 if ((prot & VM_PROT_EXECUTE) == 0)
3146 if (pbits != obits) {
3148 if (!atomic_cmpset_64(pte, obits, pbits))
3151 if (!atomic_cmpset_int((u_int *)pte, obits,
3156 pmap_invalidate_page(pmap, sva);
3164 pmap_invalidate_all(pmap);
3165 vm_page_unlock_queues();
3170 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3171 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3172 * For promotion to occur, two conditions must be met: (1) the 4KB page
3173 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3174 * mappings must have identical characteristics.
3176 * Managed (PG_MANAGED) mappings within the kernel address space are not
3177 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3178 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3182 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3185 pt_entry_t *firstpte, oldpte, pa, *pte;
3186 vm_offset_t oldpteva;
3189 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3192 * Examine the first PTE in the specified PTP. Abort if this PTE is
3193 * either invalid, unused, or does not map the first 4KB physical page
3194 * within a 2- or 4MB page.
3196 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3199 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3200 pmap_pde_p_failures++;
3201 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3202 " in pmap %p", va, pmap);
3205 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3206 pmap_pde_p_failures++;
3207 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3208 " in pmap %p", va, pmap);
3211 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3213 * When PG_M is already clear, PG_RW can be cleared without
3214 * a TLB invalidation.
3216 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3223 * Examine each of the other PTEs in the specified PTP. Abort if this
3224 * PTE maps an unexpected 4KB physical page or does not have identical
3225 * characteristics to the first PTE.
3227 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3228 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3231 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3232 pmap_pde_p_failures++;
3233 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3234 " in pmap %p", va, pmap);
3237 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3239 * When PG_M is already clear, PG_RW can be cleared
3240 * without a TLB invalidation.
3242 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3246 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3248 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3249 " in pmap %p", oldpteva, pmap);
3251 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3252 pmap_pde_p_failures++;
3253 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3254 " in pmap %p", va, pmap);
3261 * Save the page table page in its current state until the PDE
3262 * mapping the superpage is demoted by pmap_demote_pde() or
3263 * destroyed by pmap_remove_pde().
3265 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3266 KASSERT(mpte >= vm_page_array &&
3267 mpte < &vm_page_array[vm_page_array_size],
3268 ("pmap_promote_pde: page table page is out of range"));
3269 KASSERT(mpte->pindex == va >> PDRSHIFT,
3270 ("pmap_promote_pde: page table page's pindex is wrong"));
3271 pmap_insert_pt_page(pmap, mpte);
3274 * Promote the pv entries.
3276 if ((newpde & PG_MANAGED) != 0)
3277 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3280 * Propagate the PAT index to its proper position.
3282 if ((newpde & PG_PTE_PAT) != 0)
3283 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3286 * Map the superpage.
3288 if (workaround_erratum383)
3289 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3290 else if (pmap == kernel_pmap)
3291 pmap_kenter_pde(va, PG_PS | newpde);
3293 pde_store(pde, PG_PS | newpde);
3295 pmap_pde_promotions++;
3296 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3297 " in pmap %p", va, pmap);
3301 * Insert the given physical page (p) at
3302 * the specified virtual address (v) in the
3303 * target physical map with the protection requested.
3305 * If specified, the page will be wired down, meaning
3306 * that the related pte can not be reclaimed.
3308 * NB: This is the only routine which MAY NOT lazy-evaluate
3309 * or lose information. That is, this routine must actually
3310 * insert this page into the given map NOW.
3313 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3314 vm_prot_t prot, boolean_t wired)
3318 pt_entry_t newpte, origpte;
3324 va = trunc_page(va);
3325 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3326 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3327 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3329 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
3330 VM_OBJECT_LOCKED(m->object),
3331 ("pmap_enter: page %p is not busy", m));
3335 vm_page_lock_queues();
3340 * In the case that a page table page is not
3341 * resident, we are creating it here.
3343 if (va < VM_MAXUSER_ADDRESS) {
3344 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3347 pde = pmap_pde(pmap, va);
3348 if ((*pde & PG_PS) != 0)
3349 panic("pmap_enter: attempted pmap_enter on 4MB page");
3350 pte = pmap_pte_quick(pmap, va);
3353 * Page Directory table entry not valid, we need a new PT page
3356 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3357 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3360 pa = VM_PAGE_TO_PHYS(m);
3363 opa = origpte & PG_FRAME;
3366 * Mapping has not changed, must be protection or wiring change.
3368 if (origpte && (opa == pa)) {
3370 * Wiring change, just update stats. We don't worry about
3371 * wiring PT pages as they remain resident as long as there
3372 * are valid mappings in them. Hence, if a user page is wired,
3373 * the PT page will be also.
3375 if (wired && ((origpte & PG_W) == 0))
3376 pmap->pm_stats.wired_count++;
3377 else if (!wired && (origpte & PG_W))
3378 pmap->pm_stats.wired_count--;
3381 * Remove extra pte reference
3386 if (origpte & PG_MANAGED) {
3396 * Mapping has changed, invalidate old range and fall through to
3397 * handle validating new mapping.
3401 pmap->pm_stats.wired_count--;
3402 if (origpte & PG_MANAGED) {
3403 om = PHYS_TO_VM_PAGE(opa);
3404 pv = pmap_pvh_remove(&om->md, pmap, va);
3408 KASSERT(mpte->wire_count > 0,
3409 ("pmap_enter: missing reference to page table page,"
3413 pmap->pm_stats.resident_count++;
3416 * Enter on the PV list if part of our managed memory.
3418 if ((m->oflags & VPO_UNMANAGED) == 0) {
3419 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3420 ("pmap_enter: managed mapping within the clean submap"));
3422 pv = get_pv_entry(pmap, FALSE);
3424 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
3426 } else if (pv != NULL)
3427 free_pv_entry(pmap, pv);
3430 * Increment counters
3433 pmap->pm_stats.wired_count++;
3437 * Now validate mapping with desired protection/wiring.
3439 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3440 if ((prot & VM_PROT_WRITE) != 0) {
3442 if ((newpte & PG_MANAGED) != 0)
3443 vm_page_aflag_set(m, PGA_WRITEABLE);
3446 if ((prot & VM_PROT_EXECUTE) == 0)
3451 if (va < VM_MAXUSER_ADDRESS)
3453 if (pmap == kernel_pmap)
3457 * if the mapping or permission bits are different, we need
3458 * to update the pte.
3460 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3462 if ((access & VM_PROT_WRITE) != 0)
3464 if (origpte & PG_V) {
3466 origpte = pte_load_store(pte, newpte);
3467 if (origpte & PG_A) {
3468 if (origpte & PG_MANAGED)
3469 vm_page_aflag_set(om, PGA_REFERENCED);
3470 if (opa != VM_PAGE_TO_PHYS(m))
3473 if ((origpte & PG_NX) == 0 &&
3474 (newpte & PG_NX) != 0)
3478 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3479 if ((origpte & PG_MANAGED) != 0)
3481 if ((prot & VM_PROT_WRITE) == 0)
3484 if ((origpte & PG_MANAGED) != 0 &&
3485 TAILQ_EMPTY(&om->md.pv_list) &&
3486 ((om->flags & PG_FICTITIOUS) != 0 ||
3487 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3488 vm_page_aflag_clear(om, PGA_WRITEABLE);
3490 pmap_invalidate_page(pmap, va);
3492 pte_store(pte, newpte);
3496 * If both the page table page and the reservation are fully
3497 * populated, then attempt promotion.
3499 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3500 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3501 vm_reserv_level_iffullpop(m) == 0)
3502 pmap_promote_pde(pmap, pde, va);
3505 vm_page_unlock_queues();
3510 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3511 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3512 * blocking, (2) a mapping already exists at the specified virtual address, or
3513 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3516 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3518 pd_entry_t *pde, newpde;
3520 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3521 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3522 pde = pmap_pde(pmap, va);
3524 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3525 " in pmap %p", va, pmap);
3528 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3530 if ((m->oflags & VPO_UNMANAGED) == 0) {
3531 newpde |= PG_MANAGED;
3534 * Abort this mapping if its PV entry could not be created.
3536 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3537 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3538 " in pmap %p", va, pmap);
3543 if ((prot & VM_PROT_EXECUTE) == 0)
3546 if (va < VM_MAXUSER_ADDRESS)
3550 * Increment counters.
3552 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3555 * Map the superpage.
3557 pde_store(pde, newpde);
3559 pmap_pde_mappings++;
3560 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3561 " in pmap %p", va, pmap);
3566 * Maps a sequence of resident pages belonging to the same object.
3567 * The sequence begins with the given page m_start. This page is
3568 * mapped at the given virtual address start. Each subsequent page is
3569 * mapped at a virtual address that is offset from start by the same
3570 * amount as the page is offset from m_start within the object. The
3571 * last page in the sequence is the page with the largest offset from
3572 * m_start that can be mapped at a virtual address less than the given
3573 * virtual address end. Not every virtual page between start and end
3574 * is mapped; only those for which a resident page exists with the
3575 * corresponding offset from m_start are mapped.
3578 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3579 vm_page_t m_start, vm_prot_t prot)
3583 vm_pindex_t diff, psize;
3585 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3586 psize = atop(end - start);
3589 vm_page_lock_queues();
3591 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3592 va = start + ptoa(diff);
3593 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3594 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3595 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3596 pmap_enter_pde(pmap, va, m, prot))
3597 m = &m[NBPDR / PAGE_SIZE - 1];
3599 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3601 m = TAILQ_NEXT(m, listq);
3603 vm_page_unlock_queues();
3608 * this code makes some *MAJOR* assumptions:
3609 * 1. Current pmap & pmap exists.
3612 * 4. No page table pages.
3613 * but is *MUCH* faster than pmap_enter...
3617 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3620 vm_page_lock_queues();
3622 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3623 vm_page_unlock_queues();
3628 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3629 vm_prot_t prot, vm_page_t mpte)
3635 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3636 (m->oflags & VPO_UNMANAGED) != 0,
3637 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3638 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3639 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3642 * In the case that a page table page is not
3643 * resident, we are creating it here.
3645 if (va < VM_MAXUSER_ADDRESS) {
3650 * Calculate pagetable page index
3652 ptepindex = va >> PDRSHIFT;
3653 if (mpte && (mpte->pindex == ptepindex)) {
3657 * Get the page directory entry
3659 ptepa = pmap->pm_pdir[ptepindex];
3662 * If the page table page is mapped, we just increment
3663 * the hold count, and activate it.
3668 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3671 mpte = _pmap_allocpte(pmap, ptepindex,
3682 * This call to vtopte makes the assumption that we are
3683 * entering the page into the current pmap. In order to support
3684 * quick entry into any pmap, one would likely use pmap_pte_quick.
3685 * But that isn't as quick as vtopte.
3697 * Enter on the PV list if part of our managed memory.
3699 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3700 !pmap_try_insert_pv_entry(pmap, va, m)) {
3703 if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
3704 pmap_invalidate_page(pmap, va);
3705 pmap_free_zero_pages(free);
3714 * Increment counters
3716 pmap->pm_stats.resident_count++;
3718 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3720 if ((prot & VM_PROT_EXECUTE) == 0)
3725 * Now validate mapping with RO protection
3727 if ((m->oflags & VPO_UNMANAGED) != 0)
3728 pte_store(pte, pa | PG_V | PG_U);
3730 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3735 * Make a temporary mapping for a physical address. This is only intended
3736 * to be used for panic dumps.
3739 pmap_kenter_temporary(vm_paddr_t pa, int i)
3743 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3744 pmap_kenter(va, pa);
3746 return ((void *)crashdumpmap);
3750 * This code maps large physical mmap regions into the
3751 * processor address space. Note that some shortcuts
3752 * are taken, but the code works.
3755 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3756 vm_pindex_t pindex, vm_size_t size)
3759 vm_paddr_t pa, ptepa;
3763 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3764 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3765 ("pmap_object_init_pt: non-device object"));
3767 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3768 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3770 p = vm_page_lookup(object, pindex);
3771 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3772 ("pmap_object_init_pt: invalid page %p", p));
3773 pat_mode = p->md.pat_mode;
3776 * Abort the mapping if the first page is not physically
3777 * aligned to a 2/4MB page boundary.
3779 ptepa = VM_PAGE_TO_PHYS(p);
3780 if (ptepa & (NBPDR - 1))
3784 * Skip the first page. Abort the mapping if the rest of
3785 * the pages are not physically contiguous or have differing
3786 * memory attributes.
3788 p = TAILQ_NEXT(p, listq);
3789 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3791 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3792 ("pmap_object_init_pt: invalid page %p", p));
3793 if (pa != VM_PAGE_TO_PHYS(p) ||
3794 pat_mode != p->md.pat_mode)
3796 p = TAILQ_NEXT(p, listq);
3800 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3801 * "size" is a multiple of 2/4M, adding the PAT setting to
3802 * "pa" will not affect the termination of this loop.
3805 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3806 size; pa += NBPDR) {
3807 pde = pmap_pde(pmap, addr);
3809 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3810 PG_U | PG_RW | PG_V);
3811 pmap->pm_stats.resident_count += NBPDR /
3813 pmap_pde_mappings++;
3815 /* Else continue on if the PDE is already valid. */
3823 * Routine: pmap_change_wiring
3824 * Function: Change the wiring attribute for a map/virtual-address
3826 * In/out conditions:
3827 * The mapping must already exist in the pmap.
3830 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3834 boolean_t are_queues_locked;
3836 are_queues_locked = FALSE;
3839 pde = pmap_pde(pmap, va);
3840 if ((*pde & PG_PS) != 0) {
3841 if (!wired != ((*pde & PG_W) == 0)) {
3842 if (!are_queues_locked) {
3843 are_queues_locked = TRUE;
3844 if (!mtx_trylock(&vm_page_queue_mtx)) {
3846 vm_page_lock_queues();
3850 if (!pmap_demote_pde(pmap, pde, va))
3851 panic("pmap_change_wiring: demotion failed");
3855 pte = pmap_pte(pmap, va);
3857 if (wired && !pmap_pte_w(pte))
3858 pmap->pm_stats.wired_count++;
3859 else if (!wired && pmap_pte_w(pte))
3860 pmap->pm_stats.wired_count--;
3863 * Wiring is not a hardware characteristic so there is no need to
3866 pmap_pte_set_w(pte, wired);
3867 pmap_pte_release(pte);
3869 if (are_queues_locked)
3870 vm_page_unlock_queues();
3877 * Copy the range specified by src_addr/len
3878 * from the source map to the range dst_addr/len
3879 * in the destination map.
3881 * This routine is only advisory and need not do anything.
3885 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3886 vm_offset_t src_addr)
3890 vm_offset_t end_addr = src_addr + len;
3893 if (dst_addr != src_addr)
3896 if (!pmap_is_current(src_pmap))
3899 vm_page_lock_queues();
3900 if (dst_pmap < src_pmap) {
3901 PMAP_LOCK(dst_pmap);
3902 PMAP_LOCK(src_pmap);
3904 PMAP_LOCK(src_pmap);
3905 PMAP_LOCK(dst_pmap);
3908 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3909 pt_entry_t *src_pte, *dst_pte;
3910 vm_page_t dstmpte, srcmpte;
3911 pd_entry_t srcptepaddr;
3914 KASSERT(addr < UPT_MIN_ADDRESS,
3915 ("pmap_copy: invalid to pmap_copy page tables"));
3917 pdnxt = (addr + NBPDR) & ~PDRMASK;
3920 ptepindex = addr >> PDRSHIFT;
3922 srcptepaddr = src_pmap->pm_pdir[ptepindex];
3923 if (srcptepaddr == 0)
3926 if (srcptepaddr & PG_PS) {
3927 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
3928 ((srcptepaddr & PG_MANAGED) == 0 ||
3929 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
3931 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
3933 dst_pmap->pm_stats.resident_count +=
3939 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
3940 KASSERT(srcmpte->wire_count > 0,
3941 ("pmap_copy: source page table page is unused"));
3943 if (pdnxt > end_addr)
3946 src_pte = vtopte(addr);
3947 while (addr < pdnxt) {
3951 * we only virtual copy managed pages
3953 if ((ptetemp & PG_MANAGED) != 0) {
3954 dstmpte = pmap_allocpte(dst_pmap, addr,
3956 if (dstmpte == NULL)
3958 dst_pte = pmap_pte_quick(dst_pmap, addr);
3959 if (*dst_pte == 0 &&
3960 pmap_try_insert_pv_entry(dst_pmap, addr,
3961 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
3963 * Clear the wired, modified, and
3964 * accessed (referenced) bits
3967 *dst_pte = ptetemp & ~(PG_W | PG_M |
3969 dst_pmap->pm_stats.resident_count++;
3972 if (pmap_unwire_pte_hold(dst_pmap,
3974 pmap_invalidate_page(dst_pmap,
3976 pmap_free_zero_pages(free);
3980 if (dstmpte->wire_count >= srcmpte->wire_count)
3989 vm_page_unlock_queues();
3990 PMAP_UNLOCK(src_pmap);
3991 PMAP_UNLOCK(dst_pmap);
3994 static __inline void
3995 pagezero(void *page)
3997 #if defined(I686_CPU)
3998 if (cpu_class == CPUCLASS_686) {
3999 #if defined(CPU_ENABLE_SSE)
4000 if (cpu_feature & CPUID_SSE2)
4001 sse2_pagezero(page);
4004 i686_pagezero(page);
4007 bzero(page, PAGE_SIZE);
4011 * pmap_zero_page zeros the specified hardware page by mapping
4012 * the page into KVM and using bzero to clear its contents.
4015 pmap_zero_page(vm_page_t m)
4017 struct sysmaps *sysmaps;
4019 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4020 mtx_lock(&sysmaps->lock);
4021 if (*sysmaps->CMAP2)
4022 panic("pmap_zero_page: CMAP2 busy");
4024 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4025 pmap_cache_bits(m->md.pat_mode, 0);
4026 invlcaddr(sysmaps->CADDR2);
4027 pagezero(sysmaps->CADDR2);
4028 *sysmaps->CMAP2 = 0;
4030 mtx_unlock(&sysmaps->lock);
4034 * pmap_zero_page_area zeros the specified hardware page by mapping
4035 * the page into KVM and using bzero to clear its contents.
4037 * off and size may not cover an area beyond a single hardware page.
4040 pmap_zero_page_area(vm_page_t m, int off, int size)
4042 struct sysmaps *sysmaps;
4044 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4045 mtx_lock(&sysmaps->lock);
4046 if (*sysmaps->CMAP2)
4047 panic("pmap_zero_page_area: CMAP2 busy");
4049 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4050 pmap_cache_bits(m->md.pat_mode, 0);
4051 invlcaddr(sysmaps->CADDR2);
4052 if (off == 0 && size == PAGE_SIZE)
4053 pagezero(sysmaps->CADDR2);
4055 bzero((char *)sysmaps->CADDR2 + off, size);
4056 *sysmaps->CMAP2 = 0;
4058 mtx_unlock(&sysmaps->lock);
4062 * pmap_zero_page_idle zeros the specified hardware page by mapping
4063 * the page into KVM and using bzero to clear its contents. This
4064 * is intended to be called from the vm_pagezero process only and
4068 pmap_zero_page_idle(vm_page_t m)
4072 panic("pmap_zero_page_idle: CMAP3 busy");
4074 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4075 pmap_cache_bits(m->md.pat_mode, 0);
4083 * pmap_copy_page copies the specified (machine independent)
4084 * page by mapping the page into virtual memory and using
4085 * bcopy to copy the page, one machine dependent page at a
4089 pmap_copy_page(vm_page_t src, vm_page_t dst)
4091 struct sysmaps *sysmaps;
4093 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4094 mtx_lock(&sysmaps->lock);
4095 if (*sysmaps->CMAP1)
4096 panic("pmap_copy_page: CMAP1 busy");
4097 if (*sysmaps->CMAP2)
4098 panic("pmap_copy_page: CMAP2 busy");
4100 invlpg((u_int)sysmaps->CADDR1);
4101 invlpg((u_int)sysmaps->CADDR2);
4102 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4103 pmap_cache_bits(src->md.pat_mode, 0);
4104 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4105 pmap_cache_bits(dst->md.pat_mode, 0);
4106 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4107 *sysmaps->CMAP1 = 0;
4108 *sysmaps->CMAP2 = 0;
4110 mtx_unlock(&sysmaps->lock);
4114 * Returns true if the pmap's pv is one of the first
4115 * 16 pvs linked to from this page. This count may
4116 * be changed upwards or downwards in the future; it
4117 * is only necessary that true be returned for a small
4118 * subset of pmaps for proper page aging.
4121 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4123 struct md_page *pvh;
4128 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4129 ("pmap_page_exists_quick: page %p is not managed", m));
4131 vm_page_lock_queues();
4132 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4133 if (PV_PMAP(pv) == pmap) {
4141 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4142 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4143 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4144 if (PV_PMAP(pv) == pmap) {
4153 vm_page_unlock_queues();
4158 * pmap_page_wired_mappings:
4160 * Return the number of managed mappings to the given physical page
4164 pmap_page_wired_mappings(vm_page_t m)
4169 if ((m->oflags & VPO_UNMANAGED) != 0)
4171 vm_page_lock_queues();
4172 count = pmap_pvh_wired_mappings(&m->md, count);
4173 if ((m->flags & PG_FICTITIOUS) == 0) {
4174 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4177 vm_page_unlock_queues();
4182 * pmap_pvh_wired_mappings:
4184 * Return the updated number "count" of managed mappings that are wired.
4187 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4193 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4195 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4198 pte = pmap_pte_quick(pmap, pv->pv_va);
4199 if ((*pte & PG_W) != 0)
4208 * Returns TRUE if the given page is mapped individually or as part of
4209 * a 4mpage. Otherwise, returns FALSE.
4212 pmap_page_is_mapped(vm_page_t m)
4216 if ((m->oflags & VPO_UNMANAGED) != 0)
4218 vm_page_lock_queues();
4219 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4220 ((m->flags & PG_FICTITIOUS) == 0 &&
4221 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4222 vm_page_unlock_queues();
4227 * Remove all pages from specified address space
4228 * this aids process exit speeds. Also, this code
4229 * is special cased for current process only, but
4230 * can have the more generic (and slightly slower)
4231 * mode enabled. This is much faster than pmap_remove
4232 * in the case of running down an entire address space.
4235 pmap_remove_pages(pmap_t pmap)
4237 pt_entry_t *pte, tpte;
4238 vm_page_t free = NULL;
4239 vm_page_t m, mpte, mt;
4241 struct md_page *pvh;
4242 struct pv_chunk *pc, *npc;
4245 uint32_t inuse, bitmask;
4248 if (pmap != PCPU_GET(curpmap)) {
4249 printf("warning: pmap_remove_pages called with non-current pmap\n");
4252 vm_page_lock_queues();
4255 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4257 for (field = 0; field < _NPCM; field++) {
4258 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4259 while (inuse != 0) {
4261 bitmask = 1UL << bit;
4262 idx = field * 32 + bit;
4263 pv = &pc->pc_pventry[idx];
4266 pte = pmap_pde(pmap, pv->pv_va);
4268 if ((tpte & PG_PS) == 0) {
4269 pte = vtopte(pv->pv_va);
4270 tpte = *pte & ~PG_PTE_PAT;
4275 "TPTE at %p IS ZERO @ VA %08x\n",
4281 * We cannot remove wired pages from a process' mapping at this time
4288 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4289 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4290 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4291 m, (uintmax_t)m->phys_addr,
4294 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4295 m < &vm_page_array[vm_page_array_size],
4296 ("pmap_remove_pages: bad tpte %#jx",
4302 * Update the vm_page_t clean/reference bits.
4304 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4305 if ((tpte & PG_PS) != 0) {
4306 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4313 PV_STAT(pv_entry_frees++);
4314 PV_STAT(pv_entry_spare++);
4316 pc->pc_map[field] |= bitmask;
4317 if ((tpte & PG_PS) != 0) {
4318 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4319 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4320 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4321 if (TAILQ_EMPTY(&pvh->pv_list)) {
4322 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4323 if (TAILQ_EMPTY(&mt->md.pv_list))
4324 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4326 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4328 pmap_remove_pt_page(pmap, mpte);
4329 pmap->pm_stats.resident_count--;
4330 KASSERT(mpte->wire_count == NPTEPG,
4331 ("pmap_remove_pages: pte page wire count error"));
4332 mpte->wire_count = 0;
4333 pmap_add_delayed_free_list(mpte, &free, FALSE);
4334 atomic_subtract_int(&cnt.v_wire_count, 1);
4337 pmap->pm_stats.resident_count--;
4338 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4339 if (TAILQ_EMPTY(&m->md.pv_list) &&
4340 (m->flags & PG_FICTITIOUS) == 0) {
4341 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4342 if (TAILQ_EMPTY(&pvh->pv_list))
4343 vm_page_aflag_clear(m, PGA_WRITEABLE);
4345 pmap_unuse_pt(pmap, pv->pv_va, &free);
4350 PV_STAT(pv_entry_spare -= _NPCPV);
4351 PV_STAT(pc_chunk_count--);
4352 PV_STAT(pc_chunk_frees++);
4353 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4354 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4355 pmap_qremove((vm_offset_t)pc, 1);
4356 vm_page_unwire(m, 0);
4358 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4362 pmap_invalidate_all(pmap);
4363 vm_page_unlock_queues();
4365 pmap_free_zero_pages(free);
4371 * Return whether or not the specified physical page was modified
4372 * in any physical maps.
4375 pmap_is_modified(vm_page_t m)
4379 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4380 ("pmap_is_modified: page %p is not managed", m));
4383 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
4384 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4385 * is clear, no PTEs can have PG_M set.
4387 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4388 if ((m->oflags & VPO_BUSY) == 0 &&
4389 (m->aflags & PGA_WRITEABLE) == 0)
4391 vm_page_lock_queues();
4392 rv = pmap_is_modified_pvh(&m->md) ||
4393 ((m->flags & PG_FICTITIOUS) == 0 &&
4394 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4395 vm_page_unlock_queues();
4400 * Returns TRUE if any of the given mappings were used to modify
4401 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4402 * mappings are supported.
4405 pmap_is_modified_pvh(struct md_page *pvh)
4412 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4415 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4418 pte = pmap_pte_quick(pmap, pv->pv_va);
4419 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4429 * pmap_is_prefaultable:
4431 * Return whether or not the specified virtual address is elgible
4435 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4443 pde = pmap_pde(pmap, addr);
4444 if (*pde != 0 && (*pde & PG_PS) == 0) {
4453 * pmap_is_referenced:
4455 * Return whether or not the specified physical page was referenced
4456 * in any physical maps.
4459 pmap_is_referenced(vm_page_t m)
4463 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4464 ("pmap_is_referenced: page %p is not managed", m));
4465 vm_page_lock_queues();
4466 rv = pmap_is_referenced_pvh(&m->md) ||
4467 ((m->flags & PG_FICTITIOUS) == 0 &&
4468 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4469 vm_page_unlock_queues();
4474 * Returns TRUE if any of the given mappings were referenced and FALSE
4475 * otherwise. Both page and 4mpage mappings are supported.
4478 pmap_is_referenced_pvh(struct md_page *pvh)
4485 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4488 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4491 pte = pmap_pte_quick(pmap, pv->pv_va);
4492 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4502 * Clear the write and modified bits in each of the given page's mappings.
4505 pmap_remove_write(vm_page_t m)
4507 struct md_page *pvh;
4508 pv_entry_t next_pv, pv;
4511 pt_entry_t oldpte, *pte;
4514 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4515 ("pmap_remove_write: page %p is not managed", m));
4518 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
4519 * another thread while the object is locked. Thus, if PGA_WRITEABLE
4520 * is clear, no page table entries need updating.
4522 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4523 if ((m->oflags & VPO_BUSY) == 0 &&
4524 (m->aflags & PGA_WRITEABLE) == 0)
4526 vm_page_lock_queues();
4528 if ((m->flags & PG_FICTITIOUS) != 0)
4529 goto small_mappings;
4530 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4531 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4535 pde = pmap_pde(pmap, va);
4536 if ((*pde & PG_RW) != 0)
4537 (void)pmap_demote_pde(pmap, pde, va);
4541 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4544 pde = pmap_pde(pmap, pv->pv_va);
4545 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4546 " a 4mpage in page %p's pv list", m));
4547 pte = pmap_pte_quick(pmap, pv->pv_va);
4550 if ((oldpte & PG_RW) != 0) {
4552 * Regardless of whether a pte is 32 or 64 bits
4553 * in size, PG_RW and PG_M are among the least
4554 * significant 32 bits.
4556 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4557 oldpte & ~(PG_RW | PG_M)))
4559 if ((oldpte & PG_M) != 0)
4561 pmap_invalidate_page(pmap, pv->pv_va);
4565 vm_page_aflag_clear(m, PGA_WRITEABLE);
4567 vm_page_unlock_queues();
4571 * pmap_ts_referenced:
4573 * Return a count of reference bits for a page, clearing those bits.
4574 * It is not necessary for every reference bit to be cleared, but it
4575 * is necessary that 0 only be returned when there are truly no
4576 * reference bits set.
4578 * XXX: The exact number of bits to check and clear is a matter that
4579 * should be tested and standardized at some point in the future for
4580 * optimal aging of shared pages.
4583 pmap_ts_referenced(vm_page_t m)
4585 struct md_page *pvh;
4586 pv_entry_t pv, pvf, pvn;
4588 pd_entry_t oldpde, *pde;
4593 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4594 ("pmap_ts_referenced: page %p is not managed", m));
4595 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4596 vm_page_lock_queues();
4598 if ((m->flags & PG_FICTITIOUS) != 0)
4599 goto small_mappings;
4600 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4604 pde = pmap_pde(pmap, va);
4606 if ((oldpde & PG_A) != 0) {
4607 if (pmap_demote_pde(pmap, pde, va)) {
4608 if ((oldpde & PG_W) == 0) {
4610 * Remove the mapping to a single page
4611 * so that a subsequent access may
4612 * repromote. Since the underlying
4613 * page table page is fully populated,
4614 * this removal never frees a page
4617 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4619 pmap_remove_page(pmap, va, NULL);
4631 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4634 pvn = TAILQ_NEXT(pv, pv_list);
4635 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4636 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4639 pde = pmap_pde(pmap, pv->pv_va);
4640 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4641 " found a 4mpage in page %p's pv list", m));
4642 pte = pmap_pte_quick(pmap, pv->pv_va);
4643 if ((*pte & PG_A) != 0) {
4644 atomic_clear_int((u_int *)pte, PG_A);
4645 pmap_invalidate_page(pmap, pv->pv_va);
4651 } while ((pv = pvn) != NULL && pv != pvf);
4655 vm_page_unlock_queues();
4660 * Clear the modify bits on the specified physical page.
4663 pmap_clear_modify(vm_page_t m)
4665 struct md_page *pvh;
4666 pv_entry_t next_pv, pv;
4668 pd_entry_t oldpde, *pde;
4669 pt_entry_t oldpte, *pte;
4672 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4673 ("pmap_clear_modify: page %p is not managed", m));
4674 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
4675 KASSERT((m->oflags & VPO_BUSY) == 0,
4676 ("pmap_clear_modify: page %p is busy", m));
4679 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4680 * If the object containing the page is locked and the page is not
4681 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
4683 if ((m->aflags & PGA_WRITEABLE) == 0)
4685 vm_page_lock_queues();
4687 if ((m->flags & PG_FICTITIOUS) != 0)
4688 goto small_mappings;
4689 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4690 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4694 pde = pmap_pde(pmap, va);
4696 if ((oldpde & PG_RW) != 0) {
4697 if (pmap_demote_pde(pmap, pde, va)) {
4698 if ((oldpde & PG_W) == 0) {
4700 * Write protect the mapping to a
4701 * single page so that a subsequent
4702 * write access may repromote.
4704 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4706 pte = pmap_pte_quick(pmap, va);
4708 if ((oldpte & PG_V) != 0) {
4710 * Regardless of whether a pte is 32 or 64 bits
4711 * in size, PG_RW and PG_M are among the least
4712 * significant 32 bits.
4714 while (!atomic_cmpset_int((u_int *)pte,
4716 oldpte & ~(PG_M | PG_RW)))
4719 pmap_invalidate_page(pmap, va);
4727 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4730 pde = pmap_pde(pmap, pv->pv_va);
4731 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4732 " a 4mpage in page %p's pv list", m));
4733 pte = pmap_pte_quick(pmap, pv->pv_va);
4734 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4736 * Regardless of whether a pte is 32 or 64 bits
4737 * in size, PG_M is among the least significant
4740 atomic_clear_int((u_int *)pte, PG_M);
4741 pmap_invalidate_page(pmap, pv->pv_va);
4746 vm_page_unlock_queues();
4750 * pmap_clear_reference:
4752 * Clear the reference bit on the specified physical page.
4755 pmap_clear_reference(vm_page_t m)
4757 struct md_page *pvh;
4758 pv_entry_t next_pv, pv;
4760 pd_entry_t oldpde, *pde;
4764 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4765 ("pmap_clear_reference: page %p is not managed", m));
4766 vm_page_lock_queues();
4768 if ((m->flags & PG_FICTITIOUS) != 0)
4769 goto small_mappings;
4770 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4771 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4775 pde = pmap_pde(pmap, va);
4777 if ((oldpde & PG_A) != 0) {
4778 if (pmap_demote_pde(pmap, pde, va)) {
4780 * Remove the mapping to a single page so
4781 * that a subsequent access may repromote.
4782 * Since the underlying page table page is
4783 * fully populated, this removal never frees
4784 * a page table page.
4786 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4788 pmap_remove_page(pmap, va, NULL);
4794 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4797 pde = pmap_pde(pmap, pv->pv_va);
4798 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4799 " a 4mpage in page %p's pv list", m));
4800 pte = pmap_pte_quick(pmap, pv->pv_va);
4801 if ((*pte & PG_A) != 0) {
4803 * Regardless of whether a pte is 32 or 64 bits
4804 * in size, PG_A is among the least significant
4807 atomic_clear_int((u_int *)pte, PG_A);
4808 pmap_invalidate_page(pmap, pv->pv_va);
4813 vm_page_unlock_queues();
4817 * Miscellaneous support routines follow
4820 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4821 static __inline void
4822 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4827 * The cache mode bits are all in the low 32-bits of the
4828 * PTE, so we can just spin on updating the low 32-bits.
4831 opte = *(u_int *)pte;
4832 npte = opte & ~PG_PTE_CACHE;
4834 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4837 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
4838 static __inline void
4839 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4844 * The cache mode bits are all in the low 32-bits of the
4845 * PDE, so we can just spin on updating the low 32-bits.
4848 opde = *(u_int *)pde;
4849 npde = opde & ~PG_PDE_CACHE;
4851 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4855 * Map a set of physical memory pages into the kernel virtual
4856 * address space. Return a pointer to where it is mapped. This
4857 * routine is intended to be used for mapping device memory,
4861 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4863 vm_offset_t va, offset;
4866 offset = pa & PAGE_MASK;
4867 size = roundup(offset + size, PAGE_SIZE);
4870 if (pa < KERNLOAD && pa + size <= KERNLOAD)
4873 va = kmem_alloc_nofault(kernel_map, size);
4875 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4877 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4878 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
4879 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
4880 pmap_invalidate_cache_range(va, va + size);
4881 return ((void *)(va + offset));
4885 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
4888 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
4892 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4895 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4899 pmap_unmapdev(vm_offset_t va, vm_size_t size)
4901 vm_offset_t base, offset, tmpva;
4903 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
4905 base = trunc_page(va);
4906 offset = va & PAGE_MASK;
4907 size = roundup(offset + size, PAGE_SIZE);
4908 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
4909 pmap_kremove(tmpva);
4910 pmap_invalidate_range(kernel_pmap, va, tmpva);
4911 kmem_free(kernel_map, base, size);
4915 * Sets the memory attribute for the specified page.
4918 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4921 m->md.pat_mode = ma;
4922 if ((m->flags & PG_FICTITIOUS) != 0)
4926 * If "m" is a normal page, flush it from the cache.
4927 * See pmap_invalidate_cache_range().
4929 * First, try to find an existing mapping of the page by sf
4930 * buffer. sf_buf_invalidate_cache() modifies mapping and
4931 * flushes the cache.
4933 if (sf_buf_invalidate_cache(m))
4937 * If page is not mapped by sf buffer, but CPU does not
4938 * support self snoop, map the page transient and do
4939 * invalidation. In the worst case, whole cache is flushed by
4940 * pmap_invalidate_cache_range().
4942 if ((cpu_feature & CPUID_SS) == 0)
4947 pmap_flush_page(vm_page_t m)
4949 struct sysmaps *sysmaps;
4950 vm_offset_t sva, eva;
4952 if ((cpu_feature & CPUID_CLFSH) != 0) {
4953 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4954 mtx_lock(&sysmaps->lock);
4955 if (*sysmaps->CMAP2)
4956 panic("pmap_flush_page: CMAP2 busy");
4958 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
4959 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
4960 invlcaddr(sysmaps->CADDR2);
4961 sva = (vm_offset_t)sysmaps->CADDR2;
4962 eva = sva + PAGE_SIZE;
4965 * Use mfence despite the ordering implied by
4966 * mtx_{un,}lock() because clflush is not guaranteed
4967 * to be ordered by any other instruction.
4970 for (; sva < eva; sva += cpu_clflush_line_size)
4973 *sysmaps->CMAP2 = 0;
4975 mtx_unlock(&sysmaps->lock);
4977 pmap_invalidate_cache();
4981 * Changes the specified virtual address range's memory type to that given by
4982 * the parameter "mode". The specified virtual address range must be
4983 * completely contained within either the kernel map.
4985 * Returns zero if the change completed successfully, and either EINVAL or
4986 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4987 * of the virtual address range was not mapped, and ENOMEM is returned if
4988 * there was insufficient memory available to complete the change.
4991 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4993 vm_offset_t base, offset, tmpva;
4996 int cache_bits_pte, cache_bits_pde;
4999 base = trunc_page(va);
5000 offset = va & PAGE_MASK;
5001 size = roundup(offset + size, PAGE_SIZE);
5004 * Only supported on kernel virtual addresses above the recursive map.
5006 if (base < VM_MIN_KERNEL_ADDRESS)
5009 cache_bits_pde = pmap_cache_bits(mode, 1);
5010 cache_bits_pte = pmap_cache_bits(mode, 0);
5014 * Pages that aren't mapped aren't supported. Also break down
5015 * 2/4MB pages into 4KB pages if required.
5017 PMAP_LOCK(kernel_pmap);
5018 for (tmpva = base; tmpva < base + size; ) {
5019 pde = pmap_pde(kernel_pmap, tmpva);
5021 PMAP_UNLOCK(kernel_pmap);
5026 * If the current 2/4MB page already has
5027 * the required memory type, then we need not
5028 * demote this page. Just increment tmpva to
5029 * the next 2/4MB page frame.
5031 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5032 tmpva = trunc_4mpage(tmpva) + NBPDR;
5037 * If the current offset aligns with a 2/4MB
5038 * page frame and there is at least 2/4MB left
5039 * within the range, then we need not break
5040 * down this page into 4KB pages.
5042 if ((tmpva & PDRMASK) == 0 &&
5043 tmpva + PDRMASK < base + size) {
5047 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5048 PMAP_UNLOCK(kernel_pmap);
5052 pte = vtopte(tmpva);
5054 PMAP_UNLOCK(kernel_pmap);
5059 PMAP_UNLOCK(kernel_pmap);
5062 * Ok, all the pages exist, so run through them updating their
5063 * cache mode if required.
5065 for (tmpva = base; tmpva < base + size; ) {
5066 pde = pmap_pde(kernel_pmap, tmpva);
5068 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5069 pmap_pde_attr(pde, cache_bits_pde);
5072 tmpva = trunc_4mpage(tmpva) + NBPDR;
5074 pte = vtopte(tmpva);
5075 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5076 pmap_pte_attr(pte, cache_bits_pte);
5084 * Flush CPU caches to make sure any data isn't cached that
5085 * shouldn't be, etc.
5088 pmap_invalidate_range(kernel_pmap, base, tmpva);
5089 pmap_invalidate_cache_range(base, tmpva);
5095 * perform the pmap work for mincore
5098 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5101 pt_entry_t *ptep, pte;
5107 pdep = pmap_pde(pmap, addr);
5109 if (*pdep & PG_PS) {
5111 /* Compute the physical address of the 4KB page. */
5112 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5114 val = MINCORE_SUPER;
5116 ptep = pmap_pte(pmap, addr);
5118 pmap_pte_release(ptep);
5119 pa = pte & PG_FRAME;
5127 if ((pte & PG_V) != 0) {
5128 val |= MINCORE_INCORE;
5129 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5130 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5131 if ((pte & PG_A) != 0)
5132 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5134 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5135 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5136 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5137 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5138 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5141 PA_UNLOCK_COND(*locked_pa);
5147 pmap_activate(struct thread *td)
5149 pmap_t pmap, oldpmap;
5154 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5155 oldpmap = PCPU_GET(curpmap);
5156 cpuid = PCPU_GET(cpuid);
5158 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5159 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5161 CPU_CLR(cpuid, &oldpmap->pm_active);
5162 CPU_SET(cpuid, &pmap->pm_active);
5165 cr3 = vtophys(pmap->pm_pdpt);
5167 cr3 = vtophys(pmap->pm_pdir);
5170 * pmap_activate is for the current thread on the current cpu
5172 td->td_pcb->pcb_cr3 = cr3;
5174 PCPU_SET(curpmap, pmap);
5179 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5184 * Increase the starting virtual address of the given mapping if a
5185 * different alignment might result in more superpage mappings.
5188 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5189 vm_offset_t *addr, vm_size_t size)
5191 vm_offset_t superpage_offset;
5195 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5196 offset += ptoa(object->pg_color);
5197 superpage_offset = offset & PDRMASK;
5198 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5199 (*addr & PDRMASK) == superpage_offset)
5201 if ((*addr & PDRMASK) < superpage_offset)
5202 *addr = (*addr & ~PDRMASK) + superpage_offset;
5204 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5208 #if defined(PMAP_DEBUG)
5209 pmap_pid_dump(int pid)
5216 sx_slock(&allproc_lock);
5217 FOREACH_PROC_IN_SYSTEM(p) {
5218 if (p->p_pid != pid)
5224 pmap = vmspace_pmap(p->p_vmspace);
5225 for (i = 0; i < NPDEPTD; i++) {
5228 vm_offset_t base = i << PDRSHIFT;
5230 pde = &pmap->pm_pdir[i];
5231 if (pde && pmap_pde_v(pde)) {
5232 for (j = 0; j < NPTEPG; j++) {
5233 vm_offset_t va = base + (j << PAGE_SHIFT);
5234 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5239 sx_sunlock(&allproc_lock);
5242 pte = pmap_pte(pmap, va);
5243 if (pte && pmap_pte_v(pte)) {
5247 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5248 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5249 va, pa, m->hold_count, m->wire_count, m->flags);
5264 sx_sunlock(&allproc_lock);
5271 static void pads(pmap_t pm);
5272 void pmap_pvdump(vm_paddr_t pa);
5274 /* print address space of pmap*/
5282 if (pm == kernel_pmap)
5284 for (i = 0; i < NPDEPTD; i++)
5286 for (j = 0; j < NPTEPG; j++) {
5287 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5288 if (pm == kernel_pmap && va < KERNBASE)
5290 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5292 ptep = pmap_pte(pm, va);
5293 if (pmap_pte_v(ptep))
5294 printf("%x:%x ", va, *ptep);
5300 pmap_pvdump(vm_paddr_t pa)
5306 printf("pa %x", pa);
5307 m = PHYS_TO_VM_PAGE(pa);
5308 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
5310 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);