2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _MACHINE_APICVAR_H_
33 #define _MACHINE_APICVAR_H_
36 * Local && I/O APIC variable definitions.
40 * Layout of local APIC interrupt vectors:
42 * 0xff (255) +-------------+
43 * | | 15 (Spurious / IPIs / Local Interrupts)
44 * 0xf0 (240) +-------------+
45 * | | 14 (I/O Interrupts / Timer)
46 * 0xe0 (224) +-------------+
47 * | | 13 (I/O Interrupts)
48 * 0xd0 (208) +-------------+
49 * | | 12 (I/O Interrupts)
50 * 0xc0 (192) +-------------+
51 * | | 11 (I/O Interrupts)
52 * 0xb0 (176) +-------------+
53 * | | 10 (I/O Interrupts)
54 * 0xa0 (160) +-------------+
55 * | | 9 (I/O Interrupts)
56 * 0x90 (144) +-------------+
57 * | | 8 (I/O Interrupts / System Calls)
58 * 0x80 (128) +-------------+
59 * | | 7 (I/O Interrupts)
60 * 0x70 (112) +-------------+
61 * | | 6 (I/O Interrupts)
62 * 0x60 (96) +-------------+
63 * | | 5 (I/O Interrupts)
64 * 0x50 (80) +-------------+
65 * | | 4 (I/O Interrupts)
66 * 0x40 (64) +-------------+
67 * | | 3 (I/O Interrupts)
68 * 0x30 (48) +-------------+
69 * | | 2 (ATPIC Interrupts)
70 * 0x20 (32) +-------------+
71 * | | 1 (Exceptions, traps, faults, etc.)
72 * 0x10 (16) +-------------+
73 * | | 0 (Exceptions, traps, faults, etc.)
74 * 0x00 (0) +-------------+
76 * Note: 0x80 needs to be handled specially and not allocated to an
80 #define MAX_APIC_ID 0xfe
81 #define APIC_ID_ALL 0xff
83 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
84 #define APIC_IO_INTS (IDT_IO_INTS + 16)
85 #define APIC_NUM_IOINTS 191
87 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
88 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
91 ********************* !!! WARNING !!! ******************************
92 * Each local apic has an interrupt receive fifo that is two entries deep
93 * for each interrupt priority class (higher 4 bits of interrupt vector).
94 * Once the fifo is full the APIC can no longer receive interrupts for this
95 * class and sending IPIs from other CPUs will be blocked.
96 * To avoid deadlocks there should be no more than two IPI interrupts
97 * pending at the same time.
98 * Currently this is guaranteed by dividing the IPIs in two groups that have
99 * each at most one IPI interrupt pending. The first group is protected by the
100 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
101 * at a time) The second group uses a single interrupt and a bitmap to avoid
102 * redundant IPI interrupts.
105 /* Interrupts for local APIC LVT entries other than the timer. */
107 /* These are the Xen i386 APIC definitions */
108 #define APIC_LOCAL_INTS 240
109 #define APIC_ERROR_INT APIC_LOCAL_INTS
110 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
111 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 2)
113 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
114 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
115 #define IPI_INVLPG (APIC_IPI_INTS + 2)
116 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
117 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
118 #define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */
119 /* Vector to handle bitmap based IPIs */
120 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6)
122 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
123 #define IPI_AST 0 /* Generate software trap. */
124 #define IPI_PREEMPT 1
125 #define IPI_HARDCLOCK 2
126 #define IPI_STATCLOCK 3
127 #define IPI_PROFCLOCK 4
128 #define IPI_BITMAP_LAST IPI_PROFCLOCK
129 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
131 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
132 #define IPI_STOP_HARD (APIC_IPI_INTS + 8) /* Stop CPU with a NMI. */
135 /* These are the normal i386 APIC definitions */
136 #define APIC_LOCAL_INTS 240
137 #define APIC_ERROR_INT APIC_LOCAL_INTS
138 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
139 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 2)
141 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
142 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
143 #define IPI_INVLPG (APIC_IPI_INTS + 2)
144 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
145 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
146 #define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */
147 /* Vector to handle bitmap based IPIs */
148 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6)
150 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
151 #define IPI_AST 0 /* Generate software trap. */
152 #define IPI_PREEMPT 1
153 #define IPI_HARDCLOCK 2
154 #define IPI_STATCLOCK 3
155 #define IPI_PROFCLOCK 4
156 #define IPI_BITMAP_LAST IPI_PROFCLOCK
157 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
159 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
160 #define IPI_STOP_HARD (APIC_IPI_INTS + 8) /* Stop CPU with a NMI. */
164 * The spurious interrupt can share the priority class with the IPIs since
165 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
167 #define APIC_SPURIOUS_INT 255
174 #define LVT_THERMAL 5
175 #define LVT_MAX LVT_THERMAL
179 #define APIC_IPI_DEST_SELF -1
180 #define APIC_IPI_DEST_ALL -2
181 #define APIC_IPI_DEST_OTHERS -3
183 #define APIC_BUS_UNKNOWN -1
184 #define APIC_BUS_ISA 0
185 #define APIC_BUS_EISA 1
186 #define APIC_BUS_PCI 2
187 #define APIC_BUS_MAX APIC_BUS_PCI
190 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
191 * CPU's and I/O APIC's.
193 struct apic_enumerator {
194 const char *apic_name;
195 int (*apic_probe)(void);
196 int (*apic_probe_cpus)(void);
197 int (*apic_setup_local)(void);
198 int (*apic_setup_io)(void);
199 SLIST_ENTRY(apic_enumerator) apic_next;
203 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
204 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
205 IDTVEC(apic_isr7), IDTVEC(spuriousint), IDTVEC(timerint);
207 extern vm_paddr_t lapic_paddr;
208 extern int apic_cpuids[];
210 u_int apic_alloc_vector(u_int apic_id, u_int irq);
211 u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count,
213 void apic_disable_vector(u_int apic_id, u_int vector);
214 void apic_enable_vector(u_int apic_id, u_int vector);
215 void apic_free_vector(u_int apic_id, u_int vector, u_int irq);
216 u_int apic_idt_to_irq(u_int apic_id, u_int vector);
217 void apic_register_enumerator(struct apic_enumerator *enumerator);
218 u_int apic_cpuid(u_int apic_id);
219 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
220 int ioapic_disable_pin(void *cookie, u_int pin);
221 int ioapic_get_vector(void *cookie, u_int pin);
222 void ioapic_register(void *cookie);
223 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
224 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
225 int ioapic_set_extint(void *cookie, u_int pin);
226 int ioapic_set_nmi(void *cookie, u_int pin);
227 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
228 int ioapic_set_triggermode(void *cookie, u_int pin,
229 enum intr_trigger trigger);
230 int ioapic_set_smi(void *cookie, u_int pin);
231 void lapic_create(u_int apic_id, int boot_cpu);
232 void lapic_disable(void);
233 void lapic_dump(const char *str);
234 void lapic_eoi(void);
235 u_int lapic_error(void);
237 void lapic_init(vm_paddr_t addr);
238 int lapic_intr_pending(u_int vector);
239 void lapic_ipi_raw(register_t icrlo, u_int dest);
240 void lapic_ipi_vectored(u_int vector, int dest);
241 int lapic_ipi_wait(int delay);
242 void lapic_handle_intr(int vector, struct trapframe *frame);
243 void lapic_handle_timer(struct trapframe *frame);
244 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
245 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
246 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
247 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
248 enum intr_polarity pol);
249 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
250 enum intr_trigger trigger);
251 void lapic_set_tpr(u_int vector);
252 void lapic_setup(int boot);
253 int lapic_setup_clock(void);
256 #endif /* _MACHINE_APICVAR_H_ */