2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@freebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/mutex.h>
41 #include <sys/malloc.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/pci_cfgreg.h>
47 #include <machine/pc/bios.h>
50 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
54 #include <machine/pmap.h>
57 #include <machine/xbox.h>
60 #define PRVERB(a) do { \
66 struct pcie_cfg_elem {
67 TAILQ_ENTRY(pcie_cfg_elem) elem;
81 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
82 static uint64_t pcie_base;
83 static int pcie_minbus, pcie_maxbus;
84 static uint32_t pcie_badslots;
87 static struct mtx pcicfg_mtx;
88 static int mcfg_enable = 1;
89 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
90 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
91 "Enable support for PCI-e memory mapped config access");
93 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
95 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
96 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
98 static int pcireg_cfgopen(void);
100 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
101 unsigned reg, unsigned bytes);
102 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
103 unsigned reg, int data, unsigned bytes);
106 * Some BIOS writers seem to want to ignore the spec and put
107 * 0 in the intline rather than 255 to indicate none. Some use
108 * numbers in the range 128-254 to indicate something strange and
109 * apparently undocumented anywhere. Assume these are completely bogus
110 * and map them to 255, which means "none".
113 pci_i386_map_intline(int line)
115 if (line == 0 || line >= 128)
116 return (PCI_INVALID_IRQ);
122 pcibios_get_version(void)
124 struct bios_regs args;
126 if (PCIbios.ventry == 0) {
127 PRVERB(("pcibios: No call entry point\n"));
130 args.eax = PCIBIOS_BIOS_PRESENT;
131 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
132 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
135 if (args.edx != 0x20494350) {
136 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
139 return (args.ebx & 0xffff);
144 * Initialise access to PCI configuration space
152 static int opened = 0;
160 if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0)
163 v = pcibios_get_version();
165 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
167 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
170 /* $PIR requires PCI BIOS 2.10 or greater. */
174 if (cfgmech == CFGMECH_PCIE)
178 * Grope around in the PCI config space to see if this is a
179 * chipset that is capable of doing memory-mapped config cycles.
180 * This also implies that it can do PCIe extended config cycles.
183 /* Check for supported chipsets */
184 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
185 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
191 /* Intel 7520 or 7320 */
192 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
193 pcie_cfgregopen(pciebar, 0, 255);
198 /* Intel 915, 925, or 915GM */
199 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
200 pcie_cfgregopen(pciebar, 0, 255);
210 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
213 if (cfgmech == CFGMECH_PCIE &&
214 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
215 (bus != 0 || !(1 << slot & pcie_badslots)))
216 return (pciereg_cfgread(bus, slot, func, reg, bytes));
218 return (pcireg_cfgread(bus, slot, func, reg, bytes));
222 * Read configuration space register
225 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
230 * Some BIOS writers seem to want to ignore the spec and put
231 * 0 in the intline rather than 255 to indicate none. The rest of
232 * the code uses 255 as an invalid IRQ.
234 if (reg == PCIR_INTLINE && bytes == 1) {
235 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
236 return (pci_i386_map_intline(line));
238 return (pci_docfgregread(bus, slot, func, reg, bytes));
242 * Write configuration space register
245 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
248 if (cfgmech == CFGMECH_PCIE &&
249 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
250 (bus != 0 || !(1 << slot & pcie_badslots)))
251 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
253 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
257 * Configuration space access using direct register operations
260 /* enable configuration space accesses and return data port address */
262 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
267 if (arch_i386_is_xbox) {
269 * The Xbox MCPX chipset is a derivative of the nForce 1
270 * chipset. It almost has the same bus layout; some devices
271 * cannot be used, because they have been removed.
275 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
276 * the nForce chipset, but on the Xbox, using them will lockup
279 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
283 * Bus 1 only contains a VGA controller at 01:00.0. When you try
284 * to probe beyond that device, you only get garbage, which
285 * could cause lockups.
287 if (bus == 1 && (slot != 0 || func != 0))
291 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
292 * doesn't have one. Probing it can cause lockups.
299 if (bus <= PCI_BUSMAX
301 && func <= PCI_FUNCMAX
302 && (unsigned)reg <= PCI_REGMAX
304 && (unsigned)bytes <= 4
305 && (reg & (bytes - 1)) == 0) {
309 outl(CONF1_ADDR_PORT, (1 << 31)
310 | (bus << 16) | (slot << 11)
311 | (func << 8) | (reg & ~0x03));
312 dataport = CONF1_DATA_PORT + (reg & 0x03);
315 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
316 outb(CONF2_FORWARD_PORT, bus);
317 dataport = 0xc000 | (slot << 8) | reg;
324 /* disable configuration space accesses */
332 * Do nothing for the config mechanism 1 case.
333 * Writing a 0 to the address port can apparently
334 * confuse some bridges and cause spurious
339 outb(CONF2_ENABLE_PORT, 0);
345 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
350 mtx_lock_spin(&pcicfg_mtx);
351 port = pci_cfgenable(bus, slot, func, reg, bytes);
366 mtx_unlock_spin(&pcicfg_mtx);
371 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
375 mtx_lock_spin(&pcicfg_mtx);
376 port = pci_cfgenable(bus, slot, func, reg, bytes);
391 mtx_unlock_spin(&pcicfg_mtx);
395 /* check whether the configuration mechanism has been correctly identified */
397 pci_cfgcheck(int maxdev)
405 printf("pci_cfgcheck:\tdevice ");
407 for (device = 0; device < maxdev; device++) {
409 printf("%d ", device);
411 port = pci_cfgenable(0, device, 0, 0, 4);
413 if (id == 0 || id == 0xffffffff)
416 port = pci_cfgenable(0, device, 0, 8, 4);
417 class = inl(port) >> 8;
419 printf("[class=%06x] ", class);
420 if (class == 0 || (class & 0xf870ff) != 0)
423 port = pci_cfgenable(0, device, 0, 14, 1);
426 printf("[hdr=%02x] ", header);
427 if ((header & 0x7e) != 0)
431 printf("is there (id=%08x)\n", id);
437 printf("-- nothing found\n");
446 uint32_t mode1res, oldval1;
447 uint8_t mode2res, oldval2;
449 /* Check for type #1 first. */
450 oldval1 = inl(CONF1_ADDR_PORT);
453 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
460 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
462 mode1res = inl(CONF1_ADDR_PORT);
463 outl(CONF1_ADDR_PORT, oldval1);
466 printf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
470 if (pci_cfgcheck(32))
474 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
475 mode1res = inl(CONF1_ADDR_PORT);
476 outl(CONF1_ADDR_PORT, oldval1);
479 printf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
482 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
483 if (pci_cfgcheck(32))
487 /* Type #1 didn't work, so try type #2. */
488 oldval2 = inb(CONF2_ENABLE_PORT);
491 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
495 if ((oldval2 & 0xf0) == 0) {
500 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
501 mode2res = inb(CONF2_ENABLE_PORT);
502 outb(CONF2_ENABLE_PORT, oldval2);
505 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
506 mode2res, CONF2_ENABLE_CHK);
508 if (mode2res == CONF2_ENABLE_RES) {
510 printf("pci_open(2a):\tnow trying mechanism 2\n");
512 if (pci_cfgcheck(16))
517 /* Nothing worked, so punt. */
518 cfgmech = CFGMECH_NONE;
524 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
526 struct pcie_cfg_list *pcielist;
527 struct pcie_cfg_elem *pcie_array, *elem;
542 if (base >= 0x100000000) {
545 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
552 printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
556 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
560 pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
562 if (pcie_array == NULL)
565 va = kmem_alloc_nofault(kernel_map, PCIE_CACHE * PAGE_SIZE);
567 free(pcie_array, M_DEVBUF);
572 pcielist = &pcie_list[pc->pc_cpuid];
574 pcielist = &pcie_list[0];
576 TAILQ_INIT(pcielist);
577 for (i = 0; i < PCIE_CACHE; i++) {
578 elem = &pcie_array[i];
579 elem->vapage = va + (i * PAGE_SIZE);
581 TAILQ_INSERT_HEAD(pcielist, elem, elem);
586 pcie_minbus = minbus;
587 pcie_maxbus = maxbus;
588 cfgmech = CFGMECH_PCIE;
592 * On some AMD systems, some of the devices on bus 0 are
593 * inaccessible using memory-mapped PCI config access. Walk
594 * bus 0 looking for such devices. For these devices, we will
595 * fall back to using type 1 config access instead.
597 if (pci_cfgregopen() != 0) {
598 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
599 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
600 if (val1 == 0xffffffff)
603 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
605 pcie_badslots |= (1 << slot);
613 #define PCIE_PADDR(bar, reg, bus, slot, func) \
615 (((bus) & 0xff) << 20) | \
616 (((slot) & 0x1f) << 15) | \
617 (((func) & 0x7) << 12) | \
621 * Find an element in the cache that matches the physical page desired, or
622 * create a new mapping from the least recently used element.
623 * A very simple LRU algorithm is used here, does it need to be more
626 static __inline struct pcie_cfg_elem *
627 pciereg_findelem(vm_paddr_t papage)
629 struct pcie_cfg_list *pcielist;
630 struct pcie_cfg_elem *elem;
632 pcielist = &pcie_list[PCPU_GET(cpuid)];
633 TAILQ_FOREACH(elem, pcielist, elem) {
634 if (elem->papage == papage)
639 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
640 if (elem->papage != 0) {
641 pmap_kremove(elem->vapage);
642 invlpg(elem->vapage);
644 pmap_kenter(elem->vapage, papage);
645 elem->papage = papage;
648 if (elem != TAILQ_FIRST(pcielist)) {
649 TAILQ_REMOVE(pcielist, elem, elem);
650 TAILQ_INSERT_HEAD(pcielist, elem, elem);
656 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
659 struct pcie_cfg_elem *elem;
660 volatile vm_offset_t va;
661 vm_paddr_t pa, papage;
664 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
665 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
669 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
670 papage = pa & ~PAGE_MASK;
671 elem = pciereg_findelem(papage);
672 va = elem->vapage | (pa & PAGE_MASK);
676 data = *(volatile uint32_t *)(va);
679 data = *(volatile uint16_t *)(va);
682 data = *(volatile uint8_t *)(va);
691 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
694 struct pcie_cfg_elem *elem;
695 volatile vm_offset_t va;
696 vm_paddr_t pa, papage;
698 if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
699 func > PCI_FUNCMAX || reg > PCIE_REGMAX)
703 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
704 papage = pa & ~PAGE_MASK;
705 elem = pciereg_findelem(papage);
706 va = elem->vapage | (pa & PAGE_MASK);
710 *(volatile uint32_t *)(va) = data;
713 *(volatile uint16_t *)(va) = data;
716 *(volatile uint8_t *)(va) = data;