sys/ia64/ia64/exception.S

   1 /*-
   2  * Copyright (c) 2003,2004 Marcel Moolenaar
   3  * Copyright (c) 2000 Doug Rabson
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <machine/asm.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <opt_xtrace.h>
  32
  33 #include <machine/pte.h>
  34 #include <assym.s>
  35
  36 /*
  37  * ar.k7 = kernel memory stack
  38  * ar.k6 = kernel register stack
  39  * ar.k5 = EPC gateway page
  40  * ar.k4 = PCPU data
  41  */
  42
  43 #ifdef EXCEPTION_TRACING
  44
  45         .data
  46         .global xtrace, xhead
  47 xtrace: .space  1024*5*8
  48 xhead:  data8   xtrace
  49
  50 #define XTRACE(offset)                          \
  51 {       .mmi ;                                  \
  52         mov     r24=ar.itc ;                    \
  53         mov     r25=cr.iip ;                    \
  54         mov     r27=offset ;                    \
  55 } ;                                             \
  56 {       .mlx ;                                  \
  57         mov     r28=cr.ifa ;                    \
  58         movl    r29=xhead ;;                    \
  59 } ;                                             \
  60 {       .mmi ;                                  \
  61         ld8     r29=[r29] ;;                    \
  62         st8     [r29]=r24,8 ;                   \
  63         nop     0 ;;                            \
  64 } ;                                             \
  65 {       .mmi ;                                  \
  66         st8     [r29]=r27,8 ;;                  \
  67         mov     r24=cr.isr ;                    \
  68         add     r27=8,r29 ;;                    \
  69 } ;                                             \
  70 {       .mmi ;                                  \
  71         st8     [r29]=r25,16 ;;                 \
  72         st8     [r27]=r28,16 ;                  \
  73         mov     r25=pr ;;                       \
  74 } ;                                             \
  75 {       .mlx ;                                  \
  76         st8     [r29]=r24 ;                     \
  77         movl    r28=xhead ;;                    \
  78 } ;                                             \
  79 {       .mii ;                                  \
  80         cmp.eq  p15,p0=r27,r28 ;                \
  81         addl    r29=1024*5*8,r0 ;;              \
  82 (p15)   sub     r27=r28,r29 ;;                  \
  83 } ;                                             \
  84 {       .mib ;                                  \
  85         st8     [r28]=r27 ;                     \
  86         mov     pr=r25,0x1ffff ;                \
  87         nop     0 ;;                            \
  88 }
  89
  90 #else
  91
  92 #define XTRACE(offset)
  93
  94 #endif
  95
  96         .text
  97
  98 /*
  99  * exception_save: save interrupted state
 100  *
 101  * Arguments:
 102  *      r16     address of bundle that contains the branch. The
 103  *              return address will be the next bundle.
 104  *      r17     the value to save as ifa in the trapframe. This
 105  *              normally is cr.ifa, but some interruptions set
 106  *              set cr.iim and not cr.ifa.
 107  *
 108  * Returns:
 109  *      p15     interrupted from user stack
 110  *      p14     interrupted from kernel stack
 111  *      p13     interrupted from user backing store
 112  *      p12     interrupted from kernel backing store
 113  *      p11     interrupts were enabled
 114  *      p10     interrupts were disabled
 115  */
 116 ENTRY_NOPROFILE(exception_save, 0)
 117 {       .mii
 118         mov             r20=ar.unat
 119         extr.u          r31=sp,61,3
 120         mov             r18=pr
 121         ;;
 122 }
 123 {       .mmi
 124         cmp.le          p14,p15=5,r31
 125         ;;
 126 (p15)   mov             r23=ar.k7               // kernel memory stack
 127 (p14)   mov             r23=sp
 128         ;;
 129 }
 130 {       .mii
 131         mov             r21=ar.rsc
 132         add             r30=-SIZEOF_TRAPFRAME,r23
 133         ;;
 134         dep             r30=0,r30,0,10
 135         ;;
 136 }
 137 {       .mmi
 138         mov             ar.rsc=0
 139         sub             r19=r23,r30
 140         add             r31=8,r30
 141         ;;
 142 }
 143 {       .mlx
 144         mov             r22=cr.iip
 145         movl            r26=exception_save_restart
 146         ;;
 147 }
 148
 149         /*
 150          * We have a 1KB aligned trapframe, pointed to by sp. If we write
 151          * to the trapframe, we may trigger a data nested TLB fault. By
 152          * aligning the trapframe on a 1KB boundary, we guarantee that if
 153          * we get a data nested TLB fault, it will be on the very first
 154          * write. Since the data nested TLB fault does not preserve any
 155          * state, we have to be careful what we clobber. Consequently, we
 156          * have to be careful what we use here. Below a list of registers
 157          * that are currently alive:
 158          *      r16,r17=arguments
 159          *      r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS
 160          *      r26=restart point
 161          *      r30,r31=trapframe pointers
 162          *      p14,p15=memory stack switch
 163          */
 164 exception_save_restart:
 165 {       .mmi
 166         st8             [r30]=r19,16            // length
 167         st8             [r31]=r0,16             // flags
 168         add             r19=16,r19
 169         ;;
 170 }
 171 {       .mmi
 172         st8.spill       [r30]=sp,16             // sp
 173         st8             [r31]=r20,16            // unat
 174         sub             sp=r23,r19
 175         ;;
 176 }
 177 {       .mmi
 178         mov             r19=ar.rnat
 179         mov             r20=ar.bspstore
 180         mov             r23=rp
 181         ;;
 182 }
 183         // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp
 184 {       .mmi
 185         st8             [r30]=r23,16            // rp
 186         st8             [r31]=r18,16            // pr
 187         mov             r24=ar.pfs
 188         ;;
 189 }
 190 {       .mmb
 191         st8             [r30]=r24,16            // pfs
 192         st8             [r31]=r20,16            // bspstore
 193         cover
 194         ;;
 195 }
 196 {       .mmi
 197         mov             r18=ar.fpsr
 198         mov             r23=cr.ipsr
 199         extr.u          r24=r20,61,3
 200         ;;
 201 }
 202         // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr
 203 {       .mmi
 204         st8             [r30]=r19,16            // rnat
 205         st8             [r31]=r0,16             // __spare
 206         cmp.le          p12,p13=5,r24
 207         ;;
 208 }
 209 {       .mmi
 210         st8.spill       [r30]=r13,16            // tp
 211         st8             [r31]=r21,16            // rsc
 212         tbit.nz         p11,p10=r23,14          // p11=interrupts enabled
 213         ;;
 214 }
 215 {       .mmi
 216 (p13)   mov             r21=ar.k6               // kernel register stack
 217         ;;
 218         st8             [r30]=r18,16            // fpsr
 219 (p13)   dep             r20=r20,r21,0,9         // align dirty registers
 220         ;;
 221 }
 222         // r19=rnat, r20=bspstore, r22=iip, r23=ipsr
 223 {       .mmi
 224         st8             [r31]=r23,16            // psr
 225 (p13)   mov             ar.bspstore=r20
 226         nop             0
 227         ;;
 228 }
 229 {       .mmb
 230 (p13)   mov             ar.rnat=r19
 231         mov             r18=ar.bsp
 232         nop             0
 233         ;;
 234 }
 235 {       .mmi
 236         mov             r19=cr.ifs
 237         st8.spill       [r30]=gp,16             // gp
 238         sub             r18=r18,r20
 239         ;;
 240 }
 241         // r19=ifs, r22=iip
 242 {       .mmb
 243         st8             [r31]=r18,16            // ndirty
 244         st8             [r30]=r19,16            // cfm
 245         nop             0
 246         ;;
 247 }
 248 {       .mmi
 249         mov             r18=cr.isr
 250         st8             [r31]=r22,16            // iip
 251         add             r29=16,r30
 252         ;;
 253 }
 254 {       .mmb
 255         st8             [r30]=r17,24            // ifa
 256         st8             [r31]=r18,24            // isr
 257         nop             0
 258         ;;
 259 }
 260 {       .mmi
 261         .mem.offset     0,0
 262         st8.spill       [r30]=r2,16             // r2
 263         .mem.offset     8,0
 264         st8.spill       [r31]=r3,16             // r3
 265         add             r2=9*8,r29
 266         ;;
 267 }
 268 {       .mmi
 269         .mem.offset     0,0
 270         st8.spill       [r30]=r8,16             // r8
 271         .mem.offset     8,0
 272         st8.spill       [r31]=r9,16             // r9
 273         add             r3=8,r2
 274         ;;
 275 }
 276 {       .mmi
 277         .mem.offset     0,0
 278         st8.spill       [r30]=r10,16            // r10
 279         .mem.offset     8,0
 280         st8.spill       [r31]=r11,16            // r11
 281         add             r8=16,r16
 282         ;;
 283 }
 284 {       .mmi
 285         .mem.offset     0,0
 286         st8.spill       [r30]=r14               // r14
 287         .mem.offset     8,0
 288         st8.spill       [r31]=r15               // r15
 289         mov             r9=r29
 290 }
 291 {       .mmb
 292         mov             r10=ar.csd
 293         mov             r11=ar.ssd
 294         bsw.1
 295         ;;
 296 }
 297 {       .mmi
 298         .mem.offset     0,0
 299         st8.spill       [r2]=r16,16             // r16
 300         .mem.offset     8,0
 301         st8.spill       [r3]=r17,16             // r17
 302         mov             r14=b6
 303         ;;
 304 }
 305 {       .mmi
 306         .mem.offset     0,0
 307         st8.spill       [r2]=r18,16             // r18
 308         .mem.offset     8,0
 309         st8.spill       [r3]=r19,16             // r19
 310         mov             r15=b7
 311         ;;
 312 }
 313 {       .mmi
 314         .mem.offset     0,0
 315         st8.spill       [r2]=r20,16             // r20
 316         .mem.offset     8,0
 317         st8.spill       [r3]=r21,16             // r21
 318         mov             b7=r8
 319         ;;
 320 }
 321 {       .mmi
 322         .mem.offset     0,0
 323         st8.spill       [r2]=r22,16             // r22
 324         .mem.offset     8,0
 325         st8.spill       [r3]=r23,16             // r23
 326         ;;
 327 }
 328
 329         .mem.offset     0,0
 330         st8.spill       [r2]=r24,16             // r24
 331         .mem.offset     8,0
 332         st8.spill       [r3]=r25,16             // r25
 333         ;;
 334         .mem.offset     0,0
 335         st8.spill       [r2]=r26,16             // r26
 336         .mem.offset     8,0
 337         st8.spill       [r3]=r27,16             // r27
 338         ;;
 339         .mem.offset     0,0
 340         st8.spill       [r2]=r28,16             // r28
 341         .mem.offset     8,0
 342         st8.spill       [r3]=r29,16             // r29
 343         ;;
 344         .mem.offset     0,0
 345         st8.spill       [r2]=r30,16             // r30
 346         .mem.offset     8,0
 347         st8.spill       [r3]=r31,16             // r31
 348         ;;
 349
 350 {       .mmi
 351         st8             [r2]=r14,16             // b6
 352         mov             r17=ar.unat
 353         nop             0
 354         ;;
 355 }
 356 {       .mmi
 357         st8             [r3]=r15,16             // b7
 358         mov             r16=ar.ccv
 359         nop             0
 360         ;;
 361 }
 362 {       .mmi
 363         st8             [r2]=r16,16             // ccv
 364         st8             [r3]=r10,16             // csd
 365         nop             0
 366         ;;
 367 }
 368 {       .mmi
 369         st8             [r2]=r11,24             // ssd
 370         st8             [r9]=r17
 371         nop             0
 372         ;;
 373 }
 374
 375         stf.spill       [r3]=f6,32              // f6
 376         stf.spill       [r2]=f7,32              // f7
 377         ;;
 378         stf.spill       [r3]=f8,32              // f8
 379         stf.spill       [r2]=f9,32              // f9
 380         ;;
 381         stf.spill       [r3]=f10,32             // f10
 382         stf.spill       [r2]=f11,32             // f11
 383         ;;
 384         stf.spill       [r3]=f12,32             // f12
 385         stf.spill       [r2]=f13,32             // f13
 386         ;;
 387         stf.spill       [r3]=f14                // f14
 388         stf.spill       [r2]=f15                // f15
 389         ;;
 390 {       .mmi
 391         mov             ar.rsc=3
 392         mov             r13=ar.k4
 393         nop             0
 394         ;;
 395 }
 396 {       .mlx
 397         ssm             psr.ic|psr.dfh
 398         movl            gp=__gp
 399         ;;
 400 }
 401 {       .mfb
 402         srlz.d
 403         nop             0
 404         br.sptk         b7
 405         ;;
 406 }
 407 END(exception_save)
 408
 409 /*
 410  * exception_restore:   restore interrupted state
 411  *
 412  * Arguments:
 413  *      sp+16   trapframe pointer
 414  */
 415 ENTRY_NOPROFILE(exception_restore, 0)
 416 {       .mmi
 417         rsm             psr.i
 418         add             r3=SIZEOF_TRAPFRAME-16,sp
 419         add             r2=SIZEOF_TRAPFRAME,sp
 420         ;;
 421 }
 422 {       .mmi
 423         srlz.d
 424         add             r8=SIZEOF_SPECIAL+32,sp
 425         nop             0
 426         ;;
 427 }
 428         // The next load can trap. Let it be...
 429         ldf.fill        f15=[r2],-32            // f15
 430         ldf.fill        f14=[r3],-32            // f14
 431         add             sp=16,sp
 432         ;;
 433         ldf.fill        f13=[r2],-32            // f13
 434         ldf.fill        f12=[r3],-32            // f12
 435         ;;
 436         ldf.fill        f11=[r2],-32            // f11
 437         ldf.fill        f10=[r3],-32            // f10
 438         ;;
 439         ldf.fill        f9=[r2],-32             // f9
 440         ldf.fill        f8=[r3],-32             // f8
 441         ;;
 442         ldf.fill        f7=[r2],-24             // f7
 443         ldf.fill        f6=[r3],-16             // f6
 444         ;;
 445
 446 {       .mmi
 447         ld8             r8=[r8]                 // unat (after)
 448         ;;
 449         mov             ar.unat=r8
 450         nop             0
 451         ;;
 452 }
 453
 454         ld8             r10=[r2],-16            // ssd
 455         ld8             r11=[r3],-16            // csd
 456         ;;
 457         mov             ar.ssd=r10
 458         mov             ar.csd=r11
 459
 460         ld8             r14=[r2],-16            // ccv
 461         ld8             r15=[r3],-16            // b7
 462         ;;
 463
 464 {       .mmi
 465         mov             ar.ccv=r14
 466         ld8             r8=[r2],-16             // b6
 467         mov             b7=r15
 468         ;;
 469 }
 470 {       .mmi
 471         ld8.fill        r31=[r3],-16            // r31
 472         ld8.fill        r30=[r2],-16            // r30
 473         mov             b6=r8
 474         ;;
 475 }
 476
 477         ld8.fill        r29=[r3],-16            // r29
 478         ld8.fill        r28=[r2],-16            // r28
 479         ;;
 480         ld8.fill        r27=[r3],-16            // r27
 481         ld8.fill        r26=[r2],-16            // r26
 482         ;;
 483         ld8.fill        r25=[r3],-16            // r25
 484         ld8.fill        r24=[r2],-16            // r24
 485         ;;
 486         ld8.fill        r23=[r3],-16            // r23
 487         ld8.fill        r22=[r2],-16            // r22
 488         ;;
 489         ld8.fill        r21=[r3],-16            // r21
 490         ld8.fill        r20=[r2],-16            // r20
 491         ;;
 492         ld8.fill        r19=[r3],-16            // r19
 493         ld8.fill        r18=[r2],-16            // r18
 494         ;;
 495
 496 {       .mmb
 497         ld8.fill        r17=[r3],-16            // r17
 498         ld8.fill        r16=[r2],-16            // r16
 499         bsw.0
 500         ;;
 501 }
 502 {       .mmi
 503         ld8.fill        r15=[r3],-16            // r15
 504         ld8.fill        r14=[r2],-16            // r14
 505         add             r31=16,sp
 506         ;;
 507 }
 508 {       .mmi
 509         ld8             r16=[sp]                // tf_length
 510         ld8.fill        r11=[r3],-16            // r11
 511         add             r30=24,sp
 512         ;;
 513 }
 514 {       .mmi
 515         ld8.fill        r10=[r2],-16            // r10
 516         ld8.fill        r9=[r3],-16             // r9
 517         add             r16=r16,sp              // ar.k7
 518         ;;
 519 }
 520 {       .mmi
 521         ld8.fill        r8=[r2],-16             // r8
 522         ld8.fill        r3=[r3]                 // r3
 523         ;;
 524 }
 525         // We want nested TLB faults from here on...
 526         rsm             psr.ic|psr.i
 527         ld8.fill        r2=[r2]                 // r2
 528         nop             0
 529         ;;
 530         srlz.d
 531         ld8.fill        sp=[r31],16             // sp
 532         nop             0
 533         ;;
 534
 535         ld8             r17=[r30],16            // unat
 536         ld8             r29=[r31],16            // rp
 537         ;;
 538         ld8             r18=[r30],16            // pr
 539         ld8             r28=[r31],16            // pfs
 540         mov             rp=r29
 541         ;;
 542         ld8             r20=[r30],24            // bspstore
 543         ld8             r21=[r31],24            // rnat
 544         mov             ar.pfs=r28
 545         ;;
 546         ld8.fill        r29=[r30],16            // tp
 547         ld8             r22=[r31],16            // rsc
 548         ;;
 549 {       .mmi
 550         ld8             r23=[r30],16            // fpsr
 551         ld8             r24=[r31],16            // psr
 552         extr.u          r28=r20,61,3
 553         ;;
 554 }
 555 {       .mmi
 556         ld8.fill        r1=[r30],16             // gp
 557         ld8             r25=[r31],16            // ndirty
 558         cmp.le          p14,p15=5,r28
 559         ;;
 560 }
 561 {       .mmb
 562         ld8             r26=[r30]               // cfm
 563         ld8             r19=[r31]               // ip
 564         nop             0
 565         ;;
 566 }
 567 {       .mib
 568         // Switch register stack
 569         alloc           r30=ar.pfs,0,0,0,0      // discard current frame
 570         shl             r31=r25,16              // value for ar.rsc
 571         nop             0
 572         ;;
 573 }
 574         // The loadrs can fault if the backing store is not currently
 575         // mapped. We assured forward progress by getting everything we
 576         // need from the trapframe so that we don't care if the CPU
 577         // purges that translation when it needs to insert a new one for
 578         // the backing store.
 579 {       .mmi
 580         mov             ar.rsc=r31              // setup for loadrs
 581         mov             ar.k7=r16
 582 (p15)   mov             r13=r29
 583         ;;
 584 }
 585 exception_restore_restart:
 586 {       .mmi
 587         mov             r30=ar.bspstore
 588         ;;
 589         loadrs                                  // load user regs
 590         nop             0
 591         ;;
 592 }
 593 {       .mmi
 594         mov             r31=ar.bspstore
 595         ;;
 596         mov             ar.bspstore=r20
 597         dep             r31=0,r31,0,13          // 8KB aligned
 598         ;;
 599 }
 600 {       .mmb
 601         mov             ar.k6=r31
 602         mov             ar.rnat=r21
 603         nop             0
 604         ;;
 605 }
 606 {       .mmb
 607         mov             ar.unat=r17
 608         mov             cr.iip=r19
 609         nop             0
 610 }
 611 {       .mmi
 612         mov             cr.ipsr=r24
 613         mov             cr.ifs=r26
 614         mov             pr=r18,0x1ffff
 615         ;;
 616 }
 617 {       .mmb
 618         mov             ar.rsc=r22
 619         mov             ar.fpsr=r23
 620         rfi
 621         ;;
 622 }
 623 END(exception_restore)
 624
 625 /*
 626  * Call exception_save_regs to preserve the interrupted state in a
 627  * trapframe. Note that we don't use a call instruction because we
 628  * must be careful not to lose track of the RSE state. We then call
 629  * trap() with the value of _n_ as an argument to handle the
 630  * exception. We arrange for trap() to return to exception_restore
 631  * which will restore the interrupted state before executing an rfi to
 632  * resume it.
 633  */
 634 #define CALL(_func_, _n_, _ifa_)                \
 635 {       .mib ;                                  \
 636         mov             r17=_ifa_ ;             \
 637         mov             r16=ip ;                \
 638         br.sptk         exception_save ;;       \
 639 } ;                                             \
 640 {       .mmi ;                                  \
 641         alloc           r15=ar.pfs,0,0,2,0 ;;   \
 642 (p11)   ssm             psr.i ;                 \
 643         mov             out0=_n_ ;;             \
 644 } ;                                             \
 645 {       .mib ;                                  \
 646 (p11)   srlz.d ;                                \
 647         add             out1=16,sp ;            \
 648         br.call.sptk    rp=_func_ ;;            \
 649 } ;                                             \
 650 {       .mfb ;                                  \
 651         nop             0 ;                     \
 652         nop             0 ;                     \
 653         br.sptk         exception_restore ;;    \
 654 }
 655
 656 #define IVT_ENTRY(name, offset)                 \
 657         .org    ia64_vector_table + offset;     \
 658         .global ivt_##name;                     \
 659         .proc   ivt_##name;                     \
 660         .prologue;                              \
 661         .unwabi @svr4, 'I';                     \
 662         .save   rp, r0;                         \
 663         .body;                                  \
 664 ivt_##name:                                     \
 665         XTRACE(offset)
 666
 667 #define IVT_END(name)                           \
 668         .endp   ivt_##name
 669
 670 #ifdef COMPAT_IA32
 671 #define IA32_TRAP       ia32_trap
 672 #else
 673 #define IA32_TRAP       trap
 674 #endif
 675
 676 /*
 677  * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64
 678  * bundles per vector and 48 slots with 16 bundles per vector.
 679  */
 680
 681         .section .text.ivt,"ax"
 682
 683         .align  32768
 684         .global ia64_vector_table
 685         .size   ia64_vector_table, 32768
 686 ia64_vector_table:
 687
 688 IVT_ENTRY(VHPT_Translation, 0x0000)
 689         CALL(trap, 0, cr.ifa)
 690 IVT_END(VHPT_Translation)
 691
 692 IVT_ENTRY(Instruction_TLB, 0x0400)
 693         mov     r16=cr.ifa
 694         mov     r17=pr
 695         ;;
 696         thash   r18=r16
 697         ttag    r19=r16
 698         ;;
 699         add     r21=16,r18              // tag
 700         add     r20=24,r18              // collision chain
 701         ;;
 702         ld8     r21=[r21]               // check VHPT tag
 703         ld8     r20=[r20]               // bucket head
 704         ;;
 705         cmp.ne  p15,p0=r21,r19
 706 (p15)   br.dpnt.few 1f
 707         ;;
 708         ld8     r21=[r18]               // read pte
 709         ;;
 710         itc.i   r21                     // insert pte
 711         mov     pr=r17,0x1ffff
 712         ;;
 713         rfi                             // done
 714         ;;
 715 1:      rsm     psr.dt                  // turn off data translations
 716         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 717         ;;
 718         srlz.d                          // serialize
 719         ld8     r20=[r20]               // first entry
 720         ;;
 721 2:      cmp.eq  p15,p0=r0,r20           // done?
 722 (p15)   br.cond.spnt.few 9f             // bail if done
 723         ;;
 724         add     r21=16,r20              // tag location
 725         ;;
 726         ld8     r21=[r21]               // read tag
 727         ;;
 728         cmp.ne  p15,p0=r21,r19          // compare tags
 729 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 730         ;;
 731         ld8     r21=[r20]               // read pte
 732         mov     r22=PTE_ACCESSED
 733         ;;
 734         or      r21=r21,r22
 735         ;;
 736         st8     [r20]=r21,8
 737         ;;
 738         ld8     r22=[r20]               // read rest of pte
 739         ;;
 740         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 741         ;;
 742         add     r20=16,r18              // address of tag
 743         ;;
 744         ld8.acq r23=[r20]               // read old tag
 745         ;;
 746         dep     r23=-1,r23,63,1         // set ti bit
 747         ;;
 748         st8.rel [r20]=r23               // store old tag + ti
 749         ;;
 750         mf                              // make sure everyone sees
 751         ;;
 752         st8     [r18]=r21,8             // store pte
 753         ;;
 754         st8     [r18]=r22,8
 755         ;;
 756         st8.rel [r18]=r19               // store new tag
 757         ;;
 758         itc.i   r21                     // and place in TLB
 759         ssm     psr.dt
 760         ;;
 761         srlz.d
 762         mov     pr=r17,0x1ffff          // restore predicates
 763         rfi
 764         ;;
 765 3:      add     r20=24,r20              // next in chain
 766         ;;
 767         ld8     r20=[r20]               // read chain
 768         br.cond.sptk.few 2b             // loop
 769         ;;
 770 9:      ssm     psr.dt
 771         mov     pr=r17,0x1ffff          // restore predicates
 772         ;;
 773         srlz.d
 774         ;;
 775         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 776 IVT_END(Instruction_TLB)
 777
 778 IVT_ENTRY(Data_TLB, 0x0800)
 779         mov     r16=cr.ifa
 780         mov     r17=pr
 781         ;;
 782         thash   r18=r16
 783         ttag    r19=r16
 784         ;;
 785         add     r21=16,r18              // tag
 786         add     r20=24,r18              // collision chain
 787         ;;
 788         ld8     r21=[r21]               // check VHPT tag
 789         ld8     r20=[r20]               // bucket head
 790         ;;
 791         cmp.ne  p15,p0=r21,r19
 792 (p15)   br.dpnt.few 1f
 793         ;;
 794         ld8     r21=[r18]               // read pte
 795         ;;
 796         itc.d   r21                     // insert pte
 797         mov     pr=r17,0x1ffff
 798         ;;
 799         rfi                             // done
 800         ;;
 801 1:      rsm     psr.dt                  // turn off data translations
 802         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
 803         ;;
 804         srlz.d                          // serialize
 805         ld8     r20=[r20]               // first entry
 806         ;;
 807 2:      cmp.eq  p15,p0=r0,r20           // done?
 808 (p15)   br.cond.spnt.few 9f             // bail if done
 809         ;;
 810         add     r21=16,r20              // tag location
 811         ;;
 812         ld8     r21=[r21]               // read tag
 813         ;;
 814         cmp.ne  p15,p0=r21,r19          // compare tags
 815 (p15)   br.cond.sptk.few 3f             // if not, read next in chain
 816         ;;
 817         ld8     r21=[r20]               // read pte
 818         mov     r22=PTE_ACCESSED
 819         ;;
 820         or      r21=r21,r22
 821         ;;
 822         st8     [r20]=r21,8
 823         ;;
 824         ld8     r22=[r20]               // read rest of pte
 825         ;;
 826         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
 827         ;;
 828         add     r20=16,r18              // address of tag
 829         ;;
 830         ld8.acq r23=[r20]               // read old tag
 831         ;;
 832         dep     r23=-1,r23,63,1         // set ti bit
 833         ;;
 834         st8.rel [r20]=r23               // store old tag + ti
 835         ;;
 836         mf                              // make sure everyone sees
 837         ;;
 838         st8     [r18]=r21,8             // store pte
 839         ;;
 840         st8     [r18]=r22,8
 841         ;;
 842         st8.rel [r18]=r19               // store new tag
 843         ;;
 844         itc.d   r21                     // and place in TLB
 845         ssm     psr.dt
 846         ;;
 847         srlz.d
 848         mov     pr=r17,0x1ffff          // restore predicates
 849         rfi
 850         ;;
 851 3:      add     r20=24,r20              // next in chain
 852         ;;
 853         ld8     r20=[r20]               // read chain
 854         br.cond.sptk.few 2b             // loop
 855         ;;
 856 9:      ssm     psr.dt
 857         mov     pr=r17,0x1ffff          // restore predicates
 858         ;;
 859         srlz.d
 860         ;;
 861         CALL(trap, 20, cr.ifa)          // Page Not Present trap
 862 IVT_END(Data_TLB)
 863
 864 IVT_ENTRY(Alternate_Instruction_TLB, 0x0c00)
 865         mov     r16=cr.ifa              // where did it happen
 866         mov     r18=pr                  // save predicates
 867         ;;
 868         extr.u  r17=r16,61,3            // get region number
 869         ;;
 870         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 871         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 872 (p13)   br.spnt 9f
 873         ;;
 874 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 875                         PTE_AR_RX+PTE_ED
 876 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 877                         PTE_AR_RX
 878         ;;
 879         dep     r16=0,r16,50,14         // clear bits above PPN
 880         ;;
 881         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 882         ;;
 883         itc.i   r16
 884         mov     pr=r18,0x1ffff          // restore predicates
 885         ;;
 886         rfi
 887         ;;
 888 9:      mov     pr=r18,0x1ffff          // restore predicates
 889         CALL(trap, 3, cr.ifa)
 890 IVT_END(Alternate_Instruction_TLB)
 891
 892 IVT_ENTRY(Alternate_Data_TLB, 0x1000)
 893         mov     r16=cr.ifa              // where did it happen
 894         mov     r18=pr                  // save predicates
 895         ;;
 896         extr.u  r17=r16,61,3            // get region number
 897         ;;
 898         cmp.ge  p13,p0=5,r17            // RR0-RR5?
 899         cmp.eq  p15,p14=7,r17           // RR7->p15, RR6->p14
 900 (p13)   br.spnt 9f
 901         ;;
 902 (p15)   movl    r17=PTE_PRESENT+PTE_MA_WB+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 903                         PTE_AR_RW+PTE_ED
 904 (p14)   movl    r17=PTE_PRESENT+PTE_MA_UC+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+ \
 905                         PTE_AR_RW
 906         ;;
 907         dep     r16=0,r16,50,14         // clear bits above PPN
 908         ;;
 909         dep     r16=r17,r16,0,12        // put pte bits in 0..11
 910         ;;
 911         itc.d   r16
 912         mov     pr=r18,0x1ffff          // restore predicates
 913         ;;
 914         rfi
 915         ;;
 916 9:      mov     pr=r18,0x1ffff          // restore predicates
 917         CALL(trap, 4, cr.ifa)
 918 IVT_END(Alternate_Data_TLB)
 919
 920 IVT_ENTRY(Data_Nested_TLB, 0x1400)
 921         // See exception_save_restart and exception_restore_restart for the
 922         // contexts that may cause a data nested TLB. We can only use the
 923         // banked general registers and predicates, but don't use:
 924         //      p14 & p15       -       Set in exception save
 925         //      r16 & r17       -       Arguments to exception save
 926         //      r30             -       Faulting address (modulo page size)
 927         // We assume r30 has the virtual addresses that relate to the data
 928         // nested TLB fault. The address does not have to be exact, as long
 929         // as it's in the same page. We use physical addressing to avoid
 930         // double nested faults. Since all virtual addresses we encounter
 931         // here are direct mapped region 7 addresses, we have no problem
 932         // constructing physical addresses.
 933 {       .mlx
 934         rsm             psr.dt
 935         movl            r27=ia64_kptdir
 936         ;;
 937 }
 938 {       .mii
 939         srlz.d
 940         dep             r27=0,r27,61,3
 941         ;;
 942         extr.u          r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3    // dir L0 index
 943 }
 944 {       .mii
 945         ld8             r27=[r27]                               // dir L0 page
 946         extr.u          r29=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3    // dir L1 index
 947         ;;
 948         dep             r27=0,r27,61,3
 949         ;;
 950 }
 951 {       .mmi
 952         shladd          r27=r28,3,r27
 953         ;;
 954         ld8             r27=[r27]                               // dir L1 page
 955         extr.u          r28=r30,PAGE_SHIFT,PAGE_SHIFT-5         // pte index
 956         ;;
 957 }
 958 {       .mmi
 959         shladd          r27=r29,3,r27
 960         ;;
 961         mov             r29=rr[r30]
 962         dep             r27=0,r27,61,3
 963         ;;
 964 }
 965 {       .mii
 966         ld8             r27=[r27]                               // pte page
 967         shl             r28=r28,5
 968         dep             r29=0,r29,0,2
 969         ;;
 970 }
 971 {       .mmi
 972         add             r27=r28,r27
 973         ;;
 974         mov             cr.ifa=r30
 975         dep             r27=0,r27,61,3
 976         ;;
 977 }
 978 {       .mmi
 979         ld8             r28=[r27]               // pte
 980         ;;
 981         mov             cr.itir=r29
 982         or              r28=PTE_DIRTY+PTE_ACCESSED,r28
 983         ;;
 984 }
 985 {       .mlx
 986         st8             [r27]=r28
 987         movl            r29=exception_save_restart
 988         ;;
 989 }
 990 {       .mmi
 991         itc.d           r28
 992         ;;
 993         ssm             psr.dt
 994         cmp.eq          p12,p13=r26,r29
 995         ;;
 996 }
 997 {       .mbb
 998         srlz.d
 999 (p12)   br.sptk         exception_save_restart
1000 (p13)   br.sptk         exception_restore_restart
1001         ;;
1002 }
1003 IVT_END(Data_Nested_TLB)
1004
1005 IVT_ENTRY(Instruction_Key_Miss, 0x1800)
1006         CALL(trap, 6, cr.ifa)
1007 IVT_END(Instruction_Key_Miss)
1008
1009 IVT_ENTRY(Data_Key_Miss, 0x1c00)
1010         CALL(trap, 7, cr.ifa)
1011 IVT_END(Data_Key_Miss)
1012
1013 IVT_ENTRY(Dirty_Bit, 0x2000)
1014         mov     r16=cr.ifa
1015         mov     r17=pr
1016         ;;
1017         thash   r18=r16
1018         ;;
1019         ttag    r19=r16
1020         add     r20=24,r18              // collision chain
1021         ;;
1022         ld8     r20=[r20]               // bucket head
1023         ;;
1024         rsm     psr.dt                  // turn off data translations
1025         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1026         ;;
1027         srlz.d                          // serialize
1028         ld8     r20=[r20]               // first entry
1029         ;;
1030 1:      cmp.eq  p15,p0=r0,r20           // done?
1031 (p15)   br.cond.spnt.few 9f             // bail if done
1032         ;;
1033         add     r21=16,r20              // tag location
1034         ;;
1035         ld8     r21=[r21]               // read tag
1036         ;;
1037         cmp.ne  p15,p0=r21,r19          // compare tags
1038 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1039         ;;
1040         ld8     r21=[r20]               // read pte
1041         mov     r22=PTE_DIRTY+PTE_ACCESSED
1042         ;;
1043         or      r21=r22,r21             // set dirty & access bit
1044         ;;
1045         st8     [r20]=r21,8             // store back
1046         ;;
1047         ld8     r22=[r20]               // read rest of pte
1048         ;;
1049         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1050         ;;
1051         add     r20=16,r18              // address of tag
1052         ;;
1053         ld8.acq r23=[r20]               // read old tag
1054         ;;
1055         dep     r23=-1,r23,63,1         // set ti bit
1056         ;;
1057         st8.rel [r20]=r23               // store old tag + ti
1058         ;;
1059         mf                              // make sure everyone sees
1060         ;;
1061         st8     [r18]=r21,8             // store pte
1062         ;;
1063         st8     [r18]=r22,8
1064         ;;
1065         st8.rel [r18]=r19               // store new tag
1066         ;;
1067         itc.d   r21                     // and place in TLB
1068         ssm     psr.dt
1069         ;;
1070         srlz.d
1071         mov     pr=r17,0x1ffff          // restore predicates
1072         rfi
1073         ;;
1074 2:      add     r20=24,r20              // next in chain
1075         ;;
1076         ld8     r20=[r20]               // read chain
1077         br.cond.sptk.few 1b             // loop
1078         ;;
1079 9:      ssm     psr.dt
1080         mov     pr=r17,0x1ffff          // restore predicates
1081         ;;
1082         srlz.d
1083         ;;
1084         CALL(trap, 8, cr.ifa)                   // die horribly
1085 IVT_END(Dirty_Bit)
1086
1087 IVT_ENTRY(Instruction_Access_Bit, 0x2400)
1088         mov     r16=cr.ifa
1089         mov     r17=pr
1090         ;;
1091         thash   r18=r16
1092         ;;
1093         ttag    r19=r16
1094         add     r20=24,r18              // collision chain
1095         ;;
1096         ld8     r20=[r20]               // bucket head
1097         ;;
1098         rsm     psr.dt                  // turn off data translations
1099         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1100         ;;
1101         srlz.d                          // serialize
1102         ld8     r20=[r20]               // first entry
1103         ;;
1104 1:      cmp.eq  p15,p0=r0,r20           // done?
1105 (p15)   br.cond.spnt.few 9f             // bail if done
1106         ;;
1107         add     r21=16,r20              // tag location
1108         ;;
1109         ld8     r21=[r21]               // read tag
1110         ;;
1111         cmp.ne  p15,p0=r21,r19          // compare tags
1112 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1113         ;;
1114         ld8     r21=[r20]               // read pte
1115         mov     r22=PTE_ACCESSED
1116         ;;
1117         or      r21=r22,r21             // set accessed bit
1118         ;;
1119         st8     [r20]=r21,8             // store back
1120         ;;
1121         ld8     r22=[r20]               // read rest of pte
1122         ;;
1123         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1124         ;;
1125         add     r20=16,r18              // address of tag
1126         ;;
1127         ld8.acq r23=[r20]               // read old tag
1128         ;;
1129         dep     r23=-1,r23,63,1         // set ti bit
1130         ;;
1131         st8.rel [r20]=r23               // store old tag + ti
1132         ;;
1133         mf                              // make sure everyone sees
1134         ;;
1135         st8     [r18]=r21,8             // store pte
1136         ;;
1137         st8     [r18]=r22,8
1138         ;;
1139         st8.rel [r18]=r19               // store new tag
1140         ;;
1141         itc.i   r21                     // and place in TLB
1142         ssm     psr.dt
1143         ;;
1144         srlz.d
1145         mov     pr=r17,0x1ffff          // restore predicates
1146         rfi                             // walker will retry the access
1147         ;;
1148 2:      add     r20=24,r20              // next in chain
1149         ;;
1150         ld8     r20=[r20]               // read chain
1151         br.cond.sptk.few 1b             // loop
1152         ;;
1153 9:      ssm     psr.dt
1154         mov     pr=r17,0x1ffff          // restore predicates
1155         ;;
1156         srlz.d
1157         ;;
1158         CALL(trap, 9, cr.ifa)
1159 IVT_END(Instruction_Access_Bit)
1160
1161 IVT_ENTRY(Data_Access_Bit, 0x2800)
1162         mov     r16=cr.ifa
1163         mov     r17=pr
1164         ;;
1165         thash   r18=r16
1166         ;;
1167         ttag    r19=r16
1168         add     r20=24,r18              // collision chain
1169         ;;
1170         ld8     r20=[r20]               // bucket head
1171         ;;
1172         rsm     psr.dt                  // turn off data translations
1173         dep     r20=0,r20,61,3          // convert vhpt ptr to physical
1174         ;;
1175         srlz.d                          // serialize
1176         ld8     r20=[r20]               // first entry
1177         ;;
1178 1:      cmp.eq  p15,p0=r0,r20           // done?
1179 (p15)   br.cond.spnt.few 9f             // bail if done
1180         ;;
1181         add     r21=16,r20              // tag location
1182         ;;
1183         ld8     r21=[r21]               // read tag
1184         ;;
1185         cmp.ne  p15,p0=r21,r19          // compare tags
1186 (p15)   br.cond.sptk.few 2f             // if not, read next in chain
1187         ;;
1188         ld8     r21=[r20]               // read pte
1189         mov     r22=PTE_ACCESSED
1190         ;;
1191         or      r21=r22,r21             // set accessed bit
1192         ;;
1193         st8     [r20]=r21,8             // store back
1194         ;;
1195         ld8     r22=[r20]               // read rest of pte
1196         ;;
1197         dep     r18=0,r18,61,3          // convert vhpt ptr to physical
1198         ;;
1199         add     r20=16,r18              // address of tag
1200         ;;
1201         ld8.acq r23=[r20]               // read old tag
1202         ;;
1203         dep     r23=-1,r23,63,1         // set ti bit
1204         ;;
1205         st8.rel [r20]=r23               // store old tag + ti
1206         ;;
1207         mf                              // make sure everyone sees
1208         ;;
1209         st8     [r18]=r21,8             // store pte
1210         ;;
1211         st8     [r18]=r22,8
1212         ;;
1213         st8.rel [r18]=r19               // store new tag
1214         ;;
1215         itc.d   r21                     // and place in TLB
1216         ssm     psr.dt
1217         ;;
1218         srlz.d
1219         mov     pr=r17,0x1ffff          // restore predicates
1220         rfi                             // walker will retry the access
1221         ;;
1222 2:      add     r20=24,r20              // next in chain
1223         ;;
1224         ld8     r20=[r20]               // read chain
1225         br.cond.sptk.few 1b             // loop
1226         ;;
1227 9:      ssm     psr.dt
1228         mov     pr=r17,0x1ffff          // restore predicates
1229         ;;
1230         srlz.d
1231         ;;
1232         CALL(trap, 10, cr.ifa)
1233 IVT_END(Data_Access_Bit)
1234
1235 IVT_ENTRY(Break_Instruction, 0x2c00)
1236 {       .mib
1237         mov             r17=cr.iim
1238         mov             r16=ip
1239         br.sptk         exception_save
1240         ;;
1241 }
1242 {       .mmi
1243         alloc           r15=ar.pfs,0,0,2,0
1244         ;;
1245 (p11)   ssm             psr.i
1246         mov             out0=11
1247         ;;
1248 }
1249 {       .mmi
1250         flushrs
1251         ;;
1252 (p11)   srlz.d
1253         add             out1=16,sp
1254 }
1255 {       .mfb
1256         nop             0
1257         nop             0
1258         br.call.sptk    rp=trap
1259         ;;
1260 }
1261 {       .mfb
1262         nop             0
1263         nop             0
1264         br.sptk         exception_restore
1265         ;;
1266 }
1267 IVT_END(Break_Instruction)
1268
1269 IVT_ENTRY(External_Interrupt, 0x3000)
1270 {       .mib
1271         mov             r17=cr.ivr      // Put the vector in the trap frame.
1272         mov             r16=ip
1273         br.sptk         exception_save
1274         ;;
1275 }
1276 {       .mfb
1277         alloc           r15=ar.pfs,0,0,1,0
1278         nop             0
1279         nop             0
1280         ;;
1281 }
1282 {       .mfb
1283         add             out0=16,sp
1284         nop             0
1285         br.call.sptk    rp=interrupt
1286         ;;
1287 }
1288 {       .mfb
1289         nop             0
1290         nop             0
1291         br.sptk         exception_restore
1292         ;;
1293 }
1294 IVT_END(External_Interrupt)
1295
1296 IVT_ENTRY(Reserved_3400, 0x3400)
1297         CALL(trap, 13, cr.ifa)
1298 IVT_END(Reserved_3400)
1299
1300 IVT_ENTRY(Reserved_3800, 0x3800)
1301         CALL(trap, 14, cr.ifa)
1302 IVT_END(Reserved_3800)
1303
1304 IVT_ENTRY(Reserved_3c00, 0x3c00)
1305         CALL(trap, 15, cr.ifa)
1306 IVT_END(Reserved_3c00)
1307
1308 IVT_ENTRY(Reserved_4000, 0x4000)
1309         CALL(trap, 16, cr.ifa)
1310 IVT_END(Reserved_4000)
1311
1312 IVT_ENTRY(Reserved_4400, 0x4400)
1313         CALL(trap, 17, cr.ifa)
1314 IVT_END(Reserved_4400)
1315
1316 IVT_ENTRY(Reserved_4800, 0x4800)
1317         CALL(trap, 18, cr.ifa)
1318 IVT_END(Reserved_4800)
1319
1320 IVT_ENTRY(Reserved_4c00, 0x4c00)
1321         CALL(trap, 19, cr.ifa)
1322 IVT_END(Reserved_4c00)
1323
1324 IVT_ENTRY(Page_Not_Present, 0x5000)
1325         CALL(trap, 20, cr.ifa)
1326 IVT_END(Page_Not_Present)
1327
1328 IVT_ENTRY(Key_Permission, 0x5100)
1329         CALL(trap, 21, cr.ifa)
1330 IVT_END(Key_Permission)
1331
1332 IVT_ENTRY(Instruction_Access_Rights, 0x5200)
1333         CALL(trap, 22, cr.ifa)
1334 IVT_END(Instruction_Access_Rights)
1335
1336 IVT_ENTRY(Data_Access_Rights, 0x5300)
1337         CALL(trap, 23, cr.ifa)
1338 IVT_END(Data_Access_Rights)
1339
1340 IVT_ENTRY(General_Exception, 0x5400)
1341         CALL(trap, 24, cr.ifa)
1342 IVT_END(General_Exception)
1343
1344 IVT_ENTRY(Disabled_FP_Register, 0x5500)
1345         CALL(trap, 25, cr.ifa)
1346 IVT_END(Disabled_FP_Register)
1347
1348 IVT_ENTRY(NaT_Consumption, 0x5600)
1349         CALL(trap, 26, cr.ifa)
1350 IVT_END(NaT_Consumption)
1351
1352 IVT_ENTRY(Speculation, 0x5700)
1353         CALL(trap, 27, cr.iim)
1354 IVT_END(Speculation)
1355
1356 IVT_ENTRY(Reserved_5800, 0x5800)
1357         CALL(trap, 28, cr.ifa)
1358 IVT_END(Reserved_5800)
1359
1360 IVT_ENTRY(Debug, 0x5900)
1361         CALL(trap, 29, cr.ifa)
1362 IVT_END(Debug)
1363
1364 IVT_ENTRY(Unaligned_Reference, 0x5a00)
1365         CALL(trap, 30, cr.ifa)
1366 IVT_END(Unaligned_Reference)
1367
1368 IVT_ENTRY(Unsupported_Data_Reference, 0x5b00)
1369         CALL(trap, 31, cr.ifa)
1370 IVT_END(Unsupported_Data_Reference)
1371
1372 IVT_ENTRY(Floating_Point_Fault, 0x5c00)
1373         CALL(trap, 32, cr.ifa)
1374 IVT_END(Floating_Point_Fault)
1375
1376 IVT_ENTRY(Floating_Point_Trap, 0x5d00)
1377         CALL(trap, 33, cr.ifa)
1378 IVT_END(Floating_Point_Trap)
1379
1380 IVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00)
1381         CALL(trap, 34, cr.ifa)
1382 IVT_END(Lower_Privilege_Transfer_Trap)
1383
1384 IVT_ENTRY(Taken_Branch_Trap, 0x5f00)
1385         CALL(trap, 35, cr.ifa)
1386 IVT_END(Taken_Branch_Trap)
1387
1388 IVT_ENTRY(Single_Step_Trap, 0x6000)
1389         CALL(trap, 36, cr.ifa)
1390 IVT_END(Single_Step_Trap)
1391
1392 IVT_ENTRY(Reserved_6100, 0x6100)
1393         CALL(trap, 37, cr.ifa)
1394 IVT_END(Reserved_6100)
1395
1396 IVT_ENTRY(Reserved_6200, 0x6200)
1397         CALL(trap, 38, cr.ifa)
1398 IVT_END(Reserved_6200)
1399
1400 IVT_ENTRY(Reserved_6300, 0x6300)
1401         CALL(trap, 39, cr.ifa)
1402 IVT_END(Reserved_6300)
1403
1404 IVT_ENTRY(Reserved_6400, 0x6400)
1405         CALL(trap, 40, cr.ifa)
1406 IVT_END(Reserved_6400)
1407
1408 IVT_ENTRY(Reserved_6500, 0x6500)
1409         CALL(trap, 41, cr.ifa)
1410 IVT_END(Reserved_6500)
1411
1412 IVT_ENTRY(Reserved_6600, 0x6600)
1413         CALL(trap, 42, cr.ifa)
1414 IVT_END(Reserved_6600)
1415
1416 IVT_ENTRY(Reserved_6700, 0x6700)
1417         CALL(trap, 43, cr.ifa)
1418 IVT_END(Reserved_6700)
1419
1420 IVT_ENTRY(Reserved_6800, 0x6800)
1421         CALL(trap, 44, cr.ifa)
1422 IVT_END(Reserved_6800)
1423
1424 IVT_ENTRY(IA_32_Exception, 0x6900)
1425         CALL(IA32_TRAP, 45, cr.ifa)
1426 IVT_END(IA_32_Exception)
1427
1428 IVT_ENTRY(IA_32_Intercept, 0x6a00)
1429         CALL(IA32_TRAP, 46, cr.iim)
1430 IVT_END(IA_32_Intercept)
1431
1432 IVT_ENTRY(IA_32_Interrupt, 0x6b00)
1433         CALL(IA32_TRAP, 47, cr.ifa)
1434 IVT_END(IA_32_Interrupt)
1435
1436 IVT_ENTRY(Reserved_6c00, 0x6c00)
1437         CALL(trap, 48, cr.ifa)
1438 IVT_END(Reserved_6c00)
1439
1440 IVT_ENTRY(Reserved_6d00, 0x6d00)
1441         CALL(trap, 49, cr.ifa)
1442 IVT_END(Reserved_6d00)
1443
1444 IVT_ENTRY(Reserved_6e00, 0x6e00)
1445         CALL(trap, 50, cr.ifa)
1446 IVT_END(Reserved_6e00)
1447
1448 IVT_ENTRY(Reserved_6f00, 0x6f00)
1449         CALL(trap, 51, cr.ifa)
1450 IVT_END(Reserved_6f00)
1451
1452 IVT_ENTRY(Reserved_7000, 0x7000)
1453         CALL(trap, 52, cr.ifa)
1454 IVT_END(Reserved_7000)
1455
1456 IVT_ENTRY(Reserved_7100, 0x7100)
1457         CALL(trap, 53, cr.ifa)
1458 IVT_END(Reserved_7100)
1459
1460 IVT_ENTRY(Reserved_7200, 0x7200)
1461         CALL(trap, 54, cr.ifa)
1462 IVT_END(Reserved_7200)
1463
1464 IVT_ENTRY(Reserved_7300, 0x7300)
1465         CALL(trap, 55, cr.ifa)
1466 IVT_END(Reserved_7300)
1467
1468 IVT_ENTRY(Reserved_7400, 0x7400)
1469         CALL(trap, 56, cr.ifa)
1470 IVT_END(Reserved_7400)
1471
1472 IVT_ENTRY(Reserved_7500, 0x7500)
1473         CALL(trap, 57, cr.ifa)
1474 IVT_END(Reserved_7500)
1475
1476 IVT_ENTRY(Reserved_7600, 0x7600)
1477         CALL(trap, 58, cr.ifa)
1478 IVT_END(Reserved_7600)
1479
1480 IVT_ENTRY(Reserved_7700, 0x7700)
1481         CALL(trap, 59, cr.ifa)
1482 IVT_END(Reserved_7700)
1483
1484 IVT_ENTRY(Reserved_7800, 0x7800)
1485         CALL(trap, 60, cr.ifa)
1486 IVT_END(Reserved_7800)
1487
1488 IVT_ENTRY(Reserved_7900, 0x7900)
1489         CALL(trap, 61, cr.ifa)
1490 IVT_END(Reserved_7900)
1491
1492 IVT_ENTRY(Reserved_7a00, 0x7a00)
1493         CALL(trap, 62, cr.ifa)
1494 IVT_END(Reserved_7a00)
1495
1496 IVT_ENTRY(Reserved_7b00, 0x7b00)
1497         CALL(trap, 63, cr.ifa)
1498 IVT_END(Reserved_7b00)
1499
1500 IVT_ENTRY(Reserved_7c00, 0x7c00)
1501         CALL(trap, 64, cr.ifa)
1502 IVT_END(Reserved_7c00)
1503
1504 IVT_ENTRY(Reserved_7d00, 0x7d00)
1505         CALL(trap, 65, cr.ifa)
1506 IVT_END(Reserved_7d00)
1507
1508 IVT_ENTRY(Reserved_7e00, 0x7e00)
1509         CALL(trap, 66, cr.ifa)
1510 IVT_END(Reserved_7e00)
1511
1512 IVT_ENTRY(Reserved_7f00, 0x7f00)
1513         CALL(trap, 67, cr.ifa)
1514 IVT_END(Reserved_7f00)