2 /* $NetBSD: interrupt.c,v 1.23 1998/02/24 07:38:01 thorpej Exp $ */
5 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
8 * Authors: Keith Bostic, Chris G. Demetriou
10 * Permission to use, copy, modify and distribute this software and
11 * its documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
20 * Carnegie Mellon requests users of this software to return to
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
31 * Additional Copyright (c) 1997 by Matthew Jacob for NASA/Ames Research Center.
32 * Redistribute and modify at will, leaving only this additional copyright
38 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
44 #include <sys/vmmeter.h>
46 #include <sys/malloc.h>
49 #include <sys/mutex.h>
50 #include <sys/sched.h>
52 #include <sys/sysctl.h>
53 #include <sys/syslog.h>
55 #include <machine/clock.h>
56 #include <machine/cpu.h>
57 #include <machine/fpu.h>
58 #include <machine/frame.h>
59 #include <machine/intr.h>
60 #include <machine/md_var.h>
61 #include <machine/pcb.h>
62 #include <machine/reg.h>
63 #include <machine/sapicvar.h>
64 #include <machine/smp.h>
67 struct evcnt clock_intr_evcnt; /* event counter for clock intrs. */
69 #include <sys/interrupt.h>
70 #include <machine/intrcnt.h>
77 static void ia64_dispatch_intr(void *, u_int);
80 dummy_perf(unsigned long vector, struct trapframe *tf)
82 printf("performance interrupt!\n");
85 void (*perf_irq)(unsigned long, struct trapframe *) = dummy_perf;
87 static unsigned int ints[MAXCPU];
88 SYSCTL_OPAQUE(_debug, OID_AUTO, ints, CTLFLAG_RW, &ints, sizeof(ints), "IU",
91 static unsigned int clks[MAXCPU];
93 SYSCTL_OPAQUE(_debug, OID_AUTO, clks, CTLFLAG_RW, &clks, sizeof(clks), "IU",
96 SYSCTL_INT(_debug, OID_AUTO, clks, CTLFLAG_RW, clks, 0, "");
100 static unsigned int asts[MAXCPU];
101 SYSCTL_OPAQUE(_debug, OID_AUTO, asts, CTLFLAG_RW, &asts, sizeof(asts), "IU",
104 static unsigned int rdvs[MAXCPU];
105 SYSCTL_OPAQUE(_debug, OID_AUTO, rdvs, CTLFLAG_RW, &rdvs, sizeof(rdvs), "IU",
109 SYSCTL_NODE(_debug, OID_AUTO, clock, CTLFLAG_RW, 0, "clock statistics");
111 static int adjust_edges = 0;
112 SYSCTL_INT(_debug_clock, OID_AUTO, adjust_edges, CTLFLAG_RD,
113 &adjust_edges, 0, "Number of times ITC got more than 12.5% behind");
115 static int adjust_excess = 0;
116 SYSCTL_INT(_debug_clock, OID_AUTO, adjust_excess, CTLFLAG_RD,
117 &adjust_excess, 0, "Total number of ignored ITC interrupts");
119 static int adjust_lost = 0;
120 SYSCTL_INT(_debug_clock, OID_AUTO, adjust_lost, CTLFLAG_RD,
121 &adjust_lost, 0, "Total number of lost ITC interrupts");
123 static int adjust_ticks = 0;
124 SYSCTL_INT(_debug_clock, OID_AUTO, adjust_ticks, CTLFLAG_RD,
125 &adjust_ticks, 0, "Total number of ITC interrupts with adjustment");
128 interrupt(struct trapframe *tf)
131 volatile struct ia64_interrupt_block *ib = IA64_INTERRUPT_BLOCK;
132 uint64_t adj, clk, itc;
138 ia64_set_fpsr(IA64_FPSR_DEFAULT);
142 vector = tf->tf_special.ifa;
146 * Handle ExtINT interrupts by generating an INTA cycle to
148 * IPI_STOP_HARD is mapped to IPI_STOP so it is not necessary
149 * to add it to this switch-like construct.
153 printf("ExtINT interrupt: vector=%u\n", (int)inta);
155 __asm __volatile("mov cr.eoi = r0;; srlz.d");
159 } else if (vector == 15)
162 if (vector == CLOCK_VECTOR) {/* clock interrupt */
163 /* CTR0(KTR_INTR, "clock interrupt"); */
165 itc = ia64_get_itc();
167 PCPU_INC(cnt.v_intr);
168 #ifdef EVCNT_COUNTERS
169 clock_intr_evcnt.ev_count++;
171 intrcnt[INTRCNT_CLOCK]++;
173 clks[PCPU_GET(cpuid)]++;
177 adj = PCPU_GET(clockadj);
178 clk = PCPU_GET(clock);
181 while (delta >= ia64_clock_reload) {
182 /* Only the BSP runs the real clock */
183 if (PCPU_GET(cpuid) == 0)
184 hardclock(TRAPF_USERMODE(tf), TRAPF_PC(tf));
186 hardclock_cpu(TRAPF_USERMODE(tf));
188 profclock(TRAPF_USERMODE(tf), TRAPF_PC(tf));
189 statclock(TRAPF_USERMODE(tf));
190 delta -= ia64_clock_reload;
191 clk += ia64_clock_reload;
196 ia64_set_itm(ia64_get_itc() + ia64_clock_reload - adj);
198 adjust_lost += count - 1;
199 if (delta > (ia64_clock_reload >> 3)) {
202 adj = ia64_clock_reload >> 4;
209 PCPU_SET(clock, clk);
210 PCPU_SET(clockadj, adj);
215 } else if (vector == ipi_vector[IPI_AST]) {
216 asts[PCPU_GET(cpuid)]++;
217 CTR1(KTR_SMP, "IPI_AST, cpuid=%d", PCPU_GET(cpuid));
218 } else if (vector == ipi_vector[IPI_HIGH_FP]) {
219 struct thread *thr = PCPU_GET(fpcurthread);
221 mtx_lock_spin(&thr->td_md.md_highfp_mtx);
222 save_high_fp(&thr->td_pcb->pcb_high_fp);
223 thr->td_pcb->pcb_fpcpu = NULL;
224 PCPU_SET(fpcurthread, NULL);
225 mtx_unlock_spin(&thr->td_md.md_highfp_mtx);
227 } else if (vector == ipi_vector[IPI_RENDEZVOUS]) {
228 rdvs[PCPU_GET(cpuid)]++;
229 CTR1(KTR_SMP, "IPI_RENDEZVOUS, cpuid=%d", PCPU_GET(cpuid));
231 smp_rendezvous_action();
233 } else if (vector == ipi_vector[IPI_STOP]) {
234 cpumask_t mybit = PCPU_GET(cpumask);
236 savectx(PCPU_PTR(pcb));
237 atomic_set_int(&stopped_cpus, mybit);
238 while ((started_cpus & mybit) == 0)
240 atomic_clear_int(&started_cpus, mybit);
241 atomic_clear_int(&stopped_cpus, mybit);
242 } else if (vector == ipi_vector[IPI_PREEMPT]) {
243 CTR1(KTR_SMP, "IPI_PREEMPT, cpuid=%d", PCPU_GET(cpuid));
244 __asm __volatile("mov cr.eoi = r0;; srlz.d");
246 sched_preempt(curthread);
251 ints[PCPU_GET(cpuid)]++;
252 atomic_add_int(&td->td_intr_nesting_level, 1);
253 ia64_dispatch_intr(tf, vector);
254 atomic_subtract_int(&td->td_intr_nesting_level, 1);
257 __asm __volatile("mov cr.eoi = r0;; srlz.d");
258 vector = ia64_get_ivr();
263 if (TRAPF_USERMODE(tf)) {
266 mtx_assert(&Giant, MA_NOTOWNED);
272 * Hardware irqs have vectors starting at this offset.
274 #define IA64_HARDWARE_IRQ_BASE 0x20
277 struct intr_event *event; /* interrupt event */
278 volatile long *cntp; /* interrupt counter */
283 static struct ia64_intr *ia64_intrs[256];
286 ia64_intr_eoi(void *arg)
288 u_int vector = (uintptr_t)arg;
291 i = ia64_intrs[vector];
293 sapic_eoi(i->sapic, vector);
297 ia64_intr_mask(void *arg)
299 u_int vector = (uintptr_t)arg;
302 i = ia64_intrs[vector];
304 sapic_mask(i->sapic, i->irq);
305 sapic_eoi(i->sapic, vector);
310 ia64_intr_unmask(void *arg)
312 u_int vector = (uintptr_t)arg;
315 i = ia64_intrs[vector];
317 sapic_unmask(i->sapic, i->irq);
321 ia64_setup_intr(const char *name, int irq, driver_filter_t filter,
322 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
330 /* Get the I/O SAPIC that corresponds to the IRQ. */
331 sa = sapic_lookup(irq);
336 * XXX - There's a priority implied by the choice of vector.
337 * We should therefore relate the vector to the interrupt type.
339 vector = irq + IA64_HARDWARE_IRQ_BASE;
341 i = ia64_intrs[vector];
343 i = malloc(sizeof(struct ia64_intr), M_DEVBUF, M_NOWAIT);
347 error = intr_event_create(&i->event, (void *)(uintptr_t)vector,
348 0, irq, ia64_intr_mask, ia64_intr_unmask, ia64_intr_eoi,
349 NULL, "irq%u:", irq);
355 if (!atomic_cmpset_ptr(&ia64_intrs[vector], NULL, i)) {
356 intr_event_destroy(i->event);
358 i = ia64_intrs[vector];
363 i->cntp = intrcnt + irq + INTRCNT_ISA_IRQ;
364 if (name != NULL && *name != '\0') {
365 /* XXX needs abstraction. Too error prone. */
366 intrname = intrnames +
367 (irq + INTRCNT_ISA_IRQ) * INTRNAME_LEN;
368 memset(intrname, ' ', INTRNAME_LEN - 1);
369 bcopy(name, intrname, strlen(name));
372 sapic_enable(i->sapic, irq, vector);
376 error = intr_event_add_handler(i->event, name, filter, handler, arg,
377 intr_priority(flags), flags, cookiep);
382 ia64_teardown_intr(void *cookie)
385 return (intr_event_remove_handler(cookie));
389 ia64_dispatch_intr(void *frame, u_int vector)
392 struct intr_event *ie; /* our interrupt event */
395 * Find the interrupt thread for this vector.
397 i = ia64_intrs[vector];
398 KASSERT(i != NULL, ("%s: unassigned vector", __func__));
403 KASSERT(ie != NULL, ("%s: interrupt without event", __func__));
405 if (intr_event_handle(ie, frame) != 0) {
407 * XXX: The pre-INTR_FILTER code didn't mask stray
410 ia64_intr_mask((void *)(uintptr_t)vector);
411 log(LOG_ERR, "stray irq%u\n", i->irq);
418 db_print_vector(u_int vector, int always)
422 i = ia64_intrs[vector];
424 db_printf("vector %u (%p): ", vector, i);
425 sapic_print(i->sapic, i->irq);
427 db_printf("vector %u: unassigned\n", vector);
430 DB_SHOW_COMMAND(vector, db_show_vector)
435 vector = ((addr >> 4) % 16) * 10 + (addr % 16);
437 db_printf("error: vector %u not in range [0..255]\n",
440 db_print_vector(vector, 1);
442 for (vector = 0; vector < 256; vector++)
443 db_print_vector(vector, 0);