2 * Copyright (c) 2011 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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29 #include <machine/asm.h>
30 #include <machine/ia64_cpu.h>
31 #include <machine/pte.h>
35 * AP wake-up entry point. The handoff state is similar as for the BSP,
36 * as described on page 3-9 of the IPF SAL Specification. The difference
37 * lies in the contents of register b0. For APs this register holds the
38 * return address into the SAL rendezvous routine.
40 * Note that we're responsible for clearing the IRR bit by reading cr.ivr
41 * and issuing the EOI to the local SAPIC.
44 ENTRY_NOPROFILE(os_boot_rendez,0)
46 st8 [gp] = gp // trace = 0x00
47 mov r8 = cr.ivr // clear IRR bit
53 mov cr.eoi = r0 // ACK the wake-up
59 rsm IA64_PSR_IC | IA64_PSR_I
60 mov r16 = (IA64_PBVM_RR << 8) | (IA64_PBVM_PAGE_SHIFT << 2)
65 st8 [gp] = r2 // trace = 0x08
66 dep.z r17 = IA64_PBVM_RR, 61, 3
71 movl r18 = IA64_PBVM_PGTBL
77 st8 [gp] = r3 // trace = 0x10
82 ld8 r16 = [r2], 16 // as_pgtbl_pte
83 ld8 r17 = [r3], 16 // as_pgtbl_itir
101 st8 [gp] = r2 // trace = 0x18
113 ld8 r16 = [r2], 16 // as_text_va
114 st8 [gp] = r3 // trace = 0x20
119 ld8 r17 = [r3], 16 // as_text_pte
120 ld8 r18 = [r2], 16 // as_text_itir
138 st8 [gp] = r3 // trace = 0x30
149 st8 [gp] = r2 // trace = 0x38
164 ld8 r16 = [r3], 16 // as_data_va
169 st8 [gp] = r3 // trace = 0x40
170 ld8 r17 = [r2], 16 // as_data_pte
176 ld8 r18 = [r3], 16 // as_data_itir
191 mov r19 = IA64_DCR_DEFAULT
202 st8 [gp] = r2 // trace = 0x48
204 ld8 r16 = [r2], 16 // as_kstack
208 ld8 r17 = [r3], 16 // as_kstack_top
215 movl r18 = IA64_PSR_BN | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_IC | \
216 IA64_PSR_RT | IA64_PSR_DFH
221 movl r19 = ia64_vector_table // set up IVT early
237 st8 [gp] = r2 // trace = 0x58
245 mov ar.bspstore = r16
258 alloc r18 = ar.pfs, 0, 0, 0, 0
264 br.call.sptk.few rp = ia64_ap_startup