1 /* $NetBSD: if_admsw.c,v 1.3 2007/04/22 19:26:25 dyoung Exp $ */
4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
7 * Redistribution and use in source and binary forms, with or
8 * without modification, are permitted provided that the following
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
16 * 3. The names of the authors may not be used to endorse or promote
17 * products derived from this software without specific prior
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 * Copyright (c) 2001 Wasabi Systems, Inc.
35 * All rights reserved.
37 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 * 3. All advertising materials mentioning features or use of this software
48 * must display the following acknowledgement:
49 * This product includes software developed for the NetBSD Project by
50 * Wasabi Systems, Inc.
51 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
52 * or promote products derived from this software without specific prior
55 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
65 * POSSIBILITY OF SUCH DAMAGE.
69 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media
74 * Better Rx buffer management; we want to get new Rx buffers
75 * to the chip more quickly than we currently do.
78 #include <sys/cdefs.h>
79 __FBSDID("$FreeBSD$");
81 #include <sys/param.h>
82 #include <sys/systm.h>
84 #include <sys/kernel.h>
86 #include <sys/malloc.h>
87 #include <sys/module.h>
89 #include <sys/socket.h>
90 #include <sys/sockio.h>
91 #include <sys/sysctl.h>
92 #include <machine/bus.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_mib.h>
100 #include <net/if_types.h>
103 #include <netinet/in.h>
104 #include <netinet/in_systm.h>
105 #include <netinet/in_var.h>
106 #include <netinet/ip.h>
110 #include <net/bpfdesc.h>
112 #include <mips/adm5120/adm5120reg.h>
113 #include <mips/adm5120/if_admswreg.h>
114 #include <mips/adm5120/if_admswvar.h>
116 /* TODO: add locking */
117 #define ADMSW_LOCK(sc) do {} while(0);
118 #define ADMSW_UNLOCK(sc) do {} while(0);
120 static uint8_t vlan_matrix[SW_DEVS] = {
121 (1 << 6) | (1 << 0), /* CPU + port0 */
122 (1 << 6) | (1 << 1), /* CPU + port1 */
123 (1 << 6) | (1 << 2), /* CPU + port2 */
124 (1 << 6) | (1 << 3), /* CPU + port3 */
125 (1 << 6) | (1 << 4), /* CPU + port4 */
126 (1 << 6) | (1 << 5), /* CPU + port5 */
129 /* ifnet entry points */
130 static void admsw_start(struct ifnet *);
131 static void admsw_watchdog(void *);
132 static int admsw_ioctl(struct ifnet *, u_long, caddr_t);
133 static void admsw_init(void *);
134 static void admsw_stop(struct ifnet *, int);
136 static void admsw_reset(struct admsw_softc *);
137 static void admsw_set_filter(struct admsw_softc *);
139 static void admsw_txintr(struct admsw_softc *, int);
140 static void admsw_rxintr(struct admsw_softc *, int);
141 static int admsw_add_rxbuf(struct admsw_softc *, int, int);
142 #define admsw_add_rxhbuf(sc, idx) admsw_add_rxbuf(sc, idx, 1)
143 #define admsw_add_rxlbuf(sc, idx) admsw_add_rxbuf(sc, idx, 0)
145 static int admsw_mediachange(struct ifnet *);
146 static void admsw_mediastatus(struct ifnet *, struct ifmediareq *);
148 static int admsw_intr(void *);
150 /* bus entry points */
151 static int admsw_probe(device_t dev);
152 static int admsw_attach(device_t dev);
153 static int admsw_detach(device_t dev);
154 static int admsw_shutdown(device_t dev);
157 admsw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
164 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
166 *addr = segs->ds_addr;
170 admsw_rxbuf_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
172 struct admsw_descsoft *ds;
177 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
181 ds->ds_addr[0] = segs[0].ds_addr;
182 ds->ds_len[0] = segs[0].ds_len;
187 admsw_mbuf_map_addr(void *arg, bus_dma_segment_t *segs, int nseg,
188 bus_size_t mapsize, int error)
190 struct admsw_descsoft *ds;
197 if((nseg != 1) && (nseg != 2))
198 panic("%s: nseg == %d\n", __func__, nseg);
201 ds->ds_addr[0] = segs[0].ds_addr;
202 ds->ds_len[0] = segs[0].ds_len;
205 ds->ds_addr[1] = segs[1].ds_addr;
206 ds->ds_len[1] = segs[1].ds_len;
213 admsw_probe(device_t dev)
216 device_set_desc(dev, "ADM5120 Switch Engine");
220 #define REG_READ(o) bus_read_4((sc)->mem_res, (o))
221 #define REG_WRITE(o,v) bus_write_4((sc)->mem_res, (o),(v))
224 admsw_init_bufs(struct admsw_softc *sc)
227 struct admsw_desc *desc;
229 for (i = 0; i < ADMSW_NTXHDESC; i++) {
230 if (sc->sc_txhsoft[i].ds_mbuf != NULL) {
231 m_freem(sc->sc_txhsoft[i].ds_mbuf);
232 sc->sc_txhsoft[i].ds_mbuf = NULL;
234 desc = &sc->sc_txhdescs[i];
237 desc->len = MAC_BUFLEN;
239 ADMSW_CDTXHSYNC(sc, i,
240 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
242 sc->sc_txhdescs[ADMSW_NTXHDESC - 1].data |= ADM5120_DMA_RINGEND;
243 ADMSW_CDTXHSYNC(sc, ADMSW_NTXHDESC - 1,
244 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
246 for (i = 0; i < ADMSW_NRXHDESC; i++) {
247 if (sc->sc_rxhsoft[i].ds_mbuf == NULL) {
248 if (admsw_add_rxhbuf(sc, i) != 0)
249 panic("admsw_init_bufs\n");
251 ADMSW_INIT_RXHDESC(sc, i);
254 for (i = 0; i < ADMSW_NTXLDESC; i++) {
255 if (sc->sc_txlsoft[i].ds_mbuf != NULL) {
256 m_freem(sc->sc_txlsoft[i].ds_mbuf);
257 sc->sc_txlsoft[i].ds_mbuf = NULL;
259 desc = &sc->sc_txldescs[i];
262 desc->len = MAC_BUFLEN;
264 ADMSW_CDTXLSYNC(sc, i,
265 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
267 sc->sc_txldescs[ADMSW_NTXLDESC - 1].data |= ADM5120_DMA_RINGEND;
268 ADMSW_CDTXLSYNC(sc, ADMSW_NTXLDESC - 1,
269 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
271 for (i = 0; i < ADMSW_NRXLDESC; i++) {
272 if (sc->sc_rxlsoft[i].ds_mbuf == NULL) {
273 if (admsw_add_rxlbuf(sc, i) != 0)
274 panic("admsw_init_bufs\n");
276 ADMSW_INIT_RXLDESC(sc, i);
279 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
280 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
281 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
282 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
284 sc->sc_txfree = ADMSW_NTXLDESC;
291 admsw_setvlan(struct admsw_softc *sc, char matrix[6])
295 i = matrix[0] + (matrix[1] << 8) + (matrix[2] << 16) + (matrix[3] << 24);
296 REG_WRITE(VLAN_G1_REG, i);
297 i = matrix[4] + (matrix[5] << 8);
298 REG_WRITE(VLAN_G2_REG, i);
302 admsw_reset(struct admsw_softc *sc)
307 REG_WRITE(PORT_CONF0_REG,
308 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK);
309 REG_WRITE(CPUP_CONF_REG,
310 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP);
312 /* Wait for DMA to complete. Overkill. In 3ms, we can
313 * send at least two entire 1500-byte packets at 10 Mb/s.
317 /* The datasheet recommends that we move all PHYs to reset
318 * state prior to software reset.
320 REG_WRITE(PHY_CNTL2_REG,
321 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK);
323 /* Reset the switch. */
324 REG_WRITE(ADMSW_SW_RES, 0x1);
328 REG_WRITE(ADMSW_BOOT_DONE, ADMSW_BOOT_DONE_BO);
331 REG_WRITE(CPUP_CONF_REG,
332 CPUP_CONF_DCPUP | CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK |
333 CPUP_CONF_DMCP_MASK);
335 REG_WRITE(PORT_CONF0_REG, PORT_CONF0_EMCP_MASK | PORT_CONF0_EMBP_MASK);
337 REG_WRITE(PHY_CNTL2_REG,
338 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK | PHY_CNTL2_PHYR_MASK |
339 PHY_CNTL2_AMDIX_MASK);
341 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);
343 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
344 REG_WRITE(ADMSW_INT_ST, INT_MASK);
347 * While in DDB, we stop servicing interrupts, RX ring
348 * fills up and when free block counter falls behind FC
349 * threshold, the switch starts to emit 802.3x PAUSE
350 * frames. This can upset peer switches.
352 * Stop this from happening by disabling FC and D2
356 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK));
358 admsw_setvlan(sc, vlan_matrix);
360 for (i = 0; i < SW_DEVS; i++) {
361 REG_WRITE(MAC_WT1_REG,
363 (sc->sc_enaddr[3]<<8) |
364 (sc->sc_enaddr[4]<<16) |
365 ((sc->sc_enaddr[5]+i)<<24));
366 REG_WRITE(MAC_WT0_REG, (i<<MAC_WT0_VLANID_SHIFT) |
367 (sc->sc_enaddr[0]<<16) | (sc->sc_enaddr[1]<<24) |
368 MAC_WT0_WRITE | MAC_WT0_VLANID_EN);
370 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE));
373 wdog1 = REG_READ(ADM5120_WDOG1);
374 REG_WRITE(ADM5120_WDOG1, wdog1 & ~ADM5120_WDOG1_WDE);
378 admsw_attach(device_t dev)
380 uint8_t enaddr[ETHER_ADDR_LEN];
381 struct admsw_softc *sc = (struct admsw_softc *) device_get_softc(dev);
386 device_printf(dev, "ADM5120 Switch Engine, %d ports\n", SW_DEVS);
389 /* XXXMIPS: fix it */
397 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
399 device_printf(sc->sc_dev, "base Ethernet address %s\n",
400 ether_sprintf(enaddr));
401 callout_init(&sc->sc_watchdog, 1);
404 if ((sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
405 RF_ACTIVE)) == NULL) {
406 device_printf(dev, "unable to allocate memory resource\n");
410 /* Hook up the interrupt handler. */
412 if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
413 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
414 device_printf(dev, "unable to allocate IRQ resource\n");
418 if ((error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET,
419 admsw_intr, NULL, sc, &sc->sc_ih)) != 0) {
421 "WARNING: unable to register interrupt handler\n");
426 * Allocate the control data structures, and create and load the
429 if ((error = bus_dma_tag_create(NULL, 4, 0,
430 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
431 NULL, NULL, sizeof(struct admsw_control_data), 1,
432 sizeof(struct admsw_control_data), 0, NULL, NULL,
433 &sc->sc_control_dmat)) != 0) {
434 device_printf(sc->sc_dev,
435 "unable to create control data DMA map, error = %d\n",
440 if ((error = bus_dmamem_alloc(sc->sc_control_dmat,
441 (void **)&sc->sc_control_data, BUS_DMA_NOWAIT,
442 &sc->sc_cddmamap)) != 0) {
443 device_printf(sc->sc_dev,
444 "unable to allocate control data, error = %d\n", error);
448 if ((error = bus_dmamap_load(sc->sc_control_dmat, sc->sc_cddmamap,
449 sc->sc_control_data, sizeof(struct admsw_control_data),
450 admsw_dma_map_addr, &sc->sc_cddma, 0)) != 0) {
451 device_printf(sc->sc_dev,
452 "unable to load control data DMA map, error = %d\n", error);
457 * Create the transmit buffer DMA maps.
459 if ((error = bus_dma_tag_create(NULL, 1, 0,
460 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
461 NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, NULL,
462 &sc->sc_bufs_dmat)) != 0) {
463 device_printf(sc->sc_dev,
464 "unable to create control data DMA map, error = %d\n",
469 for (i = 0; i < ADMSW_NTXHDESC; i++) {
470 if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
471 &sc->sc_txhsoft[i].ds_dmamap)) != 0) {
472 device_printf(sc->sc_dev,
473 "unable to create txh DMA map %d, error = %d\n",
477 sc->sc_txhsoft[i].ds_mbuf = NULL;
480 for (i = 0; i < ADMSW_NTXLDESC; i++) {
481 if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
482 &sc->sc_txlsoft[i].ds_dmamap)) != 0) {
483 device_printf(sc->sc_dev,
484 "unable to create txl DMA map %d, error = %d\n",
488 sc->sc_txlsoft[i].ds_mbuf = NULL;
492 * Create the receive buffer DMA maps.
494 for (i = 0; i < ADMSW_NRXHDESC; i++) {
495 if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
496 &sc->sc_rxhsoft[i].ds_dmamap)) != 0) {
497 device_printf(sc->sc_dev,
498 "unable to create rxh DMA map %d, error = %d\n",
502 sc->sc_rxhsoft[i].ds_mbuf = NULL;
505 for (i = 0; i < ADMSW_NRXLDESC; i++) {
506 if ((error = bus_dmamap_create(sc->sc_bufs_dmat, 0,
507 &sc->sc_rxlsoft[i].ds_dmamap)) != 0) {
508 device_printf(sc->sc_dev,
509 "unable to create rxl DMA map %d, error = %d\n",
513 sc->sc_rxlsoft[i].ds_mbuf = NULL;
519 for (i = 0; i < SW_DEVS; i++) {
520 ifmedia_init(&sc->sc_ifmedia[i], 0, admsw_mediachange,
522 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_10_T, 0, NULL);
523 ifmedia_add(&sc->sc_ifmedia[i],
524 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
525 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_100_TX, 0, NULL);
526 ifmedia_add(&sc->sc_ifmedia[i],
527 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
528 ifmedia_add(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO, 0, NULL);
529 ifmedia_set(&sc->sc_ifmedia[i], IFM_ETHER|IFM_AUTO);
531 ifp = sc->sc_ifnet[i] = if_alloc(IFT_ETHER);
533 /* Setup interface parameters */
535 if_initname(ifp, device_get_name(dev), i);
536 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
537 ifp->if_ioctl = admsw_ioctl;
538 ifp->if_output = ether_output;
539 ifp->if_start = admsw_start;
540 ifp->if_init = admsw_init;
541 ifp->if_mtu = ETHERMTU;
542 ifp->if_baudrate = IF_Mbps(100);
543 IFQ_SET_MAXLEN(&ifp->if_snd, max(ADMSW_NTXLDESC, ifqmaxlen));
544 ifp->if_snd.ifq_drv_maxlen = max(ADMSW_NTXLDESC, ifqmaxlen);
545 IFQ_SET_READY(&ifp->if_snd);
546 ifp->if_capabilities |= IFCAP_VLAN_MTU;
548 /* Attach the interface. */
549 ether_ifattach(ifp, enaddr);
553 /* XXX: admwdog_attach(sc); */
555 /* leave interrupts and cpu port disabled */
560 admsw_detach(device_t dev)
563 printf("TODO: DETACH\n");
570 * Make sure the interface is stopped at reboot time.
573 admsw_shutdown(device_t dev)
575 struct admsw_softc *sc;
578 sc = device_get_softc(dev);
579 for (i = 0; i < SW_DEVS; i++)
580 admsw_stop(sc->sc_ifnet[i], 1);
586 * admsw_start: [ifnet interface function]
588 * Start packet transmission on the interface.
591 admsw_start(struct ifnet *ifp)
593 struct admsw_softc *sc = ifp->if_softc;
595 struct admsw_descsoft *ds;
596 struct admsw_desc *desc;
598 struct ether_header *eh;
599 int error, nexttx, len, i;
603 * Loop through the send queues, setting up transmit descriptors
604 * unitl we drain the queues, or use up all available transmit
613 ifp = sc->sc_ifnet[i];
614 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE))
615 == IFF_DRV_RUNNING) {
616 /* Grab a packet off the queue. */
617 IF_DEQUEUE(&ifp->if_snd, m0);
630 /* Get a spare descriptor. */
631 if (sc->sc_txfree == 0) {
632 /* No more slots left; notify upper layer. */
633 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
636 nexttx = sc->sc_txnext;
637 desc = &sc->sc_txldescs[nexttx];
638 ds = &sc->sc_txlsoft[nexttx];
639 dmamap = ds->ds_dmamap;
642 * Load the DMA map. If this fails, the packet either
643 * didn't fit in the alloted number of segments, or we
644 * were short on resources. In this case, we'll copy
647 if (m0->m_pkthdr.len < ETHER_MIN_LEN ||
648 bus_dmamap_load_mbuf(sc->sc_bufs_dmat, dmamap, m0,
649 admsw_mbuf_map_addr, ds, BUS_DMA_NOWAIT) != 0) {
650 MGETHDR(m, M_DONTWAIT, MT_DATA);
652 device_printf(sc->sc_dev,
653 "unable to allocate Tx mbuf\n");
656 if (m0->m_pkthdr.len > MHLEN) {
657 MCLGET(m, M_DONTWAIT);
658 if ((m->m_flags & M_EXT) == 0) {
659 device_printf(sc->sc_dev,
660 "unable to allocate Tx cluster\n");
665 m->m_pkthdr.csum_flags = m0->m_pkthdr.csum_flags;
666 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
667 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
668 if (m->m_pkthdr.len < ETHER_MIN_LEN) {
669 if (M_TRAILINGSPACE(m) < ETHER_MIN_LEN - m->m_pkthdr.len)
670 panic("admsw_start: M_TRAILINGSPACE\n");
671 memset(mtod(m, uint8_t *) + m->m_pkthdr.len, 0,
672 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len);
673 m->m_pkthdr.len = m->m_len = ETHER_MIN_LEN;
675 error = bus_dmamap_load_mbuf(sc->sc_bufs_dmat,
676 dmamap, m, admsw_mbuf_map_addr, ds, BUS_DMA_NOWAIT);
678 device_printf(sc->sc_dev,
679 "unable to load Tx buffer, error = %d\n",
691 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
694 /* Sync the DMA map. */
695 bus_dmamap_sync(sc->sc_bufs_dmat, dmamap, BUS_DMASYNC_PREWRITE);
697 if (ds->ds_nsegs != 1 && ds->ds_nsegs != 2)
698 panic("admsw_start: nsegs == %d\n", ds->ds_nsegs);
699 desc->data = ds->ds_addr[0];
700 desc->len = len = ds->ds_len[0];
701 if (ds->ds_nsegs > 1) {
702 len += ds->ds_len[1];
703 desc->cntl = ds->ds_addr[1] | ADM5120_DMA_BUF2ENABLE;
706 desc->status = (len << ADM5120_DMA_LENSHIFT) | (1 << vlan);
707 eh = mtod(m0, struct ether_header *);
708 if (ntohs(eh->ether_type) == ETHERTYPE_IP &&
709 m0->m_pkthdr.csum_flags & CSUM_IP)
710 desc->status |= ADM5120_DMA_CSUM;
711 if (nexttx == ADMSW_NTXLDESC - 1)
712 desc->data |= ADM5120_DMA_RINGEND;
713 desc->data |= ADM5120_DMA_OWN;
715 /* Sync the descriptor. */
716 ADMSW_CDTXLSYNC(sc, nexttx,
717 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
719 REG_WRITE(SEND_TRIG_REG, 1);
720 /* printf("send slot %d\n",nexttx); */
723 * Store a pointer to the packet so we can free it later.
727 /* Advance the Tx pointer. */
729 sc->sc_txnext = ADMSW_NEXTTXL(nexttx);
731 /* Pass the packet to any BPF listeners. */
734 /* Set a watchdog timer in case the chip flakes out. */
740 * admsw_watchdog: [ifnet interface function]
742 * Watchdog timer handler.
745 admsw_watchdog(void *arg)
747 struct admsw_softc *sc = arg;
751 callout_reset(&sc->sc_watchdog, hz, admsw_watchdog, sc);
752 if (sc->sc_timer == 0 || --sc->sc_timer > 0)
755 /* Check if an interrupt was lost. */
756 if (sc->sc_txfree == ADMSW_NTXLDESC) {
757 device_printf(sc->sc_dev, "watchdog false alarm\n");
760 if (sc->sc_timer != 0)
761 device_printf(sc->sc_dev, "watchdog timer is %d!\n",
764 if (sc->sc_txfree == ADMSW_NTXLDESC) {
765 device_printf(sc->sc_dev, "tx IRQ lost (queue empty)\n");
768 if (sc->sc_timer != 0) {
769 device_printf(sc->sc_dev, "tx IRQ lost (timer recharged)\n");
773 device_printf(sc->sc_dev, "device timeout, txfree = %d\n",
775 for (vlan = 0; vlan < SW_DEVS; vlan++)
776 admsw_stop(sc->sc_ifnet[vlan], 0);
779 ifp = sc->sc_ifnet[0];
781 /* Try to get more packets going. */
786 * admsw_ioctl: [ifnet interface function]
788 * Handle control requests from the operator.
791 admsw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
793 struct admsw_softc *sc = ifp->if_softc;
803 while(port < SW_DEVS)
804 if(ifp == sc->sc_ifnet[port])
811 error = ifmedia_ioctl(ifp, (struct ifreq *)data,
812 &sc->sc_ifmedia[port], cmd);
817 ifd = (struct ifdrv *) data;
818 if (ifd->ifd_cmd != 0 || ifd->ifd_len != sizeof(vlan_matrix)) {
822 if (cmd == SIOCGDRVSPEC) {
823 error = copyout(vlan_matrix, ifd->ifd_data,
824 sizeof(vlan_matrix));
826 error = copyin(ifd->ifd_data, vlan_matrix,
827 sizeof(vlan_matrix));
828 admsw_setvlan(sc, vlan_matrix);
833 error = ether_ioctl(ifp, cmd, data);
834 if (error == ENETRESET) {
836 * Multicast list has changed; set the hardware filter
839 admsw_set_filter(sc);
845 /* Try to get more packets going. */
856 * Interrupt service routine.
859 admsw_intr(void *arg)
861 struct admsw_softc *sc = arg;
864 pending = REG_READ(ADMSW_INT_ST);
865 REG_WRITE(ADMSW_INT_ST, pending);
868 return (FILTER_STRAY);
870 if ((pending & ADMSW_INTR_RHD) != 0)
873 if ((pending & ADMSW_INTR_RLD) != 0)
876 if ((pending & ADMSW_INTR_SHD) != 0)
879 if ((pending & ADMSW_INTR_SLD) != 0)
882 return (FILTER_HANDLED);
888 * Helper; handle transmit interrupts.
891 admsw_txintr(struct admsw_softc *sc, int prio)
894 struct admsw_desc *desc;
895 struct admsw_descsoft *ds;
899 /* printf("txintr: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
900 for (i = sc->sc_txdirty; sc->sc_txfree != ADMSW_NTXLDESC;
901 i = ADMSW_NEXTTXL(i)) {
903 ADMSW_CDTXLSYNC(sc, i,
904 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
906 desc = &sc->sc_txldescs[i];
907 ds = &sc->sc_txlsoft[i];
908 if (desc->data & ADM5120_DMA_OWN) {
909 ADMSW_CDTXLSYNC(sc, i,
910 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
914 bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
915 BUS_DMASYNC_POSTWRITE);
916 bus_dmamap_unload(sc->sc_bufs_dmat, ds->ds_dmamap);
917 m_freem(ds->ds_mbuf);
920 vlan = ffs(desc->status & 0x3f) - 1;
921 if (vlan < 0 || vlan >= SW_DEVS)
922 panic("admsw_txintr: bad vlan\n");
923 ifp = sc->sc_ifnet[vlan];
925 /* printf("clear tx slot %d\n",i); */
934 for (vlan = 0; vlan < SW_DEVS; vlan++)
935 sc->sc_ifnet[vlan]->if_drv_flags &= ~IFF_DRV_OACTIVE;
937 ifp = sc->sc_ifnet[0];
939 /* Try to queue more packets. */
943 * If there are no more pending transmissions,
944 * cancel the watchdog timer.
946 if (sc->sc_txfree == ADMSW_NTXLDESC)
951 /* printf("txintr end: txdirty: %d, txfree: %d\n",sc->sc_txdirty, sc->sc_txfree); */
957 * Helper; handle receive interrupts.
960 admsw_rxintr(struct admsw_softc *sc, int high)
963 struct admsw_descsoft *ds;
966 int i, len, port, vlan;
968 /* printf("rxintr\n"); */
971 panic("admsw_rxintr: high priority packet\n");
974 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
975 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
976 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0)
977 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
978 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
982 ADMSW_CDRXLSYNC(sc, i,
983 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
984 i = ADMSW_NEXTRXL(i);
985 /* the ring is empty, just return. */
986 if (i == sc->sc_rxptr)
988 ADMSW_CDRXLSYNC(sc, i,
989 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
990 } while (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN);
992 ADMSW_CDRXLSYNC(sc, i,
993 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
995 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
996 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
998 if ((sc->sc_rxldescs[sc->sc_rxptr].data & ADM5120_DMA_OWN) == 0)
999 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
1000 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1002 ADMSW_CDRXLSYNC(sc, sc->sc_rxptr,
1003 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1004 /* We've fallen behind the chip: catch it. */
1006 device_printf(sc->sc_dev,
1007 "RX ring resync, base=%x, work=%x, %d -> %d\n",
1008 REG_READ(RECV_LBADDR_REG),
1009 REG_READ(RECV_LWADDR_REG), sc->sc_rxptr, i);
1012 /* ADMSW_EVCNT_INCR(&sc->sc_ev_rxsync); */
1016 for (i = sc->sc_rxptr;; i = ADMSW_NEXTRXL(i)) {
1017 ds = &sc->sc_rxlsoft[i];
1019 ADMSW_CDRXLSYNC(sc, i,
1020 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1022 if (sc->sc_rxldescs[i].data & ADM5120_DMA_OWN) {
1023 ADMSW_CDRXLSYNC(sc, i,
1024 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1028 /* printf("process slot %d\n",i); */
1030 bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
1031 BUS_DMASYNC_POSTREAD);
1033 stat = sc->sc_rxldescs[i].status;
1034 len = (stat & ADM5120_DMA_LEN) >> ADM5120_DMA_LENSHIFT;
1035 len -= ETHER_CRC_LEN;
1036 port = (stat & ADM5120_DMA_PORTID) >> ADM5120_DMA_PORTSHIFT;
1038 for (vlan = 0; vlan < SW_DEVS; vlan++)
1039 if ((1 << port) & vlan_matrix[vlan])
1042 if (vlan == SW_DEVS)
1045 ifp = sc->sc_ifnet[vlan];
1048 if (admsw_add_rxlbuf(sc, i) != 0) {
1050 ADMSW_INIT_RXLDESC(sc, i);
1051 bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap,
1052 BUS_DMASYNC_PREREAD);
1056 m->m_pkthdr.rcvif = ifp;
1057 m->m_pkthdr.len = m->m_len = len;
1058 if ((stat & ADM5120_DMA_TYPE) == ADM5120_DMA_TYPE_IP) {
1059 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1060 if (!(stat & ADM5120_DMA_CSUMFAIL))
1061 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1067 (*ifp->if_input)(ifp, m);
1071 /* Update the receive pointer. */
1076 * admsw_init: [ifnet interface function]
1078 * Initialize the interface.
1081 admsw_init(void *xsc)
1083 struct admsw_softc *sc = xsc;
1087 for (i = 0; i < SW_DEVS; i++) {
1088 ifp = sc->sc_ifnet[i];
1089 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1090 if (sc->ndevs == 0) {
1091 admsw_init_bufs(sc);
1093 REG_WRITE(CPUP_CONF_REG,
1094 CPUP_CONF_CRCP | CPUP_CONF_DUNP_MASK |
1095 CPUP_CONF_DMCP_MASK);
1096 /* clear all pending interrupts */
1097 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1099 /* enable needed interrupts */
1100 REG_WRITE(ADMSW_INT_MASK,
1101 REG_READ(ADMSW_INT_MASK) &
1102 ~(ADMSW_INTR_SHD | ADMSW_INTR_SLD |
1103 ADMSW_INTR_RHD | ADMSW_INTR_RLD |
1104 ADMSW_INTR_HDF | ADMSW_INTR_LDF));
1106 callout_reset(&sc->sc_watchdog, hz,
1107 admsw_watchdog, sc);
1113 /* mark iface as running */
1114 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1115 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1118 /* Set the receive filter. */
1119 admsw_set_filter(sc);
1123 * admsw_stop: [ifnet interface function]
1125 * Stop transmission on the interface.
1128 admsw_stop(struct ifnet *ifp, int disable)
1130 struct admsw_softc *sc = ifp->if_softc;
1132 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1135 if (--sc->ndevs == 0) {
1136 /* printf("debug: de-initializing hardware\n"); */
1138 /* disable cpu port */
1139 REG_WRITE(CPUP_CONF_REG,
1140 CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
1141 CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK);
1143 /* XXX We should disable, then clear? --dyoung */
1144 /* clear all pending interrupts */
1145 REG_WRITE(ADMSW_INT_ST, INT_MASK);
1147 /* disable interrupts */
1148 REG_WRITE(ADMSW_INT_MASK, INT_MASK);
1150 /* Cancel the watchdog timer. */
1152 callout_stop(&sc->sc_watchdog);
1155 /* Mark the interface as down. */
1156 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1164 * Set up the receive filter.
1167 admsw_set_filter(struct admsw_softc *sc)
1170 uint32_t allmc, anymc, conf, promisc;
1172 struct ifmultiaddr *ifma;
1174 /* Find which ports should be operated in promisc mode. */
1175 allmc = anymc = promisc = 0;
1176 for (i = 0; i < SW_DEVS; i++) {
1177 ifp = sc->sc_ifnet[i];
1178 if (ifp->if_flags & IFF_PROMISC)
1179 promisc |= vlan_matrix[i];
1181 ifp->if_flags &= ~IFF_ALLMULTI;
1183 if_maddr_rlock(ifp);
1184 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
1186 if (ifma->ifma_addr->sa_family != AF_LINK)
1189 anymc |= vlan_matrix[i];
1191 if_maddr_runlock(ifp);
1194 conf = REG_READ(CPUP_CONF_REG);
1195 /* 1 Disable forwarding of unknown & multicast packets to
1197 * 2 Enable forwarding of unknown & multicast packets to
1198 * CPU on ports where IFF_PROMISC or IFF_ALLMULTI is set.
1200 conf |= CPUP_CONF_DUNP_MASK | CPUP_CONF_DMCP_MASK;
1201 /* Enable forwarding of unknown packets to CPU on selected ports. */
1202 conf ^= ((promisc << CPUP_CONF_DUNP_SHIFT) & CPUP_CONF_DUNP_MASK);
1203 conf ^= ((allmc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK);
1204 conf ^= ((anymc << CPUP_CONF_DMCP_SHIFT) & CPUP_CONF_DMCP_MASK);
1205 REG_WRITE(CPUP_CONF_REG, conf);
1211 * Add a receive buffer to the indicated descriptor.
1214 admsw_add_rxbuf(struct admsw_softc *sc, int idx, int high)
1216 struct admsw_descsoft *ds;
1221 ds = &sc->sc_rxhsoft[idx];
1223 ds = &sc->sc_rxlsoft[idx];
1225 MGETHDR(m, M_DONTWAIT, MT_DATA);
1229 MCLGET(m, M_DONTWAIT);
1230 if ((m->m_flags & M_EXT) == 0) {
1235 if (ds->ds_mbuf != NULL)
1236 bus_dmamap_unload(sc->sc_bufs_dmat, ds->ds_dmamap);
1240 error = bus_dmamap_load(sc->sc_bufs_dmat, ds->ds_dmamap,
1241 m->m_ext.ext_buf, m->m_ext.ext_size, admsw_rxbuf_map_addr,
1242 ds, BUS_DMA_NOWAIT);
1244 device_printf(sc->sc_dev,
1245 "can't load rx DMA map %d, error = %d\n", idx, error);
1246 panic("admsw_add_rxbuf"); /* XXX */
1249 bus_dmamap_sync(sc->sc_bufs_dmat, ds->ds_dmamap, BUS_DMASYNC_PREREAD);
1252 ADMSW_INIT_RXHDESC(sc, idx);
1254 ADMSW_INIT_RXLDESC(sc, idx);
1260 admsw_mediachange(struct ifnet *ifp)
1262 struct admsw_softc *sc = ifp->if_softc;
1264 struct ifmedia *ifm;
1267 while(port < SW_DEVS) {
1268 if(ifp == sc->sc_ifnet[port])
1274 ifm = &sc->sc_ifmedia[port];
1276 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1279 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1280 val = PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX;
1281 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1282 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1283 val = PHY_CNTL2_100M|PHY_CNTL2_FDX;
1285 val = PHY_CNTL2_100M;
1286 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1287 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1288 val = PHY_CNTL2_FDX;
1294 old = REG_READ(PHY_CNTL2_REG);
1295 new = old & ~((PHY_CNTL2_AUTONEG|PHY_CNTL2_100M|PHY_CNTL2_FDX) << port);
1296 new |= (val << port);
1299 REG_WRITE(PHY_CNTL2_REG, new);
1305 admsw_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1307 struct admsw_softc *sc = ifp->if_softc;
1311 while(port < SW_DEVS) {
1312 if(ifp == sc->sc_ifnet[port])
1318 ifmr->ifm_status = IFM_AVALID;
1319 ifmr->ifm_active = IFM_ETHER;
1321 status = REG_READ(PHY_ST_REG) >> port;
1323 if ((status & PHY_ST_LINKUP) == 0) {
1324 ifmr->ifm_active |= IFM_NONE;
1328 ifmr->ifm_status |= IFM_ACTIVE;
1329 ifmr->ifm_active |= (status & PHY_ST_100M) ? IFM_100_TX : IFM_10_T;
1330 if (status & PHY_ST_FDX)
1331 ifmr->ifm_active |= IFM_FDX;
1334 static device_method_t admsw_methods[] = {
1335 /* Device interface */
1336 DEVMETHOD(device_probe, admsw_probe),
1337 DEVMETHOD(device_attach, admsw_attach),
1338 DEVMETHOD(device_detach, admsw_detach),
1339 DEVMETHOD(device_shutdown, admsw_shutdown),
1344 static devclass_t admsw_devclass;
1346 static driver_t admsw_driver = {
1349 sizeof(struct admsw_softc),
1352 DRIVER_MODULE(admsw, obio, admsw_driver, admsw_devclass, 0, 0);
1353 MODULE_DEPEND(admsw, ether, 1, 1, 1);