2 * Copyright (c) 2010 Adrian Chadd
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
56 #include <mips/atheros/ar71xx_chip.h>
58 #include <mips/atheros/ar71xx_cpudef.h>
60 #include <mips/sentry5/s5reg.h>
62 /* XXX these should replace the current definitions in ar71xxreg.h */
63 /* XXX perhaps an ar71xx_chip.h header file? */
64 #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00
65 #define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04
66 #define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10
67 #define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14
69 #define AR71XX_PLL_DIV_SHIFT 3
70 #define AR71XX_PLL_DIV_MASK 0x1f
71 #define AR71XX_CPU_DIV_SHIFT 16
72 #define AR71XX_CPU_DIV_MASK 0x3
73 #define AR71XX_DDR_DIV_SHIFT 18
74 #define AR71XX_DDR_DIV_MASK 0x3
75 #define AR71XX_AHB_DIV_SHIFT 20
76 #define AR71XX_AHB_DIV_MASK 0x7
78 /* XXX these shouldn't be in here - this file is a per-chip file */
79 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
80 uint32_t u_ar71xx_cpu_freq;
81 uint32_t u_ar71xx_ahb_freq;
82 uint32_t u_ar71xx_ddr_freq;
85 ar71xx_chip_detect_mem_size(void)
90 ar71xx_chip_detect_sys_frequency(void)
96 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
98 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
99 freq = div * AR71XX_BASE_FREQ;
101 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
102 u_ar71xx_cpu_freq = freq / div;
104 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
105 u_ar71xx_ddr_freq = freq / div;
107 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
108 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
112 * This does not lock the CPU whilst doing the work!
115 ar71xx_chip_device_stop(uint32_t mask)
119 reg = ATH_READ_REG(AR71XX_RST_RESET);
120 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
124 ar71xx_chip_device_start(uint32_t mask)
128 reg = ATH_READ_REG(AR71XX_RST_RESET);
129 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
133 ar71xx_chip_device_stopped(uint32_t mask)
137 reg = ATH_READ_REG(AR71XX_RST_RESET);
138 return ((reg & mask) == mask);
141 /* Speed is either 10, 100 or 1000 */
143 ar71xx_chip_set_pll_ge0(int speed)
149 pll = PLL_ETH_INT_CLK_10;
152 pll = PLL_ETH_INT_CLK_100;
155 pll = PLL_ETH_INT_CLK_1000;
158 printf("ar71xx_chip_set_pll_ge0: invalid speed %d\n", speed);
162 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll, AR71XX_PLL_ETH0_SHIFT);
166 ar71xx_chip_set_pll_ge1(int speed)
172 pll = PLL_ETH_INT_CLK_10;
175 pll = PLL_ETH_INT_CLK_100;
178 pll = PLL_ETH_INT_CLK_1000;
181 printf("ar71xx_chip_set_pll_ge1: invalid speed %d\n", speed);
185 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll, AR71XX_PLL_ETH1_SHIFT);
189 ar71xx_chip_ddr_flush_ge0(void)
191 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
195 ar71xx_chip_ddr_flush_ge1(void)
197 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
201 ar71xx_chip_ddr_flush_ip2(void)
203 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
207 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
213 ar71xx_chip_init_usb_peripheral(void)
215 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
218 ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
221 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
222 USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
223 USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
225 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
226 (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
231 struct ar71xx_cpu_def ar71xx_chip_def = {
232 &ar71xx_chip_detect_mem_size,
233 &ar71xx_chip_detect_sys_frequency,
234 &ar71xx_chip_device_stop,
235 &ar71xx_chip_device_start,
236 &ar71xx_chip_device_stopped,
237 &ar71xx_chip_set_pll_ge0,
238 &ar71xx_chip_set_pll_ge1,
239 &ar71xx_chip_ddr_flush_ge0,
240 &ar71xx_chip_ddr_flush_ge1,
241 &ar71xx_chip_get_eth_pll,
242 &ar71xx_chip_ddr_flush_ip2,
243 &ar71xx_chip_init_usb_peripheral,