2 * Copyright (c) 2009 Oleksandr Tymoshenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _AR71XX_REG_H_
30 #define _AR71XX_REG_H_
33 #define AR71XX_PCI_MEM_BASE 0x10000000
35 * PCI mem windows is 0x08000000 bytes long but we exclude control
36 * region from the resource manager
38 #define AR71XX_PCI_MEM_SIZE 0x07000000
39 #define AR71XX_PCI_IRQ_START 0
40 #define AR71XX_PCI_IRQ_END 2
41 #define AR71XX_PCI_NIRQS 3
43 * PCI devices slots are starting from this number
45 #define AR71XX_PCI_BASE_SLOT 17
47 /* PCI config registers */
48 #define AR71XX_PCI_LCONF_CMD 0x17010000
49 #define PCI_LCONF_CMD_READ 0x00000000
50 #define PCI_LCONF_CMD_WRITE 0x00010000
51 #define AR71XX_PCI_LCONF_WRITE_DATA 0x17010004
52 #define AR71XX_PCI_LCONF_READ_DATA 0x17010008
53 #define AR71XX_PCI_CONF_ADDR 0x1701000C
54 #define AR71XX_PCI_CONF_CMD 0x17010010
55 #define PCI_CONF_CMD_READ 0x0000000A
56 #define PCI_CONF_CMD_WRITE 0x0000000B
57 #define AR71XX_PCI_CONF_WRITE_DATA 0x17010014
58 #define AR71XX_PCI_CONF_READ_DATA 0x17010018
59 #define AR71XX_PCI_ERROR 0x1701001C
60 #define AR71XX_PCI_ERROR_ADDR 0x17010020
61 #define AR71XX_PCI_AHB_ERROR 0x17010024
62 #define AR71XX_PCI_AHB_ERROR_ADDR 0x17010028
66 * Size is not really true actual APB window size is
67 * 0x01000000 but it should handle OHCI memory as well
68 * because this controller's interrupt is routed through
71 #define AR71XX_APB_BASE 0x18000000
72 #define AR71XX_APB_SIZE 0x06000000
75 #define AR71XX_DDR_CONFIG 0x18000000
76 #define AR71XX_DDR_CONFIG2 0x18000004
77 #define AR71XX_DDR_MODE_REGISTER 0x18000008
78 #define AR71XX_DDR_EXT_MODE_REGISTER 0x1800000C
79 #define AR71XX_DDR_CONTROL 0x18000010
80 #define AR71XX_DDR_REFRESH 0x18000014
81 #define AR71XX_DDR_RD_DATA_THIS_CYCLE 0x18000018
82 #define AR71XX_TAP_CONTROL0 0x1800001C
83 #define AR71XX_TAP_CONTROL1 0x18000020
84 #define AR71XX_TAP_CONTROL2 0x18000024
85 #define AR71XX_TAP_CONTROL3 0x18000028
86 #define AR71XX_PCI_WINDOW0 0x1800007C
87 #define AR71XX_PCI_WINDOW1 0x18000080
88 #define AR71XX_PCI_WINDOW2 0x18000084
89 #define AR71XX_PCI_WINDOW3 0x18000088
90 #define AR71XX_PCI_WINDOW4 0x1800008C
91 #define AR71XX_PCI_WINDOW5 0x18000090
92 #define AR71XX_PCI_WINDOW6 0x18000094
93 #define AR71XX_PCI_WINDOW7 0x18000098
94 #define AR71XX_WB_FLUSH_GE0 0x1800009C
95 #define AR71XX_WB_FLUSH_GE1 0x180000A0
96 #define AR71XX_WB_FLUSH_USB 0x180000A4
97 #define AR71XX_WB_FLUSH_PCI 0x180000A8
100 * Values for PCI_WINDOW_X registers
102 #define PCI_WINDOW0_ADDR 0x10000000
103 #define PCI_WINDOW1_ADDR 0x11000000
104 #define PCI_WINDOW2_ADDR 0x12000000
105 #define PCI_WINDOW3_ADDR 0x13000000
106 #define PCI_WINDOW4_ADDR 0x14000000
107 #define PCI_WINDOW5_ADDR 0x15000000
108 #define PCI_WINDOW6_ADDR 0x16000000
109 #define PCI_WINDOW7_ADDR 0x17000000
110 /* This value enables acces to PCI config registers */
111 #define PCI_WINDOW7_CONF_ADDR 0x07000000
113 #define AR71XX_UART_ADDR 0x18020000
115 #define AR71XX_USB_CTRL_FLADJ 0x18030000
116 #define USB_CTRL_FLADJ_HOST_SHIFT 12
117 #define USB_CTRL_FLADJ_A5_SHIFT 10
118 #define USB_CTRL_FLADJ_A4_SHIFT 8
119 #define USB_CTRL_FLADJ_A3_SHIFT 6
120 #define USB_CTRL_FLADJ_A2_SHIFT 4
121 #define USB_CTRL_FLADJ_A1_SHIFT 2
122 #define USB_CTRL_FLADJ_A0_SHIFT 0
123 #define AR71XX_USB_CTRL_CONFIG 0x18030004
124 #define USB_CTRL_CONFIG_OHCI_DES_SWAP (1 << 19)
125 #define USB_CTRL_CONFIG_OHCI_BUF_SWAP (1 << 18)
126 #define USB_CTRL_CONFIG_EHCI_DES_SWAP (1 << 17)
127 #define USB_CTRL_CONFIG_EHCI_BUF_SWAP (1 << 16)
128 #define USB_CTRL_CONFIG_DISABLE_XTL (1 << 13)
129 #define USB_CTRL_CONFIG_OVERRIDE_XTL (1 << 12)
130 #define USB_CTRL_CONFIG_CLK_SEL_SHIFT 4
131 #define USB_CTRL_CONFIG_CLK_SEL_MASK 3
132 #define USB_CTRL_CONFIG_CLK_SEL_12 0
133 #define USB_CTRL_CONFIG_CLK_SEL_24 1
134 #define USB_CTRL_CONFIG_CLK_SEL_48 2
135 #define USB_CTRL_CONFIG_OVER_CURRENT_AS_GPIO (1 << 8)
136 #define USB_CTRL_CONFIG_SS_SIMULATION_MODE (1 << 2)
137 #define USB_CTRL_CONFIG_RESUME_UTMI_PLS_DIS (1 << 1)
138 #define USB_CTRL_CONFIG_UTMI_BACKWARD_ENB (1 << 0)
140 #define AR71XX_GPIO_BASE 0x18040000
141 #define AR71XX_GPIO_OE 0x00
142 #define AR71XX_GPIO_IN 0x04
143 #define AR71XX_GPIO_OUT 0x08
144 #define AR71XX_GPIO_SET 0x0c
145 #define AR71XX_GPIO_CLEAR 0x10
146 #define AR71XX_GPIO_INT 0x14
147 #define AR71XX_GPIO_INT_TYPE 0x18
148 #define AR71XX_GPIO_INT_POLARITY 0x1c
149 #define AR71XX_GPIO_INT_PENDING 0x20
150 #define AR71XX_GPIO_INT_MASK 0x24
151 #define AR71XX_GPIO_FUNCTION 0x28
152 #define GPIO_FUNC_STEREO_EN (1 << 17)
153 #define GPIO_FUNC_SLIC_EN (1 << 16)
154 #define GPIO_FUNC_SPI_CS2_EN (1 << 13)
155 /* CS2 is shared with GPIO_1 */
156 #define GPIO_FUNC_SPI_CS1_EN (1 << 12)
157 /* CS1 is shared with GPIO_0 */
158 #define GPIO_FUNC_UART_EN (1 << 8)
159 #define GPIO_FUNC_USB_OC_EN (1 << 4)
160 #define GPIO_FUNC_USB_CLK_EN (0)
162 #define AR71XX_BASE_FREQ 40000000
163 #define AR71XX_PLL_CPU_BASE 0x18050000
164 #define AR71XX_PLL_CPU_CONFIG 0x18050000
165 #define PLL_SW_UPDATE (1U << 31)
166 #define PLL_LOCKED (1 << 30)
167 #define PLL_AHB_DIV_SHIFT 20
168 #define PLL_AHB_DIV_MASK 7
169 #define PLL_DDR_DIV_SEL_SHIFT 18
170 #define PLL_DDR_DIV_SEL_MASK 3
171 #define PLL_CPU_DIV_SEL_SHIFT 16
172 #define PLL_CPU_DIV_SEL_MASK 3
173 #define PLL_LOOP_BW_SHIFT 12
174 #define PLL_LOOP_BW_MASK 0xf
175 #define PLL_DIV_IN_SHIFT 10
176 #define PLL_DIV_IN_MASK 3
177 #define PLL_DIV_OUT_SHIFT 8
178 #define PLL_DIV_OUT_MASK 3
179 #define PLL_FB_SHIFT 3
180 #define PLL_FB_MASK 0x1f
181 #define PLL_BYPASS (1 << 1)
182 #define PLL_POWER_DOWN (1 << 0)
183 #define AR71XX_PLL_SEC_CONFIG 0x18050004
184 #define AR71XX_PLL_ETH0_SHIFT 17
185 #define AR71XX_PLL_ETH1_SHIFT 19
186 #define AR71XX_PLL_CPU_CLK_CTRL 0x18050008
187 #define AR71XX_PLL_ETH_INT0_CLK 0x18050010
188 #define AR71XX_PLL_ETH_INT1_CLK 0x18050014
189 #define XPLL_ETH_INT_CLK_10 0x00991099
190 #define XPLL_ETH_INT_CLK_100 0x00441011
191 #define XPLL_ETH_INT_CLK_1000 0x13110000
192 #define XPLL_ETH_INT_CLK_1000_GMII 0x14110000
193 #define PLL_ETH_INT_CLK_10 0x00991099
194 #define PLL_ETH_INT_CLK_100 0x00001099
195 #define PLL_ETH_INT_CLK_1000 0x00110000
196 #define AR71XX_PLL_ETH_EXT_CLK 0x18050018
197 #define AR71XX_PLL_PCI_CLK 0x1805001C
200 #define AR71XX_RST_BLOCK_BASE 0x18060000
202 #define AR71XX_RST_WDOG_CONTROL 0x18060008
203 #define RST_WDOG_LAST (1U << 31)
204 #define RST_WDOG_ACTION_MASK 3
205 #define RST_WDOG_ACTION_RESET 3
206 #define RST_WDOG_ACTION_NMI 2
207 #define RST_WDOG_ACTION_GP_INTR 1
208 #define RST_WDOG_ACTION_NOACTION 0
210 #define AR71XX_RST_WDOG_TIMER 0x1806000C
212 * APB interrupt status and mask register and interrupt bit numbers for
214 #define AR71XX_MISC_INTR_STATUS 0x18060010
215 #define AR71XX_MISC_INTR_MASK 0x18060014
216 #define MISC_INTR_TIMER 0
217 #define MISC_INTR_ERROR 1
218 #define MISC_INTR_GPIO 2
219 #define MISC_INTR_UART 3
220 #define MISC_INTR_WATCHDOG 4
221 #define MISC_INTR_PERF 5
222 #define MISC_INTR_OHCI 6
223 #define MISC_INTR_DMA 7
225 #define AR71XX_PCI_INTR_STATUS 0x18060018
226 #define AR71XX_PCI_INTR_MASK 0x1806001C
227 #define PCI_INTR_CORE (1 << 4)
229 #define AR71XX_RST_RESET 0x18060024
230 #define RST_RESET_FULL_CHIP (1 << 24) /* Same as pulling
232 #define RST_RESET_CPU_COLD (1 << 20) /* Cold reset */
233 #define RST_RESET_GE1_MAC (1 << 13)
234 #define RST_RESET_GE1_PHY (1 << 12)
235 #define RST_RESET_GE0_MAC (1 << 9)
236 #define RST_RESET_GE0_PHY (1 << 8)
237 #define RST_RESET_USB_OHCI_DLL (1 << 6)
238 #define RST_RESET_USB_HOST (1 << 5)
239 #define RST_RESET_USB_PHY (1 << 4)
240 #define RST_RESET_PCI_BUS (1 << 1)
241 #define RST_RESET_PCI_CORE (1 << 0)
243 /* Chipset revision details */
244 #define AR71XX_RST_RESET_REG_REV_ID 0x18060090
245 #define REV_ID_MAJOR_MASK 0xfff0
246 #define REV_ID_MAJOR_AR71XX 0x00a0
247 #define REV_ID_MAJOR_AR913X 0x00b0
248 #define REV_ID_MAJOR_AR7240 0x00c0
249 #define REV_ID_MAJOR_AR7241 0x0100
250 #define REV_ID_MAJOR_AR7242 0x1100
252 /* AR71XX chipset revision details */
253 #define AR71XX_REV_ID_MINOR_MASK 0x3
254 #define AR71XX_REV_ID_MINOR_AR7130 0x0
255 #define AR71XX_REV_ID_MINOR_AR7141 0x1
256 #define AR71XX_REV_ID_MINOR_AR7161 0x2
257 #define AR71XX_REV_ID_REVISION_MASK 0x3
258 #define AR71XX_REV_ID_REVISION_SHIFT 2
260 /* AR724X chipset revision details */
261 #define AR724X_REV_ID_REVISION_MASK 0x3
263 /* AR91XX chipset revision details */
264 #define AR91XX_REV_ID_MINOR_MASK 0x3
265 #define AR91XX_REV_ID_MINOR_AR9130 0x0
266 #define AR91XX_REV_ID_MINOR_AR9132 0x1
267 #define AR91XX_REV_ID_REVISION_MASK 0x3
268 #define AR91XX_REV_ID_REVISION_SHIFT 2
271 AR71XX_MII_MODE_NONE = 0,
272 AR71XX_MII_MODE_GMII,
274 AR71XX_MII_MODE_RGMII,
275 AR71XX_MII_MODE_RMII,
279 * AR71xx MII control region
281 #define AR71XX_MII0_CTRL 0x18070000
282 #define MII_CTRL_SPEED_SHIFT 4
283 #define MII_CTRL_SPEED_MASK 3
284 #define MII_CTRL_SPEED_10 0
285 #define MII_CTRL_SPEED_100 1
286 #define MII_CTRL_SPEED_1000 2
287 #define MII_CTRL_IF_MASK 3
288 #define MII_CTRL_IF_SHIFT 0
289 #define MII0_CTRL_IF_GMII 0
290 #define MII0_CTRL_IF_MII 1
291 #define MII0_CTRL_IF_RGMII 2
292 #define MII0_CTRL_IF_RMII 3
294 #define AR71XX_MII1_CTRL 0x18070004
296 #define MII1_CTRL_IF_RGMII 0
297 #define MII1_CTRL_IF_RMII 1
300 * GigE adapters region
302 #define AR71XX_MAC0_BASE 0x19000000
303 #define AR71XX_MAC1_BASE 0x1A000000
305 #define AR71XX_MAC_CFG1 0x00
306 #define MAC_CFG1_SOFT_RESET (1U << 31)
307 #define MAC_CFG1_SIMUL_RESET (1 << 30)
308 #define MAC_CFG1_MAC_RX_BLOCK_RESET (1 << 19)
309 #define MAC_CFG1_MAC_TX_BLOCK_RESET (1 << 18)
310 #define MAC_CFG1_RX_FUNC_RESET (1 << 17)
311 #define MAC_CFG1_TX_FUNC_RESET (1 << 16)
312 #define MAC_CFG1_LOOPBACK (1 << 8)
313 #define MAC_CFG1_RXFLOW_CTRL (1 << 5)
314 #define MAC_CFG1_TXFLOW_CTRL (1 << 4)
315 #define MAC_CFG1_SYNC_RX (1 << 3)
316 #define MAC_CFG1_RX_ENABLE (1 << 2)
317 #define MAC_CFG1_SYNC_TX (1 << 1)
318 #define MAC_CFG1_TX_ENABLE (1 << 0)
319 #define AR71XX_MAC_CFG2 0x04
320 #define MAC_CFG2_PREAMBLE_LEN_MASK 0xf
321 #define MAC_CFG2_PREAMBLE_LEN_SHIFT 12
322 #define MAC_CFG2_IFACE_MODE_1000 (2 << 8)
323 #define MAC_CFG2_IFACE_MODE_10_100 (1 << 8)
324 #define MAC_CFG2_IFACE_MODE_SHIFT 8
325 #define MAC_CFG2_IFACE_MODE_MASK 3
326 #define MAC_CFG2_HUGE_FRAME (1 << 5)
327 #define MAC_CFG2_LENGTH_FIELD (1 << 4)
328 #define MAC_CFG2_ENABLE_PADCRC (1 << 2)
329 #define MAC_CFG2_ENABLE_CRC (1 << 1)
330 #define MAC_CFG2_FULL_DUPLEX (1 << 0)
331 #define AR71XX_MAC_IFG 0x08
332 #define AR71XX_MAC_HDUPLEX 0x0C
333 #define AR71XX_MAC_MAX_FRAME_LEN 0x10
334 #define AR71XX_MAC_MII_CFG 0x20
335 #define MAC_MII_CFG_RESET (1U << 31)
336 #define MAC_MII_CFG_SCAN_AUTO_INC (1 << 5)
337 #define MAC_MII_CFG_PREAMBLE_SUP (1 << 4)
338 #define MAC_MII_CFG_CLOCK_SELECT_MASK 0x7
339 #define MAC_MII_CFG_CLOCK_SELECT_MASK_AR933X 0xf
340 #define MAC_MII_CFG_CLOCK_DIV_4 0
341 #define MAC_MII_CFG_CLOCK_DIV_6 2
342 #define MAC_MII_CFG_CLOCK_DIV_8 3
343 #define MAC_MII_CFG_CLOCK_DIV_10 4
344 #define MAC_MII_CFG_CLOCK_DIV_14 5
345 #define MAC_MII_CFG_CLOCK_DIV_20 6
346 #define MAC_MII_CFG_CLOCK_DIV_28 7
348 /* .. and the AR933x/AR934x extensions */
349 #define MAC_MII_CFG_CLOCK_DIV_34 8
350 #define MAC_MII_CFG_CLOCK_DIV_42 9
351 #define MAC_MII_CFG_CLOCK_DIV_50 10
352 #define MAC_MII_CFG_CLOCK_DIV_58 11
353 #define MAC_MII_CFG_CLOCK_DIV_66 12
354 #define MAC_MII_CFG_CLOCK_DIV_74 13
355 #define MAC_MII_CFG_CLOCK_DIV_82 14
356 #define MAC_MII_CFG_CLOCK_DIV_98 15
358 #define AR71XX_MAC_MII_CMD 0x24
359 #define MAC_MII_CMD_SCAN_CYCLE (1 << 1)
360 #define MAC_MII_CMD_READ 1
361 #define MAC_MII_CMD_WRITE 0
362 #define AR71XX_MAC_MII_ADDR 0x28
363 #define MAC_MII_PHY_ADDR_SHIFT 8
364 #define MAC_MII_PHY_ADDR_MASK 0xff
365 #define MAC_MII_REG_MASK 0x1f
366 #define AR71XX_MAC_MII_CONTROL 0x2C
367 #define MAC_MII_CONTROL_MASK 0xffff
368 #define AR71XX_MAC_MII_STATUS 0x30
369 #define MAC_MII_STATUS_MASK 0xffff
370 #define AR71XX_MAC_MII_INDICATOR 0x34
371 #define MAC_MII_INDICATOR_NOT_VALID (1 << 2)
372 #define MAC_MII_INDICATOR_SCANNING (1 << 1)
373 #define MAC_MII_INDICATOR_BUSY (1 << 0)
374 #define AR71XX_MAC_IFCONTROL 0x38
375 #define MAC_IFCONTROL_SPEED (1 << 16)
376 #define AR71XX_MAC_STA_ADDR1 0x40
377 #define AR71XX_MAC_STA_ADDR2 0x44
378 #define AR71XX_MAC_FIFO_CFG0 0x48
379 #define FIFO_CFG0_TX_FABRIC (1 << 4)
380 #define FIFO_CFG0_TX_SYSTEM (1 << 3)
381 #define FIFO_CFG0_RX_FABRIC (1 << 2)
382 #define FIFO_CFG0_RX_SYSTEM (1 << 1)
383 #define FIFO_CFG0_WATERMARK (1 << 0)
384 #define FIFO_CFG0_ALL ((1 << 5) - 1)
385 #define FIFO_CFG0_ENABLE_SHIFT 8
386 #define AR71XX_MAC_FIFO_CFG1 0x4C
387 #define AR71XX_MAC_FIFO_CFG2 0x50
388 #define AR71XX_MAC_FIFO_TX_THRESHOLD 0x54
389 #define AR71XX_MAC_FIFO_RX_FILTMATCH 0x58
391 * These flags applicable both to AR71XX_MAC_FIFO_RX_FILTMASK and
392 * to AR71XX_MAC_FIFO_RX_FILTMATCH
394 #define FIFO_RX_MATCH_UNICAST (1 << 17)
395 #define FIFO_RX_MATCH_TRUNC_FRAME (1 << 16)
396 #define FIFO_RX_MATCH_VLAN_TAG (1 << 15)
397 #define FIFO_RX_MATCH_UNSUP_OPCODE (1 << 14)
398 #define FIFO_RX_MATCH_PAUSE_FRAME (1 << 13)
399 #define FIFO_RX_MATCH_CTRL_FRAME (1 << 12)
400 #define FIFO_RX_MATCH_LONG_EVENT (1 << 11)
401 #define FIFO_RX_MATCH_DRIBBLE_NIBBLE (1 << 10)
402 #define FIFO_RX_MATCH_BCAST (1 << 9)
403 #define FIFO_RX_MATCH_MCAST (1 << 8)
404 #define FIFO_RX_MATCH_OK (1 << 7)
405 #define FIFO_RX_MATCH_OORANGE (1 << 6)
406 #define FIFO_RX_MATCH_LEN_MSMTCH (1 << 5)
407 #define FIFO_RX_MATCH_CRC_ERROR (1 << 4)
408 #define FIFO_RX_MATCH_CODE_ERROR (1 << 3)
409 #define FIFO_RX_MATCH_FALSE_CARRIER (1 << 2)
410 #define FIFO_RX_MATCH_RX_DV_EVENT (1 << 1)
411 #define FIFO_RX_MATCH_DROP_EVENT (1 << 0)
413 * Exclude unicast and truncated frames from matching
415 #define FIFO_RX_FILTMATCH_DEFAULT \
416 (FIFO_RX_MATCH_VLAN_TAG | \
417 FIFO_RX_MATCH_UNSUP_OPCODE | \
418 FIFO_RX_MATCH_PAUSE_FRAME | \
419 FIFO_RX_MATCH_CTRL_FRAME | \
420 FIFO_RX_MATCH_LONG_EVENT | \
421 FIFO_RX_MATCH_DRIBBLE_NIBBLE | \
422 FIFO_RX_MATCH_BCAST | \
423 FIFO_RX_MATCH_MCAST | \
425 FIFO_RX_MATCH_OORANGE | \
426 FIFO_RX_MATCH_LEN_MSMTCH | \
427 FIFO_RX_MATCH_CRC_ERROR | \
428 FIFO_RX_MATCH_CODE_ERROR | \
429 FIFO_RX_MATCH_FALSE_CARRIER | \
430 FIFO_RX_MATCH_RX_DV_EVENT | \
431 FIFO_RX_MATCH_DROP_EVENT)
432 #define AR71XX_MAC_FIFO_RX_FILTMASK 0x5C
433 #define FIFO_RX_MASK_BYTE_MODE (1 << 19)
434 #define FIFO_RX_MASK_NO_SHORT_FRAME (1 << 18)
435 #define FIFO_RX_MASK_BIT17 (1 << 17)
436 #define FIFO_RX_MASK_BIT16 (1 << 16)
437 #define FIFO_RX_MASK_TRUNC_FRAME (1 << 15)
438 #define FIFO_RX_MASK_LONG_EVENT (1 << 14)
439 #define FIFO_RX_MASK_VLAN_TAG (1 << 13)
440 #define FIFO_RX_MASK_UNSUP_OPCODE (1 << 12)
441 #define FIFO_RX_MASK_PAUSE_FRAME (1 << 11)
442 #define FIFO_RX_MASK_CTRL_FRAME (1 << 10)
443 #define FIFO_RX_MASK_DRIBBLE_NIBBLE (1 << 9)
444 #define FIFO_RX_MASK_BCAST (1 << 8)
445 #define FIFO_RX_MASK_MCAST (1 << 7)
446 #define FIFO_RX_MASK_OK (1 << 6)
447 #define FIFO_RX_MASK_OORANGE (1 << 5)
448 #define FIFO_RX_MASK_LEN_MSMTCH (1 << 4)
449 #define FIFO_RX_MASK_CODE_ERROR (1 << 3)
450 #define FIFO_RX_MASK_FALSE_CARRIER (1 << 2)
451 #define FIFO_RX_MASK_RX_DV_EVENT (1 << 1)
452 #define FIFO_RX_MASK_DROP_EVENT (1 << 0)
455 * Len. mismatch, unsup. opcode and short frmae bits excluded
457 #define FIFO_RX_FILTMASK_DEFAULT \
458 (FIFO_RX_MASK_NO_SHORT_FRAME | \
459 FIFO_RX_MASK_BIT17 | \
460 FIFO_RX_MASK_BIT16 | \
461 FIFO_RX_MASK_TRUNC_FRAME | \
462 FIFO_RX_MASK_LONG_EVENT | \
463 FIFO_RX_MASK_VLAN_TAG | \
464 FIFO_RX_MASK_PAUSE_FRAME | \
465 FIFO_RX_MASK_CTRL_FRAME | \
466 FIFO_RX_MASK_DRIBBLE_NIBBLE | \
467 FIFO_RX_MASK_BCAST | \
468 FIFO_RX_MASK_MCAST | \
470 FIFO_RX_MASK_OORANGE | \
471 FIFO_RX_MASK_CODE_ERROR | \
472 FIFO_RX_MASK_FALSE_CARRIER | \
473 FIFO_RX_MASK_RX_DV_EVENT | \
474 FIFO_RX_MASK_DROP_EVENT)
476 #define AR71XX_MAC_FIFO_RAM0 0x60
477 #define AR71XX_MAC_FIFO_RAM1 0x64
478 #define AR71XX_MAC_FIFO_RAM2 0x68
479 #define AR71XX_MAC_FIFO_RAM3 0x6C
480 #define AR71XX_MAC_FIFO_RAM4 0x70
481 #define AR71XX_MAC_FIFO_RAM5 0x74
482 #define AR71XX_MAC_FIFO_RAM6 0x78
483 #define AR71XX_DMA_TX_CONTROL 0x180
484 #define DMA_TX_CONTROL_EN (1 << 0)
485 #define AR71XX_DMA_TX_DESC 0x184
486 #define AR71XX_DMA_TX_STATUS 0x188
487 #define DMA_TX_STATUS_PCOUNT_MASK 0xff
488 #define DMA_TX_STATUS_PCOUNT_SHIFT 16
489 #define DMA_TX_STATUS_BUS_ERROR (1 << 3)
490 #define DMA_TX_STATUS_UNDERRUN (1 << 1)
491 #define DMA_TX_STATUS_PKT_SENT (1 << 0)
492 #define AR71XX_DMA_RX_CONTROL 0x18C
493 #define DMA_RX_CONTROL_EN (1 << 0)
494 #define AR71XX_DMA_RX_DESC 0x190
495 #define AR71XX_DMA_RX_STATUS 0x194
496 #define DMA_RX_STATUS_PCOUNT_MASK 0xff
497 #define DMA_RX_STATUS_PCOUNT_SHIFT 16
498 #define DMA_RX_STATUS_BUS_ERROR (1 << 3)
499 #define DMA_RX_STATUS_OVERFLOW (1 << 2)
500 #define DMA_RX_STATUS_PKT_RECVD (1 << 0)
501 #define AR71XX_DMA_INTR 0x198
502 #define AR71XX_DMA_INTR_STATUS 0x19C
503 #define DMA_INTR_ALL ((1 << 8) - 1)
504 #define DMA_INTR_RX_BUS_ERROR (1 << 7)
505 #define DMA_INTR_RX_OVERFLOW (1 << 6)
506 #define DMA_INTR_RX_PKT_RCVD (1 << 4)
507 #define DMA_INTR_TX_BUS_ERROR (1 << 3)
508 #define DMA_INTR_TX_UNDERRUN (1 << 1)
509 #define DMA_INTR_TX_PKT_SENT (1 << 0)
511 #define AR71XX_SPI_BASE 0x1f000000
512 #define AR71XX_SPI_FS 0x00
513 #define AR71XX_SPI_CTRL 0x04
514 #define SPI_CTRL_REMAP_DISABLE (1 << 6)
515 #define SPI_CTRL_CLOCK_DIVIDER_MASK ((1 << 6) - 1)
516 #define AR71XX_SPI_IO_CTRL 0x08
517 #define SPI_IO_CTRL_CS2 (1 << 18)
518 #define SPI_IO_CTRL_CS1 (1 << 17)
519 #define SPI_IO_CTRL_CS0 (1 << 16)
520 #define SPI_IO_CTRL_CSMASK (7 << 16)
521 #define SPI_IO_CTRL_CLK (1 << 8)
522 #define SPI_IO_CTRL_DO 1
523 #define AR71XX_SPI_RDS 0x0C
525 #define ATH_READ_REG(reg) \
526 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg)))
528 #define ATH_WRITE_REG(reg, val) \
529 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((reg))) = (val)
532 ar71xx_ddr_flush(uint32_t reg)
534 ATH_WRITE_REG(reg, 1);
535 while ((ATH_READ_REG(reg) & 0x1))
537 ATH_WRITE_REG(reg, 1);
538 while ((ATH_READ_REG(reg) & 0x1))
543 ar71xx_write_pll(uint32_t cfg_reg, uint32_t pll_reg, uint32_t pll, uint32_t pll_reg_shift)
547 /* set PLL registers */
548 sec_cfg = ATH_READ_REG(cfg_reg);
549 sec_cfg &= ~(3 << pll_reg_shift);
550 sec_cfg |= (2 << pll_reg_shift);
552 ATH_WRITE_REG(cfg_reg, sec_cfg);
555 ATH_WRITE_REG(pll_reg, pll);
556 sec_cfg |= (3 << pll_reg_shift);
557 ATH_WRITE_REG(cfg_reg, sec_cfg);
560 sec_cfg &= ~(3 << pll_reg_shift);
561 ATH_WRITE_REG(cfg_reg, sec_cfg);
565 #endif /* _AR71XX_REG_H_ */