2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
39 #include <sys/reboot.h>
42 #include <vm/vm_page.h>
44 #include <net/ethernet.h>
46 #include <machine/clock.h>
47 #include <machine/cpu.h>
48 #include <machine/cpuregs.h>
49 #include <machine/hwfunc.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
52 #include <machine/vmparam.h>
54 #include <mips/atheros/ar71xxreg.h>
55 #include <mips/atheros/ar933xreg.h>
57 #include <mips/atheros/ar71xx_cpudef.h>
58 #include <mips/atheros/ar71xx_setup.h>
60 #include <mips/atheros/ar71xx_chip.h>
61 #include <mips/atheros/ar933x_chip.h>
64 ar933x_chip_detect_mem_size(void)
69 ar933x_chip_detect_sys_frequency(void)
76 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
77 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
78 u_ar71xx_refclk = (40 * 1000 * 1000);
80 u_ar71xx_refclk = (25 * 1000 * 1000);
82 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
83 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
84 u_ar71xx_cpu_freq = u_ar71xx_refclk;
85 u_ar71xx_ahb_freq = u_ar71xx_refclk;
86 u_ar71xx_ddr_freq = u_ar71xx_refclk;
88 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
90 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
92 freq = u_ar71xx_refclk / t;
94 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
95 AR933X_PLL_CPU_CONFIG_NINT_MASK;
98 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
99 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
105 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
106 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
107 u_ar71xx_cpu_freq = freq / t;
109 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
110 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
111 u_ar71xx_ddr_freq = freq / t;
113 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
114 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
115 u_ar71xx_ahb_freq = freq / t;
118 /* On the AR933x, the UART frequency is the reference clock,
119 * not the AHB bus clock.
121 u_ar71xx_uart_freq = u_ar71xx_refclk;
124 * XXX check what the watchdog frequency should be?
126 u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
130 ar933x_chip_device_stop(uint32_t mask)
134 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
135 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
139 ar933x_chip_device_start(uint32_t mask)
143 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
144 ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
148 ar933x_chip_device_stopped(uint32_t mask)
152 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
153 return ((reg & mask) == mask);
157 ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
168 ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
179 printf("%s: invalid PLL set for arge unit: %d\n",
186 ar933x_chip_ddr_flush_ge(int unit)
191 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
194 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
197 printf("%s: invalid DDR flush for arge unit: %d\n",
204 ar933x_chip_ddr_flush_ip2(void)
207 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
211 ar933x_chip_get_eth_pll(unsigned int mac, int speed)
217 pll = AR933X_PLL_VAL_10;
220 pll = AR933X_PLL_VAL_100;
223 pll = AR933X_PLL_VAL_1000;
226 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
233 ar933x_chip_init_usb_peripheral(void)
235 ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
238 ar71xx_device_start(AR933X_RESET_USB_HOST);
241 ar71xx_device_start(AR933X_RESET_USB_PHY);
245 struct ar71xx_cpu_def ar933x_chip_def = {
246 &ar933x_chip_detect_mem_size,
247 &ar933x_chip_detect_sys_frequency,
248 &ar933x_chip_device_stop,
249 &ar933x_chip_device_start,
250 &ar933x_chip_device_stopped,
251 &ar933x_chip_set_pll_ge,
252 &ar933x_chip_set_mii_speed,
253 &ar71xx_chip_set_mii_if,
254 &ar933x_chip_ddr_flush_ge,
255 &ar933x_chip_get_eth_pll,
256 &ar933x_chip_ddr_flush_ip2,
257 &ar933x_chip_init_usb_peripheral