2 * Copyright (c) 2009, Oleksandr Tymoshenko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 * AR71XX gigabit ethernet driver
34 #ifdef HAVE_KERNEL_OPTION_HEADERS
35 #include "opt_device_polling.h"
38 #include <sys/param.h>
39 #include <sys/endian.h>
40 #include <sys/systm.h>
41 #include <sys/sockio.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/taskqueue.h>
48 #include <sys/sysctl.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
59 #include <machine/bus.h>
60 #include <machine/cache.h>
61 #include <machine/resource.h>
62 #include <vm/vm_param.h>
65 #include <machine/pmap.h>
69 #include <dev/mii/mii.h>
70 #include <dev/mii/miivar.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
75 MODULE_DEPEND(arge, ether, 1, 1, 1);
76 MODULE_DEPEND(arge, miibus, 1, 1, 1);
78 #include "miibus_if.h"
80 #include <mips/atheros/ar71xxreg.h>
81 #include <mips/atheros/if_argevar.h>
82 #include <mips/atheros/ar71xx_setup.h>
83 #include <mips/atheros/ar71xx_cpudef.h>
86 ARGE_DBG_MII = 0x00000001,
87 ARGE_DBG_INTR = 0x00000002,
88 ARGE_DBG_TX = 0x00000004,
89 ARGE_DBG_RX = 0x00000008,
90 ARGE_DBG_ERR = 0x00000010,
91 ARGE_DBG_RESET = 0x00000020,
95 #define ARGEDEBUG(_sc, _m, ...) \
97 if ((_m) & (_sc)->arge_debug) \
98 device_printf((_sc)->arge_dev, __VA_ARGS__); \
101 #define ARGEDEBUG(_sc, _m, ...)
104 static int arge_attach(device_t);
105 static int arge_detach(device_t);
106 static void arge_flush_ddr(struct arge_softc *);
107 static int arge_ifmedia_upd(struct ifnet *);
108 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
109 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
110 static void arge_init(void *);
111 static void arge_init_locked(struct arge_softc *);
112 static void arge_link_task(void *, int);
113 static void arge_set_pll(struct arge_softc *, int, int);
114 static int arge_miibus_readreg(device_t, int, int);
115 static void arge_miibus_statchg(device_t);
116 static int arge_miibus_writereg(device_t, int, int, int);
117 static int arge_probe(device_t);
118 static void arge_reset_dma(struct arge_softc *);
119 static int arge_resume(device_t);
120 static int arge_rx_ring_init(struct arge_softc *);
121 static int arge_tx_ring_init(struct arge_softc *);
122 #ifdef DEVICE_POLLING
123 static int arge_poll(struct ifnet *, enum poll_cmd, int);
125 static int arge_shutdown(device_t);
126 static void arge_start(struct ifnet *);
127 static void arge_start_locked(struct ifnet *);
128 static void arge_stop(struct arge_softc *);
129 static int arge_suspend(device_t);
131 static int arge_rx_locked(struct arge_softc *);
132 static void arge_tx_locked(struct arge_softc *);
133 static void arge_intr(void *);
134 static int arge_intr_filter(void *);
135 static void arge_tick(void *);
138 * ifmedia callbacks for multiPHY MAC
140 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
141 int arge_multiphy_mediachange(struct ifnet *);
143 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
144 static int arge_dma_alloc(struct arge_softc *);
145 static void arge_dma_free(struct arge_softc *);
146 static int arge_newbuf(struct arge_softc *, int);
147 static __inline void arge_fixup_rx(struct mbuf *);
149 static device_method_t arge_methods[] = {
150 /* Device interface */
151 DEVMETHOD(device_probe, arge_probe),
152 DEVMETHOD(device_attach, arge_attach),
153 DEVMETHOD(device_detach, arge_detach),
154 DEVMETHOD(device_suspend, arge_suspend),
155 DEVMETHOD(device_resume, arge_resume),
156 DEVMETHOD(device_shutdown, arge_shutdown),
159 DEVMETHOD(miibus_readreg, arge_miibus_readreg),
160 DEVMETHOD(miibus_writereg, arge_miibus_writereg),
161 DEVMETHOD(miibus_statchg, arge_miibus_statchg),
166 static driver_t arge_driver = {
169 sizeof(struct arge_softc)
172 static devclass_t arge_devclass;
174 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
175 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
178 * RedBoot passes MAC address to entry point as environment
179 * variable. platfrom_start parses it and stores in this variable
181 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
183 static struct mtx miibus_mtx;
185 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
192 arge_flush_ddr(struct arge_softc *sc)
194 if (sc->arge_mac_unit == 0)
195 ar71xx_device_flush_ddr_ge0();
197 ar71xx_device_flush_ddr_ge1();
201 arge_probe(device_t dev)
204 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
209 arge_attach_sysctl(device_t dev)
211 struct arge_softc *sc = device_get_softc(dev);
212 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
213 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
216 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
217 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
218 "arge interface debugging flags");
221 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
222 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
223 "number of TX aligned packets");
225 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
226 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 0,
227 "number of TX unaligned packets");
230 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
231 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
232 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
233 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
234 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
235 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
240 arge_attach(device_t dev)
242 uint8_t eaddr[ETHER_ADDR_LEN];
244 struct arge_softc *sc;
245 int error = 0, rid, phymask;
247 int is_base_mac_empty, i, phys_total;
249 long eeprom_mac_addr = 0;
251 sc = device_get_softc(dev);
253 sc->arge_mac_unit = device_get_unit(dev);
256 * Some units (eg the TP-Link WR-1043ND) do not have a convenient
257 * EEPROM location to read the ethernet MAC address from.
258 * OpenWRT simply snaffles it from a fixed location.
260 * Since multiple units seem to use this feature, include
261 * a method of setting the MAC address based on an flash location
262 * in CPU address space.
264 if (sc->arge_mac_unit == 0 &&
265 resource_long_value(device_get_name(dev), device_get_unit(dev),
266 "eeprommac", &eeprom_mac_addr) == 0) {
268 const char *mac = (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
269 device_printf(dev, "Overriding MAC from EEPROM\n");
270 for (i = 0; i < 6; i++) {
271 ar711_base_mac[i] = mac[i];
275 KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
276 ("if_arge: Only MAC0 and MAC1 supported"));
279 * Get which PHY of 5 available we should use for this unit
281 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
282 "phymask", &phymask) != 0) {
284 * Use port 4 (WAN) for GE0. For any other port use
285 * its PHY the same as its unit number
287 if (sc->arge_mac_unit == 0)
290 /* Use all phys up to 4 */
291 phymask = (1 << 4) - 1;
293 device_printf(dev, "No PHY specified, using mask %d\n", phymask);
297 * Get default media & duplex mode, by default its Base100T
300 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
301 "media", &hint) != 0)
305 sc->arge_media_type = IFM_1000_T;
307 sc->arge_media_type = IFM_100_TX;
309 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
310 "fduplex", &hint) != 0)
314 sc->arge_duplex_mode = IFM_FDX;
316 sc->arge_duplex_mode = 0;
318 sc->arge_phymask = phymask;
320 mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
322 callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
323 TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
325 /* Map control/status registers. */
327 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
328 &sc->arge_rid, RF_ACTIVE);
330 if (sc->arge_res == NULL) {
331 device_printf(dev, "couldn't map memory\n");
336 /* Allocate interrupts */
338 sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
339 RF_SHAREABLE | RF_ACTIVE);
341 if (sc->arge_irq == NULL) {
342 device_printf(dev, "couldn't map interrupt\n");
347 /* Allocate ifnet structure. */
348 ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
351 device_printf(dev, "couldn't allocate ifnet structure\n");
357 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
359 ifp->if_ioctl = arge_ioctl;
360 ifp->if_start = arge_start;
361 ifp->if_init = arge_init;
362 sc->arge_if_flags = ifp->if_flags;
364 /* XXX: add real size */
365 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
366 ifp->if_snd.ifq_maxlen = ifqmaxlen;
367 IFQ_SET_READY(&ifp->if_snd);
369 ifp->if_capenable = ifp->if_capabilities;
370 #ifdef DEVICE_POLLING
371 ifp->if_capabilities |= IFCAP_POLLING;
374 is_base_mac_empty = 1;
375 for (i = 0; i < ETHER_ADDR_LEN; i++) {
376 eaddr[i] = ar711_base_mac[i] & 0xff;
378 is_base_mac_empty = 0;
381 if (is_base_mac_empty) {
383 * No MAC address configured. Generate the random one.
387 "Generating random ethernet address.\n");
393 eaddr[3] = (rnd >> 24) & 0xff;
394 eaddr[4] = (rnd >> 16) & 0xff;
395 eaddr[5] = (rnd >> 8) & 0xff;
398 if (sc->arge_mac_unit != 0)
399 eaddr[5] += sc->arge_mac_unit;
401 if (arge_dma_alloc(sc) != 0) {
406 /* Initialize the MAC block */
408 /* Step 1. Soft-reset MAC */
409 ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
412 /* Step 2. Punt the MAC core from the central reset register */
413 ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC);
415 ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC);
417 /* Step 3. Reconfigure MAC block */
418 ARGE_WRITE(sc, AR71XX_MAC_CFG1,
419 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
420 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
422 reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
423 reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
424 ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
426 ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
429 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
431 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
435 * Set all Ethernet address registers to the same initial values
436 * set all four addresses to 66-88-aa-cc-dd-ee
438 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1,
439 (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]);
440 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]);
442 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
443 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
445 switch (ar71xx_soc) {
446 case AR71XX_SOC_AR7240:
447 case AR71XX_SOC_AR7241:
448 case AR71XX_SOC_AR7242:
449 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
450 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
453 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
454 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
457 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
458 FIFO_RX_FILTMATCH_DEFAULT);
460 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
461 FIFO_RX_FILTMASK_DEFAULT);
464 * Check if we have single-PHY MAC or multi-PHY
467 for (i = 0; i < ARGE_NPHY; i++)
468 if (phymask & (1 << i))
471 if (phys_total == 0) {
476 if (phys_total == 1) {
478 error = mii_attach(dev, &sc->arge_miibus, ifp,
479 arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK,
480 MII_PHY_ANY, MII_OFFSET_ANY, 0);
482 device_printf(dev, "attaching PHYs failed\n");
487 ifmedia_init(&sc->arge_ifmedia, 0,
488 arge_multiphy_mediachange,
489 arge_multiphy_mediastatus);
490 ifmedia_add(&sc->arge_ifmedia,
491 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode,
493 ifmedia_set(&sc->arge_ifmedia,
494 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode);
495 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
498 /* Call MI attach routine. */
499 ether_ifattach(ifp, eaddr);
501 /* Hook interrupt last to avoid having to lock softc */
502 error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
503 arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
506 device_printf(dev, "couldn't set up irq\n");
511 /* setup sysctl variables */
512 arge_attach_sysctl(dev);
522 arge_detach(device_t dev)
524 struct arge_softc *sc = device_get_softc(dev);
525 struct ifnet *ifp = sc->arge_ifp;
527 KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized"));
529 /* These should only be active if attach succeeded */
530 if (device_is_attached(dev)) {
533 #ifdef DEVICE_POLLING
534 if (ifp->if_capenable & IFCAP_POLLING)
535 ether_poll_deregister(ifp);
540 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
545 device_delete_child(dev, sc->arge_miibus);
547 bus_generic_detach(dev);
549 if (sc->arge_intrhand)
550 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
553 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
561 mtx_destroy(&sc->arge_mtx);
568 arge_suspend(device_t dev)
571 panic("%s", __func__);
576 arge_resume(device_t dev)
579 panic("%s", __func__);
584 arge_shutdown(device_t dev)
586 struct arge_softc *sc;
588 sc = device_get_softc(dev);
598 arge_miibus_readreg(device_t dev, int phy, int reg)
600 struct arge_softc * sc = device_get_softc(dev);
602 uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
603 | (reg & MAC_MII_REG_MASK);
605 if ((sc->arge_phymask & (1 << phy)) == 0)
608 mtx_lock(&miibus_mtx);
609 ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
610 ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr);
611 ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
613 i = ARGE_MII_TIMEOUT;
614 while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) &
615 MAC_MII_INDICATOR_BUSY) && (i--))
619 mtx_unlock(&miibus_mtx);
620 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
621 /* XXX: return ERRNO istead? */
625 result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
626 ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
627 mtx_unlock(&miibus_mtx);
629 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__,
630 phy, reg, addr, result);
636 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
638 struct arge_softc * sc = device_get_softc(dev);
641 (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
644 if ((sc->arge_phymask & (1 << phy)) == 0)
647 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
650 mtx_lock(&miibus_mtx);
651 ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr);
652 ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data);
654 i = ARGE_MII_TIMEOUT;
655 while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) &
656 MAC_MII_INDICATOR_BUSY) && (i--))
659 mtx_unlock(&miibus_mtx);
662 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
663 /* XXX: return ERRNO istead? */
671 arge_miibus_statchg(device_t dev)
673 struct arge_softc *sc;
675 sc = device_get_softc(dev);
676 taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
680 arge_link_task(void *arg, int pending)
682 struct arge_softc *sc;
683 struct mii_data *mii;
685 uint32_t media, duplex;
687 sc = (struct arge_softc *)arg;
690 mii = device_get_softc(sc->arge_miibus);
692 if (mii == NULL || ifp == NULL ||
693 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
698 if (mii->mii_media_status & IFM_ACTIVE) {
700 media = IFM_SUBTYPE(mii->mii_media_active);
702 if (media != IFM_NONE) {
703 sc->arge_link_status = 1;
704 duplex = mii->mii_media_active & IFM_GMASK;
705 arge_set_pll(sc, media, duplex);
708 sc->arge_link_status = 0;
714 arge_set_pll(struct arge_softc *sc, int media, int duplex)
716 uint32_t cfg, ifcontrol, rx_filtmask;
720 cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
721 cfg &= ~(MAC_CFG2_IFACE_MODE_1000
722 | MAC_CFG2_IFACE_MODE_10_100
723 | MAC_CFG2_FULL_DUPLEX);
725 if (duplex == IFM_FDX)
726 cfg |= MAC_CFG2_FULL_DUPLEX;
728 ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
729 ifcontrol &= ~MAC_IFCONTROL_SPEED;
731 ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
732 rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
736 cfg |= MAC_CFG2_IFACE_MODE_10_100;
740 cfg |= MAC_CFG2_IFACE_MODE_10_100;
741 ifcontrol |= MAC_IFCONTROL_SPEED;
746 cfg |= MAC_CFG2_IFACE_MODE_1000;
747 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
752 device_printf(sc->arge_dev,
753 "Unknown media %d\n", media);
756 switch (ar71xx_soc) {
757 case AR71XX_SOC_AR7240:
758 case AR71XX_SOC_AR7241:
759 case AR71XX_SOC_AR7242:
760 fifo_tx = 0x01f00140;
762 case AR71XX_SOC_AR9130:
763 case AR71XX_SOC_AR9132:
764 fifo_tx = 0x00780fff;
767 fifo_tx = 0x008001ff;
770 ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
771 ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
772 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
774 ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
776 /* set PLL registers */
777 if (sc->arge_mac_unit == 0)
778 ar71xx_device_set_pll_ge0(if_speed);
780 ar71xx_device_set_pll_ge1(if_speed);
785 arge_reset_dma(struct arge_softc *sc)
787 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
788 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
790 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
791 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
793 /* Clear all possible RX interrupts */
794 while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
795 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
798 * Clear all possible TX interrupts
800 while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
801 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
806 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
807 DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
808 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
809 DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
817 struct arge_softc *sc = xsc;
820 arge_init_locked(sc);
825 arge_init_locked(struct arge_softc *sc)
827 struct ifnet *ifp = sc->arge_ifp;
828 struct mii_data *mii;
830 ARGE_LOCK_ASSERT(sc);
834 /* Init circular RX list. */
835 if (arge_rx_ring_init(sc) != 0) {
836 device_printf(sc->arge_dev,
837 "initialization failed: no memory for rx buffers\n");
842 /* Init tx descriptors. */
843 arge_tx_ring_init(sc);
848 if (sc->arge_miibus) {
849 sc->arge_link_status = 0;
850 mii = device_get_softc(sc->arge_miibus);
855 * Sun always shines over multiPHY interface
857 sc->arge_link_status = 1;
860 ifp->if_drv_flags |= IFF_DRV_RUNNING;
861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
864 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
866 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
867 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
869 /* Start listening */
870 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
872 /* Enable interrupts */
873 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
877 * Return whether the mbuf chain is correctly aligned
878 * for the arge TX engine.
880 * The TX engine requires each fragment to be aligned to a
881 * 4 byte boundary and the size of each fragment except
882 * the last to be a multiple of 4 bytes.
885 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
889 for (m = m0; m != NULL; m = m->m_next) {
890 if((mtod(m, intptr_t) & 3) != 0)
892 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
899 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
900 * pointers to the fragment pointers.
903 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
905 struct arge_txdesc *txd;
906 struct arge_desc *desc, *prev_desc;
907 bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
908 int error, i, nsegs, prod, prev_prod;
911 ARGE_LOCK_ASSERT(sc);
914 * Fix mbuf chain, all fragments should be 4 bytes aligned and
918 if (! arge_mbuf_chain_is_tx_aligned(m)) {
919 sc->stats.tx_pkts_unaligned++;
920 m = m_defrag(*m_head, M_DONTWAIT);
927 sc->stats.tx_pkts_aligned++;
929 prod = sc->arge_cdata.arge_tx_prod;
930 txd = &sc->arge_cdata.arge_txdesc[prod];
931 error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
932 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
934 if (error == EFBIG) {
936 } else if (error != 0)
945 /* Check number of available descriptors. */
946 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
947 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
952 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
953 BUS_DMASYNC_PREWRITE);
956 * Make a list of descriptors for this packet. DMA controller will
957 * walk through it while arge_link is not zero.
960 desc = prev_desc = NULL;
961 for (i = 0; i < nsegs; i++) {
962 desc = &sc->arge_rdata.arge_tx_ring[prod];
963 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
965 if (txsegs[i].ds_addr & 3)
966 panic("TX packet address unaligned\n");
968 desc->packet_addr = txsegs[i].ds_addr;
970 /* link with previous descriptor */
972 prev_desc->packet_ctrl |= ARGE_DESC_MORE;
974 sc->arge_cdata.arge_tx_cnt++;
976 ARGE_INC(prod, ARGE_TX_RING_COUNT);
979 /* Update producer index. */
980 sc->arge_cdata.arge_tx_prod = prod;
982 /* Sync descriptors. */
983 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
984 sc->arge_cdata.arge_tx_ring_map,
985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
987 /* Start transmitting */
988 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n", __func__);
989 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
994 arge_start(struct ifnet *ifp)
996 struct arge_softc *sc;
1001 arge_start_locked(ifp);
1006 arge_start_locked(struct ifnet *ifp)
1008 struct arge_softc *sc;
1009 struct mbuf *m_head;
1014 ARGE_LOCK_ASSERT(sc);
1016 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__);
1018 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1019 IFF_DRV_RUNNING || sc->arge_link_status == 0 )
1023 * Before we go any further, check whether we're already full.
1024 * The below check errors out immediately if the ring is full
1025 * and never gets a chance to set this flag. Although it's
1026 * likely never needed, this at least avoids an unexpected
1029 if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) {
1030 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1031 ARGEDEBUG(sc, ARGE_DBG_ERR, "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n",
1032 __func__, sc->arge_cdata.arge_tx_cnt, ARGE_TX_RING_COUNT - 2);
1038 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1039 sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
1040 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1046 * Pack the data into the transmit ring.
1048 if (arge_encap(sc, &m_head)) {
1051 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1052 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1058 * If there's a BPF listener, bounce a copy of this frame
1061 ETHER_BPF_MTAP(ifp, m_head);
1063 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n", __func__, enq);
1067 arge_stop(struct arge_softc *sc)
1071 ARGE_LOCK_ASSERT(sc);
1074 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1075 if (sc->arge_miibus)
1076 callout_stop(&sc->arge_stat_callout);
1078 /* mask out interrupts */
1079 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1086 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1088 struct arge_softc *sc = ifp->if_softc;
1089 struct ifreq *ifr = (struct ifreq *) data;
1090 struct mii_data *mii;
1092 #ifdef DEVICE_POLLING
1099 if ((ifp->if_flags & IFF_UP) != 0) {
1100 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1101 if (((ifp->if_flags ^ sc->arge_if_flags)
1102 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1103 /* XXX: handle promisc & multi flags */
1107 if (!sc->arge_detach)
1108 arge_init_locked(sc);
1110 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1111 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1114 sc->arge_if_flags = ifp->if_flags;
1120 /* XXX: implement SIOCDELMULTI */
1125 if (sc->arge_miibus) {
1126 mii = device_get_softc(sc->arge_miibus);
1127 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1130 error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command);
1133 /* XXX: Check other capabilities */
1134 #ifdef DEVICE_POLLING
1135 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1136 if (mask & IFCAP_POLLING) {
1137 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1138 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1139 error = ether_poll_register(arge_poll, ifp);
1143 ifp->if_capenable |= IFCAP_POLLING;
1146 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1147 error = ether_poll_deregister(ifp);
1149 ifp->if_capenable &= ~IFCAP_POLLING;
1157 error = ether_ioctl(ifp, command, data);
1165 * Set media options.
1168 arge_ifmedia_upd(struct ifnet *ifp)
1170 struct arge_softc *sc;
1171 struct mii_data *mii;
1172 struct mii_softc *miisc;
1177 mii = device_get_softc(sc->arge_miibus);
1178 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1180 error = mii_mediachg(mii);
1187 * Report current media status.
1190 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1192 struct arge_softc *sc = ifp->if_softc;
1193 struct mii_data *mii;
1195 mii = device_get_softc(sc->arge_miibus);
1198 ifmr->ifm_active = mii->mii_media_active;
1199 ifmr->ifm_status = mii->mii_media_status;
1203 struct arge_dmamap_arg {
1204 bus_addr_t arge_busaddr;
1208 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1210 struct arge_dmamap_arg *ctx;
1215 ctx->arge_busaddr = segs[0].ds_addr;
1219 arge_dma_alloc(struct arge_softc *sc)
1221 struct arge_dmamap_arg ctx;
1222 struct arge_txdesc *txd;
1223 struct arge_rxdesc *rxd;
1226 /* Create parent DMA tag. */
1227 error = bus_dma_tag_create(
1228 bus_get_dma_tag(sc->arge_dev), /* parent */
1229 1, 0, /* alignment, boundary */
1230 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1231 BUS_SPACE_MAXADDR, /* highaddr */
1232 NULL, NULL, /* filter, filterarg */
1233 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1235 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1237 NULL, NULL, /* lockfunc, lockarg */
1238 &sc->arge_cdata.arge_parent_tag);
1240 device_printf(sc->arge_dev, "failed to create parent DMA tag\n");
1243 /* Create tag for Tx ring. */
1244 error = bus_dma_tag_create(
1245 sc->arge_cdata.arge_parent_tag, /* parent */
1246 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1247 BUS_SPACE_MAXADDR, /* lowaddr */
1248 BUS_SPACE_MAXADDR, /* highaddr */
1249 NULL, NULL, /* filter, filterarg */
1250 ARGE_TX_DMA_SIZE, /* maxsize */
1252 ARGE_TX_DMA_SIZE, /* maxsegsize */
1254 NULL, NULL, /* lockfunc, lockarg */
1255 &sc->arge_cdata.arge_tx_ring_tag);
1257 device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n");
1261 /* Create tag for Rx ring. */
1262 error = bus_dma_tag_create(
1263 sc->arge_cdata.arge_parent_tag, /* parent */
1264 ARGE_RING_ALIGN, 0, /* alignment, boundary */
1265 BUS_SPACE_MAXADDR, /* lowaddr */
1266 BUS_SPACE_MAXADDR, /* highaddr */
1267 NULL, NULL, /* filter, filterarg */
1268 ARGE_RX_DMA_SIZE, /* maxsize */
1270 ARGE_RX_DMA_SIZE, /* maxsegsize */
1272 NULL, NULL, /* lockfunc, lockarg */
1273 &sc->arge_cdata.arge_rx_ring_tag);
1275 device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n");
1279 /* Create tag for Tx buffers. */
1280 error = bus_dma_tag_create(
1281 sc->arge_cdata.arge_parent_tag, /* parent */
1282 sizeof(uint32_t), 0, /* alignment, boundary */
1283 BUS_SPACE_MAXADDR, /* lowaddr */
1284 BUS_SPACE_MAXADDR, /* highaddr */
1285 NULL, NULL, /* filter, filterarg */
1286 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
1287 ARGE_MAXFRAGS, /* nsegments */
1288 MCLBYTES, /* maxsegsize */
1290 NULL, NULL, /* lockfunc, lockarg */
1291 &sc->arge_cdata.arge_tx_tag);
1293 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1297 /* Create tag for Rx buffers. */
1298 error = bus_dma_tag_create(
1299 sc->arge_cdata.arge_parent_tag, /* parent */
1300 ARGE_RX_ALIGN, 0, /* alignment, boundary */
1301 BUS_SPACE_MAXADDR, /* lowaddr */
1302 BUS_SPACE_MAXADDR, /* highaddr */
1303 NULL, NULL, /* filter, filterarg */
1304 MCLBYTES, /* maxsize */
1305 ARGE_MAXFRAGS, /* nsegments */
1306 MCLBYTES, /* maxsegsize */
1308 NULL, NULL, /* lockfunc, lockarg */
1309 &sc->arge_cdata.arge_rx_tag);
1311 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
1315 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1316 error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
1317 (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
1318 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_tx_ring_map);
1320 device_printf(sc->arge_dev,
1321 "failed to allocate DMA'able memory for Tx ring\n");
1325 ctx.arge_busaddr = 0;
1326 error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
1327 sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
1328 ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1329 if (error != 0 || ctx.arge_busaddr == 0) {
1330 device_printf(sc->arge_dev,
1331 "failed to load DMA'able memory for Tx ring\n");
1334 sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
1336 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1337 error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
1338 (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
1339 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_rx_ring_map);
1341 device_printf(sc->arge_dev,
1342 "failed to allocate DMA'able memory for Rx ring\n");
1346 ctx.arge_busaddr = 0;
1347 error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
1348 sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
1349 ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
1350 if (error != 0 || ctx.arge_busaddr == 0) {
1351 device_printf(sc->arge_dev,
1352 "failed to load DMA'able memory for Rx ring\n");
1355 sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
1357 /* Create DMA maps for Tx buffers. */
1358 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1359 txd = &sc->arge_cdata.arge_txdesc[i];
1361 txd->tx_dmamap = NULL;
1362 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
1365 device_printf(sc->arge_dev,
1366 "failed to create Tx dmamap\n");
1370 /* Create DMA maps for Rx buffers. */
1371 if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1372 &sc->arge_cdata.arge_rx_sparemap)) != 0) {
1373 device_printf(sc->arge_dev,
1374 "failed to create spare Rx dmamap\n");
1377 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1378 rxd = &sc->arge_cdata.arge_rxdesc[i];
1380 rxd->rx_dmamap = NULL;
1381 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
1384 device_printf(sc->arge_dev,
1385 "failed to create Rx dmamap\n");
1395 arge_dma_free(struct arge_softc *sc)
1397 struct arge_txdesc *txd;
1398 struct arge_rxdesc *rxd;
1402 if (sc->arge_cdata.arge_tx_ring_tag) {
1403 if (sc->arge_cdata.arge_tx_ring_map)
1404 bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
1405 sc->arge_cdata.arge_tx_ring_map);
1406 if (sc->arge_cdata.arge_tx_ring_map &&
1407 sc->arge_rdata.arge_tx_ring)
1408 bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
1409 sc->arge_rdata.arge_tx_ring,
1410 sc->arge_cdata.arge_tx_ring_map);
1411 sc->arge_rdata.arge_tx_ring = NULL;
1412 sc->arge_cdata.arge_tx_ring_map = NULL;
1413 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
1414 sc->arge_cdata.arge_tx_ring_tag = NULL;
1417 if (sc->arge_cdata.arge_rx_ring_tag) {
1418 if (sc->arge_cdata.arge_rx_ring_map)
1419 bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
1420 sc->arge_cdata.arge_rx_ring_map);
1421 if (sc->arge_cdata.arge_rx_ring_map &&
1422 sc->arge_rdata.arge_rx_ring)
1423 bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
1424 sc->arge_rdata.arge_rx_ring,
1425 sc->arge_cdata.arge_rx_ring_map);
1426 sc->arge_rdata.arge_rx_ring = NULL;
1427 sc->arge_cdata.arge_rx_ring_map = NULL;
1428 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
1429 sc->arge_cdata.arge_rx_ring_tag = NULL;
1432 if (sc->arge_cdata.arge_tx_tag) {
1433 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1434 txd = &sc->arge_cdata.arge_txdesc[i];
1435 if (txd->tx_dmamap) {
1436 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
1438 txd->tx_dmamap = NULL;
1441 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
1442 sc->arge_cdata.arge_tx_tag = NULL;
1445 if (sc->arge_cdata.arge_rx_tag) {
1446 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1447 rxd = &sc->arge_cdata.arge_rxdesc[i];
1448 if (rxd->rx_dmamap) {
1449 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1451 rxd->rx_dmamap = NULL;
1454 if (sc->arge_cdata.arge_rx_sparemap) {
1455 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
1456 sc->arge_cdata.arge_rx_sparemap);
1457 sc->arge_cdata.arge_rx_sparemap = 0;
1459 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
1460 sc->arge_cdata.arge_rx_tag = NULL;
1463 if (sc->arge_cdata.arge_parent_tag) {
1464 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
1465 sc->arge_cdata.arge_parent_tag = NULL;
1470 * Initialize the transmit descriptors.
1473 arge_tx_ring_init(struct arge_softc *sc)
1475 struct arge_ring_data *rd;
1476 struct arge_txdesc *txd;
1480 sc->arge_cdata.arge_tx_prod = 0;
1481 sc->arge_cdata.arge_tx_cons = 0;
1482 sc->arge_cdata.arge_tx_cnt = 0;
1484 rd = &sc->arge_rdata;
1485 bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
1486 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
1487 if (i == ARGE_TX_RING_COUNT - 1)
1488 addr = ARGE_TX_RING_ADDR(sc, 0);
1490 addr = ARGE_TX_RING_ADDR(sc, i + 1);
1491 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
1492 rd->arge_tx_ring[i].next_desc = addr;
1493 txd = &sc->arge_cdata.arge_txdesc[i];
1497 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1498 sc->arge_cdata.arge_tx_ring_map,
1499 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1505 * Initialize the RX descriptors and allocate mbufs for them. Note that
1506 * we arrange the descriptors in a closed ring, so that the last descriptor
1507 * points back to the first.
1510 arge_rx_ring_init(struct arge_softc *sc)
1512 struct arge_ring_data *rd;
1513 struct arge_rxdesc *rxd;
1517 sc->arge_cdata.arge_rx_cons = 0;
1519 rd = &sc->arge_rdata;
1520 bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
1521 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
1522 rxd = &sc->arge_cdata.arge_rxdesc[i];
1524 rxd->desc = &rd->arge_rx_ring[i];
1525 if (i == ARGE_RX_RING_COUNT - 1)
1526 addr = ARGE_RX_RING_ADDR(sc, 0);
1528 addr = ARGE_RX_RING_ADDR(sc, i + 1);
1529 rd->arge_rx_ring[i].next_desc = addr;
1530 if (arge_newbuf(sc, i) != 0) {
1535 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1536 sc->arge_cdata.arge_rx_ring_map,
1537 BUS_DMASYNC_PREWRITE);
1543 * Initialize an RX descriptor and attach an MBUF cluster.
1546 arge_newbuf(struct arge_softc *sc, int idx)
1548 struct arge_desc *desc;
1549 struct arge_rxdesc *rxd;
1551 bus_dma_segment_t segs[1];
1555 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1558 m->m_len = m->m_pkthdr.len = MCLBYTES;
1559 m_adj(m, sizeof(uint64_t));
1561 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
1562 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1566 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1568 rxd = &sc->arge_cdata.arge_rxdesc[idx];
1569 if (rxd->rx_m != NULL) {
1570 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
1572 map = rxd->rx_dmamap;
1573 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
1574 sc->arge_cdata.arge_rx_sparemap = map;
1577 if (segs[0].ds_addr & 3)
1578 panic("RX packet address unaligned");
1579 desc->packet_addr = segs[0].ds_addr;
1580 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
1582 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1583 sc->arge_cdata.arge_rx_ring_map,
1584 BUS_DMASYNC_PREWRITE);
1589 static __inline void
1590 arge_fixup_rx(struct mbuf *m)
1593 uint16_t *src, *dst;
1595 src = mtod(m, uint16_t *);
1598 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
1602 if (m->m_len % sizeof(uint16_t))
1603 *(uint8_t *)dst = *(uint8_t *)src;
1605 m->m_data -= ETHER_ALIGN;
1608 #ifdef DEVICE_POLLING
1610 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1612 struct arge_softc *sc = ifp->if_softc;
1615 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1618 rx_npkts = arge_rx_locked(sc);
1624 #endif /* DEVICE_POLLING */
1628 arge_tx_locked(struct arge_softc *sc)
1630 struct arge_txdesc *txd;
1631 struct arge_desc *cur_tx;
1636 ARGE_LOCK_ASSERT(sc);
1638 cons = sc->arge_cdata.arge_tx_cons;
1639 prod = sc->arge_cdata.arge_tx_prod;
1641 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons, prod);
1646 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1647 sc->arge_cdata.arge_tx_ring_map,
1648 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1652 * Go through our tx list and free mbufs for those
1653 * frames that have been transmitted.
1655 for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
1656 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
1657 ctrl = cur_tx->packet_ctrl;
1658 /* Check if descriptor has "finished" flag */
1659 if ((ctrl & ARGE_DESC_EMPTY) == 0)
1662 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
1664 sc->arge_cdata.arge_tx_cnt--;
1665 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1667 txd = &sc->arge_cdata.arge_txdesc[cons];
1671 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1672 BUS_DMASYNC_POSTWRITE);
1673 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1675 /* Free only if it's first descriptor in list */
1680 /* reset descriptor */
1681 cur_tx->packet_addr = 0;
1684 sc->arge_cdata.arge_tx_cons = cons;
1686 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
1687 sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1692 arge_rx_locked(struct arge_softc *sc)
1694 struct arge_rxdesc *rxd;
1695 struct ifnet *ifp = sc->arge_ifp;
1696 int cons, prog, packet_len, i;
1697 struct arge_desc *cur_rx;
1701 ARGE_LOCK_ASSERT(sc);
1703 cons = sc->arge_cdata.arge_rx_cons;
1705 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1706 sc->arge_cdata.arge_rx_ring_map,
1707 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1709 for (prog = 0; prog < ARGE_RX_RING_COUNT;
1710 ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
1711 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
1712 rxd = &sc->arge_cdata.arge_rxdesc[cons];
1715 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
1718 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
1722 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
1723 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
1724 BUS_DMASYNC_POSTREAD);
1728 m->m_pkthdr.rcvif = ifp;
1729 /* Skip 4 bytes of CRC */
1730 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
1735 (*ifp->if_input)(ifp, m);
1737 cur_rx->packet_addr = 0;
1742 i = sc->arge_cdata.arge_rx_cons;
1743 for (; prog > 0 ; prog--) {
1744 if (arge_newbuf(sc, i) != 0) {
1745 device_printf(sc->arge_dev,
1746 "Failed to allocate buffer\n");
1749 ARGE_INC(i, ARGE_RX_RING_COUNT);
1752 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
1753 sc->arge_cdata.arge_rx_ring_map,
1754 BUS_DMASYNC_PREWRITE);
1756 sc->arge_cdata.arge_rx_cons = cons;
1763 arge_intr_filter(void *arg)
1765 struct arge_softc *sc = arg;
1766 uint32_t status, ints;
1768 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
1769 ints = ARGE_READ(sc, AR71XX_DMA_INTR);
1771 ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
1772 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
1773 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
1774 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
1775 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
1776 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
1778 if (status & DMA_INTR_ALL) {
1779 sc->arge_intr_status |= status;
1780 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
1781 return (FILTER_SCHEDULE_THREAD);
1784 sc->arge_intr_status = 0;
1785 return (FILTER_STRAY);
1789 arge_intr(void *arg)
1791 struct arge_softc *sc = arg;
1793 struct ifnet *ifp = sc->arge_ifp;
1795 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
1796 status |= sc->arge_intr_status;
1798 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
1799 "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
1800 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
1803 * Is it our interrupt at all?
1808 if (status & DMA_INTR_RX_BUS_ERROR) {
1809 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
1810 device_printf(sc->arge_dev, "RX bus error");
1814 if (status & DMA_INTR_TX_BUS_ERROR) {
1815 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
1816 device_printf(sc->arge_dev, "TX bus error");
1822 if (status & DMA_INTR_RX_PKT_RCVD)
1826 * RX overrun disables the receiver.
1827 * Clear indication and re-enable rx.
1829 if ( status & DMA_INTR_RX_OVERFLOW) {
1830 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
1831 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
1832 sc->stats.rx_overflow++;
1835 if (status & DMA_INTR_TX_PKT_SENT)
1838 * Underrun turns off TX. Clear underrun indication.
1839 * If there's anything left in the ring, reactivate the tx.
1841 if (status & DMA_INTR_TX_UNDERRUN) {
1842 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
1843 sc->stats.tx_underflow++;
1844 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n", __func__, sc->arge_cdata.arge_tx_cnt);
1845 if (sc->arge_cdata.arge_tx_cnt > 0 ) {
1846 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
1852 * If we've finished TXing and there's space for more packets
1853 * to be queued for TX, do so. Otherwise we may end up in a
1854 * situation where the interface send queue was filled
1855 * whilst the hardware queue was full, then the hardware
1856 * queue was drained by the interface send queue wasn't,
1857 * and thus if_start() is never called to kick-start
1858 * the send process (and all subsequent packets are simply
1861 * XXX TODO: make sure that the hardware deals nicely
1862 * with the possibility of the queue being enabled above
1863 * after a TX underrun, then having the hardware queue added
1866 if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) &&
1867 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
1868 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1869 arge_start_locked(ifp);
1873 * We handled all bits, clear status
1875 sc->arge_intr_status = 0;
1878 * re-enable all interrupts
1880 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1885 arge_tick(void *xsc)
1887 struct arge_softc *sc = xsc;
1888 struct mii_data *mii;
1890 ARGE_LOCK_ASSERT(sc);
1892 if (sc->arge_miibus) {
1893 mii = device_get_softc(sc->arge_miibus);
1895 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
1900 arge_multiphy_mediachange(struct ifnet *ifp)
1902 struct arge_softc *sc = ifp->if_softc;
1903 struct ifmedia *ifm = &sc->arge_ifmedia;
1904 struct ifmedia_entry *ife = ifm->ifm_cur;
1906 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1909 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1910 device_printf(sc->arge_dev,
1911 "AUTO is not supported for multiphy MAC");
1922 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1924 struct arge_softc *sc = ifp->if_softc;
1926 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1927 ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
1928 sc->arge_duplex_mode;