2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
33 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <machine/hwfunc.h>
38 #include <machine/md_var.h>
39 #include <machine/smp.h>
41 #include <mips/cavium/octeon_pcmap_regs.h>
43 #include <contrib/octeon-sdk/cvmx.h>
44 #include <contrib/octeon-sdk/cvmx-interrupt.h>
47 extern cvmx_bootinfo_t *octeon_bootinfo;
49 unsigned octeon_ap_boot = ~0;
52 platform_ipi_send(int cpuid)
54 cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
59 platform_ipi_clear(void)
63 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
64 KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
65 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
69 platform_ipi_intrnum(void)
75 platform_init_ap(int cpuid)
77 unsigned ipi_int_mask, clock_int_mask;
80 * Set the exception base.
82 mips_wr_ebase(0x80000000 | cpuid);
85 * Clear any pending IPIs.
87 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
95 * Unmask the clock and ipi interrupts.
97 clock_int_mask = hard_int_mask(5);
98 ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
99 set_intr_mask(ipi_int_mask | clock_int_mask);
105 platform_num_processors(void)
107 return (bitcount32(octeon_bootinfo->core_mask));
111 platform_smp_topo(void)
113 return (smp_topo_none());
117 platform_start_ap(int cpuid)
119 if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
123 if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
125 printf("Waiting for cpu%d to start\n", cpuid);