2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Derived from uart_dev_ns8250.c
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
43 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
45 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
48 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
49 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <machine/bus.h>
65 #include <machine/pcpu.h>
67 #include <dev/uart/uart.h>
68 #include <dev/uart/uart_cpu.h>
69 #include <dev/uart/uart_bus.h>
71 #include <dev/ic/ns16550.h>
73 #include <mips/cavium/octeon_pcmap_regs.h>
75 #include <contrib/octeon-sdk/cvmx.h>
80 * Clear pending interrupts. THRE is cleared by reading IIR. Data
81 * that may have been received gets lost here.
84 oct16550_clrint (struct uart_bas *bas)
88 iir = uart_getreg(bas, REG_IIR);
89 while ((iir & IIR_NOPEND) == 0) {
92 (void)uart_getreg(bas, REG_LSR);
93 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
94 (void)uart_getreg(bas, REG_DATA);
95 else if (iir == IIR_MLSC)
96 (void)uart_getreg(bas, REG_MSR);
97 else if (iir == IIR_BUSY)
98 (void) uart_getreg(bas, REG_USR);
100 iir = uart_getreg(bas, REG_IIR);
104 static int delay_changed = 1;
107 oct16550_delay (struct uart_bas *bas)
111 static int delay = 0;
113 if (!delay_changed) return delay;
115 lcr = uart_getreg(bas, REG_LCR);
116 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
118 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
120 uart_setreg(bas, REG_LCR, lcr);
124 return 10; /* return an approx delay value */
126 /* 1/10th the time to transmit 1 character (estimate). */
128 return (16000000 * divisor / bas->rclk);
129 return (16000 * divisor / (bas->rclk / 1000));
134 oct16550_divisor (int rclk, int baudrate)
136 int actual_baud, divisor;
142 divisor = (rclk / (baudrate << 3) + 1) >> 1;
143 if (divisor == 0 || divisor >= 65536)
145 actual_baud = rclk / (divisor << 4);
147 /* 10 times error in percent: */
148 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
150 /* 3.0% maximum error tolerance: */
151 if (error < -30 || error > 30)
158 oct16550_drain (struct uart_bas *bas, int what)
162 delay = oct16550_delay(bas);
164 if (what & UART_DRAIN_TRANSMITTER) {
166 * Pick an arbitrary high limit to avoid getting stuck in
167 * an infinite loop when the hardware is broken. Make the
168 * limit high enough to handle large FIFOs.
170 limit = 10*10*10*1024;
171 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
174 /* printf("oct16550: transmitter appears stuck... "); */
179 if (what & UART_DRAIN_RECEIVER) {
181 * Pick an arbitrary high limit to avoid getting stuck in
182 * an infinite loop when the hardware is broken. Make the
183 * limit high enough to handle large FIFOs and integrated
184 * UARTs. The HP rx2600 for example has 3 UARTs on the
185 * management board that tend to get a lot of data send
186 * to it when the UART is first activated.
189 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
190 (void)uart_getreg(bas, REG_DATA);
195 /* printf("oct16550: receiver appears broken... "); */
204 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
205 * drained. WARNING: this function clobbers the FIFO setting!
208 oct16550_flush (struct uart_bas *bas, int what)
213 if (what & UART_FLUSH_TRANSMITTER)
215 if (what & UART_FLUSH_RECEIVER)
217 uart_setreg(bas, REG_FCR, fcr);
222 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
231 else if (databits == 7)
233 else if (databits == 6)
243 divisor = oct16550_divisor(bas->rclk, baudrate);
246 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
248 uart_setreg(bas, REG_DLL, divisor & 0xff);
249 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
254 /* Set LCR and clear DLAB. */
255 uart_setreg(bas, REG_LCR, lcr);
261 * Low-level UART interface.
263 static int oct16550_probe(struct uart_bas *bas);
264 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
265 static void oct16550_term(struct uart_bas *bas);
266 static void oct16550_putc(struct uart_bas *bas, int);
267 static int oct16550_rxready(struct uart_bas *bas);
268 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
270 struct uart_ops uart_oct16550_ops = {
271 .probe = oct16550_probe,
272 .init = oct16550_init,
273 .term = oct16550_term,
274 .putc = oct16550_putc,
275 .rxready = oct16550_rxready,
276 .getc = oct16550_getc,
280 oct16550_probe (struct uart_bas *bas)
284 /* Check known 0 bits that don't depend on DLAB. */
285 val = uart_getreg(bas, REG_IIR);
288 val = uart_getreg(bas, REG_MCR);
291 val = uart_getreg(bas, REG_USR);
298 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
303 oct16550_param(bas, baudrate, databits, stopbits, parity);
305 /* Disable all interrupt sources. */
306 ier = uart_getreg(bas, REG_IER) & 0x0;
307 uart_setreg(bas, REG_IER, ier);
310 /* Disable the FIFO (if present). */
311 // uart_setreg(bas, REG_FCR, 0);
315 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
318 oct16550_clrint(bas);
322 oct16550_term (struct uart_bas *bas)
325 /* Clear RTS & DTR. */
326 uart_setreg(bas, REG_MCR, 0);
330 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
332 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
333 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
338 oct16550_putc (struct uart_bas *bas, int c)
342 /* 1/10th the time to transmit 1 character (estimate). */
343 delay = oct16550_delay(bas);
344 oct16550_wait_txhr_empty(bas, 100, delay);
345 uart_setreg(bas, REG_DATA, c);
347 oct16550_wait_txhr_empty(bas, 100, delay);
351 oct16550_rxready (struct uart_bas *bas)
354 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
358 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
364 /* 1/10th the time to transmit 1 character (estimate). */
365 delay = oct16550_delay(bas);
367 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
373 c = uart_getreg(bas, REG_DATA);
381 * High-level UART interface.
383 struct oct16550_softc {
384 struct uart_softc base;
390 static int oct16550_bus_attach(struct uart_softc *);
391 static int oct16550_bus_detach(struct uart_softc *);
392 static int oct16550_bus_flush(struct uart_softc *, int);
393 static int oct16550_bus_getsig(struct uart_softc *);
394 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
395 static int oct16550_bus_ipend(struct uart_softc *);
396 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
397 static int oct16550_bus_probe(struct uart_softc *);
398 static int oct16550_bus_receive(struct uart_softc *);
399 static int oct16550_bus_setsig(struct uart_softc *, int);
400 static int oct16550_bus_transmit(struct uart_softc *);
401 static void oct16550_bus_grab(struct uart_softc *);
402 static void oct16550_bus_ungrab(struct uart_softc *);
404 static kobj_method_t oct16550_methods[] = {
405 KOBJMETHOD(uart_attach, oct16550_bus_attach),
406 KOBJMETHOD(uart_detach, oct16550_bus_detach),
407 KOBJMETHOD(uart_flush, oct16550_bus_flush),
408 KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
409 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
410 KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
411 KOBJMETHOD(uart_param, oct16550_bus_param),
412 KOBJMETHOD(uart_probe, oct16550_bus_probe),
413 KOBJMETHOD(uart_receive, oct16550_bus_receive),
414 KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
415 KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
416 KOBJMETHOD(uart_grab, oct16550_bus_grab),
417 KOBJMETHOD(uart_ungrab, oct16550_bus_ungrab),
421 struct uart_class uart_oct16550_class = {
424 sizeof(struct oct16550_softc),
425 .uc_ops = &uart_oct16550_ops,
430 #define SIGCHG(c, i, s, d) \
432 i |= (i & s) ? s : s | d; \
434 i = (i & s) ? (i & ~s) | d : i; \
438 oct16550_bus_attach (struct uart_softc *sc)
440 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
441 struct uart_bas *bas;
444 unit = device_get_unit(sc->sc_dev);
447 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
448 oct16550->mcr = uart_getreg(bas, REG_MCR);
449 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
450 uart_setreg(bas, REG_FCR, oct16550->fcr);
452 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
454 if (oct16550->mcr & MCR_DTR)
455 sc->sc_hwsig |= SER_DTR;
456 if (oct16550->mcr & MCR_RTS)
457 sc->sc_hwsig |= SER_RTS;
458 oct16550_bus_getsig(sc);
460 oct16550_clrint(bas);
461 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
462 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
463 uart_setreg(bas, REG_IER, oct16550->ier);
470 oct16550_bus_detach (struct uart_softc *sc)
472 struct uart_bas *bas;
476 ier = uart_getreg(bas, REG_IER) & 0xf0;
477 uart_setreg(bas, REG_IER, ier);
479 oct16550_clrint(bas);
484 oct16550_bus_flush (struct uart_softc *sc, int what)
486 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
487 struct uart_bas *bas;
491 uart_lock(sc->sc_hwmtx);
492 if (sc->sc_rxfifosz > 1) {
493 oct16550_flush(bas, what);
494 uart_setreg(bas, REG_FCR, oct16550->fcr);
498 error = oct16550_drain(bas, what);
499 uart_unlock(sc->sc_hwmtx);
504 oct16550_bus_getsig (struct uart_softc *sc)
506 uint32_t new, old, sig;
512 uart_lock(sc->sc_hwmtx);
513 msr = uart_getreg(&sc->sc_bas, REG_MSR);
514 uart_unlock(sc->sc_hwmtx);
515 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
516 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
517 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
518 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
519 new = sig & ~SER_MASK_DELTA;
520 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
525 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
527 struct uart_bas *bas;
528 int baudrate, divisor, error;
533 uart_lock(sc->sc_hwmtx);
535 case UART_IOCTL_BREAK:
536 lcr = uart_getreg(bas, REG_LCR);
541 uart_setreg(bas, REG_LCR, lcr);
544 case UART_IOCTL_IFLOW:
545 lcr = uart_getreg(bas, REG_LCR);
547 uart_setreg(bas, REG_LCR, 0xbf);
549 efr = uart_getreg(bas, REG_EFR);
554 uart_setreg(bas, REG_EFR, efr);
556 uart_setreg(bas, REG_LCR, lcr);
559 case UART_IOCTL_OFLOW:
560 lcr = uart_getreg(bas, REG_LCR);
562 uart_setreg(bas, REG_LCR, 0xbf);
564 efr = uart_getreg(bas, REG_EFR);
569 uart_setreg(bas, REG_EFR, efr);
571 uart_setreg(bas, REG_LCR, lcr);
574 case UART_IOCTL_BAUD:
575 lcr = uart_getreg(bas, REG_LCR);
576 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
578 divisor = uart_getreg(bas, REG_DLL) |
579 (uart_getreg(bas, REG_DLH) << 8);
581 uart_setreg(bas, REG_LCR, lcr);
583 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
586 *(int*)data = baudrate;
594 uart_unlock(sc->sc_hwmtx);
600 oct16550_bus_ipend(struct uart_softc *sc)
602 struct uart_bas *bas;
607 uart_lock(sc->sc_hwmtx);
609 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
610 if (iir != IIR_NOPEND) {
612 if (iir == IIR_RLS) {
613 lsr = uart_getreg(bas, REG_LSR);
615 ipend |= SER_INT_OVERRUN;
617 ipend |= SER_INT_BREAK;
619 ipend |= SER_INT_RXREADY;
621 } else if (iir == IIR_RXRDY) {
622 ipend |= SER_INT_RXREADY;
624 } else if (iir == IIR_RXTOUT) {
625 ipend |= SER_INT_RXREADY;
627 } else if (iir == IIR_TXRDY) {
628 ipend |= SER_INT_TXIDLE;
630 } else if (iir == IIR_MLSC) {
631 ipend |= SER_INT_SIGCHG;
633 } else if (iir == IIR_BUSY) {
634 (void) uart_getreg(bas, REG_USR);
637 uart_unlock(sc->sc_hwmtx);
643 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
644 int stopbits, int parity)
646 struct uart_bas *bas;
650 uart_lock(sc->sc_hwmtx);
651 error = oct16550_param(bas, baudrate, databits, stopbits, parity);
652 uart_unlock(sc->sc_hwmtx);
657 oct16550_bus_probe (struct uart_softc *sc)
659 struct uart_bas *bas;
663 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
665 error = oct16550_probe(bas);
670 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
673 * Enable FIFOs. And check that the UART has them. If not, we're
674 * done. Since this is the first time we enable the FIFOs, we reset
677 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
678 #define ENABLE_OCTEON_FIFO 1
679 #ifdef ENABLE_OCTEON_FIFO
680 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
684 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
686 if (device_get_unit(sc->sc_dev)) {
687 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
689 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
691 #ifdef ENABLE_OCTEON_FIFO
692 sc->sc_rxfifosz = 64;
693 sc->sc_txfifosz = 64;
702 * XXX there are some issues related to hardware flow control and
703 * it's likely that uart(4) is the cause. This basicly needs more
704 * investigation, but we avoid using for hardware flow control
707 /* 16650s or higher have automatic flow control. */
708 if (sc->sc_rxfifosz > 16) {
718 oct16550_bus_receive (struct uart_softc *sc)
720 struct uart_bas *bas;
725 uart_lock(sc->sc_hwmtx);
726 lsr = uart_getreg(bas, REG_LSR);
728 while (lsr & LSR_RXRDY) {
729 if (uart_rx_full(sc)) {
730 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
733 xc = uart_getreg(bas, REG_DATA);
735 xc |= UART_STAT_FRAMERR;
737 xc |= UART_STAT_PARERR;
739 lsr = uart_getreg(bas, REG_LSR);
741 /* Discard everything left in the Rx FIFO. */
743 * First do a dummy read/discard anyway, in case the UART was lying to us.
744 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
745 * Results in a stuck ipend loop.
747 (void)uart_getreg(bas, REG_DATA);
748 while (lsr & LSR_RXRDY) {
749 (void)uart_getreg(bas, REG_DATA);
751 lsr = uart_getreg(bas, REG_LSR);
753 uart_unlock(sc->sc_hwmtx);
758 oct16550_bus_setsig (struct uart_softc *sc, int sig)
760 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
761 struct uart_bas *bas;
768 if (sig & SER_DDTR) {
769 SIGCHG(sig & SER_DTR, new, SER_DTR,
772 if (sig & SER_DRTS) {
773 SIGCHG(sig & SER_RTS, new, SER_RTS,
776 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
777 uart_lock(sc->sc_hwmtx);
778 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
780 oct16550->mcr |= MCR_DTR;
782 oct16550->mcr |= MCR_RTS;
783 uart_setreg(bas, REG_MCR, oct16550->mcr);
785 uart_unlock(sc->sc_hwmtx);
790 oct16550_bus_transmit (struct uart_softc *sc)
792 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
793 struct uart_bas *bas;
797 uart_lock(sc->sc_hwmtx);
798 #ifdef NO_UART_INTERRUPTS
799 for (i = 0; i < sc->sc_txdatasz; i++) {
800 oct16550_putc(bas, sc->sc_txbuf[i]);
804 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
805 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
808 for (i = 0; i < sc->sc_txdatasz; i++) {
809 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
814 uart_unlock(sc->sc_hwmtx);
819 oct16550_bus_grab(struct uart_softc *sc)
821 struct uart_bas *bas = &sc->sc_bas;
824 * turn off all interrupts to enter polling mode. Leave the
825 * saved mask alone. We'll restore whatever it was in ungrab.
826 * All pending interupt signals are reset when IER is set to 0.
828 uart_lock(sc->sc_hwmtx);
829 uart_setreg(bas, REG_IER, 0);
831 uart_unlock(sc->sc_hwmtx);
835 oct16550_bus_ungrab(struct uart_softc *sc)
837 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
838 struct uart_bas *bas = &sc->sc_bas;
841 * Restore previous interrupt mask
843 uart_lock(sc->sc_hwmtx);
844 uart_setreg(bas, REG_IER, oct16550->ier);
846 uart_unlock(sc->sc_hwmtx);